AMT49406GLPTR

AMT49406 50 V Code-Free FOC BLDC Motor Controller FEATURES AND BENEFITS DESCRIPTION • • • • • • • • • • The AMT49406 is a 3-phase, sensorless, brushless DC (BLDC) motor driver (gate driver) which can operate from 5.5 to 50 V. Code-free sensorless field-oriented control (FOC) Proprietary non-reverse fast startup Soft-On Soft-Off (SOSO) for quiet operation Analog / PWM / Clock mode speed control Closed-loop speed control Configurable current limit Windmill startup operation Lock detection Short-circuit protection (OCP) Brake and direction inputs APPLICATIONS • • • • A field-oriented control (FOC) algorithm is fully integrated to achieve the best efficiency and acoustic noise performance. The device optimizes the motor startup performance in a stationary condition, a windmill condition, and even in a reverse windmill condition. Motor speed is controlled through analog, PWM, or CLOCK input. Closed-loop speed control is optional, and RPM-to-clock frequency ratio is programmable. A simple I2C interface is provided for setting motor-rated voltage, rated current, rated speed, resistance, and startup profiles. Ceiling fans Pedestal fans Bathroom exhaust fans Home appliance fans and pumps The AMT49406 is available in a 24-contact 4 mm × 4 mm QFN with exposed thermal pad (suffix ES) and a 24-lead TSSOP with exposed thermal pad (suffix LP). These packages are lead (Pb) free, with 100% matte-tin leadframe plating. PACKAGES 24-contact QFN with exposed thermal pad 4 mm × 4 mm × 0.75 mm (ES package) 24-lead TSSOP with exposed thermal pad (LP package) Not to scale VBB 0.1 µF FG SPD FAULT DIR BRK 0.22 µF CP1 CP2 0.1 µF VCP VBB AMT49406 VREG SENN SENP GHx GLx LSS Figure 1: Typical Application AMT49406-DS, Rev. 2 MCO-0000542 June 2, 2020 AMT49406 50 V Code-Free FOC BLDC Motor Controller SELECTION GUIDE Part Number Ambient Temperature Range (TA) (°C) Packaging Packing AMT49406GESSR –40 to 105 24-contact QFN with exposed thermal pad 6000 pieces per 13-inch reel AMT49406GLPTR –40 to 105 24-lead TSSOP with exposed thermal pad 4000 pieces per 13-inch reel ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Notes Supply Voltage VBB Logic Input Voltage Range VIN SPD, BRAKE, DIR Logic Output VO FG (I < 5 mA) LSS VLSS VREG VREG SENN, SENP VSENN, VSENP Output Voltage VOUT GHx VGHx GLx VCP DC tW < 500 ns DC tW < 500 ns SA, SB, SC Rating Unit 50 V –0.3 to 6 V 6 V ±500 mV ±4 V 0 to 4 V ±500 mV ±4 V –2 to VBB + 2 V VSx – 0.3 to VCP + 0.3 V VGLx VLSS – 0.3 to 8.5 V VCP VBB – 0.3 to VBB + 8 V CP1 VCP1  – 0.3 to VBB + 0.3 V CP2 VCP2 VBB – 0.3 to VCP + 0.3 V Junction Temperature TJ 150 °C Storage Temperature Range Tstg –55 to 150 °C Operating Temperature Range TA –40 to 105 °C Range G THERMAL CHARACTERISTICS Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* Value Unit 24-contact QFN (package ES), on 2-sided PCB 1-in.2 copper 45 °C/W 24-lead TSSOP (package LP), on 2-sided PCB 1-in.2 copper 36 °C/W *Additional thermal information available on the Allegro website. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 AMT49406 50 V Code-Free FOC BLDC Motor Controller 19 VREG 20 SPD 21 DIR 22 FAULT 23 FG 24 SENN PINOUT DIAGRAMS AND TERMINAL LIST TABLE CP2 1 24 VBB CP1 2 23 VCP SENP 1 18 BRAKE GND 2 17 CP1 VREG 4 GLA 3 16 CP2 SPD 5 GLB 4 15 VBB DIR 6 GLC 5 14 VCP FAULT 7 LSS 6 13 NC 21 GHC 20 SC PAD 19 GHB 18 SB 17 GHA FG 8 GHC 12 SC 11 GHB 10 9 SB SA 7 GHA 8 PAD 22 NC BRAKE 3 SENN 9 16 SA SENP 10 15 LSS GND 11 14 GLC GLA 12 13 GLB ES Package Pinouts LP Package Pinouts Terminal List Table Terminal Number Name Function ES Package LP Package 16 1 CP2 Charge pump 17 2 CP1 Charge pump 18 3 BRAKE Logic input 19 4 VREG 2.8 V regulator voltage 20 5 SPD PWM or clock mode speed control 21 6 DIR Direction control 22 7 FAULT 23 8 FG 24 9 SENN Current sense negative terminal 1 10 SENP Current sense positive terminal 2 11 GND Ground 3 12 GLA Low-side gate drive output 4 13 GLB Low-side gate drive output 5 14 GLC Low-side gate drive output 6 15 LSS Low-side source 7 16 SA 8 17 GHA 9 18 SB 10 19 GHB Fault indicator output Motor speed output Motor output High-side gate drive output Motor output High-side gate drive output 11 20 SC 12 21 GHC Motor output 13 22 NC No connect 14 23 VCP Charge pump 15 24 VBB Power supply PAD PAD PAD Exposed pad for enhanced thermal dissipation High-side gate drive output Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 AMT49406 50 V Code-Free FOC BLDC Motor Controller ELECTRICAL CHARACTERISTICS [1]: Valid over operating ambient temperature range and operating voltage range, unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Unit Driving 5.5 – 48 V Operating 5.5 – 50 V – 8 12 mA GENERAL Supply Voltage Range VBB Supply Current Reference Voltage VBB IBB VREG IVREG = 0 mA Standby mode – 10 20 µA IOUT = 10 mA 2.7 2.86 2.95 V VBB = 8 V 6.5 6.8 – V VBB = 24 V 6.5 6.8 – V VBB = 8 V 6.5 7.3 – V VBB = 24 V 6.5 7.3 – V GATE DRIVE High Side Gate Drive Output VGH Low Side Gate Drive Output VGL Gate Drive Source Current ISO – 55 – mA Gate Drive Sink Current ISI – 105 – mA 0.5 % MOTOR DRIVE PWM Duty On Threshold PWMON Relative to target –0.5 – PWM Duty Off Threshold PWMOFF Relative to target –0.5 – 0.5 % PWM input frequency setting = 0 2.5 – 100 kHz PWM input frequency setting = 1 80 – 3200 Hz CLOCK mode 1 – 2000 Hz PWM Input Frequency Range fPWM(MIN) Clock Input Frequency Range fCLOCK SPD Standby Threshold (Analog Enter) VSPD(TH_ENT) 50 100 150 mV SPD Standby Threshold (Analog Exit) VSPD(TH_EXIT) 0.4 0.75 1 V 210 250 290 mV SPD On Threshold SPD Max VSPD(ON) ON/OFF setting = 10% VSPD(MAX) – 2.5 – V SPD ADC Resolution VSPDADC(RES) – 9.78 – mV SPD ADC Accuracy VSPDADC(ACC) VSPD = 0.2 to 2.5 V –40 – 40 mV PWM mode or Analog mode –5 – 5 % rpm Speed Closed Loop Accuracy fSPD(ACC) –0.1 – 0.1 tDT Code = 9 – 400 – ns fPWM TA = 25°C 23.3 24.4 25.4 kHz VBB UVLO VBB(UVLO) VBB rising – 4.75 4.95 V VBB UVLO Hysteresis VBB(HYS) Dead Time Motor PWM Frequency Clock mode PROTECTION Thermal Shutdown Temperature Thermal Shutdown Hysteresis 200 300 450 mV TJTSD Temperature increasing – 165 – °C ΔTJ Recovery = TJTSD – ΔTJ – 20 – °C Continued on next page... Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 AMT49406 50 V Code-Free FOC BLDC Motor Controller ELECTRICAL CHARACTERISTICS [1] (continued): Valid over operating ambient temperature range and operating voltage range, unless noted otherwise Characteristics LOGIC, IO, Symbol Test Conditions Min. Typ. Max. Unit SPD, FG; VIN = 0 to 5.5 V –5 1 5 µA BRK, DIR; VIN = 5 V – 50 – µA 0 – 0.8 V  I2C Input Current IIN Logic Input, Low Level VIL Logic Input, High Level VIH 2 – 5.5 V Logic Input Hysteresis VHYS 200 300 600 mV – – 1 µA FG Output Leakage [1] Specified IFG V = 5.5 V limits are tested at 25°C and 125°C and statistically assured over operating temperature range by design and characterization. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 AMT49406 50 V Code-Free FOC BLDC Motor Controller FUNCTIONAL DESCRIPTION The AMT49406 is a three-phase BLDC controller with integrated gate driver. It operates from 5.5 to 50 V and targets pedestal fan, ceiling fan, and ventilation fan applications. The integrated field-oriented control (FOC) algorithm achieves the best efficiency and dynamic response and minimizes acoustic noise. Allegro’s proprietary non-reverse startup algorithm improves startup performance. The motor will start up towards the target direction after power-up without reverse shaking or vibration. The Soft-On Soft-Off (SOSO) feature gradually increases the current to the motor at “on” command (windmill condition), and gradually reduces the current from the motor at the “off” command, further reducing the acoustic noise and operating the motor smoothly. PWM Mode: The motor speed is controlled by the PWM duty cycle on the SPD pin, and higher duty cycle represents higher speed demand. If closed-loop speed is disabled, the output amplitude will be proportional to the PWM duty cycle. If closed-loop speed is enabled, the motor speed is proportional to the PWM duty cycle, and 100% duty represents the rated speed of the motor, which can be programmed in the EEPROM. close_loop_speed = rated_speed × duty_input The SPD PWM frequency range is 80 Hz to 100 kHz. If it is higher than 2.8 kHz, set PWMfreq = 0; if it is lower than 2.8 kHz, set PWMfreq = 1. Analog Mode: The motor speed is controlled by the analog voltage on the SPD pin, with higher voltage representing higher speed demand. If closed-loop speed is disabled, the output amplitude will be proportional to the analog voltage input. If closedloop speed is enabled, the motor speed is as follows: closed_loop_speed = rated_speed × analog_input / SPDMAX CLOCK Mode: In the clock speed control mode, the closedloop speed is always enabled. Higher frequency on the SPD pin will drive a higher motor speed as follows: close_loop_speed (rpm) = clock_input × speed_ctrl_ratio, Figure 2: Current Waveform of Soft-On where the speed_ctrl_ratio can be programmed in the EEPROM. For example, if the ratio is 4 and the clock input frequency is 60 Hz, then the motor will operate at 240 rpm. Note the number of motor pole pairs must be set properly in the programming application for the rated speed (rpm) setting to be accurate. If the clock frequency commands a speed that is higher than twice the rated speed, the AMT49406 treats it as a clock input error and stops the motor. Figure 3: Current Waveform of Soft-Off Speed Control Speed demand is provided via the SPD pin. Three speed control modes are selectable through the EEPROM. The AMT49406 also features a closed-loop speed function, which can be enabled or disabled via the EEPROM. For all three speed control modes with closed-loop speed enabled, if the demand speed is higher than the maximum speed, the system can run at a certain supply voltage and load condition, and the AMT49406 will just provide the maximum output voltage (if current limit is not triggered) or the maximum output current (if current limit is triggered). The SPD pin is also used as SCL in the I2C mode. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 AMT49406 50 V Code-Free FOC BLDC Motor Controller Motor Stop and Standby Mode If the speed demand is less than the programmed threshold, the motor will stop. On/Off Setting On Threshold Off Threshold 6% 7.8% 5.9% 10% 11.7% 9.8% 15% 14.9% 12.9% 20% 21.5% 19.6% For example, consider 10% is set as the threshold. If PWM duty is less than 9.8% (in PWM mode), or the analog voltage is less than 250 mV (in Analog mode), or the CLOCK input frequency is less than 9.8% of the “rated_speed” (in CLOCK mode), the IC will stop the motor and enter the “idle” mode. In order to enter standby, two conditions must be met: 1) the motor must be stationary, and 2) PWM or CLOCK signal must remains logic low (in PWM and CLOCK mode) or the analog voltage remains less than VSPD(TH_ENT) (in Analog mode) for longer than one second. A rising edge on PWM or CLOCK will wake the IC in PWM and CLOCK mode, and in Analog mode, the SPD voltage must be higher than VSPD(TH_EXIT) to wake up the IC. Standby Mode will turn off all circuitry including the charge pump and VREG. After powering on, the device will always be in the active mode before entering standby mode. FAULT: Open-drain output provides motor operation fault status. Default is high when there is no fault. An LED and a serial resistor is recommended between the FAULT and VREG pins. The LED indicates fault information. VREG FAULT Figure 4: AMT49406 with LED and Serial Resistor Fault Type FAULT Pin LED Pattern Lock detected low constant on OCP 0.67 seconds high 0.67 seconds low slow flashing OTP 0.67 seconds low 0.17 seconds high 0.08 seconds low 0.17 seconds high 0.08 seconds low 0.17 seconds high long-short-short flashing system error 0.08 seconds low 0.08 seconds high 0.08 seconds low 1.09 seconds high double short flashing OVP 0.17 seconds high 0.17 seconds low fast flashing zero speed demand 0.25 seconds high 0.08 seconds low 0.34 seconds high 0.67 seconds low long-short flashing The standby mode can be disabled in the EEPROM. Direction Input: Logic input to control motor direction. For logic high, the motor phases are ordered A→B→C. For logic low, the motor phases are ordered A→C→B. The AMT49406 supports changing the direction input while the motor is running. The direction can also be controlled through register. BRAKE: Active-high signal turns on all low sides for braking function. The Brake function overrides speed control input. Care should be taken to avoid stress on the MOSFET when braking while the motor is running. With braking, the current will be limited only by VBEMF/RMOTOR. The AMT49406 includes an optional feature which holds off braking until the motor speed drops to a low enough (configurable) level so that the braking current will not damage the MOSFET. FG: Open-drain output provides motor speed information to the system. The open-drain output can be pulled up to VREG or an external 3.3 or 5 V supply. The FG pin is also used as SDA in I2C mode. The first I2C command can pass only when the FG is high (open drain off). After the first I2C command, the FG pin is no longer used for speed information, and the FG pin is dedicated as a data pin for the I2C interface. FG is default high after power-on and exit from standby mode, and stays high for at least 9.8 ms. To ensure successful I2C communication, it is recommended to have the first I2C demand right after power-up or exit from standby mode within 9.8 ms. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 AMT49406 50 V Code-Free FOC BLDC Motor Controller VREG: Voltage reference (2.8 V) to power internal digital logic and analog circuitry. VREG can be used to power external circuitry with up to 10 mA bias current, if desired. A ceramic capacitor with 0.22 µF or greater is required on the pin to stabilize the supply. When VREG is loaded externally, the power consumption of the internal LDO is calculated by the equation: PLDO = (ILOAD + IINTERNAL) × (VBB – VREG). Ensure that the system has good power dissipation and the temperature is within the operating temperature range. The AMT49406 thermal shutdown function does not protect the LDO. Bus Current Sensing: A single shunt-resistor connection between SENN and SENP is used to measure the bus current for the FOC algorithm and current limit. The resistor value is approximately tens of a milliohm, depends on the rated current of the system. The voltage difference between SENN and SENP should be less than 65 mV to prevent the signal saturation. For example, if the rated current is 4 A, it is recommend to use a 15 mΩ sensing resistor, so that 4 A × 15 mΩ is between 55 and 65 mV. Use Kelvin sensing connection for the shunt resistor. Lock Detect: A logic circuit monitors the motor position to determine if motor is running as expected. If a fault is detected, the motor drive will be disabled for the configurable tLOCK time before an auto-restart is attempted. For additional information, refer to the configuration guide. Current Control: The motor’s rated current at rated speed and normal load must be programmed to the EEPROM for proper operation. The AMT49406 will limit the motor current (phase current peak value) to 1.3 times the programmed rated current during acceleration or increasing load, which protects the IC and the motor. The current profile during startup can also be programmed. Overcurrent Protection (short protection): The VDS voltages across each power MOSFET are monitored by the AMT49406. If a VDS is higher than the threshold when that MOSFET enabled, an OCP fault is triggered and the IC will stop driving immediately. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 AMT49406 50 V Code-Free FOC BLDC Motor Controller I2C OPERATION AND EEPROM MAP The I2C interface allows the user to program the register and parameters into EEPROM. The AMT49406 7-bit slave address is 0x55. After power-on, the default values in EEPROM will be loaded into the registers, which determines motor system operation. I2C can overwrite those values and change the motor system operation on the fly. I2C Writing the EEPROM I2C Overwrite Power-On Load EEPROM Register I2C can also be used to program the EEPROM, which is normally done in the production line. The figures below shows the I2C interface timing. from slave device Slave Address START SDA A6 A5 A4 A3 A2 A1 from slave device Register Address STOP A0 W ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK SCL Slave Address START SDA A6 A5 A4 A3 A2 A1 A0 from slave device R Data Byte 2 from master device Data Byte 2 no ACK from master device STOP ACK D15 D14 D13 D12 D11 D10 D9 D8 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL Figure 5: Read Command Slave Address START SDA A6 A5 A4 A3 A2 A1 from slave device Register Address from slave device Data Byte 2 from slave device Data Byte 1 A0 W ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK D15 D14 D13 D12 D11 D10 D9 D8 ACK D7 D6 D5 D4 from slave device STOP D3 D2 D1 D0 ACK SCL Figure 6: Write Command Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 AMT49406 50 V Code-Free FOC BLDC Motor Controller Register and EEPROM Map Each register bit is associated with one EEPROM bit. The register address is the associated EEPROM bit address plus 64. For example, the rated speed is in EEPROM address 8, bit[10:0]; the associated register address is 72, bit[10:0]. a custom programmer, it is recommended to use the AMT49406 application to determine the appropriate settings, save the settings file, and use the file contents to program to the EEPROM. The application’s settings file contains one line for each EEPROM address, containing addresses 8 through 22 (15 lines/addresses). In the following table, the bits shaded in gray should be kept at their default values. Changing these values may cause malfunction or damage to the part. If programming the EEPROM with Registers not shown in the table are not for users to access. Changing the value in undocumented registers may cause malfunction or damage to the part. Table 1: Register and EEPROM Map Address AMT49406 Register Map 0 1 2 Allegro internal information. No associated register for these EEPROM data 3 4 5 6 User-flexible code. No associated register for these EEPROM data. Provided to user. For example, tracking number of product, product revision info, etc. 7 3:0 8 / 72 Rated_speed [3:0] 7:4 Rated_speed [7:4] 11:8 speed_close_loop 15:12 PWMin_range Rated speed [10:8] Direction 3:0 9 / 73 10 / 74 7:4 Acceleration [7:4] 11:8 Motor_Resistance [3:0] 15:12 Motor_Resistance [7:4] 3:0 Rated Current [3:0] 7:4 Rated Current [7:4] 11:8 SPD mode Clock_PWM Rated Current [10:8] 15:12 11 / 75 Accelerate_range Acceleration [3:0] Startup_Current [2:0] 3:0 Open_Drive 7:4 Power_Ctl_En 11:8 open_ph_protect Startup_mode [1:0] 15:12 3:0 12 / 76 PID_P [3:0] 7:4 PID_P [7:4] 11:8 Motor_Inductance [3:0] 15:12 Open_Window over_Speed_Lock Motor_Inductance [4] Continued on next page... Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 AMT49406 50 V Code-Free FOC BLDC Motor Controller Table 1: Register and EEPROM Map (continued) Address 13 / 77 AMT49406 Register Map 3:0 PID_I [3:0] 7:4 PID_I [7:4] 11:8 15:12 delay_start 3:0 14 / 78 7:4 11:8 15:12 3:0 15 / 79 7:4 Angle_Error_Lock (startup) soft_on Deadtime_setting [3:0] 15:12 3:0 16 / 80 soft_off 11:8 Safe_Brake_thrd [1:0] OCP_reset_mode OCP_Enable 7:4 First_cycle_speed [1:0] 11:8 Decelerate_buffer [1:0] Accelerate_buffer [1:0] 15:12 17 / 81 BEMF_Lock_filter [1:0] 8:0 Speed_demand [8:0] 9 i2c_speed_mode 15:10 3:0 18 / 82 7:4 11:8 IPD_Current_Thr [3:0] 15:12 19 / 83 20 / 84 IPD_Current_Thr [5:4] 7:0 15:8 7:0 Rated_Voltage 15:8 Sense_Resistor 3:0 21 / 85 7:4 slight_mv_demand [2:0] 11:8 15:12 speed_input_off_threshold [1:0] standby_dis 3:0 22 / 86 speed close loop parameter 7:4 11:8 Restart_attempt Lock_restart_set speed close loop parameter vibration_lock Brake_mode 15:12 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 AMT49406 50 V Code-Free FOC BLDC Motor Controller Table 2: Register and EEPROM Map Notes Parameter Address Notes Rated_Voltage 20 [7:0] Rated Voltage (V) = Rated_voltage_register_value / 5 Rated_Speed 8 [10:0] Rated Speed (Hz) = Rated_speed_register_value × 0.530 Motor_Resistance 9 [15:8] Motor Resistance (Ω) = Motor_resistance_register_value / [ (Rated_voltage_register_value × 4.096) / (Sense_resistor_register_value / 125) / (Rated_voltage_register_value / 10) ] Rated_Current 10 [10:0] Rated Current (mA) = Rated_current_register_value / (Sense_resistor_register_value / 125) Startup_Current 10 [15:13] 0: NA. Acceleration 9 [7:0] Accelerate_range 8 [13] else Startup Current = Rated Current × 1/8 × (startup_current_register_value + 1) Acceleration (Hz/s) = Acceleration_register_value × k if range = 0 then k = 0.05, else k = 3.2 speed_close_loop 8 [11] 1: closed loop. 0: open loop. Direction 8 [14] 1: A→B→C. 0: A→C→B. SPD mode 10 [11] 1: analog 0: digital (PWM or Clock). Clock_PWM 8 [12] 1: clock mode. 0: PWM mode. PWMin_range 8 [15] 1: ≤ 2.8 kHz 0: > 2.8 kHz. clock_speed_ratio 22 [5:0] Speed_input_off_threshold 21 [9:8] Ratio (rpm/Hz) = clock_speed_ratio_value × 0.25. clock_speed_ratio maximum value is 42. 00: 10%. 01: 6% 10: 15%. 11: 20% 00: 6 pulse mode. 01: 2 pulse mode. 10: slight-move mode. 11: align & go. Startup_mode 11 [11:10] IPD_current_thrd 18 [13:8] IPD current threshold (A) = IPD_current_thrd_value × 0.086 Slight_mv_demand 21 [7:5] Amplitude demand in slight move mode (%) = value × 3.2 + 2.4 PID_P 12 [7:0] Position observer loop P gain. PID_I 13 [7:0] Position observer loop I gain. Motor_Inductance 12 [12:8] Refer to the configuration guide. Sense_Resistor 20 [15:8] Sense resistor value (mΩ) = sense_resistor_value / 3.7 Open_drive 11 [3] Refer to the configuration guild. Power_Ctrl_En 11 [7] 1: enable the current limit. Open_window 12 [15] 1: open window for inductance tuning. 0: normal delay_start 13[14] 1: delayed start. 0: start right after windmill checking. Soft_off 15 [6] Refer to the functional description. Soft_on 15 [7] Refer to the functional description. First_Cycle_Speed 16 [7:6] 00: 0.55 Hz. Accelerate_buffer 16 [9:8] Refer to the configuration guide. Decelerate_buffer 16 [11:10] Refer to the configuration guide. Deadtime_setting 15[11:8] (n + 1) × 40 ns. Standby_mode 21 [15] 0: enable. 1: disable. Brake_mode Safe_brake_thrd OCP_reset_mode 01: 1.1 Hz. 22 [8] 0: brake when safe. 1: 100% uncontrolled 15 [15:14] 00: 1× rated current. 01: 2×. 16 [3] 0: upon motor restart. 1: after 5 seconds. 10: 2.2 Hz. 11: 4.4 Hz 10: 4×. 11: 8×. Continued on next page... Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12 AMT49406 50 V Code-Free FOC BLDC Motor Controller Table 2: Register and EEPROM Map Notes (continued) Parameter OCP_Enable Address 16 [2:0] Notes 100: 480 ns filter. 111: OCP disabled. Lock detect during startup. Angle_Error_Lock 15 [3:2] BEMF_lock_filter 16 [13:12] Refer to the configuration guide. Open_ph_protect 11 [4] Refer to the configuration guide. Vibration_lock 22 [10] Refer to the configuration guide. Over_speed_lock 12 [13] Refer to the configuration guide. Restart_attempt 22 [7:6] 00: Always. 01: 3 times. Lock_restart_set 22 [11] 0: 5 seconds. 1: 10 seconds. 17 [9] 0: controlled by SPD pin. i2c_spd_mode i2c_spd_demand 17 [8:0] 00: disabled. 01: 5 degrees. 10: 9 degrees. 11: 13 degrees 10: 5 times. 11: 10 times. 1: controlled by register value in 17 [8:0]. 0~511 represents 0~100% READBACK Motor speed 120 Motor Speed (Hz) = register_value × 0.530 Hz Bus current 121 Bus current (mA) = register_value / (Sense_resistor_register_value / 125) Q-axis current 122 Q-axis current (mA) = register_value / (Sense_resistor_register_value / 125) VBB 123 VBB (V) = register_value / 5 Temperature 124 Temperature (°C) = register_value – 53 Control demand 125 0~511 represents 0~100% 126 0~511 represents 0~100% Control command Operation state 127 [15:12] Note: Refer to application note and user interface for additional detail. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 13 AMT49406 50 V Code-Free FOC BLDC Motor Controller Programming EEPROM The AMT49406 contains 24 words of EEPROM, each of 16 bit length. The EEPROM is controlled with the following I2C registers. EEPROM Control – Register 161: Used to control programming of EEPROM Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name 0 0 0 0 0 0 0 0 0 0 0 0 RD WR ER EN 4 3 2 1 0 Bit Name Description 0 EN Set EEPROM voltage required for Writing or Erasing. 1 ER Sets Mode to Erase. 2 WR Sets Mode to Write. 3 RD Sets Mode to Read. 15:4 n/a Do not use; always set to zero (0) during programming process. EEPROM Address – Register 162: Used to set the EEPROM address to be altered Bit 15 14 13 12 11 10 9 8 7 6 5 Name 0 0 0 0 0 0 0 0 0 0 0 Bit Name 0:4 eeADDRESS 15:5 n/a eeADDRESS Description Used to specify EEPROM address to be changed. There are 20 addresses. Do not change address 0 or 19 as these are factory-controlled. Do not use; always set to zero (0) during programming process. EEPROM Data_In – Register 163: Used to set the EEPROM new data to be programmed Bit 15 14 Name 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eeDATAin Bit Name 15:0 eeDATAin Description Used to specify the new EEPROM data to be changed. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 14 AMT49406 50 V Code-Free FOC BLDC Motor Controller EEPROM Commands There are three basic commands, Read, Erase, and Write. To change the contents of a memory location, the word must be first erased. The EEPROM programming process (writing or erasing) takes 10 ms per word. Each word must be written individually. The following examples are shown in the following format: I2C_register_address [data] ; comment Example #1: Write EEPROM address 7 to 261 (hex = 0x0105) 1. Erase the existing data. 2. Write the new data. A. 162 [7] ; set EEPROM address to write. B. 163 [261] ; set Data_In = 261. C. 161 [5] ; set control to Write and Set Voltage High. D. Wait 15 ms ; requires 15 ms High Voltage Pulse to Write. E. 161 [0] ; clear Voltage. Example #2: Read address 7 to confirm correct data properly programmed. 1. Read the word. A. 7 [N/A for read] ; read register 7; this will be contents of EEPROM. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 15 AMT49406 50 V Code-Free FOC BLDC Motor Controller PIN DIAGRAMS DIR VBB 2 kΩ BRAKE 100 kΩ 10 V 56 V 6.5 V 8V VCP 2 kΩ SPD 10 V GHx 6.5 V 10 V Sx FG FAULTn VBB 10 V VBB VREGINT (internal regulator) 8V GLx LSS VREG 6V CP2 VCP SENP VBB CP1 VBB SENN 6V 6V 7V Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 16 AMT49406 50 V Code-Free FOC BLDC Motor Controller PACKAGE OUTLINE DRAWING For Reference Only – Not for Tooling Use Reference Allegro DWG-2871 (Rev. A) or JEDEC MO-220WGGD-11. Dimensions in millimeters – NOT TO SCALE. Exact case and lead configuration at supplier discretion within limits shown. 0.50 0.30 4.00 ±0.15 24 24 1 2 0.95 1 2 A 4.00 ±0.15 2.70 4.10 2.70 25× D C 0.75 ±0.05 0.08 C +0.05 0.25 –0.07 SEATING PLANE 4.10 C PCB Layout Reference View 0.05 0.00 0.50 0.40 ±0.10 A B 2.60 +0.10 –0.15 B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-25W6M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals 2 1 24 2.60 Terminal #1 mark area +0.10 –0.15 Figure 7: Package ES, 24-Contact QFN with Exposed Pad Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 17 AMT49406 50 V Code-Free FOC BLDC Motor Controller For Reference Only – Not for Tooling Use (Reference MO-153 ADT) NOT TO SCALE Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 7.80 ±0.10 4.32 NOM 8º 0º 24 0.20 0.09 B 3 NOM 4.40±0.10 6.40±0.20 A 0.60 ±0.15 1.00 REF 1 2 0.25 BSC 24X 1.20 MAX 0.10 C 0.30 0.19 0.65 BSC 0.45 SEATING PLANE C GAUGE PLANE SEATING PLANE 0.15 0.00 XXXXXXXXX Date Code Lot Number 0.65 1 D Standard Branding Reference View Lines 1, 2, 3: Maximum 9 characters per line 1.65 Line 1: Part number Line 2: Logo A, 4-digit date code Line 3: Characters 5, 6, 7, 8 of Assembly Lot Number 3.00 4.32 C 6.10 A Terminal #1 mark area B Exposed thermal pad (bottom surface); dimensions may vary with device C Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Branding scale and appearance at supplier discretion PCB Layout Reference View Figure 8: Package LP, 24-Lead TSSOP with Exposed Pad Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 18 AMT49406 50 V Code-Free FOC BLDC Motor Controller Revision History Number Date Description – December 13, 2018 1 January 24, 2019 2 June 2, 2020 Initial release Updated Motor PWM Frequency (page 4) Corrected delay_start address (page 12) and minor editorial updates Copyright 2020, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 19