N04L1630C2BT2

AMI Semiconductor, Inc. ULP Memory Solutions 670 North McCarthy Blvd. Suite 220 Milpitas, CA 95035 PH: 408-935-7777, FAX: 408-935-7770 N04L1630C2B Advance Information 4Mb Ultra-Low Power Asynchronous CMOS SRAMs 256K × 16 bit POWER SAVER TECHNOLOGY TM Overview The N04L1630C2B is an integrated memory device containing a 4 Mbit Static Random Access Memory organized as 262,144 words by 16 bits. The device is designed and fabricated using AMI Semiconductor’s advanced CMOS technology to provide both high-speed performance and ultra-low power. The device operates with two chip enable (CE1 and CE2) controls and output enable (OE) to allow for easy memory expansion. Byte controls (UB and LB) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. The N04L1630C2B is optimized for the ultimate in low power and is suited for various applications where ultra-lowpower is critical such as medical applications, battery backup and power sensitive hand-held devices. The unique page mode operation saves operating power while improving the performance over standard SRAMs. The device can operate over a very wide temperature range of -40oC to +85oC and is available in JEDEC standard packages compatible with other standard 256Kb x 16 SRAMs. Features • Wide Power Supply Range 2.7 to 3.6 Volts • Very low standby current 1uA (Typical) • Very low operating current 2.0mA at 1µs (Typical) • Very low Page Mode operating current 0.8mA at 1µs (Typical) • Simple memory control Dual Chip Enables (CE1 and CE2) Byte control for independent byte operation Output Enable (OE) for memory expansion • Very fast output enable access time 30ns OE Access Time 55ns Random Access Time 30ns Page Mode Access Time • Automatic power down to standby mode • TTL compatible three-state output driver • RoHS Compliant TSOP and BGA packages Product Family Part Number N04L1630C2BB2 Package Type 48-BGA Green Operating Temperature -40oC to +85oC Power Supply (Vcc) 2.7V - 3.6V Speed Options 55ns 70ns Standby Operating Current (ISB), Current (Icc), Typical Typical 1µA 2 mA @ 1MHz N04L1630C2BT2 44-TSOP II Green (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. 1 N04L1630C2B AMI Semiconductor, Inc. Pin Configurations (4Mb) A4 A3 A2 A1 A0 CE1 I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PIN ONE 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 CE2 A8 A9 A10 A11 A17 Advance Information 1 A B C D E F G H LB I/O8 I/O9 VSS VCC 2 OE UB I/O10 I/O11 I/O12 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 VCC VSS I/O6 I/O7 NC I/O14 I/O13 I/O15 NC NC A8 48 Pin BGA (top) TSOP II Pin Descriptions Pin Name A0-A17 WE CE1 CE2 OE LB UB I/O0-I/O7 I/O8-I/O15 VCC VSS NC Pin Function Address Inputs Write Enable Input Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Lower Byte Enable Input Upper Byte Enable Input Lower Byte Data Input/Output Upper Byte Data Input/Output Power Ground Not Connected (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Functional Block Diagram Advance Information Address Inputs A1 - A4 Word Address Decode Logic Address Inputs A0, A5 - A17 CE1 CE2 WE OE UB LB Page Address Decode Logic 16K Page x 16 word x 16 bit RAM Array Input/ Output I/O0 - I/O7 Mux and Buffers I/O8 - I/O15 Word Mux Control Logic Functional Description CE1 H X L L L L CE2 X L H H H H WE X X X L H H OE X X X X3 L H UB X X H L 1 LB X X H L 1 I/O0 - I/O151 High Z High Z High Z Data In Data Out High Z MODE Standby2 Standby2 Standby Write3 Read Active POWER Standby Standby Standby Active Active Active L1 L1 L1 L 1 1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. 2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. Capacitance1 Item Input Capacitance I/O Capacitance Symbol CIN CI/O Test Condition VIN = 0V, f = 1 MHz, TA = 25oC VIN = 0V, f = 1 MHz, TA = 25oC Min Max 8 8 Unit pF pF 1. These parameters are verified in device characterization and are not 100% tested (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Absolute Maximum Ratings1 Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Soldering Temperature and Time Symbol VIN,OUT VCC PD TSTG TA TSOLDER Rating –0.3 to VCC+0.3 –0.3 to 4.5 500 –40 to 125 -40 to +85 260oC, 10sec Unit V V mW o Advance Information C oC oC 1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Characteristics (Over Specified Temperature Range) Item Supply Voltage Data Retention Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply Current @ 1 µs Cycle Time2 Read/Write Operating Supply Current @ 70 ns Cycle Time2 Page Mode Operating Supply Current @ 70ns Cycle Time2 (Refer to Power Savings with Page Mode Operation) Maximum Standby Current3 Symbol VCC VDR VIH VIL VOH VOL ILI ILO ICC1 ICC2 ICC3 IOH = -100uA IOH = -1mA IOL = 100uA IOL = 2.1mA VIN = 0 to VCC OE = VIH or Chip Disabled VCC=VCCMax, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=VCCMax, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=VCCMax, VIN=VIH or VIL Chip Enabled, IOUT = 0 VIN = VCC or 0V Chip Disabled tA= 85oC, VCC = 3.6 V Vcc = 1.8V, VIN = VCC or 0 Chip Disabled, tA= 85oC 2.5 10 Chip Disabled3 Test Conditions Min. 2.7 1.8 0.7Vcc –0.3 VCC–0.2 2.4 0.2 0.4 0.5 0.5 3.0 15.0 µA µA mA mA VCC+0.3 0.6 Typ1 3.0 Max 3.6 Unit V V V V V V V 4 8 mA ISB1 1 10.0 µA Maximum Data Retention Current3 IDR 5 µA 1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS. (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Power Savings with Page Mode Operation (WE = VIH) Advance Information Page Address (A0, A5 - A17) Open page ... Word Address (A1 - A4) Word 1 Word 2 Word 16 CE1 CE2 OE LB, UB Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power saving feature. The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open and 16-bit words of data are read from the open page. By treating addresses A1-A4 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power SRAMs. (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Timing Test Conditions Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load Operating Temperature 0.1VCC to 0.9 VCC 5ns 0.5 VCC CL = 30pF -40 to +85 oC Advance Information Timing Item Read Cycle Time Address Access Time Page Mode Address Access Time Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output Chip Enable to Low-Z output Output Enable to Low-Z Output Byte Select to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Byte Select Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Byte Select to End of Write Write Pulse Width Address Setup Time Write Recovery Time Write to High-Z Output Data to Write Time Overlap Data Hold from Write Time End Write to Low-Z Output Symbol tRC tAA tAAP tCO tOE tBE tLZ tOLZ tBZ tHZ tOHZ tBHZ tOH tWC tCW tAW tBW tWP tAS tWR tWHZ tDW tDH tOW 40 0 5 10 5 10 0 0 0 10 55 45 45 45 40 0 0 20 40 0 5 20 20 20 -55 Min. 55 55 30 55 30 55 10 5 10 0 0 0 10 70 50 50 50 40 0 0 20 20 20 20 Max. Min. 70 70 35 70 35 70 -70 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Timing of Read Cycle (CE1 = OE = VIL, WE = CE2 = VIH) tRC Address tAA tOH Advance Information Data Out Previous Data Valid Data Valid Timing Waveform of Read Cycle (WE=VIH) tRC Address tAA tHZ CE1 tCO CE2 tLZ tOE OE tOLZ tBE LB, UB tBLZ Data Out High-Z tBHZ Data Valid tOHZ (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Timing Waveform of Page Mode Read Cycle (WE = VIH) tRC Page Address (A0, A5 - A17) tAA Word Address (A1 - A4) tHZ CE1 tCO CE2 tOHZ tAAP Advance Information tOE OE tOLZ LB, UB tBLZ High-Z tBE tBHZ Data Out (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Timing Waveform of Write Cycle (WE control) tWC Address tAW CE1 tCW CE2 tBW LB, UB tAS WE tDW High-Z Data In tWHZ Data Out High-Z tDH tWP tWR Advance Information Data Valid tOW Timing Waveform of Write Cycle (CE1 Control) tWC Address tAW CE1 (for CE2 Control, use inverted signal) LB, UB tWP WE tDW Data In tLZ Data Out tWHZ tDH tCW tAS tBW tWR Data Valid High-Z (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. 44-Lead TSOP II Package (T44) Advance Information 18.41±0.13 10.16±0.13 11.76±0.20 0.80mm REF 0.45 0.30 SEE DETAIL B DETAIL B 1.10±0.15 0o-8o 0.20 0.00 0.80mm REF Note: 1. All dimensions in inches (Millimeters) (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Ball Grid Array Package A1 BALL PAD CORNER (3) D 0.28±0.05 1.24±0.10 1. 0.35±0.05 DIA. E 2. SEATING PLANE - Z 0.15 Z 0.05 TOP VIEW SIDE VIEW 1. DIMENSION IS MEASURED AT THE A1 BALL PAD MAXIMUM SOLDER BALL DIAMETER. CORNER PARALLEL TO PRIMARY Z. 2. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. A1 BALL PAD CORNER I.D. TO BE MARKED BY INK. K TYP J TYP e Z Advance Information SD e SE BOTTOM VIEW (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. N04L1630C2B AMI Semiconductor, Inc. Ordering Information Advance Information N04L1630C2BX-XX I Performance 55 = 55ns 70 = 70ns Package Type B2 = 48-ball BGA Green (RoHS Compliant) T2 = 44-pin TSOP II Green (RoHS Compliant) Revision History Revision A B C D E F G H I Date April 2003 August 2004 January 2005 January 2005 March 22, 2005 June 9, 2005 Dec. 2005 July 2006 September 2006 Change Description Initial Advanced Release Changed part number to -30 from -3W and Vcc range to 2.7 V - 3.6V Change IDR = 5 µA, ICC(typ) = 2.5mA. Modified page mode address A1-A4 configuration. General Update Changed tWP and tDW to 40ns for -55 and -70, to 45ns for -85 Added TSOP II Green Package Ordering Option Added RoHS Compliant Added BGA package Converted to AMI Semiconductor © 2006 AMI Semiconductor, Inc. All rights reserved. AMI Semiconductor, Inc. ("AMIS") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. AMIS does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications. AMIS makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does AMIS assume any liability arising out of the application or use of any product or circuit described herein. AMIS does not authorize use of its products as critical components in any application in which the failure of the AMIS product may be expected to result in significant injury or death, including life support systems and critical medical instruments. (DOC# 14-02-042 ReI I ECN# 01-1374 The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.