A61L6316V-10

A61L6316 Series 64K X 16 BIT HIGH SPEED CMOS SRAM Document Title 64K X 16 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. 0.0 1.0 History Initial issue Final spec. release Add -10 spec. Change ICC1 from 120mA to 220mA (-12) Change ICC1 from 100mA to 210mA (-15) Change ISB1 from 8mA to 12mA Change ICDR from 1mA to 5mA Add tBE, tBLZ, tBHZ, tBW parameters Issue Date July 14, 2000 May 8, 2001 Remark Preliminary Final 1.1 Add -25°C ~ +85°C grade July 17, 2002 (July, 2002, Version 1.1) AMIC Technology, Inc. A61L6316 Series 64K X 16 BIT HIGH SPEED CMOS SRAM Features n Center power pinout n Supply voltage: -10: 3.3V+10%, -5% -12, -15: 3.3V±10% n Access times: 10/12/15 ns (max.) n Current: Operating: -10: 230mA (max) -12: 220mA (max.) -15: 210mA (max.) Standby: TTL: 25mA (max.) CMOS: 12mA (max.) n Extended operating temperature range: -25°C to 85°C for -I series n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 2V (min.) n Available in 44-pin 400mil SOJ and 44-pin 400mil TSOP(II) forward packages. General Description The A61L6316 is a high speed 1,048,576-bit static random access memory organized as 65,536 words by 16 bits and operates on low power supply voltage from 3.0V to 3.6V. It is built using AMIC’s high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN, to disable the device. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Product Family Product Family A61L6316 Operating Temperature 0°C ~ +70°C -25°C ~ +85°C VCC Range Power Dissipation Speed 10/12/15 ns Data Retention (ICCDR, Typ.) 3mA Standby (ISB1, Typ.) 5mA Package Type 44L SOP 44L TSOP(II) 3.0V ~ 3.6V 1. Typical values are measured at VCC = 3.3V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 2.0V. Pin Configuration n SOJ / TSOP (II) A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A15 A14 A13 OE HB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A12 A11 A10 A9 NC A61L6316S(V) 1 (July, 2002, Version 1.1) AMIC Technology, Inc. A61L6316 Series Block Diagram A0 VCC GND 1,048,576-BIT DECODER A14 MEMORY ARRAY A15 I/O0 COLUMN I/O INPUT DATA CIRCUIT I/O8 INPUT DATA CIRCUIT I/O7 I/O15 CE LB HB OE WE CONTROL CIRCUIT (July, 2002, Version 1.1) 2 AMIC Technology, Inc. A61L6316 Series Pin Description - SOJ/TSOP(II) Pin No. 1 - 5, 18 - 21, 24 - 27,42 - 44 6 7 - 10, 13 - 16, 29 - 32, 35 - 38 17 39 40 41 11, 33 12, 34 22 , 23, 28 Symbol A0 - A15 CE I/O0 - I/O15 WE LB HB OE VCC GND NC Description Address Inputs Chip Enable Input Data Input/Outputs Write Enable Input Byte Enable Input (I/O0 to I/O7) Byte Enable Input (I/O8 to I/O15) Output Enable Input Power Ground No Connection Recommended DC Operating Conditions (TA = 0°C to + 70°C or -25°C to +85°C) Symbol *VCC GND VIH VIL CL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Output Load Min. 3.0 0 2.2 -0.3 Typ. 3.3 0 Max. 3.6 0 VCC + 0.3 0.8 30 Unit V V V V pF * -10 VCCmin: 3.135V (July, 2002, Version 1.1) 3 AMIC Technology, Inc. A61L6316 Series Absolute Maximum Ratings* VCC to GND . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C or -25°C to +85°C Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W Soldering Temp. & Time . . . . . . . . . . . . . 260°C, 10 sec *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = 0°C to + 70°C or -25°C to +85°C, -10: 3.3V+10%, -5%; -12, -15: 3.3V±10%) Symbol Parameter A61L6316-10 Min. ILI ILO Input Leakage Output Leakage Max. 2 2 A61L6316-12 Min. Max. 2 2 A61L6316-15 Min. Max. 2 2 µA µA VIN = GND to VCC CE = VIH, OE = VIH VI/O = GND to VCC CE = VIL, II/O = 0 mA Min. Cycle, Duty = 100% CE = VIH CE ≥ VCC - 0.2V, VIN ≥ VCC -0.2V or VIN ≤ 0.2V IOL = 8 mA IOH = -4 mA Unit Conditions ICC1 (2) ISB Dynamic Operating Current - 230 25 - 220 25 - 210 25 mA mA ISB1 Standby Power Supply Current - 12 - 12 - 12 mA VOL VOH Output Low Voltage Output High Voltage 2.4 0.4 - 2.4 0.4 - 2.4 0.4 - V V Notes: 1. VIL = -3.0V for pulses less than 20 ns. 2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns. (July, 2002, Version 1.1) 4 AMIC Technology, Inc. A61L6316 Series Truth Table CE H OE X WE X LB X L L L H L H L L X L L H L L H H X X X X H L H High - Z Not selected High - Z Not selected ICC1, ICC2, ICC ISB1, ISB HB X L H L L H L X I/O0 to I/O7 Mode Not selected Read Read High - Z Write Write Not Write/Hi - Z High - Z I/O8 to I/O15 Mode Not selected Read High - Z Read Write Not Write/Hi - Z Write High - Z VCC Current ISB1, ISB ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC ICC1, ICC2, ICC Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 6 8 Unit pF pF Conditions VIN = 0V VI/O = 0V * These parameters are sampled and not 100% tested. (July, 2002, Version 1.1) 5 AMIC Technology, Inc. A61L6316 Series AC Characteristics (TA = 0°C to +70°C or -25°C to +85°C, -10: 3.3V+10%, -5%; -12, -15: 3.3V±10%) Symbol Parameter A61L6316-10 Min. Read Cycle tRC tAA tACE tBE tOE tCLZ tOLZ tBLZ tCHZ tBHZ tOHZ tOH Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Output Enable to Output in Low Z Byte Enable to Output in Low Z Chip Disable Output in High Z Byte Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change 10 3 0 0 0 0 0 3 10 10 5 5 5 5 5 12 3 0 0 0 0 0 3 12 12 6 6 6 6 6 15 3 0 0 0 0 3 15 15 8 8 8 8 8 ns ns ns ns ns ns ns ns ns ns ns ns Max. A61L6316-12 Min. Max. A61L6316-15 Min. Max. Unit Write Cycle tWC tCW tBW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Byte Enable to End of Write Address Setup Time of Write Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 10 8 8 0 8 8 0 0 5 0 3 5 12 10 10 0 10 10 0 0 6 0 3 6 15 12 12 0 12 12 0 0 7 0 3 8 ns ns ns ns ns ns ns ns ns ns ns Notes: tCHZ, tBHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. (July, 2002, Version 1.1) 6 AMIC Technology, Inc. A61L6316 Series Timing Waveforms Read Cycle 1 (1, 2, 4) tRC Address tAA tOH tOH DOUT Read Cycle 2 (1, 2, 3) tRC Address tAA CE tACE tCLZ 5 tBE tCHZ 5 HB, LB tBLZ 5 tBHZ 5 OE tOHZ 5 tOE tOLZ 5 DOUT Notes: 1. W E is high for Read Cycle. 2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. (July, 2002, Version 1.1) 7 AMIC Technology, Inc. A61L6316 Series Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) tWC Address tAW tCW CE tWR3 tBW HB, LB tAS1 tWP2 WE tDW DATA IN tWHZ 4 tDH tOW DATA OUT (July, 2002, Version 1.1) 8 AMIC Technology, Inc. A61L6316 Series Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS1 CE tCW2 tWR3 tBW HB, LB tWP WE tDW DATA IN tWHZ 4 tDH tOW DATA OUT (July, 2002, Version 1.1) 9 AMIC Technology, Inc. A61L6316 Series Timing Waveforms (continued) Write Cycle 3 (Byte Enable Controlled) tWC Address tAW tCW CE tWR3 tAS1 tBW2 HB, LB tWP WE tDW tDH DATA IN tWHZ 4 tOW DATA OUT Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and, or LB ). 3. tWR is measured from the earliest of CE or W E or ( HB and, or LB ) going high to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. (July, 2002, Version 1.1) 10 AMIC Technology, Inc. A61L6316 Series AC Test Conditions Input Pulse Levels Input Rise And Fall Time Input and Output Timing Reference Levels Output Load 0V to 3.0V 3 ns 1.5 V See Figures 1 and 2 +3.3V 317Ω I/O OUTPUT ZO=50Ω RL=50Ω VT=1.5V * Including scope and jig. 351Ω 5pF* Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW Data Retention Characteristics (TA = 0°C to 70°C or -25°C to +85°C) Symbol VDR Parameter VCC for Data Retention Min. 2 Max. 3.6 Unit V Conditions CE ≥ VCC - 0.2V ICCDR Data Retention Current - 5 mA VCC = 2.0V CE ≥ VCC - 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V tCDR tR Chip Disable to Data Retention Time Operation Recovery Time 0 TRC* - ns See Retention Waveform ms tRC = Read Cycle Time (July, 2002, Version 1.1) 11 AMIC Technology, Inc. A61L6316 Series Low VCC Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR VDR ≥ 2V tVR CE VIH CE ≥ VDR - 0.2V VIH 3.0V tR Ordering Information Part No. A61L6316S-10 A61L6316S-10I 10 A61L6316V-10 A61L6316V-10I A61L6316S-12 A61L6316S-12I 12 A61L6316V-12 A61L6316V-12I A61L6316S-15 A61L6316S-15I 15 A61L6316V-15 A61L6316V-15I * I series for -25°C to +85°C 210 12 44L TSOP(II) 44L TSOP(II) 220 12 44L TSOP(II) 44L TSOP(II) 44L SOJ 44L SOJ 230 12 44L TSOP(II) 44L TSOP(II) 44L SOJ 44L SOJ Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) Package 44L SOJ 44L SOJ (July, 2002, Version 1.1) 12 AMIC Technology, Inc. A61L6316 Series Package Information SOJ 44L Outline Dimensions unit: inches/mm D 44 23 1 22 E1 E A2 C A y A1 e D 0.004 Min 0.025" b b1 Seating Plane R1 E2 θ y Symbol A A1 A2 b b1 C D E E1 E2 e R1 θ Dimensions in inches Min 0.128 0.082 0.105 0.015 0.026 0.007 1.120 0.435 0.394 Nom 0.138 0.110 0.028 1.125 0.440 0.400 0.370 BSC 0.050 BSC 0.030 0° 0.035 0.040 10° Max 0.148 0.115 0.020 0.032 0.013 1.130 0.445 0.405 Dimensions in mm Min 3.25 2.08 2.67 0.38 0.66 0.18 28.45 11.05 10.01 Nom 3.51 2.79 0.71 28.58 11.18 10.16 9.40 BSC 1.27 BSC 0.76 0° 0.89 1.02 10° Max 3.76 2.92 0.51 0.81 0.21 28.70 11.30 10.29 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension E1 is for PC Board surface mount pad pitch design reference only. (July, 2002, Version 1.1) 13 AMIC Technology, Inc. A61L6316 Series Package Information TSOP 44L (Type II) Outline Dimensions unit: inches/mm 44 E1 E θ L L1 1 D A2 b ZD Dimensions in inches D e A y A1 L L1 Dimensions in mm Min 0.05 0.95 0.30 0.12 18.28 11.56 10.03 0.49 Nom 1.00 18.41 0.805 REF 11.76 10.16 0.59 0.80 REF 0.80 BSC Max 1.20 0.15 1.05 0.45 0.21 18.54 11.96 10.29 0.69 Symbol A A1 A2 b c D ZD E E1 L L1 e y θ Min 0.002 0.037 0.012 0.005 0.720 0.455 0.395 0.019 Nom 0.039 0.725 0.032 REF 0.463 0.400 0.023 0.031 REF 0.031 BSC Max 0.047 0.006 0.041 0.018 0.008 0.730 0.471 0.405 0.027 0° - 0.004 5° 0° - 0.10 5° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension ZD includes end flash. (July, 2002, Version 1.1) 14 AMIC Technology, Inc. c