APW7073QE-TRL

APW7073 Synchronous Buck PWM Controller Features • • • • • • • • • • Single 12V Power Supply Required 0.6V Reference with 1% Accurate Shutdown and Soft-start Function Programmable Frequency Range from 50 kHz to 1000kHz Voltage Mode PWM Control Design Up to 100% Duty Cycle Under-Voltage Protection Over-Current Protection SOP-14, QFN-16 Packages Lead Free Available (RoHS Compliant) General Description The APW7073 is voltage mode, synchronous PWM controller which drives dual N-channel MOSFETs. The device integrates all of the control, monitoring and protecting functions into a single package, provides one controlled power output with under-voltage and over-current protections. The APW 7073 provides excellent regulation for output load variation. The internal 0.6V temperaturecompensated reference voltage is designed to meet the requirement of low output voltage applications. The device includes a 200kHz free-running triangle-wave oscillator that is adjustable from 50kHz to 1000kHz. The APW7073 with excellent protection functions: Applications • Graphic Cards POR, OCP and UVP. The Power-On-Reset (POR) circuit can monitor the VCC, EN, and OCSET voltage to make sure the supply voltage exceeds their threshold voltage while the controller is running. The Over-Current Protection (OCP) monitors the output current by using the voltage drop across the upper and lower MOSFET’ RDS(ON). When the output current s reaches the trip point, the controller will run the softstart function until the fault events are removed. The Under-Voltage Protection (UVP) monitors the voltage at FB pin (VFB) for short-circuit protection, when the VFB is less than 50% of VREF, the controller will shutdown the IC directly. ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 1 www.anpec.com.tw APW7073 Pin Outs SSDONE OCSET 16 SS COMP FB EN 1 2 3 4 5 REFIN 15 14 RT 13 12 PVCC LGATE GND BOOT VCC RT OCSET SS COMP 10 9 FB EN GND 1 2 3 4 5 6 7 SOP-14 TOP VIEW 14 13 12 11 10 9 8 VCC PVCC LGATE PGND BOOT UGATE PHASE Metal GND Pad (Bottom) 11 6 GND 7 PHASE 8 UGATE QFN-16 TOP VIEW Ordering and Marking Information APW7073 Lead Free Code Handling Code Temp. Range Package Code APW7073 K : APW7073 XXXXX APW7073 XXXXX Package Code K : SOP - 14 Q : QFN - 16 Temp. Range E : -20 to 70 °C Handling Code TU : Tube TR : Tape & Reel TY : Tray (for QFN only) Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code APW7073 Q : XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 2 www.anpec.com.tw APW7073 Block Diagram VCC OCSET GND EN Power-On Reset IOCSET 200uA SSDONE (QFN ONLY) ISS 30uA SS 50%VREF :2 O.C.P Comparator 0.27V BOOT UGATE Soft Start O.C.P Comparator PHASE VREF REFIN (QFN ONLY) U.V.P Comparator PVCC PWM Comparator Gate Control LGATE Error Amp PGND Sawtooth Wave Oscillator FB COMP RT Absolute Maximum Ratings Symbol VCC, PVCC BOOT UGATE, VCC, PVCC to GND BOOT to PHASE UGATE to PHASE 400ns pulse width LGATE to PGND 400ns pulse width PHASE to GND 400ns pulse width Parameter Rating -0.3 to +16 -0.3 to +16 -5 to BOOT+5 -0.3 to BOOT +0.3 -5 to PVCC+5 -0.3 to PVCC +0.3 -5 to +21 -0.3 to 16 Unit V V V LGATE V PHASE V C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 3 www.anpec.com.tw APW7073 Absolute Maximum Ratings (Cont.) Symbol RT, OCSET, SSDONE Parameter RT, OCSET, SSDONE to GND Rating VCC+0.3 -0.3 to 7 -0.3 to +0.3 -20 to 150 -65 to 150 300 ±2 Unit V V V °C °C °C KV FB, COMP, REFIN FB, COMP, REFIN to GND PGND TJ TSTG TSDR VESD PGND to GND Junction Temperature Range Storage Temperature Soldering Temperature (10 Seconds) Minimum ESD Rating NOTE 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTE 2: The device is ESD sensitive. Handling precautions are recommended. Recommended Operating Conditions Symbol VCC, PVCC VIN VOUT IOUT TA TJ IC Supply Voltage Converter Input Voltage Converter Output Voltage Converter Output Current Ambient Temperature Range Junction Temperature Range Parameter Rating 10.8 to 13.2 2.2 to 13.2 0.6 to 5 0 to 25 -20 to 70 -20 to 125 Unit V V V A °C °C Electrical Characteristics Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol Parameter Test Conditions APW7073 Min Typ Max Unit INPUT SUPPLY CURRENT ICC VCC Supply Current (Shutdown mode) VCC Supply Current POWER-ON RESET Rising VCC Threshold Falling VCC Threshold C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 4 UGATE, LGATE and EN = GND UGATE and LGATE Open 0.5 5 1 10 mA mA 9 7.5 9.5 8 10.0 8.5 V V www.anpec.com.tw APW7073 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol Parameter Test Conditions APW7073 Min Typ 1.3 0.1 1.3 0.1 -15 +15 200 50 1.6 0 0.60 -1 +1 88 15 6 0.1 5.5 0 1 100 1000 Max Unit POWER-ON RESET (Cont.) Rising VOCSET Threshold VOCSET Hysteresis Voltage Rising EN threshold Voltage EN Hysteresis Voltage OSCILLATOR Accuracy FOSC Free Running Frequency Adjustment Range VOSC Duty VREF Ramp Amplitude Duty Cycle Range Reference Voltage Reference Voltage Tolerance PWM ERROR AMPLIFIER Gain SR Open Loop Gain Slew Rate FB Input Current VCOPM COMP High Voltage VCOPM COMP Low Voltage ICOMP ICOMP IUGATE IUGATE ILGATE ILGATE COMP Source Current COMP Sink Current Upper Gate Source Current Upper Gate Sink Current Lower Gate Source Current Lower Gate Sink Current COMP = 2V COMP = 2V BOOT = 12V, VUGATE -VPHASE = 2V BOOT = 12V, VUGATE -VPHASE = 2V PVCC = 12V, VLGATE = 2V PVCC = 12V, VLGATE = 2V BOOT = 12V, IUGATE = 0.1A 5 V V V V % kHz kHz V % V % dB MHz V/us uA V V mA mA A A A A 3 2.4 Ω Ω RT = open RT pin: resistor to GND; resistor to VCC (nominal 1.35V to 2.95V) REFERENCE RL = 10k, CL = 10pF (NOTE3) RL = 10k, CL = 10pF (NOTE3) RL = 10k, CL = 10pF (NOTE3) VFB = 0.6V GBWP Open Loop Bandwidth 5 5 2.6 1.05 4.9 1.4 2 1.6 GATE DRIVERS RUGATE Upper Gate Source Impedance BOOT = 12V, IUGATE = 0.1A RUGATE Upper Gate Sink Impedance C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 www.anpec.com.tw APW7073 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol Parameter Test Conditions APW7073 Min Typ 1.3 1.25 20 Max 1.95 1.88 Unit GATE DRIVERS (Cont.) RLGATE RLGATE TD Lower Gate Source Impedance Lower Gate Sink Impedance Dead Time FB Under Voltage Level IOCSET VOCP ISS OCSET Source Current OCP Voltage Soft-Start Charge Current SSDONE Low Voltage NOTE 3: Guaranteed by design NOTE 4: QFN Only PVCC = 12V, ILGATE = 0.1A PVCC = 12V, ILGATE = 0.1A Ω Ω nS PROTECTION Percent of VREF VOCSET = 11.5V 45 150 230 24 ISSDONE = 5mA (NOTE4) 50 200 270 30 0.25 55 250 310 36 0.35 % uA mV uA V ENABLE/SOFT START Typical Application Circuit 1uF 12V 1N4148 1nF 1uH VIN PVCC VCC SSDONE RT ON OCSET 2.37K 1uF 470uFx2 0.1uF 470uF BOOT UGATE APM2509 EN OFF SS 22nF 2.2uH VOUT PHASE 1.5nF APM2506 SCD24 7.5 1000uFx2 REFIN COMP LGATE PGND GND 8.2nF 33nF FB 2.7K 1K 2K 18 68nF C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 6 www.anpec.com.tw APW7073 Function Pin Descriptions VCC Power supply input pin. Connect a nominal 12V power supply to this pin. The power-on reset function monitors the input voltage by this pin. It is recommended that a decoupling capacitor (1 to 10uF) be connected to GND for noise decoupling. PVCC This pin provides a supply voltage for the lower gate drive, connect this pin to VCC pin in normal use. BOOT This pin provides the bootstrap voltage to the upper gate driver for driving the N-channel MOSFET. PHASE This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source. This pin is also used to monitor the voltage drop across the MOSFET for over-current protection. GND This pin is the signal ground pin. Connect the GND pin to a good ground plane. PGND This pin is the power ground pin for the lower gate driver. It should be tied to GND pin on the board. COMP This pin is the output of PWM error amplifier. It is used to set the compensation components. FB RT This pin is the inverting input of the PWM error amplifier. It is used to set the output voltage and the compensation components. This pin is also monitored for undervoltage protection; if the FB voltage is under 50% of reference voltage, the device will be shut down. This pin allows adjusting the switching frequency. Connect a resistor from RT pin to the ground to increase the switching frequency. Conversely, connect a resistor from RT to the VCC to decrease the switching frequency. C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 7 www.anpec.com.tw UGATE This pin is the gate driver for the upper MOSFET of PWM output. LGATE This pin is the gate driver for the lower MOSFET of PWM output. SS Connect a capacitor to GND and a 10uA current source charges this capacitor to set the soft-start time. OCSET This pin serves two functions: a shutdown control and the setting of over current limit threshold. Pulling this pin below 1.3V will shutdown the controller, forcing the UGATE and LGATE signals to be low. A resistor (Rocset) connected between this pin and the drain of the high side MOSFET will determine the over current limit. An internal 200uA current source will flow through this resistor, creating a voltage drop, which will be compared with the voltage across the high side MOSFET. The threshold of the over current limit is therefore given by: IPEAK = R DS(ON) IOCSET (200uA ) × R OCSET EN Pull this pin above 1.3V to enable the device and pull this pin below 1.2V to disable the device. In shutdown, the SS is discharged and the UGATE and LGATE pins are held low. Note that don’ leave this pin open. t APW7073 Function Pin Descriptions (Cont.) SSDONE This pin is an open drain device; connect a pull up resistor to VCC for SSDONE function. REFIN This pin provides a external reference voltage instead of the internal 0.6V reference. The REFIN pin is pulled to 5V internally. If the REFIN voltage is less than 4V, the external voltage is used. Typical Characteristics Power On CH1 Power Off VCC=12V, Vin=12V Vo=1.5V, L=1uH CH2 CH1 VCC=12V, Vin=12V Vo=1.5V, L=1uH CH2 CH3 CH3 CH1: VCC (5V/div) CH2: SS (2V/div) CH3: Vo (1V/div) Time: 10ms/div CH1: VCC (5V/div) CH2: SS (2V/div) CH3: Vo (1V/div) Time: 2ms/div C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 8 www.anpec.com.tw APW7073 Typical Characteristics (Cont.) EN (EN=Vcc) CH1 Shutdown (EN=GND) VCC=12V, Vin=12V Vo=1.5V, L=1uH CH1 VCC=12V, Vin=12V Vo=1.5V, L=1uH CH2 CH2 CH3 CH3 CH1: EN (5V/div) CH2: SS (5V/div) CH3: Vo (1V/div) Time: 10ms/div CH1: EN (5V/div) CH2: SS (5V/div) CH3: Vo (1V/div) Time: 10ms/div UGATE Rising UGATE Falling CH1 CH1 CH2 VCC=12V, Vin=12V Vo=1.5V, L=1uH VCC=12V, Vin=12V Vo=1.5V, L=1uH CH2 CH3 CH3 CH1: Ug (20V/div) CH2: Lg (5V/div) CH3: Phase (10V/div) Time: 50ns/div CH1: Ug (20V/div) CH2: Lg (5V/div) CH3: Phase (10V/div) Time: 50ns/div C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 9 www.anpec.com.tw APW7073 Typical Characteristics (Cont.) Load Transient Response VCC=12V, Vin=12V Vo=1.5V, L=1uH CH1 Under Voltage Protection CH1 VCC=12V, Vin=12V Vo=1.5V, L=1uH CH2 CH3 CH4 CH2 CH1: Vo (500mV/div) CH2: Io (5A/div) Time: 200us/div CH1: SS (5V/div) CH2: Io (5A/div) CH3: Vo (1V/div) CH4: Ug (10V/div) Time: 10ms/div Over Current Protection CH1 Short Test CH1 VCC=12V, Vin=12V Vo=1.5V, L=1uH VCC=12V, Vin=12V,Vo=1.5V, L=1uH Rocset=1KΩ , Rds(on)=8mΩ CH2 CH3 CH2 CH3 CH4 CH4 CH1: SS (5V/div) CH2: IL (10A/div) CH3: Vo (1V/div) CH4: Ug (20V/div) Time: 10ms/div CH1: SS (5V/div) CH2: IL (10A/div) CH3: Vo (1V/div) CH4: Ug (20V/div) Time: 10ms/div C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 10 www.anpec.com.tw APW7073 Typical Characteristics (Cont.) Switching Frequency vs. Junction Temperature 205 Reference Voltage vs. Junction Temperature 0.602 0.601 Switching Frequency(KHz) 200 Reference Voltage(V) -40 -20 0 20 40 60 80 100 120 0.6 0.599 0.598 0.597 0.596 0.595 195 190 185 180 0.594 -40 -20 0 20 40 60 80 100 120 Junction Temperature ( °C) Junction Temperature ( °C) UGATE Source Current vs. UGATE Voltage 3.5 UGATE Sink Current vs. UGATE Voltage 3 VBOOT=12V 3 VBOOT=12V 2.5 UGATE Source Current (A) 2.5 2 1.5 1 0.5 0 0 2 4 6 8 10 12 UGAT Sink Current (A) 2 1.5 1 0.5 0 0 2 4 6 8 10 12 UGATE Voltage (V) UGATE Voltage (V) C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 11 www.anpec.com.tw APW7073 Typical Characteristics (Cont.) LGATE Source Current vs. LGATE Voltage 6 5 4 LGATE Sink Current vs. LGATE Voltage 3.5 LGATE Source Current (A) LGATE Sink Current (A) PVCC=12V 3 2.5 2 1.5 1 0.5 0 PVCC=12V 3 2 1 0 0 2 4 6 8 10 12 0 2 4 6 8 10 12 LGATE Voltage (V) LGATE Voltage (V) Function Descriptions Power On Reset (POR) The Power-On Reset (POR) function of APW7074 continually monitors the input supply voltage (VCC), the enable (EN) pin and OCSET pin. The supply voltage (VCC) must exceed its rising POR threshold voltage. The voltage at OCSET pin is equal to VIN less a fixed voltage drop (Vocset = VIN- VROCSET). EN pin can be pulled high with connecting a resistor to VCC. The POR function initiates soft-start operation after VCC, EN and OCSET voltages exceed their POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the +12V power source must exceed the rising VCC threshold. The POR function inhibits operation at disabled status (EN pin low). With both input supplies above their POR thresholds, the device initiates a soft-start interval. Soft-Start/EN The SS/EN pins control the soft-start and enable or disable the controller. Connect a soft-start capacitor from SS pin to GND to set the soft-start interval. Figure1. shows the soft-start interval. When VCC reaches its Power-On-Reset threshold (9.5V), internal 30uA current source starts to charge the capacitor. When the SS reaches the enabled threshold about 1.8V, the internal 0.6V reference starts to rise and follows the SS; the error amplifier output (COMP) suddenly raises to 1.35V, which is the valley of the triangle wave of the oscillator, leads the VOUT to start up. Until the SS reaches about 4.2V, the internal reference completes the soft-start interval and reaches to 0.6V; then V OUT is in regulation. The SS still rises to 5.5V and then stops. C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 12 www.anpec.com.tw APW7073 Function Descriptions (Cont.) Soft-Start/EN (Cont.) TSoft − Start = t 2 − t 1 = C SS ⋅ 2 .4 V ISS ILIMIT = I OCSET × R OCSET R DS (ON ) For the over-current is never occurred in the normal operating load range; the variation of all parameters in the above equation should be determined. - The MOSFET’ RDS(ON) is varied by temperature s and gate to source voltage, the user should determine the maximum RDS(ON) in manufacturer’ datasheet. s - The minimum IOCSET (170uA) and minimum ROCSET VSS Where: CSS = external Soft-Start capacitor ISS = Soft-Start current=30uA Voltage should be used in the above equation. - Note that the ILIMIT is the current flow through the upper MOSFET; ILIMIT must be greater than maximum output current add the half of inductor ripple current. An over current condition will shut down the device and discharge the CSS with a 30uA sink current and then initiate the soft-start sequence. If the over current condition is not removed during the soft-start interval, 4.2V VOUT 1.8V t0 t1 t2 Time the device will be shut down while the over current is detected and the SS still rises to 4V to complete its cycle. The soft start function will be cycled until the over current condition is removed. Both over-current protections have the same behavior while an over current condition is detected. Over-Current Protection (monitor lower MOSFET) The other over-current protection monitors the output current by using the voltage drop across the lower MOSFET’ RDS(ON) and this voltage drop will be coms pared with the internal 0.27V reference voltage. If the voltage drop across the lower MOSFET’ RDS(ON) is s larger than 0.27V, an over-current condition is detected. The threshold of the over current limit is given by: ILIMIT = 0.27V R DS(ON) Figure 1. Soft-Start Internal Over-Current Protection (monitor upper MOSFET) The APW7073 provides two manners to protect the converter from abnormal output load; one monitors the voltage across the upper MOSFET and use the MOSFET pin to set the over-current trip point, the other monitors the voltage across the lower MOSFET by comparing with an internal reference voltage (0.27V). A resistor (ROCSET) connected between OCSET pin and the drain of the upper MOSFET will determine the over current limit. An internal 200uA current source will flow through this resistor, creating a voltage drop, which will be compared with the voltage across the upper MOSFET. When the voltage across the upper MOSFET exceeds the voltage drop across the R OCSET, an over-current will be detected. The threshold of the over current limit is therefore given by: For the over-current is never occurred in the normal operating load range; the parameters RDS(ON) and ILIMIT in the above equation also have the same notices as the previous section. C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 13 www.anpec.com.tw APW7073 Function Descriptions (Cont.) Under Voltage Protection The FB pin is monitored during converter operation by RT Resistance (KΩ) their own Under Voltage (UV) comparator. If the FB voltage drops below 50% of the reference voltage (50% of 0.6V = 0.3V), a fault signal is internally generated, and the device turns off both high-side and low-side MOSFET and the converter’ output is latched to be s floating. Switching Frequency The APW7073 provides the oscillator switching frequency adjustment. The device includes a 200kHz free-running triangle wave oscillator. If operating in higher frequency than 200KHz, connect a resistor from RT pin to the ground to increase the switching frequency. Conversely, if operating in lower frequency than 200KHz, connect a resistor from RT to the VCC to decrease the switching frequency. Figure 2. shows how to select the resistor for the the higher frequencies and Figure 4. shows the lower frequency detail. 1000 900 800 1000 900 1000 900 800 700 600 500 400 300 200 100 0 200 300 400 500 600 700 800 900 1000 Frequency (KHz) Figure3. Oscillator Frequency vs. RT Resistance (High Frequency) RT Resistance (KΩ) desired frequency. Figure 3. shows more detail for 800 700 600 500 400 300 200 50 70 90 110 130 150 170 RT Resistance (KΩ) 700 600 500 400 300 200 100 0 10 1000 Frequency (KHz) Figure4. Oscillator Frequency vs. RT Resistance (Low Frequency) Frequency (KHz) Figure2. Oscillator Frequency vs. RT Resistance C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 14 www.anpec.com.tw APW7073 Application Information Output Voltage Selection The output voltage can be programmed with a resistive divider. Use 1% or better resistors for the resistive divider is recommended. The FB pin is the inverter input of the error amplifier, and the reference voltage is 0.6V. The output voltage is determined by:   R V OUT = 0.6 ×  1 + OUT   R GND    Where ROUT is the resistor connected from VOUT to FB and RGND is the resistor connected from FB to GND. Output Inductor Selection The inductor value determines the inductor ripple current and affects the load transient response. Higher inductor value reduces the inductor’ ripple current and s induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by: V − VOUT V IRIPPLE = IN × OUT FS × L VIN types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple voltage. Output Capacitor Selection Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is intended for switching regulator applications. In some applications, multiple capacitors have to be parallel to achieve the desired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capacitors have to handle A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (FS) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFET and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some MOSFET Selection The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance (CRSS) and maximum output current requirement. There are two components of loss in the MOSFETs: 15 www.anpec.com.tw ∆VOUT = IRIPPLE × ESR where Fs is the switching frequency of the regulator. Although increase of the inductor value and frequency reduces the ripple current and voltage, a tradeoff will exist between the inductor’ ripple current and the s regulator load transient response time. large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor 1uF can be connected between the drain of upper MOSFET and the source of lower MOSFET. C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 APW7073 Application Information (Cont.) MOSFET Selection (Cont.) conduction loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the following: PUPPER = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FS PLOWER = IOUT (1+ TC)(RDS(ON))(1-D) Where IOUT is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency D is the duty cycle Note that both MOSFETs have conduction loss while the upper MOSFET include an additional transition loss. The switching internal, tSW , is a function of the reverse transfer capacitance C RSS. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. PWM Compensation The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain slope and 180 degrees phase shift in the control loop. A compensation network among COMP, FB and VOUT should be added. The compensation network is shown in Fig. 8. The output LC filter consists of the output inductor and output capacitors. The transfer function of the LC filter is given by: GAIN LC PHASE L OUTPUT C OUT ESR Figure 5. The Output LC Filter F LC -40dB/dec GAIN (dB) tSW is the switching interval F ESR -20dB/dec Frequency(Hz) Figure 6. The LC Filter GAIN and Frequency The PWM modulator is shown in Figure 7. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator is given by: VIN GAIN PWM = ∆ V OSC V IN OSC Δ V OSC Driver PWM Comparator PHASE 1 + s × ESR × C OUT =2 s × L × C OUT + s × ESR × C OUT + 1 1 2×π× L × C OUT Output of Error Amplifier Driver The poles and zero of this transfer functions are: FLC = Figure 7. The PWM Modulator The compensation network is shown in Figure 8. It provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by: 16 www.anpec.com.tw FESR = 1 2 × π × ESR × C OUT The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 APW7073 Application Information (Cont.) PWM Compensation (Cont.) 1 1  //  R2 +  sC1  sC2  GAIN AMP = 1  R1//  R3 +  sC3    1 1    s +  × s + (R1 + R3 ) × C3  R2 × C2   R1 + R3    = × C1 + C2   1 R1 × R3 × C1   s s +  × s +  R2 × C1 × C2   R3 × C3   V = COMP V OUT 3.Place the first zero FZ1 before the output LC filter double pole frequency FLC. FZ1 = 0.75 X FLC Calculate the C2 by the equation: C2 = 1 2 × π × R2 × FLC × 0.75 4.Set the pole at the ESR zero frequency FESR: FP1 = FESR Calculate the C1 by the equation: C1 = C2 2 × π × R2 × C2 × FESR − 1 The poles and zeros of the transfer function are: F Z1 1 = 2 × π × R2 × C2 1 = 2 × π × (R1 + R3 ) × C3 1 =  C1 × C2  2 × π × R2 ×    C1 + C2  5.Set the second pole FP2 at the half of the switching frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at FP2 with the capabilities of the error amplifier. C1 F Z2 FP1 FP2 1 = 2 × π × R3 × C3 R3 C3 R2 C2 FP2 = 0.5 X FS FZ2 = FLC Combine the two equations will get the following component calculations: V COMP V OUT R1 FB V REF R3 = Figure 8. Compensation Network The closed loop gain of the converter can be written as: GAINLC X GAINPWM X GAINAMP R1 FS −1 2 × FLC 1 C3 = π × R3 × FS Figure 9. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. 1.Choose a value for R1, usually between 1K and 5K. 2.Select the desired zero crossover frequency FO: (1/5 ~ 1/10) X FS >FO>FESR Use the following equation to calculate R2: R2 = ∆ V OSC F × O × R1 V IN FLC 17 F Z1 F Z2 F P1 F P2 GAIN (dB) 20log (R2/R1) Compensation Gain 20log ( V IN/ Δ V OSC ) F LC F ESR PWM & Filter Gain Frequency(Hz) Converter Gain Figure 9. Converter Gain and Frequency www.anpec.com.tw C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 APW7073 Application Information (Cont.) Layout Considerations In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at 300KHz, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short, wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. And signal and power grounds are to be kept separate till combined using ground plane construction or single point grounding. Figure 10. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: - Keep the switching nodes (UGATE, LGATE and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UG, LG) should be short and wide. - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component, C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 18 www.anpec.com.tw the resistor dividers, boot capacitors, and SS capacitors should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain). - The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. - The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking. APW7073 VCC PVCC BOOT UGATE PHASE LGATE VIN L O A D VOUT Figure 10. Layout Guidelines APW7073 Package Information SOP – 14 (150mil) E H 0.015 x 45 D C A e B GAUGE PLANE SEATING PLANE A1 0.010 L Dim A A1 B C D E e H L θ° Millimeters Min. 1.477 0.102 0.331 0.191 8.558 3.82 1.274 5.808 0.382 0° 6.215 1.274 8° 0.228 0.015 0° Max. 1.732 0.255 0.509 0.2496 8.762 3.999 Min. 0.058 0.004 0.013 0.0075 0.336 0.150 Inches Max. 0.068 0.010 0.020 0.0098 0.344 0.157 0.050 0.244 0.050 8° C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 19 www.anpec.com.tw APW7073 Packaging Information QFN-16 D e b E E2 L D2 A2 A3 Dim A A1 A2 A3 D E b D2 E2 e L C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 A A1 Millimeters Min. 0.76 0.00 0.57 0.20 REF. 3.90 3.90 0.25 2.05 2.05 0.650 BSC 0.50 0.60 0.002 4.10 4.10 0.35 2.15 2.15 0.154 0.154 0.010 0.081 0.081 0.0257BSC 0.024 Max. 0.84 0.04 0.63 Min. 0.030 0.00 0.022 0.008 REF. 0.161 0.161 0.014 0.085 0.085 Inches Max. 0.033 0.0015 0.025 20 www.anpec.com.tw APW7073 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition TP (IR/Convection or VPR Reflow) tp Critical Zone T L to T P Ramp-up Temperature TL Tsmax tL Tsmin Ramp-down ts Preheat 25 t 25 °C to Peak Tim e Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3°C/second max. 100°C 150°C 60-120 seconds 183°C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds See table 2 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface. C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 21 www.anpec.com.tw APW7073 Classification Reflow Profiles(Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures 3 3 P ackage Thickness Volum e m m Volume mm < 350 ≥ 350 < 2.5 m m 240 +0/-5 ° C 225 +0/-5 ° C ≥ 2.5 m m 225 +0/-5 ° C 225 +0/-5 ° C T able 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 P ackage Thickness Volume mm Volume mm Volume mm < 350 3 50-2000 > 2000 < 1.6 m m 260 +0 ° C* 260 +0 ° C* 260 +0 ° C* 1 .6 m m – 2.5 m m 260 +0 ° C* 250 +0 ° C* 245 +0 ° C* ≥ 2.5 m m 250 +0 ° C* 245 +0 ° C* 245 +0 ° C* * Tolerance: The device manufacturer/supplier s hall a ssure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0 ° C. For example 260 ° C+0 ° C) at the rated MSL level. Reliability Test Program Test item S OLDERABILITY H OLT P CT T ST E SD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 SEC 1000 Hrs Bias @125 °C 168 Hrs, 100 % RH, 121°C -65°C~150 °C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 1 00mA Carrier Tape & Reel Dimensions t P P1 D Po E F W Bo Ao Ko D1 C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 22 www.anpec.com.tw APW7073 Carrier Tape & Reel Dimensions(Cont.) T2 J C A B T1 Application SOP-14 (150mil) A 330REF F 7.5 B 100REF D φ0.50 + 0.1 C 13.0 + 0.5 - 0.2 D1 φ1.50 (MIN) J 2 ± 0.5 Po 4.0 T1 16.5REF P1 2.0 T2 2.5 ± 025 Ao 6.5 W 16.0 ± 0.3 Ko 2.10 P 8 t 0.3±0.05 E 1.75 (mm) 5x5 Shipping Tray C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 23 www.anpec.com.tw APW7073 5x5 Shipping Tray (Cont.) Cover Tape Dimensions Application SOP- 14 Carrier Width 24 Cover Tape Width 21.3 Devices Per Reel 2500 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 C opyright © A NPEC Electronics Corp. Rev. A.1 - Apr., 2006 24 www.anpec.com.tw