AOZ1267QI-02

AOZ1267QI-02 24V/8A Synchronous EZBuckTM Regulator General Description Features The AOZ1267-02 is a high-efficiency, easy-to-use DC/DC synchronous buck regulator that operates up to 24V. The device is capable of supplying 8A of continuous output current with an output voltage adjustable down to 0.8V (±1.0%).  Wide input voltage range A proprietary constant on-time PWM control with input feed-forward results in ultra-fast transient response while maintaining relatively constant switching frequency over the entire input voltage range. The switching frequency can be externally programmed up to 1MHz. – 2.7V to 24V  8A continuous output current  Output voltage adjustable down to 0.8V (±1.0%)  Low RDS(ON) internal NFETs – 35m high-side – 8m low-side  Constant On-Time with input feed-forward  Programmable frequency up to 1MHz The device features multiple protection functions such as VCC under-voltage lockout, cycle-by-cycle current limit, output over-voltage protection, short-circuit protection, as well as thermal shutdown.  Selectable PFM light load operation The AOZ1267-02 is available in a 4mm x 4mm QFN-23L package and is rated over a -40°C to +85°C ambient temperature range.  Integrated bootstrap diode  Ceramic capacitor stable  Adjustable soft start  Power Good output  Cycle-by-cycle current limit  Short-circuit protection  Thermal shutdown  Thermally enhanced 4mm x 4mm QFN-23L package Applications  Portable computers  Compact desktop PCs  Servers  Graphics cards  Set-top boxes  LCD TVs  Cable modems  Point-of-load DC/DC converters  Telecom/Networking/Datacom equipment Rev. 1.1 July 2014 www.aosmd.com Page 1 of 15 AOZ1267QI-02 Typical Application RTON TON 5V R3 100kΩ BST VCC C4 1μF Input 2.7V to 24V IN C2 20μF C5 0.1μF AOZ1267-02 Power Good LX PGOOD Off On EN R1 15.8kΩ 1% L1 1μH FB R2 51kΩ 1% PFM AGND SS CSS Output 1.05V, 8A C3 88μF PGND Ordering Information Part Number Ambient Temperature Range Package Environmental AOZ1267QI-02 -40°C to +85°C 23-Pin 4mm x 4mm QFN Green Product AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. SS IN VCC BST PGND LX Pin Configuration 23 22 21 20 19 18 PGOOD 1 17 LX EN 2 16 LX PFM 3 15 PGND AGND 4 14 PGND FB 5 13 PGND TON 6 12 PGND LX 10 11 LX IN 9 LX 8 IN 7 NC IN 23-Pin 4mm x 4mm QFN (Top View) Rev. 1.1 July 2014 www.aosmd.com Page 2 of 15 AOZ1267QI-02 Pin Description Pin Number Pin Name Pin Function 1 PGOOD Power Good Signal Output. PGOOD is an open-drain output used to indicate the status of the output voltage. It is internally pulled low when the output voltage is 18% lower than the nominal regulation voltage for 50µs (typical time) or 20% higher than the nominal regulation voltage. PGOOD is pulled low during soft-start and shut down. 2 EN 3 PFM 4 AGND 5 FB 6 TON 7 NC Enable Input. The AOZ1267-02 is enabled when EN is pulled high. The device shuts down when EN is pulled low. PFM Selection Input. Connect PFM pin to VCC/VIN for forced PWM operation. Connect PFM pin to ground for PFM operation to improve light load efficiency. Analog Ground. Feedback Input. Adjust the output voltage with a resistive voltage-divider between the regulator’s output and AGND. On-Time Setting Input. Connect a resistor between VIN and TON to set the on time. Not Connected. Connect to IN pins (8 and 9) to help with heat dissipation. 8, 9, 22 IN 12, 13, 14, 15, 19 PGND Power Ground. 10, 11, 16, 17, 18 LX Switching Node. 20 BST Bootstrap Capacitor Connection. The AOZ1267-02 includes an internal bootstrap diode. Connect an external capacitor between BST and LX as shown in the Typical Application diagram. 21 VCC Supply Input for analog functions. Bypass VCC to AGND with a 1µF ceramic capacitor. Place the capacitor close to VCC pin. 23 SS Rev. 1.1 July 2014 Supply Input. IN is the regulator input. All IN pins must be connected together. Soft-Start Time Setting Pin. Connect a capacitor between SS and AGND to set the soft-start time. www.aosmd.com Page 3 of 15 AOZ1267QI-02 Absolute Maximum Ratings Exceeding the Absolute Maximum Ratings may damage the device. Parameter Maximum Operating Ratings The device is not guaranteed to operate beyond the Maximum Operating ratings. Rating IN, TON to AGND Parameter -0.3V to 30V LX to AGND Supply Voltage (VIN) -2V to 30V BST to AGND +150°C Storage Temperature (TS) -65°C to +150°C ESD Rating(1) -40°C to +85°C Package Thermal Resistance -0.3V to +0.3V Junction Temperature (TJ) 0.8V to 0.85*VIN Ambient Temperature (TA) -0.3V to 6V PGND to AGND 2.7V to 24V Output Voltage Range -0.3V to 36V SS, PGOOD, FB, EN, VCC, PFM to AGND Rating (θJA) 40°C/W (θJC) 4.5°C/W 2kV Note: 1. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5k in series with 100pF. 2. LX to PGND Transient (t 2V 1 1.5 mA IOFF Shutdown Supply Current VEN = 0V 1 20 A VFB Feedback Voltage TA = 25°C TA = 0°C to 85°C 0.800 0.800 0.808 0.812 V VUVLO Iq IFB 3.2 0.792 0.788 Load Regulation 0.5 % Line Regulation 1 % FB Input Bias Current 200 nA Enable VEN EN Input Threshold VEN_HYS EN Input Hysteresis Off threshold On threshold 0.5 2.5 200 V mV PFM Control VPFM PFM Input Threshold VPFMHYS PFM Input Hysteresis PFM Mode threshold Force PWM threshold 0.5 2.5 100 V mV Modulator TON On Time RTON = 100k, VIN = 12V RTON = 100k, VIN = 24V 200 250 150 300 ns TON_MIN Minimum On Time 100 ns TOFF_MIN Minimum Off Time 250 ns Rev. 1.1 July 2014 www.aosmd.com Page 4 of 15 AOZ1267QI-02 Electrical Characteristics (Continued) TA = 25°C, VIN = 12V, VCC = 5V, EN = 5V, unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C. Symbol Parameter Conditions Min. Typ. Max Units 7 10 15 A 0.5 V ±1 A Soft-Start ISS_OUT SS Source Current VSS = 0 CSS = 0.001F to 0.1F Power Good Signal VPG_LOW PGOOD Low Voltage IOL = 1mA PGOOD Leakage Current VPGH PGOOD Threshold (Low Level to High Level) FB rising 82 85 88 % VPGL PGOOD Threshold (High Level to Low Level) FB rising FB falling 117 79 120 82 123 85 % PGOOD Threshold Hysteresis 3 % TPG_L PGOOD Fault Delay Time (FB falling) 50 s Under Voltage and Over Voltage Protection VPL Under Voltage Threshold TPL Under Voltage Delay Time VPH TUV_LX FB falling 79 82 Over Voltage Threshold FB rising 117 120 Under Voltage Shutdown Blanking Time VIN = 12V, VEN = 0V, VCC = 5V 20 High-Side NFET On-Resistance VIN = 12V, VCC = 5V 35 High-Side NFET Leakage VEN = 0V, VLX = 0V Low-Side NFET On-Resistance VLX = 12V, VCC = 5V Low-Side NFET Leakage VEN = 0V 85 128 % s 123 % ms Power Stage Output RDS(ON) RDS(ON) 8 45 m 10 A 15 m 10 A Over-current and Thermal Protection ILIM Valley Current Limit VCC = 5V Thermal Shutdown Threshold TJ rising TJ falling Rev. 1.1 July 2014 www.aosmd.com 11 A 145 100 °C Page 5 of 15 AOZ1267QI-02 Functional Block Diagram BST IN PGood VCC EN UVLO Reference & Bias TOFF_MIN Q Timer Error Comp 0.8V SS FB ISENCE (AC) PG Logic S Q R FB Decode LX ILIM Comp ILIM_VALLEY Current Information Processing ISENSE OTP Timer PFM TON EN TON Generator Light Load Threshold Light Load Comp ISENSE PGND Rev. 1.1 July 2014 ISENSE (AC) Vcc TON Q ISENSE www.aosmd.com AGND Page 6 of 15 AOZ1267QI-02 Typical Performance Characteristics Circuit of Typical Application. TA = 25°C, VIN = 19V, VOUT = 1.05V, fs = 450kHz unless otherwise specified. Load Transient 0.8A(10%) to 7.2A(90%) Normal Operation VLX 20V/div VLX 10V/div ILX 2A/div ILX 5A/div Vo ripple 50mV/div Vo ripple 20mV/div 5μs/div 1ms/div Full Load Start-up Full Load Short VLX 20V/div ILX 5A/div EN 2V/div lLX 5A/div Vo 500mV/div Vo 1V/div 500μs/div Rev. 1.1 July 2014 LX 10V/div 50μs/div www.aosmd.com Page 7 of 15 AOZ1267QI-02 The simplified control schematic is shown in Figure 1. Detailed Description The AOZ1267-02 is a high-efficiency, easy-to-use, synchronous buck regulator optimized for notebook computers. The regulator is capable of supplying 8A of continuous output current with an output voltage adjustable down to 0.8V. The programmable operating frequency range of 200kHz to 1MHz enables optimizing the configuration for PCB area and efficiency. The input voltage of AOZ1267-02 can be as low as 2.7V. The highest input voltage of AOZ1267-02 can be 24V. Constant on-time PWM with input feed-forward control scheme results in ultra-fast transient response while maintaining relatively constant switching frequency over the entire input range. True AC current mode control scheme guarantees the regulator can be stable with a ceramic output capacitor. The switching frequency can be externally programmed up to 1MHz. Protection features include VCC under-voltage lockout, valley current limit, output over voltage and under voltage protection, short-circuit protection, and thermal shutdown. The AOZ1267-02 is available in 23-pin 4mm x 4mm QFN package. Enable and Soft Start The AOZ1267-02 has external soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. A soft start process begins when VCC rises to 4.1V and voltage on EN pin is HIGH. An internal current source charges the external soft-start capacitor; the FB voltage follows the voltage of soft-start pin (VSS) when it is lower than 0.8V. When VSS is higher than 0.8V, the FB voltage is regulated by internal precise band-gap voltage (0.8V). The soft-start time (TSS) and the time from enable ready (TVO,READY) can be calculated by the following formula: TSS(s) = 330 x CSS(nF) TVO,READY(s) = 93 x CSS(nF) IN PWM Programmable One-Shot – Comp + FB Voltage/ AC Current Information 0.8V Figure 1. Simplified Control Schematic of AOZ1267-02 The high-side switch on-time is determined solely by a one-shot whose pulse width can be programmed by one external resistor and is inversely proportional to input voltage (IN). The one-shot is triggered when the internal 0.8V is lower than the combined information of FB voltage and the AC current information of inductor, which is processed and obtained through the sensed lower-side MOSFET current once it turns on. The added AC current information can help the stability of constant-on time control even with pure ceramic output capacitors, which have very low ESR. The AC current information has no DC offset, which does not cause offset with output load change, which is fundamentally different from other V2 constant-on time control schemes. The constant-on-time PWM control architecture is a pseudo-fixed frequency with input voltage feed-forward. The internal circuit of AOZ1267-02 sets the on-time of high-side switch inversely proportional to the IN. – 12 26.3  10  R TON    T ON = ---------------------------------------------------------------V IN  V  (1) To achieve the flux balance of inductor, the buck converter has the equation: V OUT F SW = --------------------------V IN  T ON (2) If CSS is 1nF, the soft-start time will be 330µs; if CSS is 10nF, the soft-start time will be 3.3ms. Once the product of VIN x TON is constant, the switching frequency keeps constant and is independent with input voltage. Constant-On-Time PWM Control with Input Feed-Forward An external resistor between the IN and TON pin sets the switching frequency according to the following equation: The control algorithm of AOZ1267-02 is constant-on-time PWM Control with input feed-forward. Rev. 1.1 July 2014 12 V OUT  10 F SW = --------------------------------26.3  R TON www.aosmd.com (3) Page 8 of 15 AOZ1267QI-02 A further simplified equation will be: 38000  V OUT  V  F SW  kHz  = ----------------------------------------------R TON  k  (4) Inductor Current Ilim If VOUT is 1.8V, RTON is 137k, the switching frequency will be 500kHz. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. True Current Mode Control The constant-on-time control scheme is intrinsically unstable if output capacitor’s ESR is not large enough as an effective current-sense resistor. Ceramic capacitors usually cannot be used as output capacitor. The AOZ1267-02 senses the low-side MOSFET current and processes it into DC and AC current information using AOS proprietary technique. The AC current information is decoded and added on the FB pin on phase. With AC current information, the stability of constant-on-time control is significantly improved even without the help of output capacitor’s ESR, and thus the pure ceramic capacitor solution can be applicable. The pure ceramic capacitor solution can significantly reduce the output ripple (no ESR caused overshoot and undershoot) and less board area design. Valley Current-Limit Protection The AOZ1267-02 uses the valley current-limit protection by using RDSON of the lower MOSFET current sensing. To detect real current information, a minimum constantoff (150ns typical) is implemented after a constant-on time. If the current exceeds the valley current-limit threshold, the PWM controller is not allowed to initiate a new cycle. The actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the inductor value as well as input and output voltages. The current limit will keep the low-side MOSFET ON and will not allow another high-side ontime, until the current in the low-side MOSFET reduces below the current limit. Figure 2 shows the inductor current during the current limit. Rev. 1.1 July 2014 Time Figure 2. Inductor Current After 128s (typical), the AOZ1267-02 considers this is a true failed condition and therefore, turns-off both highside and low-side MOSFETs and latches off. When triggered, only the enable can restart the AOZ1267-02 again. Output Voltage Under-Voltage Protection If the output voltage is lower than 18% by over-current or short circuit, the AOZ1267-02 will wait for 128s (typical) and turns-off both high-side and low-side MOSFETs and latches off. When triggered, only the enable can restart the AOZ1267-02 again. Output Voltage Over-Voltage Protection The threshold of OVP is set 20% higher than 800mV. When the VFB voltage exceeds the OVP threshold, highside MOSFET is turned-off and low-side MOSFETs is turned-on 1s (typical) than converter will be shutdown. Power Good Output The power good (PGOOD) output, which is an open drain output, requires the pull-up resistor. When the output voltage is 18% below than the nominal regulation voltage for 50s (typical), the PGOOD is pulled low. When the output voltage is 20% higher than the nominal regulation voltage, the PGOOD is also pulled low. When combined with the under-voltage-protection circuit, this current limit method is effective in almost every circumstance. www.aosmd.com Page 9 of 15 AOZ1267QI-02 Application Information The basic AOZ1267-02 application circuit is shown in page 2. Component selection is explained below. Input Capacitor The input capacitor must be connected to the IN pins and PGND pin of the AOZ1267-02 to maintain steady input voltage and filter out the pulsing input current. A small decoupling capacitor, usually 1F, should be connected to the VCC pin and AGND pin for stable operation of the AOZ1267-02. The voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. The input ripple voltage can be approximated by equation below: Inductor VO  VO IO  V IN = -----------------   1 – ---------  --------V IN V IN f  C IN  Since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. For a buck circuit, the RMS value of input capacitor current can be calculated by: VO  VO  I CIN_RMS = I O  ---------  1 – --------- V IN  V IN The inductor is used to supply constant current to output when it is driven by a switching voltage. For given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: VO  VO  I L = -----------   1 – --------- V IN fL  The peak inductor current is: I L I Lpeak = I O + -------2 if let m equal the conversion ratio: VO -------- = m V IN The relation between the input capacitor RMS current and voltage conversion ratio is calculated and shown in Figure 3. It can be seen that when VO is half of VIN, CIN it is under the worst current stress. The worst current stress on CIN is 0.5 x IO. High inductance gives low inductor ripple current but requires a larger size inductor to avoid saturation. Low ripple current reduces inductor core losses. It also reduces RMS current through inductor and switches, which results in less conduction loss. Usually, peak to peak ripple current on inductor is designed to be 30% to 50% of output current. When selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. The inductor takes the highest current in a buck circuit. The conduction loss on the inductor needs to be checked for thermal and efficiency requirements. 0.5 0.4 Surface mount inductors in different shapes and styles are available from Coilcraft, Elytone and Murata. Shielded inductors are small and radiate less EMI noise, but they do cost more than unshielded inductors. The choice depends on EMI requirement, price and size. ICIN_RMS(m) 0.3 IO 0.2 0.1 0 For reliable operation and best performance, the input capacitors must have current rating higher than ICIN-RMS at worst operating conditions. Ceramic capacitors are preferred for input capacitors because of their low ESR and high ripple current rating. Depending on the application circuits, other low ESR tantalum capacitor or aluminum electrolytic capacitor may also be used. When selecting ceramic capacitors, X5R or X7R type dielectric ceramic capacitors are preferred for their better temperature and voltage characteristics. Note that the ripple current rating from capacitor manufactures is based on certain amount of life time. Further de-rating may be necessary for practical design requirement. 0 0.5 m 1 Figure 3. ICIN vs. Voltage Conversion Ratio Rev. 1.1 July 2014 www.aosmd.com Page 10 of 15 AOZ1267QI-02 Output Capacitor The output capacitor is selected based on the DC output voltage rating, output ripple voltage specification and ripple current rating. The selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. De-rating needs to be considered for long term reliability. Output ripple voltage specification is another important factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. It can be calculated by the equation below: 1 V O = I L   ESR CO + -------------------------  8fC  O where, CO is output capacitor value and ESRCO is the Equivalent Series Resistor of output capacitor. When a low ESR ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. Output ripple is mainly caused by capacitor value and inductor ripple current. The output ripple voltage calculation can be simplified to: 1 V O = I L  ------------------------8  f  CO If the impedance of ESR at switching frequency dominates, the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified to: V O = I L  ESR CO For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of ceramic, or other low ESR tantalum are recommended to be used as output capacitors. In a buck converter, output capacitor current is continuous. The RMS current of output capacitor is decided by the peak to peak inductor ripple current. It can be calculated by: I L I CO_RMS = ---------12 inductor ripple current is high, the output capacitor could be overstressed. Thermal Management and Layout Consideration In the AOZ1267-02 buck regulator circuit, high pulsing current flows through two circuit loops. The first loop starts from the input capacitors, to the VIN pin, to the LX pins, to the filter inductor, to the output capacitor and load, and then returns to the input capacitor through ground. Current flows in the first loop when the high side switch is on. The second loop starts from the inductor, to the output capacitors and load, to the low side switch. Current flows in the second loop when the low side switch is on. In PCB layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. A ground plane is strongly recommended to connect the input capacitor, output capacitor and PGND pin of the AOZ1267-02. In the AOZ1267-02 buck regulator circuit, the major power dissipating components are the AOZ1267-02 and output inductor. The total power dissipation of the converter circuit can be measured by input power minus output power. P total_loss = V IN  I IN – V O  I O The power dissipation of inductor can be approximately calculated by output current and DCR of inductor and output current. P inductor_loss = IO2  R inductor  1.1 The actual junction temperature can be calculated with power dissipation in the AOZ1267-02 and thermal impedance from junction to ambient. T junction =  P total_loss – P inductor_loss    JA The maximum junction temperature of AOZ1267-02 is 150ºC, which limits the maximum load current capability. The thermal performance of the AOZ1267-02 is strongly affected by the PCB layout. Extra care should be taken by users during design process to ensure that the IC will operate under the recommended environmental conditions. Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and Rev. 1.1 July 2014 www.aosmd.com Page 11 of 15 AOZ1267QI-02 Layout Considerations Several layout tips are listed below for the best electric and thermal performance. 1. The LX pins and pad are connected to internal low side switch drain. They are low resistance thermal conduction path and most noisy switching node. Connect a large copper plane to LX pin to help thermal dissipation. 4. Decoupling capacitor CVCC should be connected to VCC and AGND as close as possible. 5. Voltage divider R1 and R2 should be placed as close as possible to FB and AGND. 6. RTON should be put on PCB reverse side of feedback network or away from FB pin and FB feedback resistors to avoid unwanted touch to short Ton pin and FB together to ground to cause improperly operation. 2. The IN pins and pad are connected to internal high side switch drain. They are also low resistance thermal conduction path. Connect a large copper plane to IN pins to help thermal dissipation. 7. A ground plane is preferred; Pin 19 (PGND) must be connected to the ground plane through via. 3. Input capacitors should be connected to the IN pin and the PGND pin as close as possible to reduce the switching spikes. 8. Keep sensitive signal traces such as feedback trace far away from the LX pins. 9. Pour copper plane on all unused board area and connect it to stable DC nodes, like VIN, GND or VOUT. 9RXW   %67  3*1'  /;  9&&   3*1' /; /; 3*1'  3*1'   3*1'   3*1'  3*22'  /;    (1 ,1 /; /; ,1 3)0  9LQ 66 $*1'   ,1   )%  ,1 721 1& 9 9RXW Rev. 1.1 July 2014 www.aosmd.com Page 12 of 15 AOZ1267QI-02 Package Dimensions, QFN 4x4, 23 Lead EP2_S D D2 Pin #1 Dot By Marking D3 L1 L e E E1 E2 E3 b L2 TOP VIEW L3 D1 D1 BOTTOM VIEW A1 A A2 SIDE VIEW RECOMMENDED LAND PATTERN 0.37 0.25 0.22 3.10 0.50 0.25 0.45 2.71 3.10 3.43 0.26 0.75 1.34 0.37 0.75 0.95 UNIT: MM Dimensions in inches Dimensions in millimeters Symbols Min. Typ. Max. Symbols Min. Typ. Max. A A1 A2 E E1 E2 E3 D D1 D2 D3 L L1 L2 L3 b e 0.80 0.00 0.90 — 0.2 REF 4.00 3.05 2.66 3.05 4.00 0.75 0.95 1.34 0.40 0.62 0.28 0.62 0.25 0.50 BSC 1.00 0.05 A A1 A2 E E1 E2 E3 D D1 D2 D3 L L1 L2 L3 b e 0.031 0.000 0.035 — 0.008 REF 0.157 0.120 0.105 0.120 0.157 0.030 0.037 0.053 0.016 0.024 0.011 0.024 0.010 0.020 BSC 0.039 0.002 3.90 2.95 2.56 2.95 3.90 0.65 0.85 1.24 0.35 0.57 0.23 0.57 0.20 4.10 3.15 2.76 3.15 4.10 0.85 1.05 1.44 0.45 0.67 0.33 0.67 0.30 0.154 0.116 0.101 0.116 0.154 0.026 0.033 0.049 0.014 0.022 0.009 0.022 0.008 0.141 0.124 0.109 0.124 0.141 0.033 0.041 0.057 0.018 0.026 0.013 0.026 0.012 Notes: 1. Controlling dimensions are in millimeters. Converted inch dimensions are not necessarily exact. 2. Tolerance: ± 0.05 unless otherwise specified. 3. Radius on all corners is 0.152 max., unless otherwise specified. 4. Package wrapage: 0.012 max. 5. No plastic flash allowed on the top and bottom lead surface. 6. Pad planarity: ± 0.102 7. Crack between plastic body and lead is not allowed. Rev. 1.1 July 2014 www.aosmd.com Page 13 of 15 AOZ1267QI-02 Tape and Reel Dimensions, QFN 4x4, 23 Lead EP2_S Carrier Tape P1 P2 D1 T E1 E2 E B0 K0 D0 P0 A0 Feeding Direction UNIT: mm Package A0 B0 K0 D0 QFN 4x4 (12mm) 4.35 ±0.10 4.35 ±0.10 1.10 ±0.10 1.50 Min. D1 E 1.50 +0.10/-0 12.00 ±0.30 Reel E1 E2 P0 P1 P2 T 1.75 ±0.10 5.50 ±0.05 8.00 ±0.10 4.00 ±0.10 2.00 ±0.05 0.30 ±0.05 W1 S G N M K V R H W UNIT: mm Tape Size Reel Size 12mm ø330 M ø330.0 ±2.0 N ø79.0 ±1.0 W 12.4 +2.0/-0.0 W1 17.0 +2.6/-1.2 H ø13.0 ±0.5 K 10.5 ±0.2 S 2.0 ±0.5 G — R — V — Leader/Trailer and Orientation Trailer Tape 300mm min. Rev. 1.1 July 2014 Components Tape Orientation in Pocket www.aosmd.com Leader Tape 500mm min. Page 14 of 15 AOZ1267QI-02 Part Marking AOZ1267QI-02 (QFN4x4) Z1267QI2 FAYWLT Part Number Code Assembly Lot Code Fab & Assembly Location Year & Week Code LEGAL DISCLAIMER Applications or uses as critical components in life support devices or systems are not authorized. AOS does not assume any liability arising out of such applications or uses of its products. AOS reserves the right to make changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the product for their intended application. Customer shall comply with applicable legal requirements, including all applicable export control rules, regulations and limitations. AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at: http://www.aosmd.com/terms_and_conditions_of_sale LIFE SUPPORT POLICY ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 1.1 July 2014 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 15 of 15