AOZ5517QI-02

AOZ5517QI-02 High-Current, High-Performance DrMOS Power Module General Description Features The AOZ5517QI-02 is a high efficiency synchronous buck power stage module consisting of two asymmetrical MOSFETs and an integrated driver. The MOSFETs are individually optimized for operation in the synchronous buck configuration. The High-Side MOSFET is optimized to achieve low capacitance and gate charge for fast switching with low duty cycle operation. The Low-Side MOSFET has ultra low ON resistance to minimize conduction loss. The compact 5mm x 5mm QFN package is optimally chosen and designed to minimize parasitic inductance for minimal EMI signature.  4.5V to 25V power supply range The AOZ5517QI-02 uses PWM and/or FCCM input for accurate control of the power MOSFETs switching activities, is compatible with 5V (CMOS) logic and supports Tri-State PWM. A number of features are provided making the AOZ5517QI-02 a highly versatile power module. The bootstrap diode is integrated in the driver. The Low-Side MOSFET can be driven into diode emulation mode to provide asynchronous operation and improve light-load performance. The pin-out is also optimized for low parasitics, keeping their effects to a minimum.  4.5V to 5.5V driver supply range  60A continuous output current - Up to 80A with 10ms on pulse - Up to 120A with 10us on pulse  Up to 2MHz switching operation  5V PWM / Tri-State input compatible  Under-Voltage LockOut protection  FCCM pin control for Shutdown / Diode Emulation / CCM operation  Standard 5mm x 5mm QFN-31L package Applications  Notebook computers  Memory and graphic cards  VRMs for motherboards  Point of load DC/DC converters  Video gaming console Typical Application Circuit 4.5V ~ 20V VCC VIN THWN BOOT CBOOT HS Driver FCCM Driver Logic and Delay PWM Controller PWM CIN PHASE VSWH LS Driver VOUT L1 COUT GL AGND VCC PGND PVCC CVCC 5V Rev. 2.0 May 2020 CPVCC www.aosmd.com PGND Page 1 of 17 AOZ5517QI-02 Ordering Information Part Number Junction Temperature Range Package Environmental AOZ5517QI-02 -40°C to +150°C QFN5x5-31L RoHS AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. NC THWN PVCC PGND GL VSWH VSWH VSWH Pin Configuration 31 30 29 28 27 26 25 24 PWM 1 FCCM 2 VCC 3 21 VSWH NC 4 20 VSWH BOOT 5 19 VSWH NC 6 PHASE 7 VIN 8 23 VSWH GL 22 VSWH PGND PGND 18 VSWH VIN 17 VSWH VIN 13 14 15 PGND VIN 12 PGND 11 PGND 10 PGND 9 VIN 16 VSWH QFN5x5-31L (Top View) Rev. 2.0 May 2020 www.aosmd.com Page 2 of 17 AOZ5517QI-02 Pin Description Pin Number Pin Name Pin Function 1 PWM PWM input signal from the controller IC. This input is compatible with 5V and Tri-State logic level. 2 FCCM Continuous conduction mode of operation is allowed when FCCM = High. Discontinuous mode is allowed and diode emulation mode is active when FCCM = Low. High impedance on the input of FCCM will shutdown both High-Side and Low-Side MOSFETs. 3 VCC 4 NC Internally connected to PGND paddle. It can be left floating (No Connect) or tied to PGND. 5 BOOT High-Side MOSFET Gate Driver supply rail. Connect a 100nF ceramic capacitor between BOOT and the PHASE (Pin 7). 6 NC 7 PHASE 8, 9, 10, 11 VIN 12, 13, 14, 15 5V Bias for Internal Logic Blocks. Ensure to position a 1µF MLCC directly between VCC and PGND (Pin 28). Internally connected to VIN paddle. It can be left floating (no connect) or tied to VIN. This pin is dedicated for bootstrap capacitor AC return path connection from BOOT (Pin 5). Power stage High Voltage Input (Drain connection of High-Side MOSFET). PGND Power Ground pin for power stage (Source connection of Low-Side MOSFET). 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 VSWH Switching node connected to the Source of High-Side MOSFET and the Drain of Low-Side MOSFET. These pins are used for Zero Cross Detection and Anti-Overlap Control as well as main inductor terminal. 27 GL 28 PGND Power Ground pin for High-Side and Low-Side MOSFET Gate Drivers. Ensure to connect 1µF directly between PGND and PVCC (Pin 29). 29 PVCC 5V Power Rail for High-Side and Low-Side MOSFET Drivers. Ensure to position a 1µF MLCC directly between PVCC and PGND (Pin 28). 30 THWN Thermal warning indicator. This is an open-drain output. When the temperature at the driver IC die reaches the Over Temperature Threshold, this pin is pulled low. 31 NC Rev. 2.0 May 2020 Low-Side MOSFET Gate connection. This is for test purposes only. No Connect www.aosmd.com Page 3 of 17 AOZ5517QI-02 Functional Block Diagram PVCC VCC BOOT VIN VCC FCCM DCM/CCM Detect and Tri-State REF/BIAS UVLO HS Gate Driver Level Shifter Boot HS Sequencing and Propagation Delay Control PHASE HS Gate PHASE Check VSWH Driver Logic Control Logic LS ZCD ZCD Detect PWM PWM Tri-State PWM Tri-State LS Gate PVCC LS Gate Driver Logic Thermal Monitor PGND AGND THWN Rev. 2.0 May 2020 GL www.aosmd.com Page 4 of 17 AOZ5517QI-02 Absolute Maximum Ratings Recommended Operating Conditions Exceeding the Absolute Maximum ratings may damage the device. The device is not guaranteed to operate beyond the Maximum Recommended Operating Conditions. Parameter Rating Low Voltage Supply (VCC, PVCC) High Voltage Supply (VIN) -0.3V to 7V -0.3V to 30V Control Inputs (PWM, FCCM, THWN) Bootstrap Voltage DC (BOOT-PGND) Bootstrap Voltage Transient (BOOT-PGND) Parameter -0.3V to (VCC+0.3V) -0.3V to 35V (1) -0.3V to 7V BOOT Voltage Transient(1) (BOOT-PHASE/VSWH) -0.3V to 9V Switch Node Voltage Transient(1) (PHASE/VSWH) High Voltage Supply (VIN) 4.5V to 25V Low Voltage / MOSFET Driver Supply (VCC, PVCC) 4.5V to 5.5V Control Inputs (PWM, FCCM, THWN) Operating Frequency 0V to VCC 200kHz to 2MHz -8V to 40V Bootstrap Voltage DC (BOOT-PHASE/VSWH) Switch Node Voltage DC (PHASE/VSWH) Rating -0.3V to 30V -8V to 38V Low-Side Gate Voltage DC (GL) (PGND-0.3V) to (PVCC+0.3V) Low-Side Gate Voltage Transient(2) (GL) (PGND-2.5V) to (PVCC+0.3V) VSWH Current DC 60A VSWH Current 10ms Pulse 80A VSWH Current 10us Pulse 120A Storage Temperature (TS) -65°C to +150°C Max Junction Temperature (TJ) (3) ESD Rating 150°C 2kV Notes: 1. Peak voltages can be applied for 10ns per switching cycle. 2. Peak voltages can be applied for 20ns per switching cycle. 3. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5 in series with 100pF. Rev. 2.0 May 2020 www.aosmd.com Page 5 of 17 AOZ5517QI-02 Electrical Characteristics(4) TJ = 0°C to 150°C, VIN = 12V, VOUT = 1V, PVCC = VCC = 5V, unless otherwise specified. Min/Max values are guaranteed by test, design or statistical correlation. Symbol Parameter Conditions Min. Typ. Max. Units 4.5 25 V 4.5 5.5 V GENERAL VIN Power Stage Power Supply VCC Low Voltage Bias Supply PVCC = VCC Reference to High-Side MOSFET temperature rise 2.5 °C / W Thermal Resistance Freq = 300kHz. AOS Demo Board 12.5 °C / W VCC Rising 3.5 VCC Hysteresis 400 mV FCCM = Floating PWM = Floating 3 µA FCCM = 5V PWM = Floating 170 µA FCCM = 0V PWM = Floating 180 µA RJC(4) RJA (4) INPUT SUPPLY AND UVLO VCC_UVLO VCC_HYST IVCC Undervoltage LockOut Control Circuit Bias Current 3.9 V PWM INPUT VPWM_H Logic High Input Voltage VPWM_L Logic Low Input Voltage IPWM_SRC IPWM_SNK VPWM_TRI PWM Pin Input Current 4.2 V 0.72 V PWM = 0V -200 µA PWM = 5V 200 µA PWM Tri-State Window 1.6 VFCCM_H Logic High Input Voltage 3.9 VFCCM_L Logic Low Input Voltage 3.4 V FCCM INPUT IFCCM_SRC IFCCM_SNK VFCCM_TRI tPS4_EXIT FCCM Pin Input Current V 1.1 V FCCM = 0V -50 µA FCCM = 5V 50 µA FCCM Tri-State Window 2.0 PS4 Exit Latency 5 3.0 V 15 µs GATE DRIVER TIMING tPDLU PWM to HS Gate PWM: H  L, VSWH: H  L 30 ns tPDLL PWM to LS Gate PWM: L  H, GL: H  L 25 ns tPDHU LS to HS Gate Deadtime GL: H  L, VSWH: L  H 15 ns tPDHL HS to LS Gate Deadtime VSWH: H  1V, GL: L  H 13 ns tTSSHD Tri-State Shutdown Delay PWM: L  VTRI, GL: H  L and PWM: H  VTRI, VSWH: H  L 150 ns tTSEXIT Tri-State Propagation Delay PWM: VTRI  H, VSWH: L  H PWM: VTRI  L, GL: L  H 45 ns tLGMIN LS Minimum On Time FCCM = 0V 350 ns Rev. 2.0 May 2020 www.aosmd.com Page 6 of 17 AOZ5517QI-02 Electrical Characteristics(4) (Continued) TJ = 0°C to 150°C, VIN = 12V, VOUT = 1V, PVCC = VCC = 5V, unless otherwise specified. Min/Max values are guaranteed by test, design, or statistical correlation. Symbol THERMAL Parameter Conditions Min. Typ. Max. Units NOTIFICATION(5) TJTHWN Junction Thermal Threshold TJHYST Junction Thermal Hysteresis VTHWN THWN Pin Output Low RTHWN THWN Pull-Down Resistance Temperature Rising ITHWN = 0.5mA 135 °C 20 °C 60 mV 120 Ω Notes: 4. All voltages are specified with respect to the corresponding AGND pin. 5. Characterization value. Not tested in production. Rev. 2.0 May 2020 www.aosmd.com Page 7 of 17 AOZ5517QI-02 Timing Diagrams V PWMH PWM VPWML tPDLL tPDHL 90% GL 1V 1V tPDLU 90% tPDHU VSWH 1V 1V Figure 1. PWM Logic Input Timing Diagram PWM t TSSHD t TSSHD t TSSHD t TSSHD GL t PTS tPTS t PTS t PTS GH Figure 2. PWM Tri-State Hold Off and Exit Timing Diagram Rev. 2.0 May 2020 www.aosmd.com Page 8 of 17 AOZ5517QI-02 Typical Performance Characteristics 96% 16 94% 14 92% 12 Power Loss (W) Efficiency (%) TA = 25°C, VIN = 12V, VOUT = 1V, PVCC = VCC = 5V, unless otherwise specified. 90% 88% VIN=12V, Vo=1.8V, Fsw=600k 86% VIN=12V, Vo=1.8V, Fsw=750k 84% 80% VIN=19V, Vo=1.8V, Fsw=750k 5 10 15 20 25 30 35 VIN=12V, Vo=1.8V, Fsw=750k VIN=19V, Vo=1.8V, Fsw=600k 10 VIN=19V, Vo=1.8V, Fsw=750k 8 6 4 VIN=19V, Vo=1.8V, Fsw=600k 82% VIN=12V, Vo=1.8V, Fsw=600k 2 45 40 50 0 55 5 10 15 20 Output Current (A) 25 30 35 45 40 50 55 Output Current (A) Figure 3. Efficiency vs. Output Current, VOUT = 1.8V Figure 4. Power Loss vs. Output Current, VOUT = 1.8V 94% 16 92% 14 90% 12 Power Loss (W) Efficiency (%) VIN=12V, Vo=1V, Fsw=600k 88% 86% VIN=12V, Vo=1V, Fsw=600k 84% VIN=12V, Vo=1V, Fsw=750k VIN=19V, Vo=1V, Fsw=600k 82% 78% 5 10 15 20 25 30 35 VIN=19V, Vo=1V, Fsw=600k 10 VIN=19V, Vo=1V, Fsw=750k 8 6 4 VIN=19V, Vo=1V, Fsw=750k 80% VIN=12V, Vo=1V, Fsw=750k 2 40 45 50 0 55 5 10 15 20 Output Current (A) Figure 5. Efficiency vs. Output Current, VOUT = 1.0V 35 45 40 50 55 4.5 Logic High Threshold 4.0 4.0 3.5 Shutdown to CCM 3.5 FCCM Voltage (V) PWM Voltage (V) 30 Figure 6. Power Loss vs. Output Current, VOUT = 1.0V 4.5 3.0 Tri-state Window 2.5 2.0 CCM to Shutdown 3.0 2.5 DCM to Shutdown 2.0 1.5 1.5 1.0 1.0 0.5 -50 25 Output Current (A) Shutdown to DCM Logic Low Threshold -25 0 25 50 75 100 125 150 0.5 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Figure 7. PWM Threshold vs. Temperature Figure 8. FCCM Threshold vs. Temperature Rev. 2.0 May 2020 www.aosmd.com 150 Page 9 of 17 AOZ5517QI-02 Typical Performance Characteristics TA = 25°C, VIN = 12V, VOUT = 1V, PVCC = VCC = 5V, unless otherwise specified. 3.7 4.5 3.6 4.0 Rising Threshold 3.5 PWM Voltage (V) VCC Voltage (V) 3.5 Logic High Threshold 3.4 3.3 3.2 3.1 3.0 Tri-state Window 2.5 2.0 1.5 Falling Threshold 3.0 2.9 -50 -25 25 0 50 1.0 75 100 125 0.5 4.2 150 Logic Low Threshold 4.4 4.6 Temperature (°C) 10000.0 5.2 5.4 5.6 5.8 Figure 10. PWM Threshold vs. VCC Voltage 10000.0 1000.0 10µs RDS(ON) limited 10.0 10ms 1.0 IDM limited 1000.0 IDM limited Drain Current, ID (A) Drain Current, ID (A) 5.0 VCC Voltage (V) Figure 9. UVLO (VCC) Threshold vs. Temperature 100.0 4.8 100.0 R DS(ON) limited 10µs 10.0 10ms 1.0 0.1 0.1 TA = 25°C TA = 25°C 0.0 0.01 0.1 1 10 100 0.0 0.01 Figure 11. High-Side MOSFET SOA Rev. 2.0 May 2020 0.1 1 10 100 Drain - Source Voltage, VDS (V) Drain - Source Voltage, VDS (V) Figure 12. Low-Side MOSFET SOA www.aosmd.com Page 10 of 17 AOZ5517QI-02 Application Information Input Voltage VIN AOZ5517QI-02 is a fully integrated power module designed to work over an input voltage range of 4.5V to 25V with a separate 5V supply for gate drive and internal control circuitry. The MOSFETs are individually optimized for efficient operation on both High-Side and Low-Side for a low duty cycle synchronous buck converter. High current MOSFET Gate Drivers are integrated in the package to minimize parasitic loop inductance for optimum switching efficiency. AOZ5517QI-02 is rated to operate over a wide input range from 4.5V to 25V. For high current synchronous buck converter applications, large pulse current at high frequency and high current slew rates (di/dt) will be drawn by the module during normal operation. It is strongly recommended to place a bypass capacitor very close to the package leads at the input supply (VIN). Both X7R or X5R quality surface mount ceramic capacitors are suitable. Powering the Module and the Gate Drives The High-Side MOSFET is optimized for fast switching by using a low gate charge (QG) device. When the module is operated at high duty cycle ratio, conduction loss from the High-Side MOSFET will be higher. The total power loss for the module is still relatively low but the High-Side MOSFET higher conduction loss may have higher temperature. The two MOSFETs have their own exposed pads and PCB copper areas for heat dissipation. It is recommended that worst case junction temperature be measured for both High-Side MOSFET and Low-Side MOSFET to ensure that they are operating within Safe Operating Area (SOA). An external supply PVCC = 5V is required for driving the MOSFETs. The MOSFETs are designed with optimally customized gate thresholds voltages to achieve the most advantageous compromise between high switching speed and minimal power loss. The integrated gate driver is capable of supplying large peak current into the LowSide MOSFET to achieve fast switching. A ceramic bypass capacitor of 1F or higher is recommended from PVCC (Pin 29) to PGND (Pin 28). The control logic supply VCC (Pin 3) can be derived from the gate drive supply PVCC (Pin 29) through an RC filter to bypass the switching noise (See Typical Application Circuit). The boost supply for driving the High-Side MOSFET is generated by connecting a small capacitor (100nF) between the BOOT (Pin 5) and the switching node PHASE (Pin 7). It is recommended that this capacitor CBOOT should be connected to the device across Pin 5 and Pin 7 as closely as possible. A bootstrap switch is integrated into the device to reduce external component count. An optional resistor RBOOT in series with CBOOT between 1Ω to 5Ω can be used to slow down the turn on speed of the High-Side MOSFET to achieve both short switching time and low VSWH switching node spikes at the same time. Under-voltage LockOut AOZ5517QI-02 starts up to normal operation when VCC rises above the Under-Voltage LockOut (UVLO) threshold voltage. The UVLO release is set at 3.5V typically. Since the PWM control signal is provided from an external controller or a digital processor, extra caution must be taken during start up. AOZ5517QI-02 must be powered up before PWM input is applied. Normal system operation begins with a soft start sequence by the controller to minimize in-rush current during start up. Powering the module with a full duty cycle PWM signal may lead to many undesirable consequences due to excessive power. AOZ5517QI-02 provides some protections such as UVLO and thermal monitor. For system level protection, the PWM controller should monitor the current output and protect the load under all possible operating and transient conditions. Rev. 2.0 May 2020 PWM Input AOZ5517QI-02 is compatible with 5V (CMOS) PWM logic. Refer to Figure 1 for PWM logic timing and propagation delays diagram between PWM input and the MOSFET gate drives. The PWM is also compatible with Tri-State input. When the PWM output from the external PWM controller is in high impedance or not connected, both High-Side and Low-Side MOSFETs are turned off and VSWH is in high impedance state. Table 1 shows the thresholds level for high-to-low and low-to-high transitions as well as TriState window. There is a Holdoff Delay between the corresponding PWM Tri-State signal and the MOSFET gate drivers to prevent spurious triggering of Tri-State mode which may be caused by noise or PWM signal glitches. The Holdoff Delay is typically 150ns. Table 1. PWM Input and Tri-State Thresholds Thresholds  VPWMH VPWML VTRIH VTRIL AOZ5517QI-02 4.20V 0.72V 1.60V 3.40V Note: See Figure 2 for propagation delays and Tri-State window. www.aosmd.com Page 11 of 17 AOZ5517QI-02 Diode Mode Emulation of Low-Side MOSFET (FCCM) AOZ5517QI-02 can be operated in the diode emulation or pulse skipping mode using FCCM (Pin 2). This enables the converter to operate in asynchronous mode during start up, light load or under pre-bias conditions. When FCCM is high, the module will operate in Continuous Conduction Mode (CCM). The Driver logic will use the PWM signal and generate both the High-Side and Low-Side complementary gate drive outputs with minimal anti-overlap delays to avoid cross conduction. When FCCM is low, the module can operate in Discontinuous Conduction Mode (DCM). The High-Side MOSFET gate drive output is not affected but Low-Side MOSFET will enter diode emulation mode. See Table 2 for the truth table for PWM and FCCM inputs. Table 2. Control Logic Truth Table FCCM PWM GH GL L L L H if IL > 0A L if IL < 0A L H H L H L L H H H H L L Tri-State L L H Tri-State L L Tri-State X L L When the falling edge of switching node VSWH goes below 1V, the blanking period is activated. After a predetermined value (tPDHL), the complementary Low-Side Gate Driver output GL is turned on. This mechanism prevents cross conduction across the input bus line VIN and PGND. The anti-overlap circuit monitors the switching node VSWH to ensure a smooth transition between the two MOSFETs under any load transient conditions. Thermal Warning (THWN) The driver IC temperature is internally monitored and a thermal warning flag at THWN (Pin 30) is asserted if it exceeds 150°C. This warning flag is reset when the temperature drops back to 120°C. THWN is an open drain output that is pulled to AGND to indicate an overtemperature condition. It should be connected to VCC through a resistor for monitoring purpose. The device will not power down during the over temperature condition. Gate Drives AOZ5517QI-02 has an internal high current high speed driver that generates the floating gate driver for the HighSide MOSFET and a complementary driver for the LowSide MOSFET. An internal shoot through protection scheme is implemented to ensure that both MOSFETs cannot be turned on at the same time. The operation of PWM signal transition is illustrated as below. 1) PWM from logic Low to logic High When the falling edge of Low-Side Gate Driver output GL goes below 1V, the blanking period is activated. After a pre-determined value (tPDHU), the complementary HighSide Gate Driver output GH is turned on. 2) PWM from logic High to logic Low Rev. 2.0 May 2020 www.aosmd.com Page 12 of 17 AOZ5517QI-02 PCB Layout Guidelines AOZ5517QI-02 is a high current module rated for operation up to 2MHz. This requires high switching speed to keep the switching losses and device temperatures within limits. An integrated gate driver within the package eliminates driver-to-MOSFET gate pad parasitic of the package or on PCB. To achieve high switching speeds, high levels of slew rate (dv/dt and di/dt) will be present throughout the power train which requires careful attention to PCB layout to minimize voltage spikes and other transients. As with any synchronous buck converter layout, the critical requirement is to minimize the path of the primary switching current loop formed by the High-Side MOSFET, Low-Side MOSFET, and the input bypass capacitor CIN. The PCB design is greatly simplified by the optimization of the AOZ5517QI-02 pin out. The power inputs of VIN and PGND are located adjacent to each other and the input bypass capacitors CIN should be placed as close as possible to these pins. The area of the secondary switching loop is formed by Low-Side MOSFET, output inductor L1, and output capacitor COUT is the next critical requirement. This requires second layer or “Inner 1” to be the PGND plane. VIAs should then be placed near PGND pads. While AOZ5517QI-02 is a highly efficient module, it still dissipates a significant amount of heat under high power conditions. Special attention is required for thermal design. MOSFETs in the package are directly attached to individual exposed pads (VIN and PGND) to simplify thermal management. Both VIN and VSWH pads should be attached to large areas of PCB copper. Thermal relief pads should be placed to ensure proper heat dissipation to the board. An inner power plane layer dedicated to VIN, typically the high voltage system input, is desirable and VIAs should be provided near the device to connect the VIN pads to the power plane. Significant amount of heat can also be dissipated through multiple PGND pins. A large copper area connected to the PGND pins in addition to the system ground plane through VIAs will further improve thermal dissipation. As shown on Figure. 13, the top most layer of the PCB should comprise of wide and exposed copper area for the primary AC current loop which runs along VIN pad originating from the input capacitors C10, C11, and C12 that are mounted to a large PGND pad. They serve as thermal relief as heat flows down to the VIN exposed pad that fans out to a wider area. Adding VIAs will only help transfer heat to cooler regions of the PCB board through the other layers beneath but serve no purpose to AC activity as all the AC current sees the lowest impedance on the top layer only. Rev. 2.0 May 2020 Figure 13. Top Layer of Demo Board, VIN, VSWH and PGND Copper Pads As the primary and secondary (complimentary) AC current loops move through VIN to VSWH and through PGND to VSWH, large positive and negative voltage spikes appear at the VSWH terminal which are caused by the large internal di/dt produced by the package parasitic. To minimize the effects of this interference at the VSWH terminal, at which the main inductor L1 is mounted, size just enough for the inductor to physically fit. The goal is to employ the least amount of copper area for this VSWH terminal, only enough so the inductor can be securely mounted. To minimize the effects of switching noise coupling to the rest of the sensitive areas of the PCB, the area directly underneath the designated VSWH pad or inductor terminal is voided and the shape of this void is replicated descending down through the rest of the layers. Refer to Figure 14. Figure 14. Bottom layer of PCB Positioning VIAs through the landing pattern of the VIN and PGND thermal pads will help quickly facilitate the thermal build up and spread the heat much more quickly towards the surrounding copper layers descending from www.aosmd.com Page 13 of 17 AOZ5517QI-02 the top layer. (See RECOMMENDED PATTERN AND VIA PLACEMENT section). LANDING The exposed pads dimensional footprint of the 5x5 QFN package is shown on the package dimensions page. For optimal thermal relief, it is recommended to fill the PGND and VIN exposed landing pattern with 10mil diameter VIAs. 10mil diameter is a commonly used VIA diameter as it is optimally cost effective based on the tooling bit used in manufacturing. Each via is associated with a 20mil diameter keep out. Maintain a 5mil clearance (127um) around the inside edge of each exposed pad in case of solder overflow, which could potentially short with the adjacent exposed thermal pad. Rev. 2.0 May 2020 www.aosmd.com Page 14 of 17 AOZ5517QI-02 Package Dimensions, QFN5x5-31L RECOMMENDED LAND PATTERN UNIT: mm NOTE CONTROLLING DIMENSION IS MILLIMETER. CONVERTED INCH DIMENSIONS ARE NOT NECESSARILY EXACT. Rev. 2.0 May 2020 www.aosmd.com Page 15 of 17 AOZ5517QI-02 Tape and Reel Drawing, QFN5x5-31L Rev. 2.0 May 2020 www.aosmd.com Page 16 of 17 AOZ5517QI-02 Part Marking AOZ5517QI-02 (5mm x 5mm QFN) BP02 YWLT Year Code & Week Code Part Number Code Assembly Lot Code LEGAL DISCLAIMER Applications or uses as critical components in life support devices or systems are not authorized. AOS does not assume any liability arising out of such applications or uses of its products. AOS reserves the right to make changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the product for their intended application. Customer shall comply with applicable legal requirements, including all applicable export control rules, regulations and limitations. AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at: http://www.aosmd.com/terms_and_conditions_of_sale LIFE SUPPORT POLICY ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 2.0 May 2020 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 17 of 17