AOZ5117QI

AOZ5117QI High-Current, High-Performance DrMOS Power Module General Description Features The AOZ5117QI is a high efficiency synchronous buck power stage module consisting of two asymmetrical MOSFETs and an integrated driver. The MOSFETs are individually optimized for operation in the synchronous buck configuration. The High-Side MOSFET is optimized to achieve low capacitance and gate charge for fast switching with low duty cycle operation. The Low-Side MOSFET has ultra low ON resistance to minimize conduction loss. AOZ5117QI comes with low noise technology enhancement at switching node to reduce noise interference.  4.5V to 25V power supply range The AOZ5117QI uses a PWM and SMOD# input for accurate control of the power MOSFETs switching activities, is compatible with 3V and 5V (CMOS) logic and supports Tri-State PWM.  Thermal Shutdown A number of features are provided making the AOZ5117QI a highly versatile power module. The bootstrap diode is integrated in the driver. The Low-Side MOSFET can be driven into diode emulation mode to provide asynchronous operation and improve light-load performance. The pin-out is also optimized for low parasitics, keeping their effects to a minimum.  4.5V to 5.5V driver supply range  60A continuous output current - Up to 80A with 10ms on pulse - Up to 120A with 10us on pulse  Up to 2MHz switching operation  3V/5V PWM and Tri-State input compatible  Supports Intel® Power State 4  Thermal Warning Output  Under-Voltage LockOut protection  SMOD# control for Diode Emulation / CCM operation  Low Profile 5x5 QFN-31L package Applications  Notebook computers  VRMs for motherboards  Point of load DC/DC converters  Video gaming consoles Typical Application Circuit 4.5V ~ 25V VCC VIN THWN PWM Controller BOOT CBOOT HS Driver DISB# Driver Logic and Delay SMOD# PWM CIN PHASE VSWH LS Driver L1 VOUT COUT GL AGND VCC CVCC 5V Rev. 2.0 May 2020 PGND PVCC CPVCC www.aosmd.com PGND Page 1 of 18 AOZ5117QI Ordering Information Part Number Junction Temperature Range Package Environmental AOZ5117QI -40°C to +150°C QFN5x5-31L RoHS AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. PWM 1 SMOD# 2 VCC THWN DISB# PVCC PGND GL VSWH VSWH VSWH Pin Configuration 31 30 29 28 27 26 25 24 23 VSWH 22 VSWH 3 21 VSWH AGND 4 20 VSWH BOOT 5 19 VSWH NC 6 18 VSWH PHASE 7 17 VSWH VIN 8 16 VSWH GL PGND PGND VIN 13 14 15 PGND VIN 12 PGND 11 PGND 10 PGND 9 VIN VIN QFN5x5-31L (Top View) Rev. 2.0 May 2020 www.aosmd.com Page 2 of 18 AOZ5117QI Pin Description Pin Number Pin Name Pin Function 1 PWM PWM input signal from the controller IC. When DISB#=0V, the internal resistor divider will be disconnected and this pin will be at high impedance. 2 SMOD# Skip Mode 3−state input (see Table 1 Logic Table): 1. SMOD# = High: The zero cross comparator and the state of PWM determine if the module should perform Zero Cross Detection. 2. SMOD# = Mid: Connects PWM to internal resistor divider placing a bias voltage on an undriven PWM pin. Otherwise, logic is equivalent to SMOD# in the high state. 3. SMOD# = Low: Placing PWM into Tri−State pulls the High-Side and Low-Side MOSFET gates low without delay. There is an internal pull−up resistor to VCC on this pin. 3 VCC 5V Bias for Internal Logic Blocks. Ensure the position a 1µF MLCC directly between VCC and AGND (Pin 4). 4 AGND Signal Ground. 5 BOOT High-Side MOSFET Gate Driver supply rail. Connect a 100nF ceramic capacitor between BOOT and the PHASE (Pin 7). 6 NC 7 PHASE Internally connected to VIN paddle. It can be left floating (no connect) or tied to VIN. This pin is dedicated for bootstrap capacitor AC return path connection from BOOT (Pin 5). 8, 9, 10, 11 VIN 12, 13, 14, 15 PGND Power Ground pin for power stage (Source connection of Low-Side MOSFET). 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 VSWH Switching node connected to the Source of High-Side MOSFET and the Drain of Low-Side MOSFET. These pins are used for Zero Cross Detection and Anti-Overlap Control as well as main inductor terminal. 27 GL 28 PGND Power Ground pin for High-Side and Low-Side MOSFET Gate Drivers. Ensure to connect 1µF directly between PGND and PVCC (Pin 29). 29 PVCC 5V Power Rail for High-Side and Low-Side MOSFET Drivers. Ensure to position a 1µF MLCC directly between PVCC and PGND (Pin 28). 30 DISB# Output disable pin. When this pin is pulled to a logic low level, the IC is disabled. There is an internal pull−down resistor to AGND. 31 THWN Thermal warning indicator. This is an open−drain output. When the temperature at the driver IC die reaches the Over Temperature Threshold, this pin is pulled low. Rev. 2.0 May 2020 Power stage High Voltage Input (Drain connection of High-Side MOSFET). Low-Side MOSFET Gate connection. This is for test purposes only. www.aosmd.com Page 3 of 18 AOZ5117QI Functional Block Diagram VCC DISB# Enable BOOT PVCC REF/BIAS UVLO HS Gate Driver Level Shifter VCC SMOD# HS ZCD Detect Sequencing And Propagation Delay Control PHASE HS Gate PHASE Check VSWH Driver Logic Control Logic LS VIN ZCD ZCD Detect PWM PWM LS Gate PVCC Tri-State PWM Tri-State Logic LS Gate Driver Thermal Monitor PGND AGND THWN Rev. 2.0 May 2020 GL www.aosmd.com Page 4 of 18 AOZ5117QI Absolute Maximum Ratings Recommended Operating Conditions Exceeding the Absolute Maximum ratings may damage the device. The device is not guaranteed to operate beyond the Maximum Recommended Operating Conditions. Parameter Rating Parameter Rating Low Voltage Supply (VCC, PVCC) -0.3V to 6.5V High Voltage Supply (VIN) 4.5V to 25V High Voltage Supply (VIN) -0.3V to 30V Low Voltage / MOSFET Driver Supply (VCC, PVCC) 4.5V to 5.5V Control Inputs (PWM, SMOD#, DISB#) -0.3V to (VCC+0.3V) Output (THWN) -0.3V to (VCC+0.3V) Bootstrap Voltage DC (BOOT-PGND) Bootstrap Voltage Transient(1) (BOOT-PGND) Bootstrap Voltage DC (BOOT-PHASE/VSWH) BOOT Voltage Transient(1) (BOOT-PHASE/VSWH) Switch Node Voltage DC (PHASE/VSWH) Switch Node Voltage Transient(1) (PHASE/VSWH) -0.3V to 35V Control Inputs (PWM, SMOD#, DISB#) Operating Frequency 0V to VCC 200kHz to 2MHz -8V to 40V -0.3V to 6.5V -0.3V to 9V -0.3V to 30V -8V to 38V Low-Side Gate Voltage DC (GL) (PGND-0.3V) to (PVCC+0.3V) Low-Side Gate Voltage Transient(1) (GL) (PGND-2.5V) to (PVCC+0.3V) VSWH Current DC 60A VSWH Current 10ms Pulse 80A VSWH Current 10us Pulse 120A Storage Temperature (TS) -65°C to 150°C Max Junction Temperature (TJ) (2) ESD Rating 150°C 1.5kV Notes: 1. Peak voltages can be applied for 10ns per switching cycle. 2. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5 in series with 100pF. Rev. 2.0 May 2020 www.aosmd.com Page 5 of 18 AOZ5117QI Electrical Characteristics(3) TJ = 0°C to 150°C, VIN = 12V, VOUT = 1V, PVCC = VCC = DISB# = 5V, unless otherwise specified. Min/Max values are guaranteed by test, design or statistical correlation. Symbol Parameter Conditions Min. Typ. Max. Units 4.5 25 V 4.5 5.5 V GENERAL VIN Power Stage Power Supply VCC Low Voltage Bias Supply PVCC = VCC Thermal Resistance Reference to High-Side MOSFET temperature rise 2.5 °C / W Freq = 300kHz. AOS Demo Board 12.5 °C / W VCC Rising 3.1 VCC Hysteresis 400 RJC(4) RJA (4) INPUT SUPPLY AND UVLO VCC_UVLO VCC_HYST Undervoltage LockOut 3.3 V mV IVCC Control Circuit Shutdown Bias Current DISB# = 0V, SMOD# = 5V 0.1 1 µA DISB# = 0V, SMOD# = 0V 6 13 µA IPVCC Drive Circuit Operating Current PWM = 400kHz, 20% Duty Cycle 15.5 mA PWM INPUT VPWM_H Logic High Input Voltage VPWM_L Logic Low Input Voltage RPWM PWM Pin Input Resistance VPWM_TRI PWM Tri-State Window VPWM_FLOAT PWM Tri-State Voltage Clamp 2.65 V 0.7 SMOD# = 0V or 5V 10 SMOD# = 1.7V V MΩ 68 1.4 kΩ 2.0 1.7 V V DISB# INPUT VDISB#_ON Enable Input Voltage VDISB#_OFF Disable Input Voltage 2.0 V 0.8 RDISB# DISB# Input Resistance Pull-Down Resistor tEN_DEL Enable Delay Time DISB#: L  H, VSWH = PWM tDIS_DEL Disable Delay Time DISB#: H  L, VSWH = Floating 475 21 V kΩ 40 us 50 ns SMOD# INPUT VSMOD#_H Logic High Input Voltage VSMOD#_L Logic Low Input Voltage VSMOD#_MID RSMOD# tSMOD#_DEL 2.65 SMOD# Mid-State Window SMOD# Input Resistance V 1.4 Pull-Up Resistor 0.7 V 2.0 V 475 SMOD# Propagation Delay Time kΩ 40 ns ZCD FUNCTION VZCD tZCD_BLANK Zero Cross Detect Voltage ZCD Blanking Time Rev. 2.0 May 2020 SMOD# = 5V www.aosmd.com -6 mV 300 ns Page 6 of 18 AOZ5117QI Electrical Characteristics(3) TJ = 0°C to 150°C, VIN = 12V, VOUT = 1V, PVCC = VCC = DISB# = 5V, unless otherwise specified. Min/Max values are guaranteed by test, design or statistical correlation. Symbol Parameter Conditions Min. Typ. Max. Units GATE DRIVER TIMINGS tPDLU PWM to High-Side Gate PWM: H  L, GH(5): H  L 13 ns tPDLL PWM to Low-Side Gate PWM: L  H, GL: H  L 15 ns tPDHU LS to HS Gate Deadtime GL: H  L, GH(5): L  H 13 ns tPDHL HS to LS Gate Deadtime VSWH: H  1V, GL: L  H 12 ns Tri-State Propagation Delay PWM: VTRI  H, VSWH: L  H PWM: VTRI  L, GL: L  H 13 Temperature Rising 150 °C 15 °C tTSEXIT 25 ns THERMAL NOTIFICATION TJTHWN Junction Thermal Threshold TJHYST Junction Thermal Hysteresis ITHWN THWN Open Drain Current 5 mA THERMAL SHUTDOWN TJTHDN Junction Thermal Threshold TJTHDN_HYS Junction Thermal Hysteresis Temperature Rising 180 °C 25 °C Notes: 3. All voltages are specified with respect to the corresponding AGND pin. 4. Characterization value. Not tested in production. 5. GH is an internal pin. Rev. 2.0 May 2020 www.aosmd.com Page 7 of 18 AOZ5117QI Logic Table and Timing Diagrams Table 1. Input Control Truth Table DISB# SMOD#(6) PWM(1) GH (Not a Pin) GL L X X L L H X H H L H X L L H H Tri-State Tri-State L ZCD(7) H H Tri-State L ZCD(7) H L Tri-State L L(8) Notes: 6. PWM input is driven to Tri−State with internal divider resistors when SMOD# is driven to Tri−State and PWM input is not driven externally. 7. GL goes low following 80 ns de−bounce time, 220 ns blanking time and then VSWH exceeding ZCD threshold. 8. There is no delay before GL goes low. VPWMH PWM VPWML tPDLL tPDHL GL 1V 1V tPDLU 90% VSWH tPDHU 1V 1V Figure 1. PWM Logic Input Timing Diagram Rev. 2.0 May 2020 www.aosmd.com Page 8 of 18 AOZ5117QI Logic Table andTiming Diagrams (Continued) Inductor Current PWM GH ZCD detects GL goes low GL 300ns ZCD detects after blanking time GL goes low 300ns 300ns ZCD blanking time expires 300ns ZCD blanking time expires Figure 2. PWM Tri-State Input Logic Timing Diagram, SMOD# = 5V Inductor Current PWM GH GL SMOD# trigger GL to go low SMOD# ignored if GH is high GL goes high only GH goes low SMOD# Figure 3. SMOD# Logic Timing Diagram Rev. 2.0 May 2020 www.aosmd.com Page 9 of 18 AOZ5117QI Typical Performance Characteristics 96% 16 94% 14 92% 12 90% 88% VIN=12V, Vo=1.8V, Fsw=600k 86% VIN=12V, Vo=1.8V, Fsw=750k 84% 80% 10 15 20 25 30 40 35 VIN=19V, Vo=1.8V, Fsw=750k 8 6 4 VIN=19V, Vo=1.8V, Fsw=750k 5 VIN=12V, Vo=1.8V, Fsw=750k 10 VIN=19V, Vo=1.8V, Fsw=600k 82% VIN=12V, Vo=1.8V, Fsw=600k VIN=19V, Vo=1.8V, Fsw=600k Power Loss (W) Efficiency (%) TA = 25°C, VIN = 12V, VOUT = 1V, PVCC = VCC = 5V, unless otherwise specified. 2 45 50 0 55 5 10 15 20 Output Current (A) 25 30 35 40 45 50 55 Output Current (A) Figure 4. Efficiency vs. Output Current, VOUT = 1.8V Figure 5. Power Loss vs. Output Current, VOUT = 1.8V 94% 16 92% 14 90% 12 Power Loss (W) Efficiency (%) VIN=12V, Vo=1V, Fsw=600k 88% 86% VIN=12V, Vo=1V, Fsw=600k 84% VIN=12V, Vo=1V, Fsw=750k 78% 5 10 15 20 25 30 35 VIN=19V, Vo=1V, Fsw=750k 8 6 4 VIN=19V, Vo=1V, Fsw=750k 80% VIN=19V, Vo=1V, Fsw=600k 10 VIN=19V, Vo=1V, Fsw=600k 82% VIN=12V, Vo=1V, Fsw=750k 2 40 45 50 0 55 5 10 15 20 Output Current (A) Figure 6. Efficiency vs. Output Current, VOUT = 1.0V 35 40 45 50 55 3.2 3.1 2.8 Rising Threshold 3.0 Logic High Threshold 2.4 PWM Voltage (V) VCC Voltage (V) 30 Figure 7. Power Loss vs. Output Current, VOUT = 1.0V 3.2 2.9 2.8 2.7 Falling Threshold 2.6 2.0 Tri-State Window 1.6 1.2 0.8 2.5 2.4 - 50 25 Output Current (A) Logic Low Threshold 0.4 - 30 -10 10 30 50 70 90 110 130 150 Temperature (°C) 0.0 - 50 Figure 8. UVLO (VCC) Threshold vs. Temperature Rev. 2.0 May 2020 www.aosmd.com - 30 - 10 10 30 50 70 Temperature (°C) 90 110 130 150 Figure 9. PWM Threshold vs. Temperature Page 10 of 18 AOZ5117QI Typical Performance Characteristics TA = 25°C, VIN = 12V, VOUT = 1V, PVCC = VCC = 5V, unless otherwise specified. 3.2 3.2 2.8 2.8 Logic High Threshold 2.0 Mid-State Window 1.6 Logic HighThreshold 2.4 PWM Voltage (V) SMOD# Voltage (V) 2.4 1.2 2.0 1.6 Tri-State Window 1.2 0.8 0.8 Logic Low Threshold 0.4 0.0 -50 -30 -10 10 30 50 70 Logic Low Threshold 0.4 90 110 130 0.0 4.5 150 4.6 4.7 4.8 Figure 10. SMOD# Threshold vs. Temperature 10000.0 5.1 5.2 5.3 5.4 5.5 Figure 11. PWM Threshold vs. VCC Voltage 10µs RDS(ON) limited 10.0 10ms 1.0 IDM limited 1000.0 IDM limited Drain Current, ID (A) Drain Current, ID (A) 5.0 10000.0 1000.0 100.0 4.9 VCC Voltage (V) Temperature (°C) 100.0 R DS(ON) limited 10µs 10.0 10ms 1.0 0.1 0.1 TA = 25°C TA = 25°C 0.0 0.01 0.1 1 10 100 0.0 0.01 Figure 12. High-Side MOSFET SOA Rev. 2.0 May 2020 0.1 1 10 100 Drain - Source Voltage, VDS (V) Drain - Source Voltage, VDS (V) Figure 13. Low-Side MOSFET SOA www.aosmd.com Page 11 of 18 AOZ5117QI Application Information Disable (DISB#) Function AOZ5117QI is a fully integrated power module designed to work over an input voltage range of 4.5V to 25V with a separate 5V supply for gate drive and internal control circuitry. The MOSFETs are individually optimized for efficient operation on both High-Side and Low-Side for a low duty cycle synchronous buck converter. High current MOSFET Gate Drivers are integrated in the package to minimize parasitic loop inductance for optimum switching efficiency. The AOZ5117QI can be enabled and disabled through DISB# (Pin 30). The driver output is disabled when DISB# input is connected to AGND. The module would be in standby mode with low quiescent current of less than 1uA. The module will be active when DISB# is connected to VCC Supply. The driver output will follow PWM input signal. A weak pull-down resistor is connected between DISB# and AGND. Powering the Module and the Gate Drives An external supply PVCC = 5V is required for driving the MOSFETs. The MOSFETs are designed with optimally customized gate threshold voltages to achieve the most advantageous compromise between high switching speed and minimal power loss. The integrated gate driver is capable of supplying large peak current into the LowSide MOSFET to achieve fast switching. A ceramic bypass capacitor of 1F or higher is recommended from PVCC (Pin 29) to PGND (Pin 28). The control logic supply VCC (Pin 3) can be derived from the gate drive supply PVCC (Pin 29) through an RC filter to bypass the switching noise (See Typical Application Circuit). The boost supply for driving the High-Side MOSFET is generated by connecting a small capacitor (100nF) between the BOOT (Pin 5) and the switching node PHASE (Pin 7). It is recommended that this capacitor CBOOT should be connected to the device across Pin 5 and Pin 7 as closely as possible. A bootstrap diode is integrated into the device to reduce external diode component count. An optional resistor RBOOT in series with CBOOT between 1Ω to 5Ω can be used to slow down the turn on speed of the High-Side MOSFET to achieve both short switching time and low VSWH switching node spikes at the same time. Under-voltage LockOut AOZ5117QI starts up to normal operation when VCC rises above the Under-Voltage LockOut (UVLO) threshold voltage. The UVLO release is set at 3.1V typically. Since the PWM control signal is provided from an external controller or a digital processor, extra caution must be taken during start up. AOZ5117QI must be powered up before PWM input is applied. Normal system operation begins with a soft start sequence by the controller to minimize in-rush current during start-up. Powering the module with a full duty cycle PWM signal may lead to many undesirable consequences due to excessive power. AOZ5117QI provides some protections such as UVLO and thermal monitor. For system level protection, the PWM controller should monitor the current output and protect the load under all possible operating and transient conditions. Rev. 2.0 May 2020 Power up sequence design must be implemented to ensure proper coordination between the module and external PWM controller for soft start and system enable/ disable. It is recommended that the AOZ5117QI should be disabled before the PWM controller is disabled. This would ensure AOZ5117QI will be operating under the recommended conditions. Input Voltage VIN AOZ5117QI is rated to operate over a wide input range from 4.5V to 25V. For high current synchronous buck converter applications, large pulse current at high frequency and high current slew rates (di/dt) will be drawn by the module during normal operation. It is strongly recommended to place a bypass capacitor very close to the package leads at the input supply (VIN). Both X7R or X5R quality surface mount ceramic capacitors are suitable. The High-Side MOSFET is optimized for fast switching by using a low gate charge (QG) device. When the module is operated at high duty cycle ratio, conduction loss from the High-Side MOSFET will be higher. The total power loss for the module is still relatively low but the High-Side MOSFET higher conduction loss may have higher temperature. The two MOSFETs have their own exposed pads and PCB copper areas for heat dissipation. It is recommended that worst case junction temperature be measured for both High-Side MOSFET and Low-Side MOSFET to ensure that they are operating within Safe Operating Area (SOA). PWM Input AOZ5117QI is compatible with 3V and 5V (CMOS) PWM logic. Refer to Figure 1 for PWM logic timing and propagation delays diagram between PWM input and the MOSFET gate drives. AOZ5117QI is compatible with 3V and 5V (CMOS) PWM logic. The PWM is also compatible with Tri-State input. When the PWM output from the external PWM controller is in high impedance or not connected, both High-Side and Low-Side MOSFETs are turned off and VSWH is in high impedance state. Table 2 shows the thresholds level for high-to-low and low-to-high transitions as well as TriState window. www.aosmd.com Page 12 of 18 AOZ5117QI There is a Holdoff Delay between the corresponding PWM Tri-State signal and the MOSFET gate drivers to prevent spurious triggering of Tri-State mode which may be caused by noise or PWM signal glitches. The Holdoff Delay is typically 330ns. Table 2. PWM Input and Tri-State Thresholds Thresholds  VPWMH VPWML VTRIH VTRIL AOZ5117QI 2.65V 0.70V 1.40V 2.00V Note: See Figure 2 for propagation delays and Tri-State window. When SMOD# is low, the module can operate in Discontinuous Conduction Mode (DCM). The High-Side MOSFET gate drive output is not affected but Low-Side MOSFET will enter diode emulation mode. The LowSide MOSFET signal is dependent on the PWM signal level and not responding to ZCD signal. Table 4. Logic Table when SMOD# = Low PWM When SMOD# is high, the module will operate in Continuous Conduction Mode (CCM). The Driver logic will use the PWM signal and generate both the High-Side and Low-Side complementary gate drive outputs with minimal anti-overlap delays to avoid cross conduction. When PWM input is at Tri-State level, the driver logic will enter ZCD mode to turn off Low-Side MOSFET if load current crosses zero level. Table 3. Logic Table when SMOD# = High PWM SMOD# GH GL H H H L Tri-State H L ZCD L H L H GH GL H L H L Tri-State L L L L L L H Diode Mode Emulation of Low-Side MOSFET (SMOD#) AOZ5117QI can be operated in the diode emulation or pulse skipping mode using SMOD# (Pin 2). This enables the converter to operate in asynchronous mode during start up, light load, or under pre-bias conditions. SMOD# Gate Drives AOZ5117QI has an internal high current high speed driver that generates the floating gate driver for the High-Side MOSFET and a complementary driver for the Low-Side MOSFET. An internal shoot through protection scheme is implemented to ensure that both MOSFETs cannot be turned on at the same time. The operation of PWM signal transition is illustrated as below. 1) PWM from logic Low to logic High When the falling edge of Low-Side Gate Driver output GL goes below 1V, the blanking period is activated. After a pre-determined value (tPDHU), the complementary HighSide Gate Driver output GH is turned on. 2) PWM from logic High to logic Low When the falling edge of switching node VSWH goes below 1V, the blanking period is activated. After a predetermined value (tPDHL), the complementary Low-Side Gate Driver output GL is turned on. This mechanism prevents cross conduction across the input bus line VIN and PGND. The anti-overlap circuit monitors the switching node VSWH to ensure a smooth transition between the two MOSFETs under any load transient conditions. Thermal Warning (THWN) The driver IC temperature is internally monitored and a thermal warning flag, at THWN (Pin 31), is asserted when the temperature exceeds 150°C. The warning flag is reset when the temperature drops below 120°C. THWN is an open drain output that is pulled to AGND when the temperature exceeds the thermal warning threshold. The AOZ5117QI also incorporates thermal shutdown protection that shuts down the device when the IC temperature exceeds 180°C. Thermal shutdown is reset when the temperature drops below 155°C. Rev. 2.0 May 2020 www.aosmd.com Page 13 of 18 AOZ5117QI PCB Layout Guidelines AOZ5117QI is a high current module rated for operation up to 2MHz. This requires high switching speed to keep the switching losses and device temperatures within limits. An integrated gate driver within the package eliminates driver-to-MOSFET gate pad parasitic of the package or on PCB. To achieve high switching speeds, high levels of slew rate (dv/dt and di/dt) will be present throughout the power train which requires careful attention to PCB layout to minimize voltage spikes and other transients. As with any synchronous buck converter layout, the critical requirement is to minimize the path of the primary switching current loop formed by the High-Side MOSFET, Low-Side MOSFET, and the input bypass capacitor CIN. The PCB design is greatly simplified by the optimization of the AOZ5117QI pin out. The power inputs of VIN and PGND are located adjacent to each other and the input bypass capacitors CIN should be placed as close as possible to these pins. The area of the secondary switching loop is formed by Low-Side MOSFET, output inductor L1, and output capacitor COUT is the next critical requirement. This requires second layer or “Inner 1” to be the PGND plane. VIAs should then be placed near PGND pads. While AOZ5117QI is a highly efficient module, it still dissipates a significant amount of heat under high power conditions. Special attention is required for thermal design. MOSFETs in the package are directly attached to individual exposed pads (VIN and PGND) to simplify thermal management. Both VIN and VSWH pads should be attached to large areas of PCB copper. Thermal relief pads should be placed to ensure proper heat dissipation to the board. An inner power plane layer dedicated to VIN, typically the high voltage system input, is desirable and VIAs should be provided near the device to connect the VIN pads to the power plane. Significant amount of heat can also be dissipated through multiple PGND pins. A large copper area connected to the PGND pins in addition to the system ground plane through VIAs will further improve thermal dissipation. As shown on Figure 14, the top most layer of the PCB should comprise of wide and exposed copper area for the primary AC current loop which runs along VIN pad originating from the input capacitors C10, C11, and C12 that are mounted to a large PGND pad. They serve as thermal relief as heat flows down to the VIN exposed pad that fan out to a wider area. Adding VIAs will only help transfer heat to cooler regions of the PCB board through the other layers beneath but serve no purpose to AC activity as all the AC current sees the lowest impedance on the top layer only. Rev. 2.0 May 2020 Figure 14. Top Layer of Demo Board, VIN, VSWH and PGND Copper Pads As the primary and secondary (complimentary) AC current loops move through VIN to VSWH and through PGND to VSWH, large positive and negative voltage spikes appear at the VSWH terminal which are caused by the large internal di/dt produced by the package parasitic. To minimize the effects of this interference at the VSWH terminal, at which the main inductor L1 is mounted, size just enough for the inductor to physically fit. The goal is to employ the least amount of copper area for this VSWH terminal, only enough so the inductor can be securely mounted. To minimize the effects of switching noise coupling to the rest of the sensitive areas of the PCB, the area directly underneath the designated VSWH pad or inductor terminal is voided and the shape of this void is replicated descending down through the rest of the layers. Refer to Figure 15. Figure 15. Bottom Layer of PCB Positioning VIAs through the landing pattern of the VIN and PGND thermal pads will help quickly facilitate the thermal build-up and spread the heat much more quickly towards the surrounding copper layers descending from www.aosmd.com Page 14 of 18 AOZ5117QI the top layer. (See RECOMMENDED PATTERN AND VIA PLACEMENT section). LANDING The exposed pads dimensional footprint of the 5x5 QFN package is shown on the package dimensions page. For optimal thermal relief, it is recommended to fill the PGND and VIN exposed landing pattern with 10mil diameter VIAs. 10mil diameter is a commonly used VIA diameter as it is optimally cost effective based on the tooling bit used in manufacturing. Each via is associated with a 20mil diameter keep out. Maintain a 5mil clearance (127um) around the inside edge of each exposed pad in case of solder overflow, which could potentially short with the adjacent exposed thermal pad. Rev. 2.0 May 2020 www.aosmd.com Page 15 of 18 AOZ5117QI Package Dimensions, QFN5x5A-31L RECOMMENDED LAND PATTERN UNIT: mm NOTE CONTROLLING DIMENSION IS MILLIMETER. CONVERTED INCH DIMENSIONS ARE NOT NECESSARILY EXACT. Rev. 2.0 May 2020 www.aosmd.com Page 16 of 18 AOZ5117QI Tape and Reel Drawing, QFN5x5A-31L Rev. 2.0 May 2020 www.aosmd.com Page 17 of 18 AOZ5117QI Part Marking AOZ5117QI (5mm x 5mm QFN) CA00 YWLT Year Code & Week Code Part Number Code Assembly Lot Code LEGAL DISCLAIMER Applications or uses as critical components in life support devices or systems are not authorized. AOS does not assume any liability arising out of such applications or uses of its products. AOS reserves the right to make changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the product for their intended application. Customer shall comply with applicable legal requirements, including all applicable export control rules, regulations and limitations. AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at: http://www.aosmd.com/terms_and_conditions_of_sale LIFE SUPPORT POLICY ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 2.0 May 2020 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 18 of 18