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AOZ5278QI

AOZ5278QI

  • 厂商:

    AOSMD(美国万代)

  • 封装:

    PowerWFQFN39 模块

  • 描述:

    降压 开关稳压器 IC 正 1 输出 55A 39-PowerWFQFN 模块

  • 数据手册
  • 价格&库存
AOZ5278QI 数据手册
AOZ5278QI ALPHA & OMEGA SEMICONDUCTOR High-Current, High-Performance Smart Power Stage General Description Features The AOZ5278QI is a general-purpose Smart Power Stage (SPS) consisting of two asymmetrical MOSFETs and an integrated driver for high current, high frequency DC-DC converters. The AOZ5278QI provides an output voltage signal (IMON), which represents the real-time module current with a gain of 5 mV/A. The IMON signal can be directly used to replace inductor DCR sensing or resistor sensing in multiphase voltage regulator systems without the need for temperature compensation. The AOZ5278QI also includes an accurate module temperature monitor (TMON). TMON is a voltage sourced signal with a gain of 8 mV/°C. The MOSFETs are individually optimized for operation in the synchronous buck configuration. The High-Side (HS) MOSFET is optimized to achieve low capacitance and gate charge for fast switching with low duty cycle operation. The Low-Side (LS) MOSFET has ultra-low ON resistance to minimize conduction loss. The standard 5 mm x 6 mm QFN package is optimally designed to minimize parasitic inductance for minimal EMI signature. • • • • • • • • • • • • • 3 V to 20 V power supply range 30 V HS MOSFET provides better system ruggedness 55 A continuous output current Up to 100 A for 10 ms on pulse Up to 150 A for 10 µs on pulse Optimized for switching frequency up to 1 MHz Integrated current monitor (5 mV/A) with 5% accuracy over temperature Integrated temperature monitor (8 mV/°C) with 2% accuracy Fault Indicator Under-Voltage LockOut (UVLO) on VCC Under-Voltage LockOut (UVLO) on VIN High-Side MOSFET Over-Current and Short-Circuit Protection Zero Current Detect Function (ZCD) Over Temperature Protection (OTP) Standard QFN5x6-39L package - Applications • • • Server systems High end CPU/GPU power stage Communications Infrastructure Green Product Rev. 1.0 November 2022 www.aosmd.com Page 1 of 7 ALPHA & OMEGA AOZ5278QI SEMICONDUCTOR Typical Application 3V ~ 20V OCSET/ZCD VIN BOOT VOS EN PWM PWM Controller Driver Logic and Delay TMON/FLT IMON REFIN VSWH L1 VOUT COUT GL VCC Rev. 1.0 November 2022 CIN PHASE LS Driver AGND 5V CBOOT HS Driver CVCC PVCC PGND CPVCC www.aosmd.com PGND Page 2 of 7 ALPHA & OMEGA AOZ5278QI SEMICONDUCTOR Ordering Information Part Number Ambient Temperature Range Package Environmental AOZ5278QI -40 °C to 125 °C QFN5x6-39L RoHS AOS products are offered in packages with Pb-free plating and compliant to RoHS standards. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. REFIN IMON OCSET/ZCD TMON/FLT EN PWM BOOT PHASE PHASE VIN Pin Configuration 39 38 37 36 35 34 33 32 31 30 VOS 1 29 VIN AGND 2 28 VIN 27 VIN PVCC 4 26 VIN PGND 5 25 VIN 24 PGND 23 PGND 22 PGND 21 PGND 20 PGND VCC 3 GL PGND VIN 40 25 GL 6 41 PGND 7 PGND 20 PGND 8 13 14 15 16 17 18 19 VSWH VSWH VSWH VSWH VSWH VSWH VSWH 12 VSWH 11 VSWH 10 VSWH PGND 9 QFN5x6-39L (Top Transparent View) Rev. 1.0 November 2022 www.aosmd.com Page 3 of 7 ALPHA & OMEGA AOZ5278QI SEMICONDUCTOR Pin Description Pin Number Pin Name 1 VOS 2 AGND 3 VCC 5 V Bias for Internal Logic Blocks. Ensure to position a 1 µF MLCC directly between VCC and AGND (Pin 2). 4 PVCC 5 V Power Rail for High-Side and Low-Side MOSFET Drivers. Ensure to position a 1 µF MLCC directly between PVCC and PGND (Pin 5). 5, 40 PGND Power Ground for High-Side and Low-Side MOSFET Gate Drivers. Ensure to connect 1 µF MLCC directly between PGND and PVCC (Pin 4). 6, 41 GL 7, 8, 9, 20, 21, 22, 23, 24 PGND Power Ground pin for power stage (Source connection of Low-Side MOSFET). 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 VSWH Switching node connected to the Source of High-Side MOSFET and the Drain of Low-Side MOSFET. 25, 26, 27, 28, 29, 30 VIN 31, 32 PHASE This pin is dedicated for bootstrap capacitor AC return path connection from BOOT (Pin 33). 33 BOOT High-Side MOSFET Gate Driver supply rail. Connect a 100 nF ceramic capacitor between BOOT and the PHASE (Pin 31 and 32). 34 PWM PWM input signal from Controller IC. This input is compatible with 3.3 V and 5 V Tri-State logic levels. 35 EN 36 37 TMON/FLT Pin Function Output voltage sense. Signal Ground. Low-Side MOSFET Gate connection. This is for test purposes only. Power stage High Voltage Input (Drain connection of High-Side MOSFET). Output enable pin. When this pin is pulled to a logic low level, the IC disables most blocks. EN=HIGH enables all blocks inside IC and requires 4 µs power up time. Temperature Monitor and Fault Flag Pin. TMON/FLT will be pulled HI (~ 3.3 V) or LOW (0 V) to indicate a fault condition (see Table 5). For multi-phase application, the TMON/FLT pin can be connected together as a common bus. The highest voltage representing the highest temperature among all phases will be sent to the PWM controller. No more than 470 pF total capacitance can be directly connected across TMON/FLT and AGND (Pin 2). A higher capacitance load is allowed with a series resistor (~ 1 kΩ) for up to 1 nF. At 0°C and in normal operation, the output voltage is 0.6 V with a temperature coefficient value of 8 mV/°C. There is an internal pull up source to 3.3 V when a fault condition occurs. Setting control for OCP limit threshold and Zero Cross Detect function (ZCD). OCP limit threshold is detected and latched 120 µs after device enabled. Refer to Table 3 for the resistor value for each OCSET/ZCD current limit threshold level. After 120 µs, the OCP limit is set and this pin becomes ZCD control only. ZCD is active when this pin is floating or pulled HI. 38 IMON Current Monitor output signal referenced to REFIN (Pin 39). Connect the IMON output to the appropriate Current Sense input of the controller. No more than 47 pF capacitance can be directly connected across IMON and REFIN pins. With a 100 Ω series resistor, up to 470 pF may be used. 39 REFIN Input for external reference voltage for IMON (Pin 38). This voltage should be between 0.7 V and 2.0 V. Nominal value is 1.2 V. Place a low ESR ceramic capacitor (~ 0.1 µF) from this pin to AGND (Pin 2). Connect REFIN to the appropriate Current Sense Reference output from the controller. Rev. 1.0 November 2022 www.aosmd.com Page 4 of 20 ALPHA & OMEGA AOZ5278QI SEMICONDUCTOR Package Dimensions, QFN5x6-39L Rev. 1.0 November 2022 www.aosmd.com Page 5 of 7 ALPHA & OMEGA AOZ5278QI SEMICONDUCTOR Tape and Reel Dimensions, QFN5x6-39L Rev. 1.0 November 2022 www.aosmd.com Page 6 of 7 ALPHA & OMEGA AOZ5278QI SEMICONDUCTOR Part Marking AOZ5278QI (QFN5x6) AP00 Y W LT Date & Week Code Part Number Code Assembly Lot Code & Assembly Site T (with the dot) indicates Site 2 LEGAL DISCLAIMER Applications or uses as critical components in life support devices or systems are not authorized. Alpha and Omega Semiconductor does not assume any liability arising out of such applications or uses of its products. AOS reserves the right to make changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the product for their intended application. Customer shall comply with applicable legal requirements, including all applicable export control rules, regulations and limitations. AOS’s products are provided subject to AOS’s terms and conditions of sale which are set forth at: http://www.aosmd.com/terms_and_conditions_of_sale LIFE SUPPORT POLICY ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 1.0 November 2022 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 7 of 7
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