AX88178L

AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller Features • • • • • • • • • • Single chip USB to 10/100/1000 Gigabit Ethernet and HomePNA and HomePlug Network Controller USB specification 1.0 and 1.1 and 2.0 compliant Supports USB Full and High Speed modes with Bus power capability Supports 4 endpoints on USB interface High performance packet transfer rate over USB bus using proprietary burst transfer mechanism (submitted for US patent application) IEEE 802.3, 802.3u, and 802.3ab (10BASE-T, 100BASE-TX, and 1000BASE-T) compatible Embedded 20KB SRAM for RX packet buffering and 20KB SRAM for TX packet buffering Supports both full-duplex and half-duplex operation in Fast Ethernet Provides MII/GMII/RGMII interfaces for Ethernet PHY interface and MII interface for HomePNA/ HomePlug PHY interface Supports Jumbo packet of up to 9KB Document No: AX88178-02/4/20/2004 • • • • • • • • Supports Suspend mode and Remote Wakeup via Link-up, Magic packet, or external pin Optional PHY power down during Suspend mode Supports 256/512 bytes (93c56/93c66) of serial EEPROM (for storing USB Descriptors) Supports automatic loading of Ethernet ID, USB Descriptors and Adapter Configuration from EEPROM after power-on initialization External PHY loop-back diagnostic capability Integrates on-chip 3.3V to 2.5V voltage regulator and requires only single power supply: 3.3V Small form factor with 128-pin LQFP package 12MHz clock input from either crystal or oscillator source *IEEE is a registered trademark of the Institute of Electrical and Electronic Engineers, Inc. *All other trademarks and registered trademark are the property of their respective holders. Product Description The AX88178 USB to 10/100/1000 Gigabit Ethernet/HomePNA/HomePlug controller is a high performance and highly integrated ASIC with embedded 40KB SRAM for packet buffering. It enables low cost and affordable Gigabit Ethernet network connection to desktop and notebook PC using popular USB ports that are built-in to many PC today. It has an USB interface to communicate with USB host controller and is compliant with USB specification V1.0, V1.1 and V2.0. It implements 10/100/1000Mbps Ethernet LAN function based on IEEE802.3, IEEE802.3u, IEEE802.3ab standards or HomePNA standard. It supports media-independent interface (MII) to simplify the design on implementing Fast Ethernet and HomePNA functions. It also provides gigabit media-independent (GMII) and reduced gigabit media-independent (RGMII) interface for interfacing with Gigabit Ethernet PHY. System Block Diagram RJ45 Magnetic 10/100/1000 Gigabit Ethernet PHY RJ11 Magnetic 1/10 Mbps Home LAN PHY AX88178 USB I/F EEPROM Always contact ASIX for possible updates before starting a design. This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. ASIX ELECTRONICS CORPORATION 2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. FAX: 886-3-579-9558 TEL: 886-3-579-9500 Released Date: 4/16/2004 http://www.asix.com.tw AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller Table of Contents 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 INTRODUCTION .....................................................................................................3 SIGNAL DESCRIPTION..........................................................................................5 FUNCTION DESCRIPTION .....................................................................................8 SERIAL EEPROM MEMORY MAP .........................................................................9 USB CONFIGURATION STRUCTURE .................................................................13 USB COMMANDS.................................................................................................14 ELECTRICAL SPECIFICATIONS .........................................................................25 PACKAGE INFORMATION...................................................................................32 ORDERING INFORMATION .................................................................................33 APPENDIX A: SYSTEM APPLICATIONS ........................................................................33 REVISION HISTORY.........................................................................................................35 List of Figures FIGURE 1: AX88178 BLOCK DIAGRAM ................................................................................................3 FIGURE 2: AX88178 PINOUT DIAGRAM................................................................................................4 FIGURE 3: MULTICAST FILTER EXAMPLE ............................................................................................20 List of Tables TABLE 1: PINOUT DESCRIPTON .............................................................................................................5 TABLE 2: SERIAL EEPROM MEMORY MAP .........................................................................................9 TABLE 3: USB STANDARD COMMAND REGISTER MAP.......................................................................14 TABLE 4: USB VENDOR COMMAND REGISTER MAP ..........................................................................15 TABLE 5: REMOTE WAKEUP TRUTH TABLE ........................................................................................24 2 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 1.0 Introduction 1.1 General Description The AX88178 USB to 10/100/1000 Gigabit Ethernet/HomePNA/HomePlug controller is a high performance and highly integrated ASIC with embedded 40KB SRAM for packet buffering. It enables low cost and affordable Gigabit Ethernet network connection to desktop and notebook PC using popular USB ports that are built-in to many PC today. It has an USB interface to communicate with USB host controller and is compliant with USB specification V1.0, V1.1 and V2.0. It implements 10/100/1000Mbps Ethernet LAN function based on IEEE802.3, IEEE802.3u, IEEE802.3ab standards or HomePNA standard. It supports media-independent interface (MII) to simplify the design on implementing Fast Ethernet and HomePNA functions. It also provides gigabit media-independent (GMII) and reduced gigabit media-independent (RGMII) interface for interfacing with Gigabit Ethernet PHY. The AX88178 needs 12MHz clock for USB operation and 125MHz clock for Gigabit Ethernet operation. It is in 128-pin LQFP low profile package with CMOS process and requires only single 3.3V power supply to operate. 1.2 AX88178 Block Diagram 40KB SRAM Memory Arbiter Gigabit MAC Core MII/GMII/RGMII I/F EECS EECK EEDI EEDO GPIO2~0 SEEPROM Loader I/F General Purpose I/O USB to Ethernet Bridge STA MDC MDIO USB Core and Interface DP/DM DPRS/DMRS Figure 1: AX88178 Block Diagram 3 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 1.3 AX88178 Pinout Diagram The AX88178 is housed in the 128-pin LQFP package. DB AVDDK AVDDK AGND AVDDK AGND NC NC NC NC NC VDDK VDDK GND TXD7 TXD6 TXD5 TXD5 TXD4 VDD2 GND TXD3 TXD2 TXD1 TXD0 VDD2 GND TX_ER TX_EN TXC GTX_CLK NC NC NC NC NC 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD3 GND VDDK GND XIN125M TX_CLK RGMII_EN RX_CLK RX_DV RX_ER RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 CRS COL MDINT VDDK GND MDIO MDC PHYRST_N VDD2 GND LED USB_SPEED_LED GND VDD3 AVDDK AGND NC NC AGND NC NC AVDDK NC AGND AGND AVDDK NC NC AGND AVDDK NC NC CLKSEL CLK60EXT SCAN_ENABLE SCAN_TEST HS_TEST_MODE VDD3 GND AVDD3 AGND AVDD3 DPRS DMRS RPU AGND ASIX AX88178 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DP DM DM RREF AGND AGND AVDD3 XOUT12M XOUT12M XIN12M GND GND VDDK GNDAH GNDAH VDDAH V25 INT_REGULATOR_EN INT_REGULATOR_EN VDD3 GND GND VDDK FORCEFS_N NC TESTSPEEDUP RESET_N EXTWAKEUP_N VBUS EEDO VDD3 GND EEDI EECS EECK GPIO0 GPIO1 GPIO2 Figure 2: AX88178 Pinout Diagram 4 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 2.0 Signal Description The following abbreviations apply to the following pin description table. I2 I3 I5 O2 O3 O5 B Input, 2.5V with 3.3V tolerant Input, 3.3V Input, 3.3V with 5V tolerant Output, 2.5V with 3.3V tolerant Output, 3.3V Output, 3.3V with 5V tolerant Bi-directional I/O B2 B5 PU PD P S Bi-directional I/O, 2.5V with 3.3V tolerant Bi-directional I/O, 3.3V with 5V tolerant Internal Pull Up (75K) Internal Pull Down (75K) Power Pin Schmitt Trigger Table 1: Pinout Descripton Pin Name DP DM DPRS DMRS VBUS XIN12M XOUT12M RREF RPU Pin Description USB Interface B 32 USB 2.0 data positive pin. B 31 USB 2.0 data negative pin. B 36 USB 1.1 data positive pin. Please connect to DP through a 39ohm (+/-1%) serial resistor. B 35 USB 1.1 data negative pin. Please connect to DM through a 39ohm (+/-1%) serial resistor. I5/PD/S 10 VBUS pin input. Please connect to USB bus power. I3 26 12Mhz crystal or oscillator clock input. This clock is needed for USB PHY transceiver to operate. O3 27 12Mhz crystal or oscillator clock output. I 30 For USB PHY’s internal biasing. Please connect to AGND through a 12.1Kohm (+/-1%) resistor. I 34 For USB PHY’s internal biasing. Please connect to AVDD3 (3.3V) through a 1.5Kohm (+/-5%) resistor. Station Management Interface O2 121 Station Management Data Clock output. The timing reference for MDIO. All data transfers on MDIO are synchronized to the rising edge of this clock. The frequency of MDC is 1.5MHz. B2/PU 120 Station Management Data Input/Output. Serial data input/output transfers from/to the PHYs. The transfer protocol conforms to the IEEE 802.3u MII spec. I2/PU 117 Station Management Interrupt input. MII/GMII/RGMII Interface I2 104 Receive Clock. RX_CLK is received from PHY to provide timing reference for the transfer of RXD [7:0], RX_DV, and RX_ER signals on receive direction of MII/GMII/RGMII interface. I2 114, 113, Receive Data. RXD [7:0] is driven synchronously with respect to 112, 111, RX_CLK by PHY. In RGMII mode, only RXD [3:0] is used. 110, 109, 108, 107 I2 105 Receive Data Valid. RX_DV is driven synchronously with respect to RX_CLK by PHY. It is asserted high when valid data is present on RXD [7:0]. In RGMII mode, RX_DV acts as RX_CTL. I2 106 Receive Error. RX_ER is driven synchronously with respect to RX_CLK by PHY. It is asserted high for one or more RX_CLK periods to indicate to the MAC that an error has detected. I2 116 Collision Detected. COL is driven high by PHY when the collision is detected. I2 115 Carrier Sense. CRS is asserted high asynchronously by the PHY when either transmit or receive medium is non-idle. 5 ASIX ELECTRONICS CORPORATION Type Pin No MDC MDIO MDINT RX_CLK RXD [7:0] RX_DV RX_ER COL CRS AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller TX_CLK Transmit Clock in MII mode. TX_CLK is received from PHY to provide timing reference for the transfer of TXD [3:0], TX_EN and TX_ER signals on transmit direction of MII interface. GTX_CLK O2 91 Transmit Clock in GMII mode. GTX_CLK is output to PHY to provide timing reference for the transfer of TXD [7:0], TX_EN and TX_ER signals on transmit direction of GMII interface. TXC O2 90 Transmit Clock in RGMII mode. TXC is output to PHY to provide timing reference for the transfer of TXD [3:0], and TX_EN signals on transmit direction of RGMII interface. TXD [7:0] O2 76, 77, 78, Transmit Data. TXD [7:0] is transitioned synchronously with respect 79, 82, 83, to the rising edge of GTX_CLK in GMII mode or rising edge of 84, 85 TX_CLK in MII mode. In RGMII mode, only TXD [3:0] is used and is transitioned synchronously with respect to TXC clock output pin. TX_EN O2 89 Transmit Enable. TX_EN is transitioned synchronously with respect to the rising edge of GTX_CLK in GMII mode or rising edge of TX_CLK in MII mode. TX_EN is asserted high to indicate a valid TXD [7:0]. In RGMII mode, TX_EN acts as TX_CTL and is transitioned synchronously with respect to TXC clock output pin. TX_ER O2 88 Transmit Coding Error. TX_ER is transitioned synchronously with respect to the rising edge of GTX_CLK in GMII mode or rising edge of TX_CLK in MII mode. When asserted high for one or more GTX_CLK/TX_CLK, the PHY shall emit one or more code-groups that are not part of the valid data or delimiter set somewhere in the frame being transmitted. Serial EEPROM Interface EECK O5 4 EEPROM Clock. EECK is an output clock to EEPROM to provide timing reference for the transfer of EECS, EEDI, and EEDO signals. The frequency of EECK is 187.5Khz. EECS O5 5 EEPROM Chip Select. EECS is asserted high synchronously with respect to rising edge of EECK as chip select signal. EEDI O5 6 EEPROM Data In. EEDI is the serial output data to EEPROM’s data input pin and is synchronous with respect to the rising edge of EECK. EEDO I5/PD 9 EEPROM Data Out. EEDO is the serial input data from EEPROM’s data output pin. Misc. Pins XIN125M I2 101 125Mhz clock input. Connect to a 125Mhz free run clock source when in GMII or RGMII mode. In MII mode, connect to GND through a pull-down resistor. RESET_N I5/PU/S 12 Chip Reset Input. RESET_N pin is active low. When asserted, it puts the entire chip into reset state immediately. After completing reset, EEPROM data will be loaded automatically. EXTWAKEUP_N I5/PU/S 11 Remote-wakeup trigger from external pin. EXTWAKEUP_N should be asserted low for more than 2 cycles of 12MHz clock to be effective. GPIO [2:0] B5/PD 1, 2, 3 General Purpose Input/ Output Pins. These pins are default as input pins after power-on reset. Please use GPIO0 for controlling the power down pin of external Ethernet Phy. PHYRST_N O2 122 PHYRST_N is a tri-stateable output used for resetting external Ethernet PHY. This pin is default in tri-state after power-on reset. If external Ethernet PHY’s reset level is active low, connect this to PHY’s reset pin with a pulled-down resistor. If it’s active high, connect this to PHY with a pulled-up resistor. This way can make sure the external Ethernet PHY stays in reset state before software brings it out of reset. RGMII_EN I3/PD 103 RGMII mode Enable. Setting this pin high sets the Ethernet PHY interface into RGMII mode. Setting this pin low sets the Ethernet PHY interface into MII or GMII mode. I2 102 6 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller FORCEFS_N I3/PU Force USB Full Speed (active low). For normal operation, user should keep this pin NC to enable USB High Speed handshaking process to decide the speed of USB bus. Setting this pin low sets the device to operate at Full speed mode only and disables Chirp K (HS handshaking process). 125 LED indicator: When USB bus is in Full speed, this pin drives high continuously. When USB bus is in High speed, this pin drives low continuously. This pin drives high and low in turn (blinking) to indicate TX data transfer going on whenever the host controller sends bulk out data transfer. 126 USB bus speed LED indicator. When USB bus is in Full speed, this pin drives high continuously. When USB bus is in High speed, this pin drives low continuously. 13 Test pin. For normal operation, user should keep this pin NC. 42 Test pin. For normal operation, user should keep this pin NC. 43 Test pin. For normal operation, user should keep this pin NC. 44 Test pin. For normal operation, user should keep this pin NC. 45 Test pin. For normal operation, user should keep this pin NC. 46 Test pin. For normal operation, user should keep this pin NC. 65 Debug pin. For normal operation, user should connect to AVDDK through a pulled-up resistor. On-chip Regulator Pins 20 On-chip 3.3V to 2.5V voltage regulator enable. Connect this pin to VDDAH directly to enable on-chip regulator. Connect this pin to GNDAH to disable on-chip regulator. 22 3.3V Power supply to on-chip 3.3V to 2.5V voltage regulator. 23 Ground pin of on-chip 3.3V to 2.5V voltage regulator. 21 2.5V voltage output of on-chip 3.3V to 2.5V voltage regulator. Power and Ground Pins 16, 24, 74, Digital Core Power. 2.5V. 99, 118 80, 86, 123 Digital I/O Power. 2.5V. 8, 19, 41, Digital I/O Power. 3.3V. 97, 128 7, 17, 18, Digital Ground. 25, 40, 75, 81, 87, 98, 100, 119, 124, 127 49, 53, 57, Analog Core Power. 2.5V. 64, 66, 68 28, 37, 39 Analog I/O Power. 3.3V. 29, 33, 38, Analog Ground. 50, 54, 55, 60, 63, 67, 69 15 LED O3 USB_SPEED_LE D TESTSPEEDUP HS_TEST_MODE SCAN_TEST SCAN_ENABLE CLK60EXT CLKSEL DB O3 I3/PD I3/PD I3/PD I3/PD I3/PD I3/PD I2 INT_REGULATO R_EN VDDAH GNDAH V25 VDDK VDD2 VDD3 GND I P P P P P P P AVDDK AVDD3 AGND P P P 7 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 3.0 Function Description 3.1 USB Core and Interface The USB core and interface contains an USB 2.0 transceiver, serial interface engine (SIE), USB bus protocol handshaking block, USB standard command, vendor command registers, logic for supporting bulk transfer, and interrupt transfer, etc. The USB interface is used to communicate with USB host controller and is compliant with USB specification V1.0, V1.1 and V2.0. 3.2 Gigabit MAC Core The gigabit MAC core supports IEEE 802.3, 802.3u, and 802.3ab MAC sub-layer functions, such as basic MAC frame receive and transmit, CRC checking and generation, filtering, forwarding, flow-control in full-duplex mode, and collision-detection and handling in half-duplex mode, etc. It provides gigabit media-independent (GMII) and reduced gigabit media-independent (RGMII) interface for interfacing with Gigabit Ethernet PHY. 3.3 Station Management (STA) The station management interface provides a simple, two-wire, serial interface to connect to a managed PHY device for the purposes of controlling the PHY and gathering status from the PHY. The station management interface allows communicating with multiple PHY devices at the same time by identifying the managed PHY with 5-bit, unique Phy ID. 3.4 Memory Arbiter The memory arbiter block is responsible for storing received MAC frames into on-chip SRAM (packet buffer) and then forwarding to USB bus upon request from USB host via bulk in transfer. It also monitors packet buffer usage in full-duplex mode for triggering PAUSE frame transmission out on TX direction. The memory arbiter block is also responsible for storing MAC frames received from USB host via bulk out transfer and waiting to be transmitted out towards Ethernet network. 3.5 USB to Ethernet Bridge The USB to Ethernet bridge block is responsible for converting Ethernet MAC frame into USB packets or vice-versa. This block supports proprietary burst transfer mechanism (submitted for US patent application) to offload software burden and to offer very high packet transfer throughput over USB bus. 3.6 Serial EEPROM Loader The serial EEPROM loader is responsible for reading configuration data automatically from external serial EEPROM after power-on reset. 3.7 General Purpose I/O There are 3 general purpose I/O pins provided by this ASIC. 8 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 4.0 Serial EEPROM Memory Map EEPROM OFFSET 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H-1FH Length of High-Speed Device Descriptor (bytes) Length of High-Speed Configuration Descriptor (bytes) Node ID 1 Node ID 3 Node ID 5 Language ID High Byte Length of Manufacture String (bytes) Length of Product String (bytes) Length of Serial Number String (bytes) Length of Configuration String (bytes) Length of Interface 0 String (bytes) Length of Interface 1/0 String (bytes) Length of Interface 1/1 String (bytes) Phy Register Offset for Interrupt Endpoint Max Packet Size High Byte Secondary Phy_Type [7:5] and Phy_ID [4:0] Pause Frame High Water Mark Length of Full-Speed Device Descriptor (bytes) Length of Full-Speed Configuration Descriptor (bytes) Reserved HIGH BYTE Reserved Flag EEPROM Offset of High-Speed Device Descriptor EEPROM Offset of High-Speed Configuration Descriptor Node ID 0 Node ID 2 Node ID 4 Language ID Low Byte EEPROM Offset of Manufacture String EEPROM Offset of Product String EEPROM Offset of Serial Number String EEPROM Offset of Configuration String EEPROM Offset of Interface 0 String EEPROM Offset of Interface 1/0 String EEPROM Offset of Interface 1/1 String Phy Register Offset for Interrupt Endpoint Max Packet Size Low Byte Primary Phy_Type [7:5] and Phy_ID [4:0] Pause Frame Low Water Mark EEPROM Offset of Full-Speed Device Descriptor EEPROM Offset of Full-Speed Configuration Descriptor Reserved LOW BYTE Word Count For Preload Table 2: Serial EEPROM Memory Map 9 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 4.1 Detailed Description The following sections provide detailed description for some of the field in serial EEPROM memory map, for other fields not covered here, please refer to AX88178L application note for more details. 4.1.1 Word Count for Preload (00h) The number of words to be preloaded by the EEPROM loader = 15h. 4.1.2 Flag (01h) Bit 15 Bit 7 TACE Bit 14 Bit 6 RDCE Bit 13 Bit 12 Reserved Bit 5 Bit 4 SCPR DCK Bit 11 Bit 3 1 Bit 10 Bit 2 RWU Bit 9 TDPE Bit 1 Reserved Bit 8 CEM Bit 0 SP SP: Self-Power (for USB GetStatus) 1: Self power. 0: Bus power. RWU: Remote Wakeup support. 1: Indicate that this device supports Remote Wakeup. 0: Not support. DCK: Disable Chirp K. 1: Disabled. 0: Enable. SCPR: Software Control PHY Reset. 1: The PRL and PRTE bits of Software Reset Register control the PHYRST_N output level. 0: The USB reset on USB bus and PRTE bit of Software Reset Register control the PHYRST_N output level. RDCE: RX Drop CRC Enable. 1: CRC byte is dropped on received MAC frame forwarding to host. 0: CRC byte is not dropped. TACE: TX Append CRC Enable. 1: CRC byte is generated and appended by the ASIC for every transmitted MAC frame. 0: CRC byte is not appended. CEM: Capture Effective Mode. 1: Capture effective mode enable. 0: Disabled. TDPE: Test Debug Port Enable. 1: Enable test debug port for chip debug purpose. 0: Disable test debug port and the chip operate in normal function mode Bit 1, 10~15: Reserved. 4.1.3 Node ID (04~06h) The Node ID 0 to 5 bytes represent the MAC address of the device, for example, if MAC address = 01-23-45-67-89-ABh, then Node ID 0 = 01, Node ID 1 = 23, Node ID 2 = 45, Node ID 3 = 67, Node ID 4 = 89, and Node ID 5 = AB. 10 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 4.1.4 Phy Register Offset for Interrupt Endpoint (0Fh) Bit 15 Bit 7 Bit 14 Reserved Bit 6 Reserved Bit 13 Bit 5 Bit 12 Bit 4 Bit 11 Bit 10 Bit 9 Phy Register Offset 1 Bit 3 Bit 2 Bit 1 Phy Register Offset 2 Bit 8 Bit 0 Phy Register Offset 1: Fill in Phy’s Register Offset of Primary Phy here. Upon each Interrupt Endpoint issued, its register value will be reported in byte# 5 and 6 of Interrupt Endpoint packet. Phy Register Offset 2: Fill in Phy’s Register Offset of Primary Phy here. Upon each Interrupt Endpoint issued, its register value will be reported in byte# 7 and 8 of Interrupt Endpoint packet. 4.1.5 Max Packet Size High/Low Byte (10h) Fill in this field the maximum RX/TX MAC frame size supported by this ASIC when Jumbo Frame mode is disabled. The number must be even number in terms of byte and should be less than or equal to 2500 bytes. When Jumbo Frame mode is enabled, the maximum MAC frame size is fixed to 9216 bytes and this setting is ignored. 4.1.6 Primary/Secondary Phy_Type and Phy_ID (11h) The 3 bits Phy_Type field for both Primary and Secondary Phy is defined as follows, 3’b000: 10/100 Ethernet Phy or 1M HOME Phy (Link reports as normal case). 3’b100: Special case 1 (Link reports as always active). 3’b001: Gigabit Ethernet Phy. 3’b111: non-supported Phy. For example, the High Byte value of “E0h” in EEPROM offset of “11h” means that secondary Phy is not supported. 4.1.7 Pause Frame High Water and Low Water Mark (12H) When operating in full-duplex mode, correct setting of this field is very important and can affect the overall packet receive throughput performance in a great deal. The High Water Mark is the threshold to trigger sending of Pause frame and the Low Water Mark is the threshold to stop sending of Pause frame. Note that each free buffer count here represents 256 bytes of packet storage space in SRAM. Total free buffer count = 80 Stop sending Pause frame when free buffer > Low Water Mark Start sending Pause frame when free buffer < High Water Mark 0 When Jumbo frame mode is not disabled, user can fill in a smaller value in High Water Mark and a larger value in Low Water Mark fields to have more efficient use of SRAM for packet buffering. 11 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 4.1.8 Power-Up Steps After power-on reset, the ASIC will automatically perform following steps to the Ethernet Phys via MDC/MDIO lines, 1. Write to Phy_ID of 00h with Phy register offset 00h to power down all Phys attached to station management interface. 2. Write to Primary Phy_ID with Phy register offset 00h to power down Primary Phy. 3. Write to Secondary Phy_ID with Phy register offset 00h to power down Secondary Phy. 12 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 5.0 USB Configuration Structure 5.1 USB Configuration The AX88178 supports 1 Configuration only. 5.2 USB Interface The AX88178 supports 2 interfaces, the interface 0 is Data Interface and interface 1 is for Communication Interface. 5.3 USB Endpoints The AX88178 supports following 4 endpoints: Endpoint 0: Control endpoint. It is used for configuring the device, e.g., standard commands and vendor commands, etc. Endpoint 1: Interrupt endpoint. It is used for reporting status. Endpoint 2: Bulk Out endpoint. It is used for transmitting Ethernet Packet. Endpoint 3: Bulk In endpoint. It is used for receiving Ethernet Packet. 13 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 6.0 USB Commands There are three command groups for Endpoint 0 (Control Endpoint) in AX88178: The USB standard commands The USB vendor commands The USB Communication Class commands 6.1 USB Standard Commands The Language ID is 0x0904 for English PPLL means buffer length CC means configuration number I I means Interface number AA means Device Address Setup Command 8006_00 01 00 00 LLPP 8006_0002 0000_LLPP 8006_0003_0000_LLPP 8006_0103_0904_LLPP 8006_0203_0904_LLPP 8006_0303_0904_LLPP 8006_0403_0904_LLPP 8006_0503_0904_LLPP 8006_0603_0904_LLPP 8006_0703_0904_LLPP 8008_0000_0000_0100 0009_CC00_0000_0000 810A_0000 _I I00_0100 010B_AS00_0000_0000 0005_AA00_0000_0000 Data Bytes PPLL bytes in Data stage PPLL bytes in Data stage PPLL bytes in Data stage PPLL bytes in Data stage PPLL bytes in Data stage PPLL bytes in Data stage PPLL bytes in Data stage PPLL bytes in Data stage PPLL bytes in Data stage PPLL bytes in Data stage 1 bytes in Data stage No data in Data stage 1 bytes in Data stage No data in Data stage No data in Data stage Access Type Read Read Read Read Read Read Read Read Read Read Read Write Read Write Write Description Get Device Descriptor Get Configuration Descriptor Get Supported Language ID Get Manufacture String Get Product String Get Serial Number String Get Configuration String Get Interface 0 String Get Interface 1/0 String Get Interface 1/1 String Get Configuration Set Configuration Get Interface Set Interface Set Address Table 3: USB Standard Command Register Map 14 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 6.2 USB Vendor Commands No 1. 2. 3. 4. 5. 6. 7. 8. 9. Setup Command C002_AA0B_0C00_0800 4003_AA0B_0C00_0800 4006_0000_0000_0000 C007_ AA00_CC00_0200 4008 _AA00_CC00_0200 C009_0000_0000_0100 400A_0000_0000_0000 C00B_AA00_0000_0200 Data Bytes 8 bytes in Data stage 8 bytes in Data stage No data in Data stage 2 bytes in Data stage 2 bytes in Data stage 1 bytes in Data stage No data in Data stage 2 bytes in Data stage Access Description Type Read Rx/Tx SRAM Read Register Write Rx/Tx SRAM Write Register Write Software Serial Management Control Register Read PHY Read Register Write PHY Write Register Read Serial Management Status Register Write Hardware Serial Management Control Register Read SROM Read Register Write SROM Write Register Write SROM Write Enable Register Write SROM Write Disable Register Read Rx Control Register Write Rx Control Register Read IPG/IPG1/IPG2 Register Write IPG/IPG1/IPG2 Register Read Node ID Register Write Node ID Register 400C_AA00_CCDD_0000 No data in Data stage No data in Data stage No data in Data stage 2 bytes in Data stage No data in Data stage 3 bytes in Data stage No data in Data stage 6 bytes in Data stage 6 bytes in Data stage 10. 400D_0000_0000_0000 11. 400E_0000_0000_0000 12. C00F_0000_0000_0200 13. 4010_AABB_0000_0000 14. C011_0000_0000_0300 15. 4012_AABB_CC00_0000 16. C013_0000_0000_0600 17. 4014_0000_0000_0600 18. C015_0000_0000_0800 19. 4016_0000_0000_0800 20. 4017_AA00_0000_0000 21. C019_0000_0000_0200 22. C01A_0000_0000_0200 23. 401B_AABB_0000 _0000 24. C01C_0000_0000_0100 25. 401D_AA00_0000_0000 26. C01E _0000_0000_0100 27. 401F_AA00_0000_0000 28. 4020_AA00_0000_0000 8 bytes, MA0~MA7, in Read Multicast Filter Array Register Data stage 8 bytes, MA0~MA7, in Write Multicast Filter Array Register Data stage No data in Data stage Write Test Register 2 bytes in Data stage 2 bytes in Data stage No data in Data stage 1bytes in Data stage No data in Data stage 1 bytes in Data stage No data in Data stage No data in Data stage Read Ethernet/HomePNA Phy Address Register Read Medium Status Register Write Medium Mode Register Read Monitor Mode Status Register Write Monitor Mode Register Read GPIOs Status Register Write GPIOs Register Write Software Reset Register Table 4: USB Vendor Command Register Map 15 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 6.2.1 Detailed Register Description 6.2.1.1 Rx/Tx SRAM Read Register (02h, read only) Bit7 Bit6 Bit5 Bit4 Bit3 AA [7:0] Bit2 B [3:0] C [3:0] DD [7:0] in Data stage EE [7:0] in Data stage FF [7:0] in Data stage GG [7:0] in Data stage HH [7:0] in Data stage II [7:0] in Data stage JJ [7:0] in Data stage KK [7:0] in Data stage {B [3:0], AA [7:0]}: The read address of RX or TX SRAM. C [0]: RAM selection. 0: indicates to read from RX SRAM. 1: indicates to read from TX SRAM. C [3:1]: Reserved. {DD [7:0], EE [7:0], FF [7:0], GG [7:0], HH [7:0], II [7:0], JJ [7:0], KK [7:0]}: The 64-bits of data presented in Data stage are the data to be written to RX or TX SRAM. Bit1 Bit0 Reserved 0h 6.2.1.2 Rx/Tx SRAM Write Register (03h, write only) Bit7 Bit6 Bit5 Bit4 Bit3 AA [7:0] Bit2 B [3:0] C [3:0] DD [7:0] in Data stage EE [7:0] in Data stage FF [7:0] in Data stage GG [7:0] in Data stage HH [7:0] in Data stage II [7:0] in Data stage JJ [7:0] in Data stage KK [7:0] in Data stage {B [3:0], AA [7:0]}: The write address of RX or TX SRAM. C [0]: RAM selection. 0: indicates to write to RX SRAM. 1: indicates to write to TX SRAM. C [3:1]: Reserved. {DD [7:0], EE [7:0], FF [7:0], GG [7:0], HH [7:0], II [7:0], JJ [7:0], KK [7:0]}: The 64-bits of data presented in Data stage are the data to be written to RX or TX SRAM. Bit1 Bit0 Reserved Reserved 6.2.1.3 Software Serial Management Control Register (06h, write only) When software needs to access to Ethernet PHY’s internal registers, one has to first issue this command to request the ownership of Serial Management Interface. The ownership status of the interface can be retrieved from Serial Management Status Register. 16 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 6.2.1.4 PHY Read Register (07h, read only) Bit7 Bit6 Bit5 Bit4 Bit3 AA [7:0] 00h CC [7:0] Bit2 Bit1 Bit0 AA [4:0]: The PHY ID value. CC [4:0]: The register address of Ethernet PHY’s internal register. AA [7:5]: Reserved CC [7:5]: Reserved 6.2.1.5 PHY Write Register (08h, write only) Bit7 Bit6 Bit5 Bit4 Bit3 AA [7:0] 00h CC [7:0] Bit2 Bit1 Bit0 AA [4:0]: The PHY ID value. CC [4:0]: The register address of Ethernet PHY’s internal register. AA [7:5]: Reserved CC [7:5]: Reserved 6.2.1.6 Serial Management Status Register (09h, read only) Bit7 Bit6 Bit5 Bit4 Reserved Bit3 Bit2 Bit1 Bit0 Host_EN Host_EN: Host access Enable. Software can read this register to determine the current ownership of Serial Management Interface. 1: Software is allowed to access Ethernet PHY’s internal registers via PHY Read Register or PHY Write Registers. 0: ASIC’s hardware owns the Serial Management Interface and software’s access is ignored. 6.2.1.7 Hardware Serial Management Control Register (0Ah, write only) When software is done accessing Serial Management Interface, one needs to issue this command to release the ownership of the Interface back to ASIC’s hardware. After issuing this command, following PHY Read Register or PHY Write Register from software will be ignored. NOTE: Software should issue this command every time after finished accessing Serial Management Interface to release the ownership back to hardware to allow periodic Interrupt Endpoint to be able to access the Ethernet PHY’s registers via the Serial Management Interface. 6.2.1.8 SROM Read Register (0Bh, read only) Bit7 Bit6 Bit5 Bit4 Bit3 AA [7:0] Bit2 Bit1 Bit0 AA [7:0]: The read address of Serial EEROM. 17 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 6.2.1.9 SROM Write Register (0Ch, write only) Bit7 Bit6 Bit5 Bit4 Bit3 AA [7:0] 00h CC [7:0] DD [7:0] Bit2 Bit1 Bit0 AA [7:0]: The write address of Serial EEROM. { DD [7:0], CC [7:0] }: The write data value of Serial EEROM 6.2.1.10 Write SROM Enable (0Dh, write only) User issues this command to enable write permission to Serial EEPROM from SROM Write Register. 6.2.1.11 Write SROM Disable (0Eh, write only) User issues this command to disable write permission to Serial EEPROM from SROM Write Register. 6.2.1.12 Rx Control Register (0Fh, read only and 10h, write only) Bit7 SO Bit6 Reserved 0h Bit5 AP Bit4 AM Bit3 Bit2 AB SEP Reserved Bit1 Bit0 AMALL PRO MFB [1:0] AA [7:0] = { SO, Reserved, AP, AM, AB, Reserved, AMALL, PRO } BB [7:0] = { 0h, Reserved [3:2], SB [1:0] } PRO: PACKET_TYPE_PROMISCUOUS. 1: All frames received by the ASIC are forwarded up toward the host. 0: Disabled (default). AMALL: PACKET_TYPE_ALL_MULTICAST. 1: All multicast frames received by the ASIC are forwarded up toward the host, not just the frames whose scrambling result of DA matching with multicast address list provided in Multicast Filter Array Register. 0: Disabled. This only allows multicast frames whose scrambling result of DA field matching with multicast address list provided in Multicast Filter Array Register to be forwarded up toward the host (default). SEP: Save Error Packet. 1: Received packets with CRC error are saved and forwarded to the host anyway. 0: Received packets with CRC error are discarded automatically without forwarding to the host (default). AB: PACKET_TYPE_BROADCAST. 1: All broadcast frames received by the ASIC are forwarded up toward the host (default). 0: Disabled. AM: PACKET_TYPE_MULTICAST. 1: All multicast frames whose scrambling result of DA matching with multicast address list are forwarded up to the host (default). 0: Disabled. AP: Accept Physical Address from Multicast Filter Array. 1: Allow unicast packets to be forwarded up toward host if the lookup of scrambling result of DA is found within multicast address list. 0: Disabled, that is, unicast packets filtering are done without regarding multicast address list (default). SO: Start Operation. 1: Cactus start. 0: Cactus stop (default). 18 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller MFB [1:0]: Maximum Frame Burst transfer on USB bus. 00: 2048 Bytes 01: 4096 Bytes 10: 8192 Bytes 11: 16384 Bytes (default). User should set to this value when Jumbo packet mode is enabled to gain better transfer throughput on USB bus. 6.2.1.13 IPG/IPG1/IPG2 Control Register (11h, read only and 12h, write only) Bit7 Bit6 Bit5 Bit4 Bit3 AA [7:0] BB [7:0] CC [7:0] Bit2 Bit1 Bit0 AA [6:0] = IPG [6:0]. BB [6:0] = IPG1 [6:0]. CC [6:0] = IPG2 [6:0]. IPG [6:0]: Inter Packet Gap for back-to-back transfer on TX direction in MII mode (default = 15h). IPG1 [6:0]: IPG part1 value (default = 0Ch). IPG2 [6:0]: IPG part1 value + part2 value (default = 12h). AA [7]: Reserved. BB [7]: Reserved. CC [7]: Reserved. 6.2.1.14 Node ID Register (13h, read only and 14h, write only) Bit7 Bit6 Bit5 Bit4 Bit3 AA [7:0] BB [7:0] CC [7:0] DD [7:0] EE [7:0] FF [7:0] Bit2 Bit1 Bit0 AA [7:0] = NOID 0. BB [7:0] = NOID 1. CC [7:0] = NOID 2. DD [7:0] = NOID 3. EE [7:0] = NOID 4. FF [7:0] = NOID 5. {FF [7:0], EE [7:0], DD [7:0], CC [7:0], BB [7:0], AA [7:0]} = Ethernet MAC address [47:0] of the node. 19 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 6.2.1.15 Multicast Filter Array (15h, read only and 16h, write only) Bit7 Bit6 Bit5 Bit4 Bit3 MA 0 [7:0] MA 1 [7:0] MA 2 [7:0] MA 3 [7:0] MA 4 [7:0] MA 5 [7:0] MA 6 [7:0] MA 7 [7:0] Bit2 Bit1 Bit0 {MA7 [7:0], MA6 [7:0], MA5 [7:0], MA4 [7:0], MA3 [7:0], MA2 [7:0], MA1 [7:0], MA0 [7:0]} = the multicast address bit map for multicast frame filtering block. See Figure 3: Multicast Filter Example, for example. DA 81 81 81 81 81 81 CRC32 {crc31, 30, 29, 28, 27, 26} Address[5:0] = 1Ah MAR[63:0] = 400_0000h Figure 3: Multicast Filter Example 6.2.1.16 Test Register (17h, write only) Bit7 Bit6 Bit5 Bit4 MM [7:6] Bit3 Bit2 Bit1 Bit0 LDRND LDRND: Load Random number into MAC’s exponential back-off timer. User writes a “1” to enable the ASIC to load a small random number into MAC’s back-off timer to shorten the back-off duration in each retry after collision. This register is used for test purpose. Default value = 0. MM [7:6]: Reserved. 6.2.1.17 Ethernet / HomePNA Phy Address Register (19h, read only) Bit7 Bit6 Bit5 SecPhyType [2:0] PriPhyType [2:0] Bit4 Bit3 Bit2 Bit1 SecPhyID [4:0] PriPhyID [4:0] Bit0 SecPhyType, SecPhyID: The Secondary PHY address loaded from serial EEPROM’s offset address 11h. PriPhyType, PriPhyID: The Primarily PHY address loaded from serial EEPROM’s offset address 11h. 20 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 6.2.1.18 Medium Status Register (1Ah, read only) and Medium Mode Register (1Bh, write only) Bit7 PF Bit6 JFE Reserved Bit5 TFC Bit4 RFC SM Bit3 ENCK SBP Bit2 AC Reserved Bit1 FD PS Bit0 GM RE AA [7:0] = {PF, JFE, TFC, RFC, EN125, AC, FD, GM}. BB [7:0] = {Reserved, SM, SBP, JE, PS, RE}. GM: Gigabit Mode. 1: GMII mode. 0: MII mode (default). PS: Port Speed in MII mode 1: 100 Mbps (default). 0: 10 Mbps. {GM, PS} RGMII/MII/GMII port speed selection 00: 10Mbps 01: 100Mbps 10: 1000Mbps 11: 1000Mbps FD: Full Duplex mode 1: Full Duplex mode (default). 0: Half Duplex mode. AC: Reserved bit. For normal operation, please always write 1 to this bit. ENCK: Enable GTX_CLK and TXC clock outputs 1: Enable. 0: Disabled (default). ENCK RGMII_EN GTX_CLK TXC 0 0 OFF OFF 0 1 OFF OFF 1 0 ON OFF 1 1 OFF ON RFC: RX Flow Control enable. 1: Enable receiving of pause frame on RX direction during full duplex mode (default). 0: Disabled. TFC: TX Flow Control enable. 1: Enable transmitting pause frame on TX direction during full duplex mode (default). 0: Disabled. JFE: Jumbo Frame Enable. 1: Enable the support of Jumbo frame in Gigabit mode (default). 0: Disabled. PF: Check only “length/type” field for Pause Frame. 1: Enable, i.e., Pause frames are identified only based on L/T filed. 0: Disabled, i.e., Pause frames are identified based on both DA and L/T fields (default). RE: Receive Enable. 1: Enable RX path of the ASIC. 0: Disabled (default). SBP: Stop BackPressure. 1: When TFC bit = 1, setting this bit enables backpressure on TX direction “continuously” during RX buffer full condition in half duplex mode. 0: When TFC bit = 1, setting this bit enable backpressure on TX direction “intermittently” during RX buffer full condition in half duplex mode (default). SM: Super Mac support. 1: Enable Super Mac to shorten exponential back-off time during transmit retry. 0: Disabled (default). 21 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 6.2.1.19 Monitor Mode Status Register (1Ch, read only) Bit7 Bit6 Reserved Bit5 Bit4 US Bit3 Reserved Bit2 RWMP Bit1 RWLU Bit0 MOM MOM: Monitor Mode. 1: Enable. All received packets will be checked on DA and CRC but not buffered into memory. 0: Disabled (default). RWLU: Remote Wakeup trigger by Ethernet Link-up. 1: Enable 0: Disabled (default). RWMP: Remote Wakeup trigger by Magic Packet. 1: Enable 0: Disabled (default). US: USB Speed. 1: High speed mode. 0: FS speed mode. 6.2.1.20 Monitor Mode Register (1Dh, write only) Bit7 Bit6 Bit5 Reserved Bit4 Bit3 Bit2 RWMP Bit1 RWLU Bit0 MOM MOM: Monitor Mode. 1: Enable. All received packets will be checked on DA and CRC but not buffered into memory. 0: Disabled (default). RWLU: Remote Wakeup trigger by Ethernet Link-up. 1: Enable. 0: Disabled (default). RWMP: Remote Wakeup trigger by Magic Packet. 1: Enable. 0: Disabled (default). AA [7:3]: Reserved. 6.2.1.21 GPIO Status Register (1Eh, read only) Bit7 Bit6 Bit5 GPI_2 Bit4 GPO_2_EN Bit3 GPI_1 Bit2 GPO_1_EN Bit1 GPI_0 Bit0 GPO_0_EN GPO_0_EN: Current level of pin GPIO0’s output enable. GPI_0: Input level on GPIO0 pin when GPIO0 is as an input pin. GPO_1_EN: Current level of pin GPIO1’s output enable. GPI_1: Input level on GPIO1 pin when GPIO1 is as an input pin. GPO_2_EN: Current level of pin GPIO2’s output enable. GPI_2: Input level on GPIO2 pin when GPIO2 is as an input pin. 22 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 6.2.1.22 GPIO Register (1Fh, write only) Bit7 RSE Bit6 Reserved Bit5 GPO_2 Bit4 GPO2EN Bit3 GPO_1 Bit2 GPO1EN Bit1 GPO_0 Bit0 GPO0EN GPO0EN: Pin GPIO0 Output Enable. 1: Output is enabled (meaning GPIO0 is used as an output pin). 0: Output is tri-stated (meaning GPIO0 is used as an input pin) (default). GPO_0: Pin GPIO0 Output Value. GPO1EN: Pin GPIO1 Output Enable. 1: Output is enabled (meaning GPIO1 is used as an output pin). 0: Output is tri-stated (meaning GPIO1 is used as an input pin) (default). GPO_1: Pin GPIO1 Output Value. 0: (default). GPO2EN: Pin GPIO2 Output Enable. 1: Output is enabled (meaning GPIO2 is used as an output pin). 0: Output is tri-stated (meaning GPIO2 is used as an input pin) (default). GPO_2: Pin GPIO2 Output Value. 0: (default). RSE: Reload Serial EEPROM. 1: Enable. 0: Disabled (default) 6.2.1.23 Software Reset Register (20h, write only) Bit7 0 Bit6 1 Bit5 0 Bit4 BZ Bit3 PRL Bit2 PRTE Bit1 RT Bit0 RR RR: Clear frame length error for Bulk In. 1: set high to clear state. 0: set low to exit clear state (default). RT: Clear frame length error for Bulk Out. 1: set high to enter clear state. 0: set low to exit clear state (default). PRTE: External Phy Reset pin Tri-state Enable. 1: Enable, i.e., the external PHYRST_N pin is tri-stated (default). This allows the PHYRST_N pin’s active level to be controlled by external pulled-up (active high during power-on) or pulled-down resistor (active low during power-on). 0: Disabled, i.e., the external PHYRST_N pin’s level is driven by either PRL bit or internal “USB RESET” based on the setting in SCPR bit in Flag byte of EEPROM. PRL: External Phy Reset pin Level. When SCPR bit = 1 and PRTE = 0, this bit controls the output level of external PHYRST_N pin. 1: Set to high (default). 0: Set to low. BZ: Force Bulk In to return a Zero-length packet. 1: Software can force Bulk In to return a zero-length USB packet. 0: Normal operation mode (default). Bit [7:5]: Please always write 010 to these bits. 23 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 6.2.2 Remote Wakeup Description After AX88178 enters into suspend mode, either the USB host or AX88178 itself can awake it up and resume back to the original operation mode before it entered suspend. Following truth table shows the chip setting, wakeup event, and device response supported by this ASIC. Note that “X” stands for don’t-care. Wakeup by Setting RWU bit Set_Feature RWLU of of Flag standard Monitor byte in command Mode EEPRO Register M X X X 0 0 X 1 1 0 1 1 1 1 1 1 1 1 X RWMP of Monitor Mode register X X 1 0 0 X Host send resume signal Wakeup Event Receiving EXTWAKE Linkup Linkup Magic UP_N pin detected detected on Packet on Secondary Primary Phy Phy X Yes X X Yes Yes Low-pulse X Yes No Yes Yes Yes Yes Device awakes up? Host Device Device Device Device Device J -> K Table 5: Remote Wakeup Truth Table 6.3 Interrupt Endpoint The Interrupt Endpoint contains 8 bytes of data and its frame format is defined as: A100_BB00_CCDD_EEFF. Where BB byte in byte 3: Bit7 Bit6 Bit5 Reserved Bit4 Bit3 MDINT Bit2 FLE Bit1 SPLS Bit0 PPLS PPLS: Primarily PHY Link State. 1: Link is up. 0: Link is down. SPLS: Secondary PHY Link State. 1: Link is up. 0: Link is down. FLE: Bulk Out Ethernet Frame Length Error. 1: Proprietary Length field has parity error during Bulk Out transaction. 0: Proprietary Length field has no parity error during Bulk Out transaction. MDINT: Input level of MDINT pin. The MDINT pin can be connectted to MDINT# pin of Ethernet Phy. 1: When MDINT input pin = 1. 0: When MDINT input pin = 0. CCDD byte in byte 5 and 6: Primary Phy’s register value, whose offset is given in High byte of EEPROM offset 0Fh. EEFF byte in byte 7 and 8: Primary Phy’s register value, whose offset is given in Low byte of EEPROM offset 0Fh. 24 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller 7.0 Electrical Specifications 7.1 DC Characteristics 7.1.1 Absolute Maximum Ratings Symbol VDDK VDD2 VDD3 AVDDK AVDD3 VIN2 VIN3 Parameter Digital core power supply Power supply of 2.5V I/O Power supply of 3.3V I/O Analog core power supply Power supply of analog I/O Input voltage of 2.5V I/O Input voltage of 2.5V I/O with 3.3V tolerant Input voltage of 3.3V I/O Input voltage of 3.3V I/O with 5V tolerant Rating - 0.3 to VDDK + 0.3 - 0.3 to VDD2 + 0.3 - 0.5 to VDD3 + 0.5 - 0.3 to AVDDK + 0.3 - 0.5 to AVDD3 + 0.5 - 0.3 to VDD2 + 0.3 - 0.3 to 3.9 - 0.3 to VDD3 + 0.3 - 0.3 to 5.5 Unit V V V V V V V V V TSTG Storage temperature - 40 to 150 ℃ Note: Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted in the optional sections of this datasheet. Exposure to absolute maximum rating condition for extended periods may affect device reliability. 7.1.2 Recommended Operating Condition Symbol VDDK VDD2 VDD3 AVDDK AVDD3 VIN2 Parameter Digital core power supply Power supply of 2.5V I/O Power supply of 3.3V I/O Analog core power supply Power supply of analog I/O Input voltage of 2.5 V I/O Input voltage of 2.5 V I/O with 3.3 V tolerance Input voltage of 3.3 V I/O Input voltage of 3.3 V I/O with 5 V tolerance Tj Commercial junction operating temperature Min 2.25 2.25 3.0 2.25 3.0 0 0 0 0 0 Typ 2.5 2.5 3.3 2.5 3.3 2.5 2.5 3.3 3.3 Max 2.75 2.75 3.6 2.75 3.6 2.75 3.6 3.6 5.25 115 Unit V V V V V V V V V ℃ VIN3 7.1.3 Leakage Current and Capacitance Symbol IIN IOZ CIN COUT CBID Parameter Input current Tri-state leakage current Input capacitance Output capacitance Bi-directional buffer capacitance Condition No pull-up or pull-down Min -10 -10 Typ ±1 ±1 3.1 3.1 3.1 Max 10 10 Unit μA μA pF pF pF 25 ASIX ELECTRONICS CORPORATION AX88178 L USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller Note: The capacitance listed above does not include pad capacitance and package capacitance. One can estimate pin capacitance by adding a pad capacitance of about 0.5pF and the package capacitance. 7.1.4 DC Characteristics of 2.5V I/O Pins Symbol VDD2 Temp Vil Vih VtVt+ Vol Voh Rpu Rpd Iin Ioz Parameter Condition Power supply of 2.5V I/O Junction temperature CMOS Input low voltage Input high voltage Schmitt trigger negative going CMOS threshold voltage Schmitt trigger positive going threshold voltage Output low voltage |Iol| = 2~16mA Output high voltage |Ioh| = 2~16mA Input pull-up resistance Input pull-down resistance Input leakage current Vin = VDD2 or 0 Tri-state output leakage current Min Typ 2.25 2.5 0 25 1.7 0.7 1.0 1.85 40 40 -10 -10 1.5 75 75 ±1 ±1 Max 2.75 115 0.7 1.7 0.4 190 190 10 10 Unit V ℃ V V V V V V KΩ KΩ μA μA 7.1.5 DC Characteristics of 3.3V I/O Pins Symbol VDD3 Temp Vil Vih VtVt+ Vol Voh Rpu Rpd Iin Ioz Parameter Condition Power supply of 3.3V I/O 3.3V I/O Junction temperature LVTTL Input low voltage Input high voltage Schmitt trigger negative going LVTTL threshold voltage Schmitt trigger positive going threshold voltage Output low voltage |Iol| = 2~16mA Output high voltage |Ioh| = 2~16mA Input pull-up resistance Input pull-down resistance Input leakage current Vin = VDD3 or 0 Tri-state output leakage current Min Typ 3.0 3.3 0 25 2.0 0.8 1.1 2.4 40 40 -10 -10 1.6 75 75 ±1 ±1 Max 3.6 115 0.8 2.0 0.4 190 190 10 10 Unit V ℃ V V V V V V KΩ KΩ μA μA 7.2 Power Consumption Symbol IVDDK2 IVDD3 IAVDDK IAVDD3 Description Condition Current consumption of VDDK/VDD2, Operating at Ethernet 1000Mbps full duplex 2.5V mode and USB High Current consumption of VDD3, 3.3V Current consumption of AVDDK, 2.5V speed mode Current consumption of AVDD3, 3.3V Min Typ 48.3