AX88872P 10/100BASE Dual Speed “Swipeater” Controller
10/100BASE Dual Speed 8-Port Repeater with 4-Port Switch
Document No.: AX872-13 / V1.3 / Aug. 11 ’99
Features
Support 8 10/100Mbps RMII I/F repeater ports and 2 10/100Mbps RMII/MII switch ports • IEEE 802.3u repeater compatible • Support virtual switch mode and Master/Slave mode for the cascade application • Build in 4-ports 10/100Mbps Switch engine with following features ü Low cost SSRAM interface to reduce system cost ü One or two 64K*32bit SSRAM to buffer packets ü 4/8 K MAC Address Entry Table is supported ü Auto learning and filtering ü Aging the MAC Address table is supported optionally ü Three forwarding modes are supported : Storeand-Forward, Fragment-Free and Auto-Forward ü Flow-control is supported optionally. ü 802.3x flow control is supported in full duplex mode ü Back-pressure base flow control is supported in half duplex mode ü Ext. Buffer Memory auto testing • ü Routing and Learning at wire speed (148800 packets/sec at 100Mbps) Up-to 4 repeaters can be cascaded for vertical expansion Up-to 3 chips can be cascaded locally for horizontal expansion All ports can be separately isolated or partitioned in response to fault condition Separate jabber and partition state machines for each port Per-port LED display for Jabber, Partition, Activity. RAM test fail and collision, buffer utilization (%) and global traffic utilization (%) for 10/100Mbps presentation Power on LED diagnosis. All the LED display will follow the “ON-OFF-ON-OFF-Normal” operation procedure during/after power on reset 50MHz Operation, 3.3volt and 208-pin PQFP
• • • • •
• •
Product description
The AX88872 10/100Mbps Dual Speed “Swipeater” Controller is “a dual speed repeater with build in 4-ports switch function” It is design for low cost dumb HUB application. The AX88872 directly supports up-to eight 10/100Mbps automatic links RMII interfaces. Maximum up-to 96 repeater ports can be constructed by stacking 1 AX88872 and 2 AX88873 chips horizontally and then cascading 4 horizontal boards vertically. About the build in 4-port switch: The switch port3 is fixed to 10Mbps speed and connects to 10Mbps repeater segment, The switch port2 is fixed to 100Mbps and connects to 100M repeater segment. The switch ports 0 and 1 are connected to external MII or RMII interfaces for various applications. For example, one port is used for down link and the other is used for up link to extend the network topology. The other case is one port for up link and the other port for server. The AX88872 is designed base on IEEE 802.3u clause 27 “ Repeater for 100Mb/s base-band networks” It is fully compatible with IEEE 802.3u standard. Please refer Ax873-12.doc to get more information about AX88873.
System Block Diagram
10Mbps and 100Mbps Vertical cascade up to 4 stacks
Buffer
10Mbps horizontal cascade 100Mbps horizontal cascade
AX88873 #1
Repeater Controller
AX88873 #0
Repeater Controller
AX88872 #0
Swipeater Controller PHY for Up-link
2 Quad RMII PHY
2 Quad RMII PHY
2 Quad RMII PHY
PHY for Down-link or Server
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
First Released Date : APR/09/1999
http://www.asix.com.tw
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-579-9558
CONFIDENTIAL
AX88872P Swipeater Controller CONTENTS
PRELIMINARY
1.0 AX88872 OVERVIEW ....................................................................................................................................... 4 1.1 GENERAL DESCRIPTION ...................................................................................................................................... 4 1.2 AX88872 BLOCK DIAGRAM: .............................................................................................................................. 5 1.3 PIN CONNECTION DIAGRAM ............................................................................................................................... 6 2.0 PIN DESCRIPTION ........................................................................................................................................... 7 2.1 RMII INTERFACE FOR REPEATER PORTS ............................................................................................................... 7 2.1.1 Repeater Port 0.......................................................................................................................................... 7 2.1.2 Repeater Port 1.......................................................................................................................................... 7 2.1.3 Repeater Port 2.......................................................................................................................................... 8 2.1.4 Repeater Port 3.......................................................................................................................................... 8 2.1.5 Repeater Port 4.......................................................................................................................................... 8 2.1.6 Repeater Port 5.......................................................................................................................................... 8 2.1.7 Repeater Port 6.......................................................................................................................................... 9 2.1.8 Repeater Port 7.......................................................................................................................................... 9 2.2 MII/RMII INTERFACE FOR SWITCH PORTS ........................................................................................................... 9 2.2.1 Switch Port 0.............................................................................................................................................. 9 2.2.2 Switch Port 1............................................................................................................................................ 10 2.3 EXPANSION BUS INTERFACE FOR 100 MBPS....................................................................................................... 11 2.4 EXPANSION BUS INTERFACE FOR 10 MBPS......................................................................................................... 11 2.5 LED DISPLAY.................................................................................................................................................. 12 2.6 BUFFER MEMORY PINS GROUP ........................................................................................................................... 13 2.7 MISCELLANEOUS .............................................................................................................................................. 14 2.8 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE ................................................................ 15 3.0 FUNCTIONAL DESCRIPTION ...................................................................................................................... 18 3.1 REPEATER STATE MACHINE.............................................................................................................................. 18 3.2 RXE /TXE CONTROL ...................................................................................................................................... 18 3.3 JABBER STATE MACHINE .................................................................................................................................. 18 3.4 PARTITION STATE MACHINE ............................................................................................................................. 18 3.5 OPERATION OF THE BUILT-IN SWITCH ............................................................................................................... 19 3.5.1 Packet Filtering and Forwarding Process ................................................................................................ 19 3.5.2 MAC Address Learning and Aging Process .............................................................................................. 19 3.5.3 Flow Control Process............................................................................................................................... 19 3.6 LED DISPLAY INTERFACE ................................................................................................................................ 20 4.0 INTERNAL REGISTERS ................................................................................................................................ 22 5.0 ELECTRICAL SPECIFICATION AND TIMING.......................................................................................... 23 5.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 23 5.2 GENERAL OPERATION CONDITIONS................................................................................................................... 23 5.3 DC CHARACTERISTICS ..................................................................................................................................... 23 5.4 AC SPECIFICATIONS ......................................................................................................................................... 24 5.4.1 LCLK ....................................................................................................................................................... 24 5.4.2 Reset Timing ............................................................................................................................................ 24 5.4.3 RMII Interface Timing TX & RX............................................................................................................... 25 5.4.4 MII Interface Timing TX & RX................................................................................................................. 26 5.4.5 SRAM read cycle...................................................................................................................................... 27 5.4.6 SRAM write cycle..................................................................................................................................... 28 5.4.7 LED DISPLAY ......................................................................................................................................... 29 5.4.8 LED Display after Reset........................................................................................................................... 29 2 ASIX ELECTRONICS CORPORATION
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AX88872P Swipeater Controller
PRELIMINARY
5.4.9 Repeater ID Daisy Chain ......................................................................................................................... 30 6.0 PACKAGE INFORMATION........................................................................................................................... 31 APPENDIX A: SYSTEM APPLICATIONS.......................................................................................................... 32 A.1 16-PORT (24-PORT) REPEATER WITH 2-PORT SWITCH......................................................................................... 32 A.2 16-PORT REPEATER WITH UP TO 4 STACKS......................................................................................................... 32 A.3 8-PORT STANDALONE REPEATER WITH 2-PORT SWITCH ...................................................................................... 33 A.4 16-PORT REPEATER WITH UP TO 4 STACKS OF AX88871A COMPATIBLE MODE .................................................... 33 A.5 16-PORT REPEATER WITH UP TO 4 STACKS AND MORE SWITCH PORTS .................................................................. 34 APPENDIX B: DESIGN NOTE............................................................................................................................. 35 B.1 USING STATION MANAGEMENT (STA) CONNECTION ........................................................................................ 35 B.2 USING MII I/F CONNECTS TO MAC.................................................................................................................. 36
FIGURES
FIG - 1 AX88872 BLOCK DIAGRAM ............................................................................................................................. 5 FIG - 2 PIN CONNECTION DIAGRAM .............................................................................................................................. 6 FIG - 3 APPLICATION FOR LED DISPLAY ..................................................................................................................... 21
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CONFIDENTIAL
AX88872P Swipeater Controller 1.0 AX88872 Overview
1.1 General Description
PRELIMINARY
The AX88872 that built in a switch is not only a simple repeater but also it provide 2 repeater expansion buses for 10M and 100M respectively. So the cascade function of the AX88872 can be backward compatible with the AX88871A “Bripeater” in virtual switch mode. Also the AX88872 can support Master/Slave mode in stack application. That all the repeater stack system forms one 100Mbps segment and one 10Mbps segment in Master/Slave mode. The two segments are communication via the switch of the master chip. In general, using RMII interface for 8 repeater ports can simplify the design and also provide a low cost solution with RMII Quad/Octet PHY and low cost 64Kx32 SSRAM as buffer memory. In additional, the AX88872 provides two 10/100M MII/RMII switch ports alternative for up-link and down-link function. AX88872 has counterpart AX88873 that is a simple dual-speed repeater controller without built-in switch. The switch port3 is fixed to 10Mbps speed and connect to 10Mbps repeater segment, The switch port2 is fixed to 100Mbps and connect to 100M repeater segment. The other switch ports 0 and 1 are connected to external MII or RMII interfaces for various applications. The built-in switch provides 4/8K look-up table that can learn, route and age with MAC address of each packet automatically for packet forwarding and filtering. That is, the AX88872 forwards and filters packets with DA (Destination Address) and the table. The performances of routing and learning fit wire speed (148800 packets/sec at 100Mbps). The switch provides three packet forwarding mode: Store-and-Forward, Fragment-Free (i.e., safe cutthrough) and auto mode. Dynamically the switch selects optimum mode for packet forwarding based on network quality. During transmission, the data is obtained from the buffer memory and routed to the destination port. For half-duplex operation, when collision occurs, the MAC controller will back off and retransmit in accordance to the IEEE802.3 specification. The switch also support flow-control mechanism. For full duplex operation mode, 802.3x flow control is supported. For half-duplex operation, an optional jamming based flow control is available to avoid loss of data. This is also well known as back-pressure. The flow control function is optional.
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AX88872P Swipeater Controller
1.2 AX88872 Block Diagram:
PRELIMINARY
RMII I/F 10/100 Q-PHY RMII /MII translation for Repeater Port 0 -7 Repeater State Machine of 100Mbps Per Port Partition Detection Per Port Jabber Detection Led Interface
10/100 Q-PHY
Cascade Arbitration Logic of 100Mbps Cascade Arbitration Logic of 10Mbps
Repeater State Machine of 10Mbps
RMII /MII
For up link P0 P2
translation
For down link or server
Ext SSRAM Interface
for Switch Port 0 and 1
P1
Built in 4 Port Switch
P3
Fig - 1 AX88872 Block Diagram
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AX88872P Swipeater Controller
1.3 Pin Connection Diagram
PRELIMINARY
AX88872
SPEED3 CRS_DV3 RXD3[0] RXD3[1] TXEN3 TXD3[0] TXD3[1] VSS SPEED4 CRS_DV4 RXD4[0] RXD4[1] TXEN4 TXD4[0] TXD4[1] BMA11 BMA10 BMA0 BMA1 BMA2 BMA3 BMA4 BMA5 BMD31 VDD BMD30 BMD29 BMD28 BMD27 BMD26 BMD25 BMD24 SPEED5 CRS_DV5 VSS RXD5[0] RXD5[1] TXEN5 TXD5[0] TXD5[1] SPEED6 CRS_DV6 RXD6[0] RXD6[1] TXEN6 TXD6[0] TXD6[1] VDD SPEED7 CRS_DV7 RXD7[0] RXD7[1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Fig - 2 Pin Connection Diagram
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96
NC /BMWE /BMOE SPEED0 CRS_DV0 RXD0[0] RXD0[1] VDD TXEN0 BMA8 TXD0[0] TXD0[1] SPEED1 BMA9 BMD15 BMD14 BMD13 VSS BMD12 BMD11 BMD10 BMD9 BMD8 BMD7 CRS_DV1 RXD1[0] RXD1[1] TXEN1 VSS TXD1[0] TXD1[1] BMD6 BMD5 BMD4 BMD3 BMD2 BMD1 BMD0 VDD SPEED2 BMA16 BMA15 BMA14 BMA13 BMA12 CRS_DV2 RXD2[0] RXD2[1] TXEN2 TXD2[0] TXD2[1] VSS
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
HIRD[3] HIRD[2] HIRD[1] HIRD[0] /HIRD_V HIRD_CK HIRD_ODIR VSS /HIR_ACTO[3] /HIR_ACTO[2] /HIR_ACTO[1] /HIR_ACTO[0] VDD BMA7 BMA6 BMD16 BMD17 VSS BMD18 BMD19 BMD20 BMD21 BMD22 BMD23 /HIR_ACTI[3] /HIR_ACTI[2] /HIR_ACTI[1] /HIR_ACTI[0] /LHIR_ACT[2] VSS /LHIR_ACT[1] /LHIR_ACT[0] /TIR_ACTO[3] /TIR_ACTO[2] VDD /TIR_ACTO[1] /TIR_ACTO[0] /TIR_ACTI[3] /TIR_ACTI[2] /TIR_ACTI[1] /TIR_ACTI[0] VSS SRXD0[3] SRXD0[2] VSS SRXD0[1] SRXD0[0] /LTIR_ACT[2] /LTIR_ACT[1] /LTIR_ACT[0] TIRD[3] TIRD[2]
SRXCLK0 TIRD[1] TIRD[0] VSS /TIRD_V TIRD_CK SRXDV0 SCOL_SP0 SCRS0 TIRD_ODIR SDUPLEX0 STXCLK0 VDD STXD0[3] STXD0[2] STXD0[1] STXD0[0] STXEN0 LED_CK LED LED VSS SRXD1[3] SRXD1[2] SRXD1[1] SRXD1[0] SRXCLK1 SRXDV1 SCOL_SP1 SCRS1 DAISY_OUT DAISY_IN BMCLK VSS LCLK VDD REF_CLK VSS SDUPLEX1 STXCLK1 STXD1[3] STXD1[2] STXD1[1] STXD1[0] STXEN1 /RST /TEST MDIO MDC TXD7[1] TXD7[0] TXEN7
CONFIDENTIAL
AX88872P Swipeater Controller 2.0 Pin Description
The following terms describe the AX88872 pin out: All pin names with the “/” suffix are asserted low. I = Input O = Output I/O = Input /Output
PRELIMINARY
2.1 RMII interface for repeater ports
2.1.1 Repeater Port 0 Signal Name Type
SPEED0 I
Pin No.
160
Description
Speed Select : SPEED0 is not standard RMII signal. This signal is source from PHY to inform repeater whether 10M or 100M speed is auto-negotiated. Active for 10Mbps speed is selected depending on power on configuration. Carrier Sense/Receive Data Valid : CRS_DV is asserted asynchronously on detection of carrier. CRS_DV is asserted by the PHY when receive medium is non-idle. Loss of carrier shall result in the desertion of CRS_DV synchronous to the cycle of REF_CLK that presents the first DI-bits of a nibble on to RXD0[1:0]. Receive Data : RXD0[1:0] is synchronous to REF_CLK RXD0[1:0] shall be “00” to indicate idle when CRS_DV is disserted. Value other than “00” are reserved for out-of-band signaling shall be ignored by MAC Upon assertion of CRS_DV, PHY shall ensure that RXD[1:0] = “00” until proper receive decoding takes place Transmit Enable : TXEN0 is synchronous to REF_CLK. TXEN0 indicates that MAC is presenting DI-bits on TXD[1:0] for transmission. TXEN0 shall be negated prior to the 1st REF_CLK rising edge following the final DI-bit of a frame Transmit Data : TXD0[1:0] shall transition synchronously to REF_CLK. TXD0[1:0] shall be “00” to indicate idle when TX_EN is disserted. Value other than “00” are reserved for out-of-band signaling shall be ignored by PHY. When TX_EN is asserted, TXD[1:0] are accepted for transmission by PHY
CRS_DV0
I
161
RXD0[1:0]
I
163, 162
TXEN0
O
165
TXD0[1:0]
O
168, 167
2.1.2 Repeater Port 1 Signal Name Type
SPEED1 CRS_DV1 RXD1[1:0] TXEN1 TXD1[1:0] I I I O O
Pin No.
169 181 183, 182 184 187, 186
Description
Speed Select : Please references section 2.1.1 PORT0 description. Carrier Sense/Receive Data Valid : Please references section 2.1.1 PORT0 description. Receive Data : Please references section 2.1.1 PORT0 description. Transmit Enable : Please references section 2.1.1 PORT0 description. Transmit Data : Please references section 2.1.1 PORT0 description.
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AX88872P Swipeater Controller
2.1.3 Repeater Port 2 Signal Name Type
SPEED2 CRS_DV2 RXD2[1:0] TXEN2 TXD2[1:0] I I I O O
PRELIMINARY
Pin No.
196 202 204, 203 205 207,206
Description
Speed Select : Please references section 2.1.1 PORT0 description. Carrier Sense/Receive Data Valid : Please references section 2.1.1 PORT0 description. Receive Data : Please references section 2.1.1 PORT0 description. Transmit Enable : Please references section 2.1.1 PORT0 description. Transmit Data : Please references section 2.1.1 PORT0 description.
2.1.4 Repeater Port 3 Signal Name Type
SPEED3 CRS_DV3 RXD3[1:0] TXEN3 TXD3[1:0] I I I O O
Pin No.
1 2 4, 3 5 7, 6
Description
Speed Select : Please references section 2.1.1 PORT0 description. Carrier Sense/Receive Data Valid : Please references section 2.1.1 PORT0 description. Receive Data : Please references section 2.1.1 PORT0 description. Transmit Enable : Please references section 2.1.1 PORT0 description. Transmit Data : Please references section 2.1.1 PORT0 description.
2.1.5 Repeater Port 4 Signal Name Type
SPEED4 CRS_DV4 RXD4[1:0] TXEN4 TXD4[1:0] I I I O O
Pin No.
9 10 12, 11 13 15, 14
Description
Speed Select : Please references section 2.1.1 PORT0 description. Carrier Sense/Receive Data Valid : Please references section 2.1.1 PORT0 description. Receive Data : Please references section 2.1.1 PORT0 description. Transmit Enable : Please references section 2.1.1PORT0 description. Transmit Data : Please references section 2.1.1 PORT0 description.
2.1.6 Repeater Port 5 Signal Name Type
SPEED5 CRS_DV5 RXD5[1:0] TXEN5 TXD5[1:0] I I I O O
Pin No.
33 34 37,36 38 40,39
Description
Speed Select : Please references section 2.1.1 PORT0 description. Carrier Sense/Receive Data Valid : Please references section 2.1.1 PORT0 description. Receive Data : Please references section 2.1.1 PORT0 description. Transmit Enable : Please references section 2.1.1 PORT0 description. Transmit Data : Please references section 2.1.1 PORT0 description.
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AX88872P Swipeater Controller
2.1.7 Repeater Port 6 Signal Name Type
SPEED6 CRS_DV6 RXD6[1:0] TXEN6 TXD6[1:0] I I I O O
PRELIMINARY
Pin No.
41 42 44,43 45 47,46
Description
Speed Select : Please references section 2.1.1 PORT0 description. Carrier Sense/Receive Data Valid : Please references section 2.1.1 PORT0 description. Receive Data : Please references section 2.1.1 PORT0 description. Transmit Enable : Please references section 2.1.1 PORT0 description. Transmit Data : Please references section 2.1.1 PORT0 description.
2.1.8 Repeater Port 7 Signal Name Type
SPEED7 CRS_DV7 RXD7[1:0] TXEN7 TXD7[1:0] I I I O O
Pin No.
49 50 52,51 53 55,54
Description
Speed Select : Please references section 2.1.1 PORT0 description. Carrier Sense/Receive Data Valid : Please references section 2.1.1 PORT0 description. Receive Data : Please references section 2.1.1 PORT0 description. Transmit Enable : Please references section 2.1.1 PORT0 description. Transmit Data : Please references section 2.1.1 PORT0 description.
2.2 MII/RMII interface for switch ports
2.2.1 Switch Port 0 Signal Name Type
STXEN0 O
Pin No.
87
Description
STXD0[3:0]
O
STXCLK0
I
SDUPLEX0
I
SCOL_SP0
I
Transmit Enable : STXEN0 is transition synchronously with respect to the rising edge of STXCLK0. STXEN0 indicates that the port is presenting nibbles on STXD0[3:0] for transmission. When RMII mode, TXEN is transition synchronously with respect to the rising edge of REF_CLK. STXEN0 indicates that the port is presenting nibbles on STXD0[1:0] for transmission. 91,90,89,88 Transmit Data : STXD0[3:0] is transition synchronously with respect to the rising edge of STXCLK0. For each STXCLK period in which STXEN is asserted, TXD[3:0] are accepted for transmission by the PHY. When RMII mode, STXD0[1:0] shall transition synchronously to REF_CLK. TXD0[1:0] shall be “00” to indicate idle when TX_EN is disserted. Value other than “00” are reserved for out-of-band signaling shall be ignored by PHY. When TX_EN is asserted, TXD[1:0] are accepted for transmission by PHY 93 Transmit Clock : STXCLK0 is a continuous clock that provides the timing reference for the transfer of the STXEN0 and STXD0[3:0] signals from the MII port the switch to the PHY. 94 Duplex Select : DUPLEX0 is not standard MII/RMII signal. This signal is source from PHY to inform switch whether 10M or 100M speed is auto-negotiated. 97 Collision : SCOL_SP0 is input from PHY, when collision is detected. 9 ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88872P Swipeater Controller
SCRS0 or SCRS_DV I 96
PRELIMINARY
SRXDV0
I
98
SRXCLK0
I
104
SRXD0[3:0]
I
114,113, 111,110
When RMII mode, the signal is stand for speed indicator. Active for 10Mbps speed is selected depending on power on configuration. Carrier Sense : Asynchronous signal SCRS0 is asserted by the PHY when receive medium is non-idle. When RMII mode, the signal is stand for CRS_DV (Carrier Sense/Receive Data Valid ). CRS_DV is asserted asynchronously on detection of carrier. CRS_DV is asserted by the PHY when receive medium is non-idle. Loss of carrier shall result in the desertion of CRS_DV synchronous to the cycle of REF_CLK, which presents the first DI-bit of a nibble on to RXD0[1:0]. Receive Data Valid : SRXDV0 is driven by the PHY synchronously with respect to SRXCLK0. Asserted high when valid data is present on SRXD0[3:0]. Receive Clock : SRXCLK0 is a continuous clock that provides the timing reference for the transfer of the SRXDV0 and SRXD0[3:0] signals from the PHY to the MII port of the repeater. Receive Data : SRXD0[3:0] is driven by the PHY synchronously with respect to RXCLK. When RMII mode, SRXD0[1:0] shall transition synchronously to REF_CLK SRXD0[1:0] shall be “00” to indicate idle when CRS_DV is disserted. Value other than “00” are reserved for out-of-band signaling shall be ignored by MAC Upon assertion of CRS_DV, PHY shall ensure that RXD[1:0] = “00” until proper receive decoding takes place
2.2.2 Switch Port 1 Signal Name Type
STXEN1 STXD1[3:0] STXCLK1 SDUPLEX1 SCOL_SP1 SCRS1 Or SCRS_DV1 SRXDV1 SRXCLK1 SRXD1[3:0] O O I I I I
Pin No.
60
Description
PORT0 PORT0 PORT0 PORT0 PORT0 PORT0
Transmit Enable : Please references section 2.2.1 SWITCH description. 64,63,62,61 Transmit Data : Please references section 2.2.1 SWITCH description. 65 Transmit Clock : Please references section 2.2.1 SWITCH description. 66 Duplex Select : Please references section 2.2.1 SWITCH description. 76 Collision : Please references section 2.2.1 SWITCH description. 75 Carrier Sense : Please references section 2.2.1 SWITCH description. 77
I I I
Receive Data Valid : Please references section 2.2.1 SWITCH PORT0 description. 78 Receive Clock : Please references section 2.2.1 SWITCH PORT0 description. 82,81,80,79 Receive Data : Please references section 2.2.1 SWITCH PORT0 description.
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AX88872P Swipeater Controller
2.3 Expansion Bus Interface for 100 Mbps
Signal Name
HIRD[3:0]
PRELIMINARY
Type Pin No.
I/O/Z /PU
Description
156, 155 INTER REPEATER DATA : Nibble data input/output. Transfer data from 154, 153 the “active” AX88872/3 to all other “inactive” AX88872/3 chips. The busmaster of the IRD bus is determined by IR_ACT bus arbitration. /HIRD_V I/O/Z 152 INTER REPEATER DATA VALID : This signal reflects the RX_DV /PU status of the active port. Used to frame good packets. HIRD_CK I/O/Z 151 INTER REPEATER CLOCK VALID : All inter repeater signals are /PU synchronized to the rising edge of this clock. HIRD_ODIR O 150 INTER REPEATER DATA IN/OUT DIRECTION : This pin indicates the direction of IRD data . “High” = HIRD[3:0], /HIRD_V , HIRD_CK are Output. “Low” = HIRD[3:0], /HIRD_V , HIRD_CK are Input. /LHIR_ACT[2:0] I/O/OC 128, 126 LOCAL REPEATER ACTIVITY IN/OUT : the function is the same as 125 /HIR_ACTO[3:0] but for local repeater activity only. /HIR_ACTI[3:0] I/PU 132, 131 INTER REPEATER ACTIVITY IN: These pins perform the same 130, 129 function as /HIR_ACTO[3:0] when they serve as input function. Then the /HIR_ACTO[3:0] insert external buffers the input function must be replaced with /HIR_ACTI [3:0]. /HIR_ACTO[3:0] I/O/OC 148, 147 INTER REPEATER ACTIVITY IN/OUT: The local repeater activity 146, 145 appearance, the signal of the related RID (Repeater ID) will be asserted and as an output pin. All other pins serve as input pins but except the collision conditions. When collision occurs , the signal of related (RID-1) pins will also serve as outputs and will active during local collision period. The exception case is when RID = 0, then (RID-1) is replaced with (RID+1).
2.4 Expansion Bus Interface for 10 Mbps
Signal Name
TIRD[3:0]
Type Pin No.
I/O/Z /PU
Description
106, 105 INTER REPEATER DATA : Nibble data input/output. Transfer data from 103, 102 the “active” AX88872/3 to all other “inactive” AX88872/3 chips. The busmaster of the IRD bus is determined by IR_ACT bus arbitration. /TIRD_V I/O/Z 100 INTER REPEATER DATA VALID : This signal reflects the RX_DV /PU status of the active port. Used to frame good packets. TIRD_CK I/O/Z 99 INTER REPEATER CLOCK VALID : All inter repeater signals are /PU synchronized to the rising edge of this clock. TIRD_ODIR O 95 INTER REPEATER DATA IN/OUT DIRECTION : This pin indicates the direction of data for external transceiver. “High” = TIRD[3:0], /TIRD_V , TIRD_CK are Output. “Low” = TIRD[3:0], /TIRD_V , TIRD_CK are Input. /LTIR_ACT[2:0] I/O/OC 109, 108 LOCAL REPEATER ACTIVITY IN/OUT : the function is the same as 107 /TIR_ACTO[3:0] but for local repeater activity only. /TIR_ACTI[3:0] I/PU 119, 118 INTER REPEATER ACTIVITY IN: These pins perform the same 117, 116 function as /HIR_ACTO[3:0] when they serve as input function. Then the /HIR_ACTO[3:0] insert external buffers the input function must be replaced with /HIR_ACTI [3:0]. /TIR_ACTO[3:0] I/O/OC 124, 123 INTER REPEATER ACTIVITY IN/OUT: The local repeater activity 121,120 appearance, the signal of the related RID (Repeater ID) will be asserted and as an output pin. All other pins serve as input pins but except the collision conditions. When collision occurs , the signal of related (RID-1) pins will also serve as outputs and will active during local collision period. The exception case is when RID = 0, then (RID-1) is replaced with (RID+1).
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AX88872P Swipeater Controller
2.5 LED Display
Signal Name
LED[1:0]
PRELIMINARY
Type Pin No.
O 85, 84
Description
Those signals indicate each port‘s statuses (such as activity, jabber and partition) and global information(such as Collision , Repeater ID, Utilization ) in sequence. For detail , see the LED timing specification The utilization of 100M segment and 10M segment are using the same scale. The Utilization % display define as following : (See also Note 1) 1: Led off 0: Led on Utilization % 0 1 5 10 15 30 60 UTI0 1 0 0 0 0 0 0 UTI1 1 1 0 0 0 0 0 UTI2 1 1 1 0 0 0 0 UTI3 1 1 1 1 0 0 0 UTI4 1 1 1 1 1 0 0 UTI5 1 1 1 1 1 1 0
The buffer utilization of internal switch uses the following definition: 1: Led off 0: Led on Utilization % 0 10 20 40 60 80 95 UTI0 1 0 0 0 0 0 0 UTI1 1 1 0 0 0 0 0 UTI2 1 1 1 0 0 0 0 UTI3 1 1 1 1 0 0 0 UTI4 1 1 1 1 1 0 0 UTI5 1 1 1 1 1 1 0
LED[0] : This signal also indicates SRAM chip 0 fail ( continue active low ) and 100M repeater collision ( Blinking ) during the interval of sequence shift data. LED[1] : This signal also indicates SRAM chip 1 fail ( continue active low ) and 10 M repeater collision ( Blinking ) during the interval of sequence shift data. LED_CK O 86 LED Clock : The signal is a discontinue clock for LED signals serial shift out. The clock period width is 400nS and last 32 cycle with every 52.4ms repeated.
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AX88872P Swipeater Controller
PRELIMINARY
2.6 Buffer memory pins group
Signal Name
BMA[16:0]
Type Pin No.
O 197-201 16,17 170,166 143,142 23-18 24, 26-32 133-138 140, 141 171-173 175-179 180, 188-194 158 159 72 SSRAM Address Bus
Description
BMD[31:24] BMD[23:16] BMD[15:8] BMD[7:0] /BMWE /BMOE BMCLK
I/O
SSRAM Data Bus
O O O
SSRAM Write Strobe SSRAM Read Strobe SSRAM CLOCK
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AX88872P Swipeater Controller
2.7 Miscellaneous
Signal Name
LCLK /RST REF_CLK DAISY_IN
PRELIMINARY
Type Pin No.
I I I I/PU 70 59 68 73
Description
Local Clock : 50-66Mhz. Used for system operation synchronous. Reset : Active Low The chip is reset when this signal is asserted Low Reference clock : The input is a continuous clock at 50Mhz for timing reference with RMII interface. Repeater Identification Number Daisy-Chain In : When MODE=” 1” , This pin is a daisy chain serial input for Repeater ID. The State machines always monitors the input if a correct data (RID) present at the pin, the (RID+1) will be written to RID register and override the power on setup RID for the chip. Repeater Identification Number Daisy-Chain Out : When MODE=” 1” , This pin is periodically shift out the RID of itself to the next chained chip to inform that this ID has already been occupied. The RID is shift out periodically every about 200us. Station Management Data In/Out : For setup PHY auto-negotiation registers. A burst write commands are issue to setup PHY register after reset. The PHY address 4h, 5h, 6h, 7h, 8h, 9h,Ah and Bh will be written as register 4h to value 00A1h ( Advertise register set to 10/100 half-duplex mode)and register 0h to value 1000h(Enable auto-negotiation). See also Appendix for more information. Station Management Data Clock Out : For MDIO reference clock. Test Pin : Active LOW The pin is just for test mode setting purpose only. Must be pull high when normal operation. NC : Keep no connection POWER : +3.3V +/-5%
DAISY_OUT
O/ML
74
MDIO
I/O
57
MDC /TEST
O I/PU
56 58
NC VDD
O I
VSS
I
157 25, 48 69, 92 122, 144 107, 120 8, 35 POWER: 0V 67, 71 83, 101 112,115 127, 139 149, 174 185, 208
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AX88872P Swipeater Controller
2.8 Power on configuration setup signals cross reference table
Signal Name
/Hash_En
PRELIMINARY
Share with
BMA[16]
Description
Hash Algorithm Enable : 0 : Enable look-up table addressing use hashing algorithm. 1 : Disable look-up table addressing use linear addressing Aging Timer Selection : Aging_S2 Aging_S1 Aging_S0 Aging Time (Min) 1 1 1 no aging (disable) 1 1 0 5 1 0 1 10 1 0 0 20 0 1 1 40 0 1 0 160 0 0 1 640 0 0 0 1 PAUSE Identification Enable : 0 : Disable 802.3x receives flow control function in full duplex. 1 : Enable 802.3x receives flow control function in full duplex. MII/RMII Interface Selection for Switch Port 1: 0 : Switch port 1 “RMII” mode is selected 1 : Switch port 1 “MII” mode is selected MII/RMII Interface Selection for Switch Port 0: 0 : Switch port 0 “RMII” mode is selected 1 : Switch port 0 “MII” mode is selected TX Partition Enable : 0 : Enable partition function of transmission. 1 : Disable partition function of transmission. RAM Size Selection : External packet buffer RAM size select RAM_S RAM SIZE 1 64K * 32 SSRAM 0 128K * 32 SSRAM Network Quality Selection: Auto forwarding mode is based on packet error percentage to select Store-and-Forward or Fragment Free mode. NetQlty_S Error Packet Ratio 1 20% 0 40% Forward Type Selection : FwTyp _S1 FwTyp _S0 Forward Mode 1 1 Store & Forward 1 0 Store & Forward 0 1 Fragment Free 0 0 Auto Threshold Selection for Flow Control : Flow control will be active when buffer memory is below the threshold: HiBndy_S1 HiBndy_S0 Buffers Left 1 1 64 packets 1 0 32 packets 0 1 16 packets 0 0 96 packets P3 Flow Control Enable : Enable flow control function of switch port 3 (Link to 10Mbps repeater port), back pressure for half duplex. 0 : Enable flow control function. 15 ASIX ELECTRONICS CORPORATION
Aging_S[2:0]
BMA[15:13]
RxFC_En
BMA[12]
MII_S1
BMA[11]
MII_S0
BMA[10]
/Part_En
BMA[9]
RAM_S
BMA[5]
NetQlty_S
BMA[4]
FwTyp_S1 FwTyp_S0
BMA[3] BMA[2]
HiBndy_S1 HiBndy_S0
BMA[1] BMA[0]
/ FlowCtl _En3
STXD0[3]
CONFIDENTIAL
AX88872P Swipeater Controller
/ FlowCtl _En2 STXD0[2]
PRELIMINARY
/ FlowCtl _En1
STXD0[1]
/FlowCtl_En0
STXD0[0]
Speed_S2
TXD7[1]
Speed_S1
STXD1[2]
Speed_S0
STXD1[1]
FdpxHi_S1
STXD1[0]
FdpxHi_S0
STXEN1
LRID_S1 LRID_S0
TXD5[1] TXD5[0]
/871_En
TXEN6
/RdPhy_En
TXD6[0]
WrPhyNo_S
TXD4[1]
WrPhyRegNo_S
TXD4[0]
WrPhyStrAddr
TXD3[1]
PktLenOpt
TXD3[0]
1 : Disable flow control function. P2 Flow Control Enable : Enable flow control function of switch port 2 (Link to 100Mbps repeater port), back pressure for half duplex. 0 : Enable flow control function. 1 : Disable flow control function. P1 Flow Control Enable : Enable flow control functions of switch port 1, 802.3x for full duplex, back pressure for half duplex. 0 : Enable flow control function. 1 : Disable flow control function. P0 Flow Control Enable : Enable flow control function of switch port 0, 802.3x for full duplex, back pressure for half duplex. 0 : Enable flow control function. 1 : Disable flow control function. Speed Setting for Repeater Port 0 to Port 7 : 0 : SPEED0~7 pin is Low for 10M,high for 100M 1 : SPEED0~7 pin is Low for 100M,high for 10M Speed Setting for Switch Port 1 : It is useful for switch port 1 in RMII mode Don’t care the setting when switch port 1 is in MII mode. 0 : SCOL_SP1 pin is Low for 10M,high for 100M 1 : SCOL_SP1 pin is Low for 100M,high for 10M Speed Setting for Switch Port 0 : It is useful for switch port 0 in RMII mode Don’t care the setting when switch port 0 is in MII mode. 0 : SCOL_SP0 pin is Low for 10M,high for 100M 1 : SCOL_SP0 pin is Low for 100M,high for 10M Duplex Setting for Switch Port 1 : Switch Port 1 “SDUPLEX1” pin function select 0 : SDUPLEX1 pin is low for half duplex,high for full duplex 1 : SDUPLEX1 pin is low for full duplex,high for half duplex Duplex Setting for Switch Port 0 : Switch Port 0 “SDUPLEX0” pin function selection 0 : SDUPLEX0 pin is low for half duplex,high for full duplex 1 : SDUPLEX0 pin is low for full duplex,high for half duplex Local Repeater ID Selection : LRID_S1 LRID_S0 LRID No. 1 1 0 1 0 1 0 1 2 0 0 reserved AX88871A Compatible Enable : 0 : Enable AX88871A compatible mode 1 : Disable AX88871A compatible mode MDIO read PHY Register 05h Information 0 : Enable 1 : Disable MDIO Write PHY Number Selection 1 : MDIO Write 8 PHY address 0 : MDIO Write 6 PHY address ( for 6R+2S application ) MDIO Write PHY Register Number Selection 0 : MDIO Write 2 Registers ( 04h, 00h ) 1 : MDIO Write 3 Registers ( 10h, 04h, 00h ) MDIO Write PHY Starting Address 0 : MDIO Write PHY from address 18h ( 18h to 1Fh ) 1 : MDIO Write PHY from address 04h ( 04h to 0Bh ) Maximun Packet Length Selection 0 : 1522 Byte 16 ASIX ELECTRONICS CORPORATION
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AX88872P Swipeater Controller
1 : 1518 Byte
PRELIMINARY
All of the above signals are pull-up for default values.
Note 1 :
The calculation formulae of Traffic Utilization between ASIX and NetCom is difference, so you will get different results when using SmartBit (SB) testing this item. We found the SmartBit calculate the Utilization without include 96 Bit time inter frame gap (IFG). So the utilization value can be 100%. As well as we found SB used min packet size (64 byte) and min IFG (96 bit-time) as 100% utilization. In theory, when max packet size (1518 byte) and min IFG the utilization will be more than 100%, but SB also treat it as 100%. In our AX88872 design, we use real cable bandwidth as calculation base. We calculate the bit counts of carrier within a unit time. Because of the existence of inter frame gap, In our calculation 100% utilization is impossible. So the above two cases (64 byte packet size and 1518 byte packet size with min. IFG), we will count as 85.7% and 99.2%. If using SB test result to indicate utilization LED the value must be modified. See the following reference table. ASIX’s Utilization% SmartBit’s Utilization% 1 2 5 7 10 12 15 17 30 34 60 68
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AX88872P Swipeater Controller 3.0 Functional Description
3.1 Repeater State Machine
PRELIMINARY
The repeater state machine is in idle state when there is no carrier presented on any ports . When there is only one port has receive activity, the repeater state machine will enter data -forwarding state to ensure correct data forwarding to other connected ports. If collision happens anytime, The repeater state machine detects collision then send jam pattern to all ports until collision ceases.
3.2 RXE /TXE Control
Idle state CRS_DV(ALL) = 0, the repeater sends no data to any port. RXE(ALL) = 0. TXE(ALL) = 0. Data Forwarding state If CRS_DV(ALL) = 1, N is the only one port that has incoming packet. RXE(N) = 1, RXE(ALLXN) = 0. TXE(N) = 0, TXE(ALLXN) = 1. Collision state If CRS_DV(ALL) > 1, the repeater sends jam pattern to all ports. RXE(ALL) = 0. TXE(ALL) = 1. One Port Left state When all packets are back off except only one port still has activity, that is CRS_DV(ALL) = 1 again . N is the only one left port that has incoming packet. The repeater sends jam pattern to all other port except for the still activity ports. RXE(ALL) = 0. TXE(ALLXN) = 1.
3.3 Jabber State Machine
To prevent an illegally long reception of data from reaching the repeater unit, each port has its own jabber timer. If a reception exceeds this duration (64K bit times for AX88872), the jabber condition will be detected. In this condition, repeater unit will disable receive and transmit packets for the jabbered port and the other ports remain the normal operation. When the carrier is no longer detected for the jabbered port or reset the repeater, the jabber state will be existed and the port will receive and transmit packets normally.
3.4 Partition State Machine
The partition state machine is used to protect network from being upset when a port suffer continuous 18 ASIX ELECTRONICS CORPORATION
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AX88872P Swipeater Controller
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collision, each port uses a partition state machine to detect and prevent this condition. When a port suffers from continuous 64 times of collision events, then it goes to Partition State. The partitioned port will be not released until a packet without collision be transmitted( more than 512 bit times for AX88872) or reset the repeater.
3.5 Operation of the Built-In Switch
In general, the basic operation of the switch is very simple. The switch receives incoming packets from one of its ports, searches in the Look-Up Table for the Destination MAC Address and then forwards the packet to the destination ports, if appropriate. If the destination MAC address is not found in the Look-Up Table, the switch treats the incoming packet as a broadcast packet and forwards it to all ports except itself. Basically the switch automatically learns the port number of attached network devices by examining the Source MAC Address of all incoming packets. The device is updated the table with the Source MAC Address if the Source MAC Address does not exist the table.
3.5.1 Packet Filtering and Forwarding Process
During the receiving process, the switch will monitor the length of the received packet. Legal Ethernet packets should have a length of no less 64 bytes and nor more than 1528 bytes. The switch discards any packet with illegal length. After a packet is received, its Source MAC Address and Destination MAC Address are received. The Source MAC Address is used to update the Look-Up Table and the Destination MAC Address is used to determine the destination port of the packet. Once a MAC Address has been learned, and the packet is buffered, it must be forwarded, That is, the packet forwarding mechanism for the switch is handled automatically based on the destination MAC Address. Under the following conditions, received packets are filtered: ¨ The switch will check all received packets for errors, e.g., FCS error, runt packet, long packet, etc. ¨ Any packet handing to its own source port will be filtered. That is, its destination port is its source port. ¨ The incoming packet will be discarded if the switch’s buffer memory is full. The switch supports three forwarding modes: Store-and-Forward, Fragment-Free and Auto. ¨ Store-and-Forward Mode: An entry packet is received, checked and stored in the buffer memory before it is forwarded. That is, each forwarded packet is correct. ¨ Fragment-Free Mode: It is a simple improvement on Cut-Through method. The switch will forward a packet whose packet length is more than 64 bytes. All runt packets will be filtered in Fragment-Free mode. ¨ Auto Mode: In Auto mode, the switch select dynamically its optimized forwarding mode based on the current network quality of each port.
3.5.2 MAC Address Learning and Aging Process
The switch can learn up to 8K unique MAC addresses with a hashing algorithm. Addresses are stored in the Look-Up Table located in external SSRAM, then each packet updates the table. The table lookup engine provides the switching information required routing the data packets. The address table is set up through auto address learning dynamically. After the switch receives a packet, the Source MAC Address and Destination MAC Address are received. The Source Address retrieved from the received packet is automatically stored in a SA buffer. The switch will check for error and perform a SA search. The switch will update the Look-Up Table with the Source MAC Address if there is no error. The Look-Up Table is cleared on power-on, or hardware reset. When the aging option is enabled, the dynamically Learned SA will be cleared if it is not refreshed in less than configured time (2 or 5 min).
3.5.3 Flow Control Process
The switch can operate at two different modes: half-duplex and full-duplex. Each port can be configured to have flow control enabled or not. The switch supports 802.3X for full-duplex operation and uses back pressure for half-duplex. In full-duplex mode, the switch will receive and transmit the packet in accordance to 802.3X. The transmission channel and the receiving channel operate independently. If the occupancy of the buffer memory is above the FlowControlActive 19 ASIX ELECTRONICS CORPORATION
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AX88872P Swipeater Controller
PRELIMINARY
threshold, the MAC of port will send out a PAUSE frame with maximum delay. The switch will send out a PAUSE frame with zero delay after below FlowControlActive threshold. For the receiving channel, the switch will not transmit the next packet whenever received a PAUSE frame with non-zero delay. The switch will resume packet transmission either after the pause timer expired or a PAUSE frames with zero delay received. In half-duplex mode, the switch will receive and transmit the packet in accordance to 802.3 CSMA/CD. If the occupancy of the buffer memory is above the FlowControlActive threshold, the MAC of port will send out JAM pattern .
3.6 LED Display Interface
AX88872 provides per-port LED status indication for partition, jabber, activity and support rate - based LED for 10 and 100Mbps segments utilization (%) and switch buffer utilization (%) . All LED[1:0] perform active low. LED[1:0] Status Driver Wave-form as follows :
LED_CK D0 LED[0]
RID3
D1
D2
D3
10M UTI4
D4
10M UTI3
D5
10M UTI2
D6
10M UTI1
D7
10M UTI0
D8
RID1
D9
D10
D11
D12
D13
D14
D15
10M RID2 UTI5
100M 100M 100M 100M 100M 100M RID0 UTI5 UTI4 UTI3 UTI2 UTI1 UTI0
D16 LED[0] Continue
D17
D18
D19
D20
D21
D22
D23
( This portation no clock presented )
Chip 0 Memory Test Fail and/or 100M Collision
ACT7 ACT6 ACT5 ACT4 ACT3 ACT2 ACT1 ACT0
LED[1]
JAB7
JAB6
JAB5
JAB4
JAB3
JAB2
JAB1
JAB0
SW SW ACT1 ACT0
SW UTI5
SW UTI4
SW UTI3
SW UTI2
SW UTI1
SW UTI0
LED[1] Continue
PART PART PART PART PART PART PART PART 7 6 5 4 3 2 1 0
Chip 1 Memory Test Fail and/or 10M Collision
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AX88872P Swipeater Controller
Notes: a. b. c. d. e. f. g. h.
PRELIMINARY
PART7~0indicates partition status for each port JAB7~0 indicates jabber status for each port ACT7~0 indicates activity status for each port RID3~0 is the ID of repeater chip 10M UTI5~0 indicate global utilization rate of 10Mbps for each 104.8ms sampling period. 100M UTI5~0 indicate global utilization rate of 100Mbps for each 104.8ms sampling period. SW UTI5~0 indicate global utilization rate of Switch packet buffers for each 104.8ms sampling period. RAM FAIL : Switch RAM test fail.
It has to use external shift register to decode data on LED[1:0]. The application shows as follows:
100M UTI5
100M UTI4
100M UTI3
100M UTI2
100M UTI1
100M UTI0
10M UTI5
10M UTI4
10M UTI3
10M UTI2
10M UTI1
10M UTI0
RID3
RID2
RID1
RID0
ACT7
ACT6
ACT5
ACT4
ACT3
ACT2
ACT1
Q 0
LED[0] LED_CK
Q 1
Q 2
Q 3
Q 4
Q 5
Q 6
Q 7
Q 0 D
Q 1
Q 2
Q 3
Q 4
Q 5
Q 6
Q 7
Q 0 D
Q 1
Q 2
Q 3
Q 4
Q 5
Q 6
D
74LS164(#1)
74LS164(#2)
74LS164(#3)
Fig - 3 Application for LED display
If the user don‘t want to show jabber status, take away the latter 74LS164(#2). The application is the same for LED[1].
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ACT0
Q 7
CONFIDENTIAL
AX88872P Swipeater Controller 4.0 INTERNAL REGISTERS
(This page keep blank)
PRELIMINARY
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AX88872P Swipeater Controller
PRELIMINARY
5.0 ELECTRICAL SPECIFICATION AND TIMING
5.1 Absolute Maximum Ratings
Description SYM Min Max Units Operating Temperature Ta 0 +70 °C Storage Temperature Ts -55 +150 °C Supply Voltage Vcc -0.3 +4 V Input Voltage Vin -0.3 Vdd+0.5 V Output Voltage Vout -0.3 Vdd+0.5 V Lead Temperature (soldering 10 seconds maximum) Tl -55 +220 °C Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability
5.2 General Operation Conditions
Description Operating Temperature Supply Voltage SYM Ta Vdd Min 0 +3.0 Max +70 +3.6 Units °C V
5.3 DC Characteristics
(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 70°C) Description Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage Input Leakage Current 1 (Note 1) Input Leakage Current 2 (Note 2) Output Leakage Current Description Power Consumption SYM Pc
SYM Vil Vih Vol Voh Iil1 Iil1 Iol Min
Min Vss-0.3 2 2.4
Max 0.8 Vdd+0.5 0.4 10 500 10 V V V V uA uA uA
Units
Typ TBD
Max mA
Units
Note : a. All the input pins without pull low or pull high. b. Those pins had been pull low or pull high.
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AX88872P Swipeater Controller
5.4 AC specifications
5.4.1 LCLK
Thigh
PRELIMINARY
LCLK
Tr Tf Tcyc Tlow
BMCLK
Tod
Symbol
Tcyc Thigh Tlow Tr/Tf Tod
Description
CYCLE TIME CLK HIGH TIME CLK LOW TIME CLK SLEW RATE LCLK TO BMCLK OUT DELAY
Min 8 8 1
Typ. 20 10 10 2
Max 12 12 4
Units ns ns ns ns ns
5.4.2 Reset Timing REF_CLK /RST
Symbol
Trst Reset pulse width
Description
Min 10
Typ. -
Max -
Units REF_Clk
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AX88872P Swipeater Controller
5.4.3 RMII Interface Timing TX & RX T0 REF_CLK T2 TX_EN T3 T1
PRELIMINARY
TXD CRS_DV T2 RXD T3
Symbol Description T0 REF_CLK Clock Cycle Time T1 REF_CLK Clock High Time T2 CRS_DV, RXD, TXEN and TXD data setup to REF_CLK rising edge T3 CRS_DV, RXD, TXEN and TXD data hold from REF_CLK rising edge
Min 19.998 7 4 2
Typ. 20 10
Max 20.002 13
Units ns ns ns ns
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AX88872P Swipeater Controller
5.4.4 MII Interface Timing TX & RX T0 TXCLK T2 TX_EN T2 T1
PRELIMINARY
T3
T3
TXD
Symbol T0 T1 T2 T3 Description TXCLK Cycle Time TXCLK High Time TX_EN Delay from TXCLK High TXD Delay from TXCLK High Min 39.996 14 7.440 3.410 Typ. 40 20 Max 40.004 26 21.760 13.320 Units ns ns ns ns
T4 RX_CLK CRS
T5
T6 RXDV T7 RXD RXER
Symbol T4 T5 T6 T7 Description RX_CLK Clock Cycle Time RX_CLK Clock High Time CRS to RXDV Delay Requirement RXD or RXDV setup to RX_CLK rise time Min 39.996 14 40 10 Typ. 40 20 Max 40.004 26 160 Units ns ns ns ns
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AX88872P Swipeater Controller
5.4.5 SRAM read cycle Read cycle
T1
PRELIMINARY
BMCLK
T2 T3
BMA[16:0]
A1
/BMWR
/BMOE
T5 T4 D1
BMD[7:0]
Symbol T1 T2 T3 T4 T5
Description Clock Cycle Time Address Bus Setup Time Address Bus Hold Time Clock to Output Invalid Clock to Output Valid
Min 15 2.5 0.5 2 -
Max 6
Units ns ns ns ns ns
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AX88872P Swipeater Controller
5.4.6 SRAM write cycle
T1
PRELIMINARY
T1
BMCLK
T2 T3
BMA[16:0]
A1
/BMWR
/BMOE
T4 T5
BMD[7:0]
D1
Symbol T1 T2 T3 T4 T7
Description Clock Cycle Time Address Bus Setup Time Address Bus Hold Time Write Data Setup Time Write Data Hold Time
Min 15 2.5 0.5 2.5 0.5
Max -
Units ns ns ns ns ns
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AX88872P Swipeater Controller
5.4.7 LED DISPLAY T3 LED_CK
PRELIMINARY
-------D0 D1 D2 .............. D22 D23
------D0 D1 D2
~ ~
T4
T3
LED_CK T1 T2 LED[1:0]
D0 D1 D2 D3 ------D15 D0
Symbol T1 T2 T3 T4
Description LED setup to LED_CK High LED hold from LED_CK High LED_CK Period Width LED_CK Cycle burst out period
Min 190 200
Typ.
Max 200 210
400 52.4
Units ns ns ns ms
5.4.8 LED Display after Reset /Reset T1 LED[2:0] T2 T2 T2 T3
Symbol Description T1 Repeater reset time T2 LED Blink Time After Reset T3 LED Dark Time Before Normal Display
Min 1000
Typ. 838.4 419.2
Max
Units ns ms ms
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AX88872P Swipeater Controller
5.4.9 Repeater ID Daisy Chain T1 T2 T2 Daisy-Out T3 Daisy-In ID0 ID1 ID2 ID0 ID1 ID2 ID0
PRELIMINARY
ID1
ID2
ID0 ID1
ID2
Symbol Description Min Typ. Max Units T1 Daisy Chain One Burst period 204.8 us T2 Start Bit Period or Data Width 12.8 us T3 Time-out occur when no data present on Daisy_in * 3.8 s Note : Daisy-Chain Data-In Time-out stands for no input data (always high level) for the specific time.
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CONFIDENTIAL
AX88872P Swipeater Controller 6.0 PACKAGE INFORMATION
He E A2
PRELIMINARY
A1
Hd
D
pin 1
b
e
θ
SYMBOL MIN.
A1 A2 b D E e Hd He L L1 θ 0 30.35 30.35 0.45 0.05 3.17 0.10 27.90 27.90
MILIMETER NOM
0.25 3.32 0.20 28.00 28.00 0.50 30.60 30.60 0.60 1.30 10 30.85 30.85 0.75
L
L1
MAX
0.5 3.47 0.30 28.10 28.10
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CONFIDENTIAL
AX88872P Swipeater Controller Appendix A: System Applications
Some typical applications for AX88872 are illustrated bellow.
PRELIMINARY
A.1 16-port (24-port) repeater with 2-port switch
10Mbps and 100Mbps Vertical cascade up to 4 stacks
Buffer
10Mbps horizontal cascade 100Mbps horizontal cascade
AX88873 #1
Repeater Controller
AX88872 #0
Swipeater Controller PHY for Up-link
2 Quad RMII PHY
2 Quad RMII PHY
PHY for Down-link or Server
Note : Add additional AX88873 to build a 24-port repeater
A.2 16-port repeater with up to 4 stacks
10Mbps and 100Mbps Vertical cascade up to 4 stacks
Buffer
10Mbps horizontal cascade 100Mbps horizontal cascade
Repeater #3 Slave
AX88873 #1
Repeater Controller
AX88872 #0
Swipeater Controller PHY for Up-link
2 Quad RMII PHY
2 Quad RMII PHY
PHY for Down-link or Server Repeater #1,#2 Slave (omitted)
Buffer
10Mbps horizontal cascade 100Mbps horizontal cascade
Repeater #0 Master
AX88873 #1
Repeater Controller
AX88872 #0
Swipeater Controller PHY for Up-link
2 Quad RMII PHY
2 Quad RMII PHY
PHY for Down-link or Server
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AX88872P Swipeater Controller
A.3 8-port standalone repeater with 2-port switch
PRELIMINARY
AX88872 #0
Swipeater Controller
2 Quad RMII PHY
PHY for Up-link
PHY for Down-link or Server
A.4 16-port repeater with up to 4 stacks of AX88871A compatible mode
100Mbps Vertical cascade up to 4 stacks Repeater #3
Buffer
100Mbps horizontal cascade
AX88872 #1
Swipeater Controller
AX88872 #0
Swipeater Controller
2 Quad RMII PHY
Twin-PHY for Servers
2 Quad RMII PHY
Twin-PHY for Uplink or Down-link Repeater #1,#2 (omitted)
Repeater #3
Buffer
100Mbps horizontal cascade
AX88872 #1
Swipeater Controller
AX88872 #0
Swipeater Controller
2 Quad RMII PHY
Twin-PHY for Servers
2 Quad RMII PHY
Twin-PHY for Uplink or Down-link
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AX88872P Swipeater Controller
A.5 16-port repeater with up to 4 stacks and more switch ports
PRELIMINARY
10Mbps and 100Mbps Vertical cascade up to 4 stacks
Buffer
10Mbps and 100Mbps horizontal cascade
Repeater #3 slave
AX88872 #1
Swipeater Controller
AX88872 #0
Swipeater Controller
2 Quad RMII PHY
Twin-PHY for Servers
2 Quad RMII PHY
Twin-PHY for Uplink or Down-link Repeater #1,#2 Slave (omitted)
Buffer
10Mbps and 100Mbps horizontal
Repeater #0 Master
AX88872 #1
Swipeater Controller
AX88872 #0
Swipeater Controller
2 Quad RMII PHY
Twin-PHY for Servers
2 Quad RMII PHY
Twin-PHY for Uplink or Down-link
Note : Only the switch ports between 10M and 100M segment of Repeater #0/AX88872 #0 are enable
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AX88872P Swipeater Controller Appendix B: Design Note
B.1 Using Station Management (STA) Connection
PRELIMINARY
There are two methods to get two switch port speed and duplex information in AX88872 . One way is by hardware pins such as SPEED0, SDUPLEX0, SPEED1, SDUPLEX1. AX88872 also provides 2 pins (MDC and MDIO, STA – Station Management connection) to read PHY Auto Negotiation Remote Capability register to get current speed and duplex status. For the PHY connected to repeater ports must be configured by STA write function. In a word, AX88872 use STA read function to get PHY register status for switch port and use STA write function to program PHY register for hub port. The address setting of PHY must be fixed as follows: Application 1: 8 hub ports + 2 switch ports application RP : repeater port SP : switch port RP0 RP1 RP2 RP3 RP4 RP5 RP6 04h 05h 06h 07h 08h 09h 0ah The corresponding option setting /RdPhy_En = 0, WrPhyNo_S = 1, WrPhyStrAddr = 1 Application 2: 6 hub ports + 2 switch ports application RP : repeater port SP : switch port RP0 RP1 RP2 RP3 RP4 RP5 SP0 18h 19h 1ah 1bh 1ch 1dh 1eh The corresponding option setting /RdPhy_En = 0, WrPhyNo_S = 0, WrPhyStrAddr = 0
RP7 0bh
SP0 0fh
SP1 10h
SP1 1fh
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AX88872P Swipeater Controller
B.2 Using MII I/F connects to MAC
PRELIMINARY
There are two ports of AX88872 can connect to MAC type MII interface. For example, Switch Port 0 is illustrated bellow.
3.3V 10K * 2
25MHz Clock
Note : 1. The MAC needs to run at fullduplex mode. 2. Care must be taken that the receive side has enough setup and/or hold time 3. Some kind of CPU with embbeded MAC can also refer to this example
BMA[10]
AX88872 / Swipeater
STXEN1
SDUPLEX0 SCOL0 STXEN0 STXCLK0 STXD0[3:0] COL CRS RX_DV RX_CLK RXD[3:0] RX_ER TX_EN TX_CLK TXD[3:0] TX_ER
SCRS0 SRXDV0 SRXCLK0 SRXD0[3:0] 10K Gnd
AX88195 / MAC
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