AT28HC64BF_09

Features • Fast Read Access Time – 70 ns • Automatic Page Write Operation – Internal Address and Data Latches for 64 Bytes • Fast Write Cycle Times – Page Write Cycle Time: 2 ms Maximum (Standard) – 1 to 64-byte Page Write Operation Low Power Dissipation – 40 mA Active Current – 100 µA CMOS Standby Current Hardware and Software Data Protection DATA Polling and Toggle Bit for End of Write Detection High Reliability CMOS Technology – Endurance: 100,000 Cycles – Data Retention: 10 Years Single 5 V ±10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-wide Pinout Industrial Temperature Ranges Green (Pb/Halide-free) Packaging Only • • • • • • • • • 64K (8K x 8) High Speed Parallel EEPROM with Page Write and Software Data Protection AT28HC64BF 1. Description The AT28HC64BF is a high-performance electrically-erasable and programmable read-only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 100 µA. The AT28HC64BF is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin. Atmel’s AT28HC64BF has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. 3648B–PEEPR–4/09 2. Pin Configurations Pin Name A0 - A12 CE OE WE I/O0 - I/O7 NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect 2.2 32-lead PLCC Top View A7 A12 NC DC VCC WE NC Note: PLCC package pins 1 and 17 are Don’t Connect. 2.1 28-lead SOIC Top View NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 2 AT28HC64BF 3648B–PEEPR–4/09 I/O1 I/O2 GND DC I/O3 I/O4 I/O5 14 15 16 17 18 19 20 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 12 13 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE A10 CE I/O7 I/O6 AT28HC64BF 3. Block Diagram VCC GND OE WE CE Y DECODER ADDRESS INPUTS X DECODER IDENTIFICATION DATA INPUTS/OUTPUTS I/O0 - I/O7 OE, CE and WE LOGIC DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING CELL MATRIX 4. Device Operation 4.1 Read The AT28HC64BF is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high-impedance state when either CE or OE is high. This dual line control gives designers flexibility in preventing bus contention in their systems. 4.2 Byte Write A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. 4.3 Page Write The page write operation of the AT28HC64BF allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; after the first byte is written, it can then be followed by 1 to 63 additional bytes. Each successive byte must be loaded within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded, the AT28HC64BF will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 to A12 inputs. For each WE high-to-low transition during the page write operation, A6 to A12 must be the same. The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. 4.4 DATA Polling The AT28HC64BF features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at any time during the write cycle. 3 3648B–PEEPR–4/09 4.5 Toggle Bit In addition to DATA Polling, the AT28HC64BF provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling, and valid data will be read. Toggle bit reading may begin at any time during the write cycle. 4.6 Data Protection If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel® has incorporated both hardware and software features that will protect the memory against inadvertent writes. 4.6.1 Hardware Protection Hardware features protect against inadvertent writes to the AT28HC64BF in the following ways: (a) VCC sense – if VCC is below 3.8 V (typical), the write function is inhibited; (b) VCC power-on delay – once VCC has reached 3.8 V, the device will automatically time out 5 ms (typical) before allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. Software Data Protection A software-controlled data protection feature has been implemented on the AT28HC64BF. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28HC64BF is shipped from Atmel with SDP disabled. SDP is enabled by the user issuing a series of three write commands in which three specific bytes of data are written to three specific addresses (refer to the “Software Data Protection Algorithm” diagram on page 10). After writing the 3-byte command sequence and waiting tWC, the entire AT28HC64BF will be protected against inadvertent writes. It should be noted that even after SDP is enabled, the user may still perform a byte or page write to the AT28HC64BF. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP. Once set, SDP remains active unless the disable command sequence is issued. Power transitions do not disable SDP, and SDP protects the AT28HC64BF during power-up and powerdown conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not actually written into the device; their addresses may still be written with user data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device, however. For the duration of tWC, read operations will effectively be polling operations. 4.6.2 4.7 Device Identification An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12 V ±0.5 V and using address locations 1FC0H to 1FFFH, the additional bytes may be written to or read from in the same manner as the regular memory array. 4 AT28HC64BF 3648B–PEEPR–4/09 AT28HC64BF 5. DC and AC Operating Range AT28HC64BF-70 Operating Temperature (Case) VCC Power Supply -40°C - 85°C 5 V ±10% AT28HC64BF-90 -40°C - 85°C 5 V ±10% AT28HC64BF-120 -40°C - 85°C 5 V ±10% 6. Operating Modes Mode Read Write(2) Standby/Write Inhibit Write Inhibit Write Inhibit Output Disable Chip Erase Notes: 1. X can be VIL or VIH. 2. See “AC Write Waveforms” on page 8. 3. VH = 12.0 V ±0.5 V. CE VIL VIL VIH X X X VIL OE VIL VIH X (1) WE VIH VIL X VIH X X VIL I/O DOUT DIN High Z X VIL VIH VH (3) High Z High Z 7. Absolute Maximum Ratings* Temperature Under Bias................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground .................................-0.6 V to +6.25 V All Output Voltages with Respect to Ground ...........................-0.6 V to VCC + 0.6 V Voltage on OE and A9 with Respect to Ground ..................................-0.6 V to +13.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability 8. DC Characteristics Symbol ILI ILO ISB1 ISB2 ICC VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1 mA IOH = -400 µA 2.4 2.0 0.40 Condition VIN = 0 V to VCC + 1 V VI/O = 0 V to VCC CE = VCC - 0.3 V to VCC + 1 V CE = 2.0 V to VCC + 1 V f = 5 MHz; IOUT = 0 mA Min Max 10 10 100 2 40 0.8 Units µA µA µA mA mA V V V V 5 3648B–PEEPR–4/09 9. AC Read Characteristics AT28HC64BF-70 Symbol tACC tCE(1) tOE(2) tDF(3)(4) tOH Parameter Address to Output Delay CE to Output Delay OE to Output Delay OE to Output Float Output Hold 0 0 0 Min Max 70 70 35 35 0 0 0 AT28HC64BF-90 Min Max 90 90 40 40 0 0 0 AT28HC64BF-120 Min Max 120 120 50 50 Units ns ns ns ns ns 10. AC Read Waveforms(1)(2)(3)(4) ADDRESS ADDRESS VALID CE tCE OE tOE tOH tACC OUTPUT Notes: tDF HIGH Z OUTPUT VALID 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 6 AT28HC64BF 3648B–PEEPR–4/09 AT28HC64BF 11. Input Test Waveforms and Measurement Level tR, tF < 5 ns 12. Output Test Load 13. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol CIN COUT Note: Typ 4 Max 6 Units pF pF Conditions VIN = 0 V VOUT = 0 V 8 12 1. This parameter is characterized and is not 100% tested. 7 3648B–PEEPR–4/09 14. AC Write Characteristics Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH Parameter Address, OE Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Setup Time Data, OE Hold Time Min 0 50 0 0 100 50 0 Max Units ns ns ns ns ns ns ns 15. AC Write Waveforms 15.1 WE Controlled OE tOES tOEH ADDRESS tAS CE tCS WE tWP tDS DATA IN tDH tCH tAH 15.2 CE Controlled tOES tOEH OE ADDRESS tAS WE tCS CE tWP tDS DATA IN tDH tCH tAH 8 AT28HC64BF 3648B–PEEPR–4/09 AT28HC64BF 16. Page Mode Characteristics Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 50 0 50 50 0 100 150 Min Max 2 Units ms ns ns ns ns ns µs ns 17. Page Mode Write Waveforms(1)(2) OE CE tWP WE tAS tAH A0 -A12 VALID ADD tDS DATA VALID DATA tDH tWPH tBLC tWC Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. 18. Chip Erase Waveforms tS tH tW tS = tH = 5 µs (min.) tW = 10 ms (min.) VH = 12.0 V ±0.5 V 9 3648B–PEEPR–4/09 19. Software Data Protection Enable Algorithm(1) LOAD DATA AA TO ADDRESS 1555 20. Software Data Protection Disable Algorithm(1) LOAD DATA AA TO ADDRESS 1555 LOAD DATA 55 TO ADDRESS 0AAA LOAD DATA 55 TO ADDRESS 0AAA LOAD DATA A0 TO ADDRESS 1555 WRITES ENABLED(2) LOAD DATA 80 TO ADDRESS 1555 LOAD DATA XX TO ANY ADDRESS(4) LOAD DATA AA TO ADDRESS 1555 LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE LOAD DATA 55 TO ADDRESS 0AAA Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A12 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data are loaded. Notes: LOAD DATA 20 TO ADDRESS 1555 EXIT DATA PROTECT STATE(3) LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A12 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data are loaded. 21. Software Protected Write Cycle Waveforms(1)(2) OE CE tWP WE tAS tAH A0 -A5 tDH tWPH tBLC A6 - A12 tDS DATA tWC Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 2. OE must be high only when WE and CE are both low. 10 AT28HC64BF 3648B–PEEPR–4/09 AT28HC64BF 22. Data Polling Characteristics(1) Symbol tDH tOEH tOE tWR Note: Parameter Data Hold Time OE Hold Time OE to Output Delay (1) Min 0 0 Typ Max Units ns ns ns Write Recovery Time 0 ns 1. These parameters are characterized and not 100% tested. See “AC Read Characteristics” on page 6. 23. Data Polling Waveforms tOEH tDH tOE tWR 24. Toggle Bit Characteristics(1) Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics” on page 6. (2) Min 10 10 Typ Max Units ns ns ns 150 0 ns ns 25. Toggle Bit Waveforms(1)(2)(3) tOEH tDH (2) tOE tWR Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used, but the address should not vary. 11 3648B–PEEPR–4/09 26. Normalized ICC Graphs 12 AT28HC64BF 3648B–PEEPR–4/09 AT28HC64BF 27. Ordering Information 27.1 tACC (ns) 120 Green Package (Pb/Halide-free) ICC (mA) Active 40 Standby 0.1 Ordering Code AT28HC64BF-12JU AT28HC64BF-12SU Package 32J 28S Operation Range Industrial (-40°C to 85°C) 27.2 Die Products Contact Atmel Sales in regards to die and wafer sales. Package Type 32J 28S 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 13 3648B–PEEPR–4/09 28. Packaging Information 28.1 32J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) E1 B E B1 E2 e D1 D A A2 A1 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D2 MIN 3.175 1.524 0.381 12.319 11.354 9.906 14.859 13.894 12.471 0.660 0.330 NOM – – – – – – – – – – – 1.270 TYP MAX 3.556 2.413 – 12.573 11.506 10.922 15.113 14.046 13.487 0.813 0.533 NOTE A A1 A2 D D1 D2 Note 2 Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E E1 E2 B B1 e Note 2 10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 32J REV. B R 14 AT28HC64BF 3648B–PEEPR–4/09 AT28HC64BF 28.2 28S – SOIC Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 0.51(0.020) 0.33(0.013) 7.60(0.2992) 10.65(0.419) 7.40(0.2914) 10.00(0.394) PIN 1 1.27(0.50) BSC TOP VIEW 18.10(0.7125) 17.70(0.6969) 2.65(0.1043) 2.35(0.0926) 0.30(0.0118) 0.10(0.0040) SIDE VIEWS 0º ~ 8º 0.32(0.0125) 0.23(0.0091) 1.27(0.050) 0.40(0.016) 8/4/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC) JEDEC Standard MS-013 DRAWING NO. 28S REV. B R 15 3648B–PEEPR–4/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support p_eeprom@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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