Features
• • • • • • • • • • • • • • •
Thermal Sensitive Layer Over a 0.35 µm CMOS Array Image Zone: 0.4 x 11.6 mm Image Array: 8 × 232 = 1856 Pixels Pixel Pitch: 50 × 50 µm = 500 dpi Resolution On-chip 8-bit Analog to Digital Converter Serial Peripheral Interface (SPI) - 2 Modes: – Fast Mode at 16 Mbps Max for Imaging – Slow Mode at 200 kbps Max for Navigation and Control Die Size: 1.5 × 15 mm Operating Voltage: 2.3 to 3.6V I/O Voltage: 1.65 to 3.6V Operating Temperature Range: -40°C to 85°C Finger Sweeping Speed from 2 to 20 cm/Second Low Power: 4.5 mA (Image Acquisition), 1.5 mA (Navigation), 4 Million Sweeps) High Protection from Electrostatic Discharge Small Form Factor Packaging
Description
Atmel’s AT77C105A fingerprint sensor is dedicated to PDA, cellular and smartphone applications. Based on FingerChip thermal technology, the AT77C105A is a linear sensor that captures fingerprint images by sweeping the finger over the sensing area. This product embeds true hardware-based 8-way navigation and click functions as well, as enabling elimination of mechanical joystick devices.
Applications
• • • • • Scrolling, Menu and Item Selection for PDAs, Cellular or Smartphone Applications Cellular and Smartphones-based Security (Device Protection, Network and ISP Access, E-commerce) Personal Digital Agenda (PDA) Access User Authentication for Private and Confidential Data Access Portable Fingerprint Acquisition
FingerChip® Thermal Fingerprint Sweep Sensor, Hardware Based Navigation and Click Functions, Extended I/O range (1.8-3.3V) AT77C105A Preliminary
Sweep your finger to make life easier
Chip-on-board Package
Actual size of sensor
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Table 1. Pin Description for Chip-on-board Package: AT77C105A-CB08V
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Note: GNDD GNDA VDDD VDDA SCK TESTA MOSI VDD_IO MISO SCANEN SSS IRQ FSS RST FPL G G P P I IO I P O I I O I I I Name Type Description Not connected Not connected Not connected Not connected Digital ground supply Analog ground supply - connect to GNDD Digital power supply Analog power supply - connect to VDD Serial Port Interface (SPI) clock Reserved for the analog test, not connected Master-out slave-in data Input/output power supply - connect IO voltage compatibility accordingly Master-in slave-out data Reserved for the scan test in factory, must be grounded Slow SPI slave select (active low Interrupt line to host (active low). Digital test pin Fast SPI slave select (active low) Reset and sleep mode control (active high) Front plane, must be grounded
The die attach is connected to pin 6 and must be grounded. The FPL pin must also be grounded.
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Figure 1. Typical Application
VDDD
VDDD 10 kΩ IRQ MISO MOSI SCK SSS FSS SCANEN GND RST GNDA FPL GNDD VDDA TESTA VDD_IO VDDD
VDD_IO
10 kΩ
NC
VDDD
10µF VDDA
10µF
GND
The pull-up must be implemented for the master controller. The noise should be lower than 30 mV peak to peak on VDDA. Figure 2. Pin Description
NC NC NC NC GNDD GNDA VDDD VDDA SCK TESTA MOSI VDD_IO MISO SCANEN SSS IRQ FSS RST FPL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
The TESTA pin is only used for testing and debugging. The SCANEN pin is not used in the final application and must be connected to ground. Warning: SSS and FSS must never be low at the same time. When both SSS and FSS equal 0, the chip switches to scan test mode. With the SPI protocol, this configuration is not possible as only one slave at a time can be selected. However, this configuration works when debugging the system.
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Specifications
Table 2. Absolute Maximum Ratings
Parameter Power supply voltage Front plane Digital input Input/output pads power supply Storage temperature Lead temperature (soldering 10 seconds) Symbol VDDD, VDDA FPL SSS, FSS, SCK, MOSI VDD_IO Tstg Tleads Do not solder Comments Value -0.5 to 4.6V GND to VDD +0.5V GND to VDD +0.5V GND to VDD +0.5V -50 to +95°C Forbidden Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 3. Recommended Conditions of Use
Parameter Positive supply voltage Front plane Digital input voltage Digital output voltage Digital load Operating temperature range Maximum current on VDDA CL Tamb IVDDA Industrial “V” grade 0 Symbol VDD FPL Comments 2.5 ±5% 3.3 ±10% Must be grounded Min 2.3 Typ 2.5 3.3 GND CMOS levels CMOS levels 20 -40 to +85 60 50 Max 3.6 Unit V V V V pF °C mA
Table 4. Resistance
Parameter ESD On pins HBM (Human Body Model) CMOS I/O On die surface (zap gun) air discharge Mechanical Abrasion Number of cycles without lubricant Multiply by a factor of 20 for correlation with a real finger Chemical Resistance Cleaning agent, acid, grease, alcohol, diluted acetone 4 hours Internal method 200 000 MIL E 12397B 2 kV (TBC) ±16 kV (TBC) MIL-STD-883 method 3015.7 NF EN 6100-4-2 Min Value Standard Method
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Note: TBC = To be confirmed
Table 5. Explanation of Test Levels
Level I II III IV V VI D Description 100% production tested at +25°C 100% production tested at +25°C, and sample tested at specified temperatures (AC testing done on sample) Sample tested only Parameter is guaranteed by design and/or characterization testing Parameter is a typical value only 100% production tested at temperature extremes 100% probe tested on wafer at Tamb = +25°C
Table 6. Specifications
Parameter Resolution Size Yield: number of bad pixels Symbol Test Level IV IV I Min(1) Typ 50 8 × 232 5 Max(1) Unit Micron Pixel Bad pixels
Power Consumption and DC Characteristics
The following characteristics are applicable to the operating temperature -40°C ≤ T ≤ +85°C. Typical conditions are: power supply = 3.3V; Tamb = 25°C; FSCK = 12 MHz (1600 slices per second); duty cycle = 50% CLOAD 120 pF on digital outputs unless otherwise specified. Table 7. Power Requirements
Name VDD IDD IDDNAV IDDCLI IDDSLP IDDSTB Note: Parameter Positive supply voltage Current on VDD in acquisition mode Current on VDD in navigation mode Current on VDD in click mode Current on VDD in sleep mode Current on VDD in stand-by mode 1. Min and max values are to be confirmed. Conditions Test Level I I I I I I Min(1) 2.3 3 1 0.2 Typ 2.5/3.3 4.5 1.5 0.3 Max(1) 3.6 6 2 0.5 10 UnitV mA mA mA µA
Refer to “Power Management” on page 32
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VDD_IO = 1.8V
Table 8. Digital Inputs
Logic Compatibility Name IIL IIH IIOZ VIL VIH VHYST Parameter Low level input current without pullup device(1) High level input current without pull-down device(1) Tri-state output leakage without pull-up/down device(1) Low level input voltage(1) High level input voltage(1) Schmitt trigger hysteresis(1) Conditions VI = 0V VI = VDD_IO VI = 0V or VDD_IO Test Level I I IV I I IV 0.6 VDD(1) 0.15 VDD_IO 0.3 VDD_IO CMOS Min Typ Max 1 1 1 0.4 VDD_IO(1) Unit µA µA µA V V V
Table 9. Digital Outputs
Logic Compatibility Name VOL VOH Note: Parameter Low level output voltage High level output voltage Conditions IOL = 4 mA VDD = 1.8V ±8% IOH = -4 mA VDD = 3.3V ±10% Test Level I I 0.85 VDD CMOS Min Typ Max 0.15 VDD_IO (1) Unit V V
1. A minimum noise margin of 0.05 VDD should be taken for Schmitt trigger input threshold switching levels compared to VIL and VIH values.
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VDD_IO = 2.3V to 3.6V
Table 10. Digital Inputs
Logic Compatibility Name IIL IIH IIOZ VIL VIH VHYST Parameter Low level input current without pullup device(1) High level input current without pull-down device(1) Tri-state output leakage without pull-up/down device(1) Low level input voltage(1) High level input voltage(1) Schmitt trigger hysteresis(1) Conditions VI = 0V VI = VDD_IO VI = 0V or VDD_IO Test Level I I IV I I IV 0.6 VDD_IO(1) 0.06 VDD_IO 0.09 VDD_IO CMOS Min Typ Max 1 1 1 0.5 VDD_IO(1) Unit µA µA µA V V V
Table 11. Digital Outputs
Logic Compatibility Name VOL Parameter Low level output voltage Conditions IOL = 4 mA VDD _IO = 2.3V to 3.6V IOH = -4 mA VDD_IO = 2.3V to 3.6V Test Level I CMOS Min Typ Max 0.10 VDD_IO (1) Unit V
VOH
High level output voltage
I
0.90 VDD
V
Input/Output Voltage Level Compatibility
The I/O voltage level compatibility is set by the power voltage driven on the VDD_IO pad. For 1.8V level compatibility, connect VDD_IO to a 1.8V power supply.
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Switching Performances
The following characteristics are applicable to the operating temperature -40°C ≤ T ≤ +85°C. Typical conditions are: nominal value; Tamb = 25°C; FSCK = 12 MHz; duty cycle = 50%; CLOAD 120 pF in digital output unless specified otherwise. Table 12. Timings
Parameter Clock frequency acquisition mode Clock frequency navigation mode and chip control Duty cycle (clock SCK) Reset setup time Slave select setup time Slave select hold time Note: 1. TSCK = 1/FCTRL (clock period) Symbol FACQ FCTRL DC TRSTSU TSSSU TSSHD Test Level IV I IV I I I ½ Min 8 20 TSCK(1) 50 Typ Max 16 0.2 80 Unit MHz MHz % ns ns ns
½ TSCK(1) ½ TSCK(1)
Table 13. 3.3V ±10% Power Supply
Parameter Data in setup time Data in hold time Data out valid Data out disable time from SS high IRQ hold time Note: All power supplies = +3.3V Symbol TSU TH TV TDIS TIRQ Test Level IV IV I IV IV 3.8 3 Min Typ 3 1 30 Max Unit ns ns ns ns µs
Table 14. 2.5V ±5% Power Supply
Parameter Data in setup time Data in hold time Data out valid Data out disable time from SS high IRQ hold time Note: All power supplies = +2.5V Symbol TSU TH TV TDIS TIRQ Test Level IV IV I IV IV 3.8 3 Min Typ 3 1 30 Max Unit ns ns ns ns µs
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Table 15. 1.8V ±5% Power Supply
Parameter Data in setup time Data in hold time Data out valid Data out disable time from SS high IRQ hold time Symbol TSU TH TV TDIS TIRQ Test Level Min Typ Max Unit ns ns ns ns µs
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Timing Diagrams: Slow and Fast SPI Interface
Figure 3. Read Timing Fast SPI Slave Mode
RST
SS Trstsu Tsssu SCK Tv MISO Tdis DC Tsshd
Figure 4. Read/Write Timing Slow SPI Slave Mode
SS Tsssu Tsshd SCK Tsu MOSI Th
MISO
Figure 5. Read Status Register to Release IRQ
SS
SCK
MOSI
1
1
0
0
0
0
X Tirq
X
IRQ
Figure 6. Chip Initialization
RST SS
Trstsu
Min = 10 µs
SCK
MISO
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Functional Description
The AT77C105A is a fingerprint sensor based on FingerChip technology. It is controlled by an SPI serial interface through which output data is also transferred (a slow SPI for the pointing function and a fast one for acquisition). Six modes are implemented: – – Sleep Mode: A very low consumption mode controlled by the reset pin RST. In this mode, the internal clocks are disabled and the registers are initialized. Stand-by Mode: Also a low consumption mode that waits for an action from the host. The slow serial port interface (SSPI) and control blocks are activated. In this mode the oscillator can remain active. Click Mode: Waits for a finger on the sensor. The SSPI and control blocks are activated. The local oscillator, the click array and the click block are all activated. Navigation Mode: Calculates the finger’s x and y movements across the sensor. The SSPI and control blocks are still activated. The local oscillator, the navigation array and the navigation block are also activated. Acquisition Mode: Slices are sent to the host for finger reconstruction and identification. The SSPI and control blocks are still activated. The fast serial port interface block (FSPI) and the acquisition array are activated, as well as the local oscillator when watchdog is required. Test: This mode is reserved for factory testing. Stand-by: Low consumption mode Pointing: Equivalent to click and navigation modes Acquisition: Fingerprint image capture
The term”host” describes the processor (controller, DSP...) linked to the sensor. It is the master. In the description of n-bit registers (see “Function Registers” on page 13), the term “b0” describes the Least Significant Bit (LSB). The term “b(n-1)” describes the Most Significant Bit (MSB). Binary data is written as 0b_ and hexadecimal data as 0x_.
–
–
–
– – – –
Note:
In the final application, three main modes are used:
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Sensor and Block Diagram
Figure 7. Functional Block Diagram
FPL VDDA GNDA VDDD GNDD VDD_IO RST
FSS Fast Serial Interface SPI (8-16 MHz)
SCK
Acquisition Pixel Array (232 x 8) Array CTRL Navigation Algorithms
MISO
Oscillator (420 kHz)
Click Pixels (12)
Click CTRL
Click Algorithm
Slow Serial Interface SPI (200 kHz) + Control Register
MOSI
SSS
IRQ Watchdog Heating SCANEN Test TESTA
The circuit is divided into the following main sections: • • • • • • An array or frame of 8 × 232 pixels + 1 dummy column An analog to digital converter An on-chip oscillator Control and status registers Navigation and click units Slow and fast serial interfaces
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Function Registers
Table 16. Registers
Register STATUS MODECTRL ENCTRL HEATCTRL NAVCTRL CLICKCTRL MOVCTRL Address (b3 down to b0) 0000 0001 0010 0011 0100 0101 0110 0111 NAVIGATION NAVIGATION
(1) (1)
Read/Write Read Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reserved Read Reserved Reserved Reserved Reserved Reserved Reserved
1000 1001 1010 1011 1100 1101 1110
NAVIGATION(1) PIXELCLICK PIXELCLICK PIXELCLICK
Note:
1. Navigation requires 3 registers. The reading of the first register (0b1000) enables the reading of all 3 registers.
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Status Register
Register Name: Status (8 bits) Access Type: Read Only Function: State of AT77C105A
b7 CLICK 0
b6 MOV 0
b5 TRANSIT 0
b4 SLICE 0
b3 READERR 0
b2 – 0
b1 – 0
b0 – 0
•
CLICK: Click detection 0: default 1: click detected MOV: Movement detection 0: default 1: X or Y movement detected TRANSIT: Not used, for testing only SLICE: Not used, for testing only READERR: Read error detection 0: default, no error 1: read error detected
To clear the interrupts, the status register is initialized after each reading from the host.
•
• • •
Note:
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Modectrl Register
Register Name: Modectrl (7 bits) Access Type: Read/Write Function: Mode control
b6 MODE (MSB) 0
b5 MODE 0
b4 MODE 0
b3 MODE (LSB) 0
b2 ANALOGRST 1
b1 – 0
b0 – 0
•
MODE: Select operating mode 0000: standby 0001: test (reserved for factory use) 0010: click 0100: navigation 1000: acquisition
Certain changes can be made. For example, MODE can be set to 0b0110 to activate click and navigation. • ANALOGRST: Reset local oscillator 0: oscillator in active mode 1: oscillator in power-down mode
1. Click or navigation modes cannot be used when the local oscillator is switched off.. 2. To return to standby mode and stop the oscillator (to save on power consumption), two Modectrl register accesses are necessary: the first one to select standby mode and the second to switch off the oscillator. 3. The read-only registers cannot be read when the oscillator is turned off. 4. To shift between navigation and acquisition modes, you must be in standby mode (Modectrl = 0b00001).
Notes:
If modes such as “acquisition and click” or “acquisition and navigation” are programmed together, they will be ignored by the system.
Programmed Mode 11xx 1x1x
Register Value 01xx 0x1x
With x = 0 or 1.
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Enctrl Register
Register Name: Enctrl (7 bits) Access Type: Read/Write Function: Interrupts control
b6 CLICKEN 0
b5 MOVEN 0
b4 TRANSITEN 0
b3 SLICEN 0
b2 READERREN 0
b1 – 0
b0 – 0
•
CLICKEN: Click interrupts enable 0: default 1: click IRQ enabled
IRQ is generated when a click is detected. • MOVEN: Movement interrupts enable 0: default 1: movement IRQ enabled
IRQ is generated when an X or Y movement is detected. • • • TRANSITEN: Not used, for testing only SLICEN: Not used, for testing only READERREN: Read error interrupts enable 0: default 1: read error IRQ enabled
The interrupt is cleared after the status register is read.
IRQ is generated when a read error is detected.
Note:
Heatctrl Register
Register Name: Heatctrl (7 bits) Access Type: Read/Write Function: Heating control
b6 HEAT 0
b5 WDOGEN 0
b4 HEATV (MSB) 0
b3 HEATV(LSB) 0
b2 – 0
b1 – 0
b0 – 0
•
HEAT: Sensor heating 0: default, no heating 1: heating The default value is recommended to optimize power consumption. WDOGEN: Watchdog enable 0: default
•
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1: watchdog enabled Watchdog automatically stops heating of the sensor after a time-out. • HEATV (2 bits): Heating power value 00: 50 mW 01: 100 mW 10: reserved 11: reserved
1. Heating can only be used in the acquisition mode (it is not allowed in navigation or click modes). 2. The oscillator has to be activated when the watchdog is required and must not be stopped while the watchdog remains active.
VDD is between 2.5 and 3.6V.
Notes:
Navctrl Register
Register Name: Navctrl (7 bits) Access Type: Read/Write Function: Navigation control
b6 NAVFREQ (MSB) 1
b5 NAVFREQ (LSB) 0
b4 NAVV ( MSB) 0
b3 NAVV (LSB) 0
b2 CLICKV (MSB) 0
b1 CLICKV (LSB) 0
b0 reserved 0
•
NAVFREQ: Navigation frequency 00: 5.8 kHz 01: 2.9 kHz (default value) 10: 1.9 kHz 11: 1.5 kHz
A faster frequency enables faster finger movement detection. A lower frequency enhances sensitivity. Refer to Notes 1 and 2 on page 18. • NAVV: Navigation pixels threshold 00: lower threshold 01: 10: 11: higher threshold
Sets the minimum analog value detected as a high level (‘1’). Refer to Note 1 on page 18. • CLICKV: Click pixels threshold 00: lower threshold 01: 10: 11: higher threshold
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Sets the minimum analog value detected as a high level (‘1’) and the maximum analog value detected as a low level (‘0’). See Note 3 on page 18.
Notes: 1. Navfreq and Navv registers should not be changed once the navigation mode is selected. Finger sensitivity refers to the minimum level of information required from a finger. The sensitivity is linked to the integration time; a longer integration time enables better sensitivity but does not tolerate fast movement. 2. The navigation frequency is the frequency needed for the reading of one new navigation frame. 3. The Clickv register should not be changed once the click mode is selected.
Clickctrl Register
Register Name: Clickctrl (7 bits) Access Type: Read/Write Function: Click control
b6 CLICKFREQ (MSB) 0
b5 CLICKFREQ (LSB) 1
b4 CLICKDET (MSB) 0
b3 CLICKDET (LSB) 1
b2 CLICKCPT (MSB) 1
b1 CLICKCPT 0
b0 CLICKCPT (LSB) 1
•
CLICKFREQ: Click pixels reading frequency 00: 180 Hz 01: 90 Hz (default value) 10: 60 Hz 11: 45 Hz
Faster frequency enables faster finger click detection. Lower frequency enables higher sensitivity. • CLICKDET: Threshold for selecting the black/white color of a slice 00: more than 7 black/white pixels and less than 5 white/black pixels 01: more than 8 black/white pixels and less than 4 white/black pixels 10: more than 9 black/white pixels and less than 3 white/black pixels 11: more than 10 black/white pixels and less than 2 white/black pixels CLICKCPT: Click detection counter (maximum number of slices read between two transitions) 000: 5 001: 7 010: 10 011: 12 100: 16 101: 20 110: 25 111: 31
•
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Two transitions are interpreted as a click if the number of slices between them is less than CLICKCPT. This is used to differentiate a touch-down/touch-up from a real click. A click is equivalent to two close touch-down/touch-up transitions.
This register adjusts the “time out” for considering the two transitions as a click.
Note: Clickfreq and Clickcpt registers should not be changed once the click mode is selected.
Movectrl Register
Register Name: Movctrl (7 bits) Access Type: Read/Write Function: In stream mode, during navigation calculation, the AT77C105A must interrupt the host when a maximum absolute X or Y movement is detected (second and third navigation registers). The MOVECTRL register enables you to control this value. This value can be set as the minimum finger movement value at which the pointing device makes a displacement.
b6 (MSB) 0
b5 – 0
b4 – 0
b3 – 0
b2 – 0
b1 – 0
b0 (LSB) 0
•
MOVCTRL: Generates an interrupt when the second or third navigation register (X or Y absolute movement) is greater than the value programmed in the Movectrl register 0b0000000 0b0000001 0b0000010 ... 0b1111111
For example, when MOVCTRL = 0b0001001, an interruption to the host is generated when the absolute X movement register (second navigation register) or absolute Y movement register (third navigation register) is greater than 0b00010010.
Note: The Movctrl register should not be changed once the navigation mode is selected.
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Navigation Register
Register Name: Navigation (3 x 8 bits) Access Type: Read Only (these three registers cannot be read individually. The reading command of the first navigation register [address 0b1000] returns the value of the three registers). Function: The format of the navigation registers is similar to the PS/2 protocol. Three registers are used to codemovements and clicks. The navigation registers are initialized after each reading. The registers only represent actions (movement, click, transition...) that have occurred since the last data packet sent to thehost. General Register
b7 YOVR 0 b6 XOVR 0 b5 YSIGN 0 b4 XSIGN 0 b3 1 1 b2 TRANS 0 b1 CLICK 0 b0 FINGER 0
•
YOVR: Y overflow 0: default 1: Y movement overflow
High (‘1’) when the Y movement counter is overflowed. • XOVR: X overflow 0: default 1: X movement overflow
High (‘1’) when the X movement counter is overflowed. • YSIGN: Y sign bit 0: default, positive Y movement 1: negative Y movement
High (‘1’) when the Y movement is negative. Low when the Y movement is positive. • XSIGN: X sign bit 0: default, positive X movement 1: negative X movement
High (‘1’) when the X movement is negative. Low when the X movement is positive. • • TRANS: Not used, for test purposes only. CLICK: Click 0: default 1: click detected
This function is not in the PS/2 protocol. • FINGER: Not used, for test purposes only.
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Note:
In the PS/2 protocol, bits b2 and b1 are used to code the middle and right buttons respectively, and b3 is set to high.
Absolute X Movement Register (0 to 255 Pixels)
b7 XMOV (MSB) 0 b6 – 0 b5 – 0 b4 – 0 b3 – 0 b2 – 0 b1 – 0 b0 XMOV (LSB) 0
Absolute Y Movement Register (0 to 255 Pixels)
b7 YMOV (MSB) 0 b6 – 0 b5 – 0 Note: b4 – 0 b3 – 0 b2 – 0 b1 – 0 b0 YMOV (LSB) 0
When a click is detected, the information is placed in the b7 bit of the status register and in the b1 bit of the general navigation register. The reading of the status register initializes the b7 bit but does not initialize the b1 bit of the general navigation register. The host must carefully correlate the two bits.
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SPI Interface General Description
Two communication busses are implemented in the device: • • The control interface, a slow bus that controls and reads the internal registers (status, navigation, control...). The pixels’ acquisition interface, a fast bus that enables full pixel acquisition by the host.
A synchronous Serial Port Interface (SPI) has been adopted for the two communication busses. The SPI protocol is a slave/master fullduplex synchronous serial communication. This protocol uses three communication signals: • • • SCK (Serial Clock): the communication clock MOSI (Master Out Slave In): the data line from the master to the slave MISO (Master In Slave Out): the data line from the slave to the master
The slaves are selected by an input pin SS/ (Slave Select). A master can communicate with several slaves. The word length of the transferred data is fixed to 8 bits. The Most Significant Bit (MSB) is sent first. For each 8-bit transfer, 8 bits are sent from the master to the slave and 8 bits transferred from the slave to the master. Transfers are still synchronized with the communication clock (SCK). Only the host can initialize transfers. To send data, the slave must wait for an access from the master. When there is no transfer, a clock is not generated.
Figure 8. One Master with Several Slaves
SS/1 Master Slave #1
SS/2 Slave #2
SS/3 Slave #3 SCK MISO MOSI
When a master is connected with several slaves, the signals SCK, MISO and MOSI are interconnected. Each slave SS is driven separately. Only one slave can be selected, the others have their MISO tri-stated and ignore MOSI data. The SS/ signal falls a half-period before the first clock edge, and rises a half-period after the last clock edge.
Clock Phase and Polarity During phase zero of the operation, the output data changes on the clock’s falling edge
and the input data is shifted in on the clock’s rising edge. In phase one of the operation, the output data changes on the clock’s rising edge and is shifted in on the clock’s falling edge.
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Polarity configures the clock’s idle level, which is high (“1”) during polarity one of the operation and low (“0”) during polarity zero of the operation.
AT77C105A and the SPI
The AT77C105A is always the slave and the host always the master. The host drives the SCK clock. Both the AT77C105A and the host transmit data with the MISO signal. The word length of the transferred data is fixed to 8 bits. The Most Significant Bit (MSB) is sent first. The AT77C105A supports only one phase and polarity configuration: • • The clock’s idle level set to high (polarity 1) The output data changed on the clock’s falling edge, and input data shifted in on the clock’s rising edge (phase 0).
Figure 9. SPI Waveform (Phase = 0, Polarity = 1)
SCK
MOSI/MISO SS/
MSB
LSB
Emission
Reception
Note:
During initialization of the SCK wire (power-on or reset), SS/ has to be inactive (“1“).
Recommendations
The SSS or FSS falling edge should be half a clock cycle before the first SCK falling edge and the SSS or FSS rising edge should be half a clock cycle after the last SCK rising edge. The control register block uses an internal finite state machine that can only be initialized by the RST pin (asynchronous reset). When SPI access does not use 8 clock pulses, the internal finite state machine is desynchronized. The only way to resynchronize it is by resetting the sensor with the RST pin. No requester modification is recorded when a write access is made on a read-only register. Reliable initialization of read-only registers is not guaranteed when the slow SPI’s maximum clock frequency is not respected.
SPI Behavior with Hazardous Access
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Control Interface (Slow SPI)
This interface controls the sensor’s internal registers. The protocol enables reading and writing of these registers. The master (host) initiates transfers to the slave (sensor). The sensor can only use its interrupt pin to communicate with the host. When the host is interrupted, it must read the status register before continuing operation. The word length of the transferred data is fixed to 8 bits. The Most Significant Bit (MSB) is sent first.
Communication Protocol Accesses to the host are structured in packets of words. The first word is the command
and the other words are the data. The b7 bit is used to differentiate the command and data. When the word is a command, b7 is high (“1”) and when the word is a piece of data, b7 is low (“0”). The following protocol is used: Command Format The host indicates to the sensor if it wants to read or write into a register and indicates the register’s address.
b7 1
b6 Read (1)/Write (0)
b5 Address (b3)
b4 Address (b2)
b3 Address (b1)
b2 Address (b0)
b1 x
b0 x
Data Format (Writing into Register)
b7 0 b6 Data (b6)
If writing into a register, the host transmits the data.
b5 Data (b5)
b4 Data (b4)
b3 Data (b3)
b2 Data (b2)
b1 Data (b1)
b0 Data (b0)
Data Format (Reading of Register)
If reading a register, the host transmits one or several packets of data and data is shifted in from the sensor. The host transmits dummy words with the data format (b7 is low [“0”]). If reading the navigation or click pixel registers, the host transmits three packets of data to read the three registers.
b7 0 Note:
b6 x
b5 x
b4 x
b3 x
b2 x
b1 x
b0 x
The host cannot communicate with the sensor without receiving data from it. Useless data is ignored by the host.
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Communication Speed
To reduce consumption, the control interface’s communication speed is set to the lowest possible speed and depends on the host’s configuration. To communicate with “fast” controllers, the sensor’s communication speed can be set to 200 kbits/s. Example for the MODECTRL Register Figure 10 represents a typical writing sequence into an internal register (MODECTRL register in this example). See Appendix B for flowchart. Figure 10. Writing into an Internal Register
SSS SCK
MOSI 1 MISO x x x x x x x x x x x x x x x x 0 0 0 0 1 x x 0 0 1 1 0 0 0 0
Writing into MODECTRL Register Requested
New Data to be Written into MODECTRL Register (Navigation and Click Mode)
Note:
The break on SCK on the SPI chronogram has been added for better comprehension only. In a real application, SCK can be continuous.
Figure 11 represents a typical reading sequence of a register different from the navigation register. In this example, the status register is used. Figure 11. Reading Sequence of a Register (Except for Navigation Registers)
SCK
MOSI 1 MISO x x x x x x x x 1 0 0 0 0 0 0 0 1 0 0 0 0 x x 0 x x x x x x x
Reading of STATUS Register Requested
Emission of the STATUS Register (Click Detected)
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Example of Navigation Registers
Figure 12 represents a typical reading sequence of the three navigation registers. Refer to “Appendix C” on page 37 for flowchart
Figure 12. Reading of the Navigation Registers
SCK MOSI MISO 1 X 1 X 1 X 0 X 0 X 0 X X X X X 0 0 X 0 X 1 X 0 X 1 X 0 X 1 X 0 0 0 X 0 X 0 X 1 X 1 X 0 X 0 X 0 0 1 X 0 X 0 X 1 X 0 X 0 X 0 X 0
Reading of Navigation Register Requested
Emission of the First Navigation Register (No Overflow, Y Negative Movement Click Detected, Black Slice)
Emission of the Second Navigation Register (X Absolute Movement = 24 Pixels)
Emission of the Third Navigation Register (Y Absolute Movement = 144 Pixels)
Image Capture (Fast SPI)
This serial interface enables full-speed acquisition of the sensor’s pixels by the host. This interface only supports the serial clock (SCK) and one data line: MISO (Master In/ Slave Out).
Communication Protocol When the sensor is in acquisition mode, the host can receive pixels through the fast SPI
(FSS/ = 0). The host must transmit the communication clock (SCK) to receive the pixels. This clock must have a regular frequency to obtain constant fingerprint slices (See “Registration Integration Time” on page 30.). With the sensor configured to acquisition mode, the controller can proceed to fast accesses.
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Figure 13. Example of an 8-bit Access
Controller
FSS/ = 0 Sensor Sending of Dummy Data 0b0000000 Reception of 2 Pixels
Sending of 2 Pixels (8 Bits)
End of Communication ?
No
Yes
FSS/ = 1
During an 8-bit access, the sensor transmits two pixels (each pixel is coded on 4 bits). Figure 14. Fast SPI Communication
SCK (Pixel Clock) MISO
Bit3 MSB
Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0
Bit3 Bit2 MSB
Bit1
Bit0
Bit3
Bit2
Bit1
Bit0
Pixel 2i
Pixel 2i - 1
Pixel 2i + 2
Pixel 2i + 1
Transmission Clock Edge (Sensor)
Reception Clock Edge (Host)
Communication Speed
The acquisition speed of the pixels is linked to the clock’s communication speed. The faster the communication clock, the faster the authorized maximum finger sweeping speed. The sensor supports fast communications up to 16 Mbps. A frame consists of 232 true columns and 1 dummy column of 8 pixels of 4 bits each. A frame starts with a dummy column.
Reading of Frame
Figure 15. Example of a Frame
Dummy Column
232 x 8 Pixels Column
0 F 0
Synchro = F0F00200
F
2 0 0 0
p1 p2 p3 p4 p5 p6 p7 p8
P9 p10 p11 P12 P13 P14 P15 p16
Pixel Frame
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The first dummy column, at the beginning of the pixel array, is added to the sensor to act as a specific easy-to-detect pattern, and represents the start of the frame tag. The pixel array is always read in the following order: the first byte, following the 4 bytes of the dummy column, which contains the value of the pixels physically located on the upper left corner of the array, when looking at the die with bond pads to the right. Then another 4 bytes are read that contain the value of the pixels located in the same column from top to bottom. The next column on the right is output, and so on, until the last line on the right, close to the bond pads, is output. Even values are first sent during the data serialization for SPI transfer. Therefore, the synchronization sequence on the chip’s MISO output is F0F00200. Figure 16. Reading of Frame
SCK MISO F 0 F 0 0 2 0 0 P2 P1 P4 P3 P6 P5 P8 P7 P10 P9
Dummy Column
First Pixel Column
Second Pixel Column
Notes:
1. For the first array or frame reading, 40 dummy clock cycles must be sent before the first data arrives. This is necessary for the initialization of the chip pipeline. Consequently, the first synchronization sequences appear after 40 clock cycles. For the following array readings, data arrives at each clock cycle. One should implement a synchronization routine in the protocol to look for the F0F00200 pattern. 2. The Most Significant Bit (MSB) is sent first.
Reading of Entire Image
The FingerChip delivers fingerprint slices or frames with a height of 0.4 mm and a width of 11.6 mm (this equals 8 × 232 pixels). Pixels are sampled/read sequentially and are synchronous with SCK. Raw slices are captured by the acquisition system and overlapped with the corresponding X or Y finger displacement computed by Atmel reconstruction software. This reconstruction software supports a sweeping speed from 2 to 20 cm/s. The table below shows finger speeds according to the different clock frequencies. The reconstruction results are obtained after acquisition of all slices. Table 17. Finger Speeds Versus Clock Frequencies
Fsck (MHz) 1 2 4 6 Data Rate (Mbit/s) 1 2 4 6 Slice Rate (Slices/s) 134 268 536 804 Absolute Maximum Finger Speed (cm/s) 3 6 12 18
Comments Too slow Too slow Minimum Normal speed
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Table 17. Finger Speeds Versus Clock Frequencies
Fsck (MHz) 8 12 16 Data Rate (Mbit/s) 8 12 16 Slice Rate (Slices/s) 1072 1608 2146 Absolute Maximum Finger Speed (cm/s) 24 36 48
Comments Good speed Very good speed Very good speed
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Registration Integration Time
The pixel’s integration time (the time needed for one frame reading) must be as regular as possible to obtain consistent fingerprint slices. This time is directly dependant on the SCK, SPI clock and frequency. Therefore, the SPI cycle of 4 × 8 × 233 clock pulses should be as regular as possible.µ
Figure 17. Regular Integration Time
Regular Integration Time
Frame n
Frame n+1
Frame n+2
Frame n+3
Clock SCK 500 µs max 4 x 8 x 233 = 7456 Pulses 7456 Pulses 233 = 232 + 1 Dummy Column 7456 Pulses 7456 pulses
Note:
The 500 µs duration corresponds to the host’s computation time (slice reconstruction, finger detection…) and in the illustration is given as an example only. Once the host detects a finger, this value remains constant, thus guaranteeing a regular integration time.
Navigation (Slow SPI)
The sensor’s navigation function includes the processing elements necessary for providing the displacement of the finger touching the sensor in an up or down and right or left direction. It is aimed at a screen menu navigation or simple pointing application. In addition, a click processing function is embedded to detect a quick touch of the finger on the sensor. It is aimed at screen text, box or object selection. A double-click function could also be implemented in the software. This interface has been designed to resemble the PS/2 mouse protocol. An interrupt signal IRQ indicates to the host that an action has been detected. The host must read the status register to obtain details on the action. The IRQ signal enables implementation of an efficient power consumption protocol.
Note:
• •
Click and navigation modes can be used together. Two configurations are implemented for the click and navigation modes: – – Stream mode, where the sensor sends an interrupt to the host when a movement or a change in the button’s state is detected. Remote mode, where the sensor does not interrupt the host but waits for its registers to be read.
In these two modes, the registers are initialized after each reading from the host.
See “Appendix D” on page 38. for an example of an interrupt generated by a movement detection.
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Navigation
See “Navigation Register” on page 20. The typical navigation slice frequency has been fixed to 2.9 kHz. A programmable divider is implemented in the control registers (NAVFREQ) to reduce this frequency. Finger displacement is provided as a number of pixels in X and Y directions. Negative movements are possible. The register is cleared after the navigation registers are read. These registers are incremented or decremented between two accesses. Table 18.
Navctrl Register (Bits b6 to b5) 00 01 10 11 Typical Navigation Slice Frequency (kHz) 5.8 2.9 1.9 1.5 Typical Integration Time (µs) 172 345 526 666 Typical Maximum Finger Speed (cm/s) 30 15 9.5 7.5
Click
See “Clickctrl Register” on page 18. The sensor generates a click detection. The host must read the b7 bit of the status register or the b1 bit of the general navigation register. The click function is composed of an array of a few pixels and a processing unit. The typical click slice frequency is 90 Hz. A programmable divider is implemented to modify this frequency in the control registers (CLICKFREQ).
Double-click
This function is performed by the controller, allowing better flexibility. It detects a succession of two clicks.
Temperature Stabilization Function and Watchdog
The sensor has an embedded temperature stabilization unit that identifies a difference in temperature between the finger and the sensor. When this difference is increased, the images are more contrasted. This function is optional and its use depends on the quality of the image processing software, therefore its management should be decided together with the image processing software. In order to limit excessive current consumption by the use of the temperature stabilization function, a watchdog has been implanted in the sensor. The local oscillator stops the heating of the module after a defined time. The oscillator should not be stopped as long as watchdog is active, otherwise the clock stops automatically. When heating of the sensor is requested “1” is written in bit 6 of the HEATCTRL register) and the watchdog is enabled “1” is written in bit 5 of the HEATCTRL register), the sensor is heated during ‘n’ seconds. Due to the oscillator frequency dispersion, the value of n is: 2 seconds (minimum) < n = 4 seconds (typical) < 7 seconds (maximum). The accuracy of n is not important since the heat register can be enabled successively. The level of power consumption is programmable. Two pre-programmed values are set to 50 or 100 mW.
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The dissipated die power is quasi constant over a significant supply voltage range as shown below (mode 50 mW selected): Figure 18.
Power = f ( Vdd )
5,40E-02 5,30E-02 Power ( W ) 5,20E-02 5,10E-02 5,00E-02 4,90E-02 4,80E-02 2 2,2 2,4 2,6 2,8 VDD Power = f ( Vdd) 3 3,2 3,4 3,6 3,8
Note:
This function is useless for navigation and click modes.
Power Management
Sleep Mode (
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