AMMP-6408-TR2G

AMMP-6408 6 to 18 GHz 1 W Power Amplifier in SMT Package Data Sheet Description The AMMP-6408 MMIC is a broadband W power amplifier in a surface mount package designed for use in transmitters that operate in various frequency bands between 6 GHz and 8 GHz. At 8 GHz, it provides 29 dBm of output power (P-dB) and 20 dB of small-signal gain from a small easy-to-use device. This MMIC optimized for linear operation with an output third order intercept point (OIP3) of 38 dBm. Features • • • • • • 5 x 5 mm Surface Mount Package Wide frequency range 6-8 GHz Highly linear: OIP3 = 38 dBm Integrated RF power detector ESD protection (50 V MM, and 250 V HBM) Input port partially matched (For narrowband applications, customer may obtain optimum matching and gain with an additional matching circuit.) Pin Connections (Top View) 1 2 3 Specifications (Vd = 5 V, Idsq = 650 mA) • • • • 4 Frequency range 6 to 8 GHz Small signal gain of 8 dB Return loss: input: -3 dB, Output: -9 dB High Power: @ 8 GHz, P-dB = 29 dBm 8 Application • • • • Microwave radio systems Satellite VSAT, DBS Up/Down Link LMDS & Pt-Pt mmW Long Haul Broadband wireless access (including 802.6 and 802.20 WiMax) • WLL and MMDS loops • Commercial grade military 7 PIN 1 2 3 4 5 6 7 8 6 FUNCTION Vgg Vdd DET_O RF_out DER_R Vdd Vgg RF_in 5 PACKAGE BASE GND Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model (Class A) ESD Human Body Model (Class A) Refer to Avago Technologies Application Note A004R: Electrostatic Discharge, Damage and Control. Note: This MMIC uses depletion mode pHEMT devices. Negative supply is used for the DC gate biasing.  Absolute Maximum Ratings[1] Symbol Vd Vg Id PD Pin Tch, max Tstg Tmax Parameters[1] Positive Supply Voltage Gate Supply Voltage Drain Current Power Dissipation CW Input Power Maximum Operating Channel Temperature Storage Case Temperature Maximum Assembly Temp (20 sec. max.) Units V V mA W dBm °C °C °C Value 6 -3 to 0.5 900 4.6 23 +55 -65 to +55 +260 Notes note 2 note 2,3 note 2 note 4,5 Notes: . Operation in excess of any one of these conditions may result in permanent damage to this device. 2. Combinations of supply voltage, drain current, input power, and output power shall not exceed PD. 3. When operating at this condition with a base plate temperature of 85°C, the median time to failure (MTTF) is significantly reduced. 4. These ratings apply to each individual FET. 5. Junction operating temperature will directly affect the device MTTF. For maximum life, it is recommended that junction temperatures be maintained at the lowest possible levels. DC Specifications/Physical Properties Symbol Id Vg Rqjc Tch Parameters and Test Conditions Drain Supply Current (Vd = 5 V, Vg set for Id Typical) Gate Supply Operating Voltage (Id(Q) = 650 (mA)) Thermal Resistance[6] (Channel-to-Base Plate) Channel Temperature Units mA V °C/W °C Value 650 -. 20 50.6 Note: 6. Assume SnPb soldering to an evaluation RF board at 80°C base plate temperatures. Worst case for the channel temperature is under the quiescent operation. At saturated output power, DC power consumption rises to 4.26 W with .4 W RF power delivered to load. Power dissipation is 3. W and the temperature rise in the channel is 68.4°C. In this condition, the base plate temperature must be remained below 86.6°C to maintain maximum operating channel temperature below 55°C. RF Specifications[1,2,3,4] Symbol Freq. Gain P-dB P-3dB OIP3 RLin RLout Isolation TA = 25°C, Vd = 5 V, Id(Q) = 650 mA, Zo = 50 Ω Parameters and Test Conditions Operational Frequency Small-Signal Gain S2[3,4] Output Power at  dB[3] Gain Compression[2] Output Power at 3 dB Gain Compression[3] Third Order Intercept Point; ∆f = 00 MHz; Pin = -20 dBm Input Return Loss[2] Output Return Loss[2] Reverse Isolation Units GHz dB dBm dBm dBm dB dB dB Minimum 6 7.5 (@ Freq = 8 GHz) 5.5 (@ Freq = 7 GHz) 28 (@ Freq = 8 GHz) 27 (@ Freq = 7 GHz) Typical 8 28.5 29.5 38 3 9 45 Maximum 8 Notes: . Small/large-signal data measured in packaged form on a 2.4 mm connecter based evaluation board at TA = 25°C. 2. This final package part performance is verified by a functional test correlated to actual performance at one or more frequencies. 3. Specifications are derived from measurements in a 50 Ω test environment. Aspects of the amplifier performance may be improved over a narrower bandwidth by application of additional conjugate, linearity, or power matching. 4. Preassembly into package performance verified 00% on-wafer published specifications at frequencies = 7, 2, and 7 GHz. 2 Typical Performances (Data Obtained from 3.5-mm Connector Based Test Fixture, and This Data is Including Connecter Loss, and Board Loss.) (TA = 25°C, Vd = 5 V, ID = 650 mA, Zin = Zout = 50 Ω) 40 35 30 S21 (dB) 25 20 15 10 5 0 2 4 6 8 10 12 14 16 18 20 S21 (dB) S12 (dB) 0 0 -20 RETURN LOSS (dB) S12 (dB) -5 -40 -10 -60 -15 S11 (dB) S22 (dB) -80 22 -20 2 4 6 8 10 12 14 16 18 20 22 FREQUENCY (GHz) FREQUENCY (GHz) Figure 1. Typical gain and reverse isolation Figure 2. Typical return loss (input and output) 35 P-1 (dBm), P-3 (dBm), PAE (%) 30 NOISE FIGURE (dB) 25 20 15 10 5 0 6 7 8 P-1 (dBm) PAE (%) @ P-1 P-3 (dBm) PAE (%) @ P-3 9 10 11 12 13 14 15 16 17 18 10 8 6 4 2 0 4 6 8 10 12 14 16 18 20 FREQUENCY (GHz) FREQUENCY (GHz) Figure 3. Typical output power (@P-1, P-3) and PAE and frequency Figure 4. Typical noise figure 40 35 Po (dBm) and PAE (%) 30 25 20 15 10 5 0 -15 -10 -5 0 Pin (dBm) 5 10 15 Pout (dBm) PAE (%) Id (TOTAL) 1000 900 IM3 LEVEL (dBc) Ids (mA) 800 700 600 -20 -22 -24 -26 -28 -30 -32 -34 -36 -38 -40 -42 -44 4 6 8 10 12 14 16 18 20 FREQUENCY (GHz) Figure 5. Typical output power, PAE, and total drain current versus input power at 8 GHz Figure 6. Typical IM3 level vs. frequency at +20 dBm output single carrier level (SCL) 3 0 -10 -20 IM3 (dBc) -30 -40 -50 -60 -70 -80 4 6 8 10 10 14 16 18 20 22 24 28 IM3 (dBc) Ids (mA) 900 850 800 IM3 (dBc) Ids (mA) 750 700 650 600 550 500 0 -10 -20 -30 -40 -50 -60 -70 -80 4 6 8 10 10 14 16 18 20 22 24 28 IM3 (dBc) Ids (mA) 900 850 800 Ids (mA) Ids (mA) Ids (mA) 750 700 650 600 550 500 SCL (dBm) SCL (dBm) Figure 7. Typical IM3 level and Ids vs. single carrier output level at 6 GHz Figure 8. Typical IM3 level and Ids vs. single carrier output level at 8 GHz 0 -10 -20 IM3 (dBc) -30 -40 -50 -60 -70 -80 4 6 8 10 10 14 16 18 20 22 24 28 IM3 (dBc) Ids (mA) 900 850 800 IM3 (dBc) Ids (mA) 750 700 650 600 550 500 0 -10 -20 -30 -40 -50 -60 -70 -80 4 6 8 10 10 14 16 18 20 22 24 28 IM3 (dBc) Ids (mA) 900 850 800 750 700 650 600 550 500 SCL (dBm) SCL (dBm) Figure 9. Typical IM3 level and Ids vs. single carrier output level at 12 GHz Figure 10. Typical IM3 level and Ids vs. single carrier output level at 14 GHz 0 -10 -20 IM3 (dBc) -30 -40 -50 -60 -70 -80 4 6 8 10 10 14 16 18 20 22 24 28 IM3 (dBc) Ids (mA) 900 850 800 IM3 (dBc) Ids (mA) 750 700 650 600 550 500 0 -10 -20 -30 -40 -50 -60 -70 -80 4 6 8 10 10 14 16 18 20 22 24 28 IM3 (dBc) Ids (mA) 900 850 800 750 700 650 600 550 500 SCL (dBm) SCL (dBm) Figure 11. Typical IM3 level and Ids vs. single carrier output level at 16 GHz Figure 12. Typical IM3 level and Ids vs. single carrier output level at 18 GHz 4 0 -5 -10 -15 -20 -25 S11_20 S11_-40 S11_85 0 5 10 15 20 25 25 20 S21 (dB) S11 (dB) 15 10 S21_20 S21_-40 S21_85 4 6 8 10 12 14 16 18 20 5 FREQUENCY (GHz) FREQUENCY (GHz) Figure 13. Typical S11 over temperature Figure 14. Typical gain over temperature 0 -5 -10 -15 -20 -25 S22_20 S22_-40 S22_85 0 5 10 15 20 25 32 30 28 P-1 (dBm) S22 (dB) 26 24 22 20 P-1_85 deg P-1_20 deg P-1_-40 deg 4 6 8 10 12 14 16 18 20 FREQUENCY (GHz) FREQUENCY (GHz) Figure 15. Typical S22 over temperature Figure 16. Typical P-1 over temperature 5 Typical Scattering Parameters [1], ( TA = 25°C, Vd =5 V, ID = 650 mA, Zin = Zout = 50 W) Freq [GHz] 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 dB -3.83 -4.33 -4.35 -2.87 -2.18 -1.88 -2.85 -5.02 -6.38 -6.79 -8.64 -14.40 -4.82 -3.86 -19.84 -4.51 -1.76 -1.30 -1.04 -0.57 -0.12 S11 Mag 0.64 0.61 0.61 0.72 0.78 0.81 0.72 0.56 0.48 0.46 0.37 0.19 0.57 0.64 0.10 0.60 0.82 0.86 0.89 0.94 0.99 Phase -7.36 -37.59 -57.25 -67.80 -81.97 -99.66 -125.26 -151.04 -177.19 167.29 129.42 34.52 -87.84 -142.34 171.38 -70.79 -104.56 -129.94 -159.31 176.91 158.94 dB 18.46 22.06 21.82 20.57 19.45 19.28 20.24 20.41 19.28 18.74 19.07 19.99 18.06 9.17 -6.42 -16.88 -24.20 -33.63 -42.07 -50.13 -44.39 S21 Mag 8.37 12.67 12.33 10.67 9.38 9.21 10.27 10.49 9.20 8.65 8.98 9.99 7.99 2.88 0.48 0.14 0.06 0.02 0.01 0.00 0.01 Phase -45.38 -160.68 105.82 30.27 -34.10 -91.39 -154.70 130.30 56.72 -8.92 -83.27 -174.68 61.47 -58.13 -160.84 -164.95 137.84 69.70 -90.70 109.52 -58.10 dB -49.36 -47.90 -55.02 -58.31 -56.32 -50.78 -48.77 -45.72 -45.56 -46.62 -47.25 -45.92 -42.49 -50.94 -39.18 -42.22 -64.23 -46.41 -41.89 -50.58 -41.20 S12 Mag 3.41E-03 4.03E-03 1.78E-03 1.21E-03 1.53E-03 2.89E-03 3.64E-03 5.17E-03 5.27E-03 4.67E-03 4.34E-03 5.06E-03 7.50E-03 2.84E-03 1.10E-02 7.74E-03 6.15E-04 4.78E-03 8.05E-03 2.96E-03 8.71E-03 Phase 59.85 -10.90 -87.02 155.08 87.15 36.92 5.73 -42.89 -90.74 -134.99 -179.47 31.89 -86.04 -115.71 -92.64 -168.17 172.50 -96.28 -130.89 122.04 -50.18 dB -9.89 -24.54 -12.59 -11.66 -9.47 -8.10 -8.11 -5.74 -5.64 -6.02 -8.44 -12.65 -12.88 -5.42 -6.15 -2.48 -1.13 -1.28 -1.01 -0.82 -0.33 S22 Mag 0.32 0.06 0.23 0.26 0.34 0.39 0.39 0.52 0.52 0.50 0.38 0.23 0.23 0.54 0.49 0.75 0.88 0.86 0.89 0.91 0.96 Phase -112.35 -97.72 -116.00 -123.36 -111.81 -107.66 -96.60 -95.19 -116.87 -158.25 163.63 142.26 -156.34 127.81 -6.31 -89.99 -122.31 -144.94 -164.03 173.03 155.22 Note: . Data obtained from an ICM test fixture with TRL calibration. Reference planes were defined at RF I/O on the package. 6 Biasing and Operation The recommended quiescent DC bias condition for optimum efficiency, performance, and reliability is Vdd = 5 volts with Vg set for Idd = 650 mA. Minor improvements in performance are possible depending on the application. The drain bias voltage range is 3 to 5 V. A single DC gate supply connected to Vg will bias all gain stages. Muting can be accomplished by setting Vgg to the pinch-off voltage Vp. A simplified schematic for the AMMP6408 MMIC die is shown in Figure 7. The MMIC die contains ESD and over voltage protection diodes for Vg, Vd, and Vd2 terminals. In a finalized package form, Vd and Vd2 terminals are commonly connected to the Vdd terminal. The package diagram for the recommended assembly is shown in Figure 8. In finalized package form, ESD diodes protect all possible ESD or over voltage damages between Vgg and ground, Vgg and Vdd, Vdd and ground. Typical ESD diode current versus diode voltage for -connected diodes in series is shown in Figure 3. Under the recommended DC quiescent biasing condition at Vds = 5 V, Ids = 650 mA, Vgg = - V, typical gate terminal current is approximately 0.3mA. If an active biasing technique is selected for the AMMP6408 MMIC PA DC biasing, the active biasing circuit must have more than 0-times higher internal current that the gate terminal current. An optional output power detector network is also provided. A typical measured detector voltage versus output power at 8 GHz is shown Figure 20. The differential voltage between the Det-Ref and Det-Out pads can be correlated with the RF power emerging from the RF output port. The detected voltage is given by, V = (Vref – Vdet) – Vofs where Vref is the voltage at the DET _R port, Vdet is a voltage at the DET _O port, and Vofs is the zero-input-power offset voltage. There are three methods to calculate Vofs: . Vofs can be measured before each detectore measurement (by removing or switching off the power source and measuring Vref – Vdet). This method gives an error due to temperature drift of less than 0.0 dB/50°C. 2. Vofs can be measured at a single reference temperature. The drift error will be less than 0.25 dB. 3. Vofs can either be characterized over temperature and stored in a lookup table, or it can be measured at two temperatures and a linear fit used to calculate Vofs at any temperature. This method gives an error close to the method #. The RF ports are AC coupled at the RF input to the first stage and the RF output of the final stage. No ground wired are needed since ground connections are made with plated through-holes to the backside of the device. 7 Vg Vd1 Vd2 50 DQ 50 50 800 µm 800 µm DET_O 6.5 µm 50 10K 200 1K RFIN RFOUT 50 800 µm 800 µm 10K 50 50 6.5 µm 200 Vg Vd1 Vd2 50 DET_R DQ Figure 17. Simplified schematic for the MMIC die 8 DET_O 1 2 3 RF INPUT 8 4 RF OUTPUT 7 6 5 DET_R PIN 1 2 3 4 5 6 7 8 FUNCTION Vgg Vdd DET_O RF_out DER_R Vdd Vgg RF_in -0.8 V 50 Ω 5V 1 µF 100 pF 100 pF 1 µF Figure 18. Schematic for recommended assemble example 20 18 16 DIODE CURRENT (mA) 14 12 10 8 6 4 2 0 5.0 5.5 6.0 6.5 VOLTAGE (V) 7.0 7.5 8.0 |Icomp (I_METER.AMP1.0)| (mA) Diode_current DET_R – DET_O (V) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 5 10 15 20 Pout (dBm) 25 30 35 1 0.1 0.01 Figure 19. Typical ESD diode current versus diode voltage for 11connected diodes in series Figure 20. Typical detector voltage and output power, freq. = 18 GHz 9 DET_R – DET_O (V) Recommended SMT Attachment for 5x5 Package The AMMP Packaged Devices are compatible with high volume surface mount PCB assembly processes. The PCB material and mounting pattern, as defined in the data sheet, optimizes RF performance and is strongly recommended. An electronic drawing of the land pattern is available upon request from Avago Sales & Application Engineering. Figure 21. Suggested PCB Land Pattern and Stencil Layout Figure 22. Stencil Outline Drawing (mm) Figure 23. Combined PCB and Stencil Layouts 0 Manual Assembly • Follow ESD precautions while handling packages. • Handling should be along the edges with tweezers. • Recommended attachment is conductive solder paste. Please see recommended solder reflow profile. Neither Conductive epoxy or hand soldering is recommended. • Apply solder paste using a stencil printer or dot placement. The volume of solder paste will be dependent on PCB and component layout and should be controlled to ensure consistent mechanical and electrical performance. • Follow solder paste and vendor’s recommendations when developing a solder reflow profile. A standard profile will have a steady ramp up from room temperature to the pre-heat temp. to avoid damage due to thermal shock. • Packages have been qualified to withstand a peak temperature of 260°C for 20 seconds. Verify that the profile will not expose device beyond these limits. 300 250 TEMPERATURE (°C) 200 150 100 50 RAMP 1 0 0 50 PREHEAT 100 RAMP 2 150 TIME (SECONDS) REFLOW 200 COOLING 250 300 PEAK = 250 ± 5°C MELTING POINT = 218°C A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. The recommended stencil layout is shown in Figure 2. The stencil has a solder paste deposition opening approximately 70% to 90% of the PCB pad. Reducing stencil opening can potentially generate more voids underneath. On the other hand, stencil openings larger than 00% will lead to excessive solder paste smear or bridging across the I/O pads. Considering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use a laser cut stencil composed of 0.27 mm (5 mils) thick stainless steel which is capable of producing the required fine stencil outline. The most commonly used solder reflow method is accomplished in a belt furnace using convection heat transfer. The suggested reflow profile for automated reflow processes is shown in Figure 22. This profile is designed to ensure reliable finished joints. However, the profile indicated in Figure  will vary among different solder pastes from different manufacturers and is shown here for reference only. Ordering Information AMMP-6408 Part Number Ordering Information Part Number AMMP-6408-BLKG AMMP-6408-TRG AMMP-6408-TR2G Devices per Container 0 00 500 Container Antistatic bag 7” Reel 7” Reel Figure 22. Suggested lead-free reflow profile for SnAgCu solder paste Package Dimensions 0.011 (0.28) 0.114 (2.90) 0.018 (0.46) 1 2 3 3 2 1 0.014 (0.365) * A 8 AMMP XXXX YWWDNN 7 6 A 5 0.016 (0.40) 8 4 0.126 (3.2) 0.059 (1.5) 4 0.100 (2.54) 0.029 (0.75) 5 B 0.016 (0.40) 6 7 0.012 (0.30) 0.028 (0.70) 0.100 (2.54) 0.93 (2.36) FRONT VIEW SYMBOL A B MIN. 0.198 (5.03) 0.0685 (1.74) SIDE VIEW MAX. 0.213 (5.4) 0.088 (2.25) DIMENSIONAL TOLERANCE: 0.002" (0.05 mm) DIMENSIONS ARE IN INCHES (MM) BACK VIEW  Carrier Tape and Pocket Dimensions 4 mm 12 mm AMMP XXXX AMMP XXXX AMMP XXXX 4.00 ± 0.10 SEE NOTE #2 2.00 ± 0.05 B ∅1.55 ± 0.05 R 0.50 TYP. 1.75 ± 0.10 5.50 ± 0.05 Bo A Ko SECTION B-B Ao A o: Bo : Ko : PITCH: WIDTH: 5.30 5.30 2.20 8.00 12.00 Ao MIN. 5.20 NOM. 5.30 MAX. 5.40 Bo 5.20 5.30 5.40 Ko 2.10 2.20 2.30 A 12.00 ± 0.10 Ao Bo B 8.00 ± 0.10 ∅1.50 (MIN.) Ko 0.30 ± 0.05 SECTION A-A NOTES: 1. Ao AND Bo MEASURED AT 0.3 mm ABOVE BASE OF POCKET. 2. 10 PITCHES CUMULATIVE TOLERANCE IS ± 0.2 mm. 3. DIMENSIONS ARE IN MILLIMETERS (mm). Note: No RF performance degradation is seen due to ESD up to 250 V HBM and 50 V MM. The DC characteristics in general show increased leakage at lower ESD discharge voltages. The user is reminded that this device is ESD sensitive and needs to be handled with all necessary ESD protocols. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. AV02-0243EN - June 28, 2007