BCM8156FBIFB

BCM8156 ® MULTIRATE LOW-POWER 10G XFI TO SFI-4.1 TRANSCEIVER FEATURES • Fully integrated multirate CDR, DEMUX, MUX, CMU • 300-pin Multisource Agreement (MSA) compatible SUMMARY OF BENEFITS • Compliant to OIF, Telcordia®, ITU-T, XFI specification, and IEEE 802.3ae standards • Compliant to ITU GR-253, XFP, and SFP+ specifications • Fault isolation with loopbacks, pattern generator, and • 16-bit LVDS interface compliant to Optical Internetworking Forum (OIF) SFI-4 • Reduces design cycle and time-to-market • RX equalization for ISI compensation • High-level of integration allows for higher port density • Limiting amplifier checker solutions. • RX phase adjustment • Lowest power SFI-4 to 10G serial transceiver • 10G serial TX preemphasis • Standard CMOS 65-nm fabrication process • PRBS generator/checker for built-in self-test (BIST) • Data rates from 9.95 Gbps to 11.352 Gbps • Line and system loopback modes • Receiver and transmitter serial data polarity inversion • LVDS polarity inversion and bit order reversal • Analog loss-of-signal output (ALOSB) and loss-of-signal input (LOSIB) • CMU and CDR lock detect • FIFO overflow alarm • Reference clock: 1/16 or 1/64 of the line data rate • Selectable RX clock and RX data squelch • Selectable timing modes/cleanup are field configurable • Internal phase detector and charge pump for cleanup phaselocked loop (PLL) (external VCXO required) • Broadcom Serial Control (BSC) interface compatible with Philips® I2C standard • Optional SPI interface • Core voltage, 1V • Low-power: 650 mW APPLICATIONS • OC-192/STM-64/10-GbE/FEC transmission equipment • ADD/DROP multiplexers • Digital cross-connects • ATM switch backbone • Terabit and edge routers • Multi-port XFP-based designs OVERVIEW System Interface Line Interface +1.0V Differential Externally AC-Coupled Internally Biased Reference Clock Inputs TXREFCLKP/N RXREFCLKP/N VCXOP/N Reference Clock Outputs TXPCLKP/N TXMCLKP/N RXMCLKP/N Transmitter Parallel Inputs TXPICLKP/N TXDIN[15:0]P/N Receiver Parallel Outputs RXPOCLKP/N RXDOUT[15:0]P/N Filter and Bias Inputs TXVCP/N RXVCP/N RDINCM +1.0V Analog Clean-up PLL Charge Pump Output PHDOUT +3.3V Analog Resistor Calibration Reference RB_CAL RB_CAL_VSS Status Outputs TXFIFOERRB TXLOCKERRB PHDLOCKERRB ALOSB RXFIFOERRB RXLOCKERRB +3.3V CMOS Control Inputs RESETB LOSIB TXREFSEL SPI_SEL +3.3V CMOS BSC SDA SCL ADR[2:0] +1.0V LVDS +1.8V/2.3V LVDS +1.0V Differential CML Externally AC-Coupled TSDP/N TSCLKP/N Transmit Serial Outputs +1.0V Differential CML Externally AC-Coupled Internally Biased RDINP/N Receive Serial Input +1.0V Differential CML Externally AC-Coupled Internally Biased AUXP/N Auxillary Input Bypass +1.0V LVDS Connect 4.75-k resistor between these two pins Open Drain CMOS +1.0V +1.8V +3.3V VSS BCM8156 Interface Block Diagram The BCM8156 is a fully integrated MSA-compatible multirate SONET/ SDH/10-GbE/Fibre-Channel/FEC transceiver operating at 9.953 Gbps, 10.3125 Gbps, 10.519 Gbps, 10.664 Gbps, 10.709 Gbps, 11.095 Gbps, 11.318 Gbps, or 11.352 Gbps. On-chip clock synthesis is performed by the high-frequency, low-jitter PLL, allowing the use of a low-frequency reference clock selectable to the line rate divided by either 16 or 64. The 10G TX clock phase is adjustable for clocked driver applications. An onchip phase detector and charge pump plus external VCXO implement a cleanup PLL. The cleanup PLL can be used to attenuate jitter on the CDR recovered clock for loop timing applications or to provide a low-jitter reference clock from a noisy system clock. Any SONET timing mode may be configured with the new BCM8156 timing architecture, making the timing mode and cleanup functions user-selectable in the field rather than during manufacturing, therefore, simplifying engineering and manufacturing requirements. New features added to the BCM8156 include: • PRBS generator/checker for BIST • 10G RX equalization for ISI compensation • 10G TX preemphasis • BSC interface (compatible with Philips I2C standard) or optional SPI interface The low-jitter LVDS interface guarantees compliance with the bit error rate requirements of the Telcordia (formerly Bellcore), ANSI, and ITUT standards. The BCM8156 is offered in two different packages: 1. 15 mm x 15 mm, 301-pin BGA compatible with the BCM8152 (0.8mm ball pitch) 2. 15 mm x 15 mm, 196-pin BGA (1-mm ball pitch) Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. ® BROADCOM CORPORATION 5300 California Avenue, Irvine, California 92617 © 2008 by BROADCOM CORPORATION. All rights reserved. 8156-PB00-R 03/13/08 Phone: 949-926-5000 Fax: 949-926-5203 E-mail: info@broadcom.com Web: www.broadcom.com