PI7C9X2G808PRNJEX

PI7C9X2G808PR PCI EXPRESS GEN 2 PACKET SWITCH 2/ 5/ 8-Port/ 8-Lane PCI Express Gen 2 Switch Green Package Family Datasheet REVISION 9 August 2022 1545 Barber Lane Milpitas, CA 95035 Telephone: 408-232-9100 FAX: 408-434-1040 Internet: http://www.diodes.com Document Number DS40341 Rev 9-2 PI7C9X2G808PR IMPORTANT NOTICE 1. DIODES INCORPORATED (Diodes) AND ITS SUBSIDIARIES MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO ANY INFORMATION CONTAINED IN THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 2. The Information contained herein is for informational purpose only and is provided only to illustrate the operation of Diodes’ products described herein and application examples. Diodes does not assume any liability arising out of the application or use of this document or any product described herein. This document is intended for skilled and technically trained engineering customers and users who design with Diodes’ products. Diodes’ products may be used to facilitate safety-related applications; however, in all instances customers and users are responsible for (a) selecting the appropriate Diodes products for their applications, (b) evaluating the suitability of Diodes’ products for their intended applications, (c) ensuring their applications, which incorporate Diodes’ products, comply the applicable legal and regulatory requirements as well as safety and functional-safety related standards, and (d) ensuring they design with appropriate safeguards (including testing, validation, quality control techniques, redundancy, malfunction prevention, and appropriate treatment for aging degradation) to minimize the risks associated with their applications. 3. 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Notwithstanding the foregoing, Diodes reserves the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the final and determinative format released by Diodes. 8. Any unauthorized copying, modification, distribution, transmission, display or other use of this document (or any portion hereof) is prohibited. Diodes assumes no responsibility for any losses incurred by the customers or users or any third parties arising from any such unauthorized use. 9. This Notice may be periodically updated with the most recent version available at https://www.diodes.com/about/company/terms-andconditions/important-notice DIODES is a trademark of Diodes Incorporated in the United States and other countries. The Diodes logo is a registered trademark of Diodes Incorporated in the United States and other countries. © 2022 Diodes Incorporated. All Rights Reserved. www.diodes.com PI7C9X2G808PR Document Number DS40341 Rev 9-2 Page 2 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR REVISION HISTORY Date 06/24/2015 Revision Number 0.1 11/24/2015 0.2 12/23/2015 0.3 01/22/2016 0.4 03/29/2016 0.5 12/23/2016 0.6 01/26/2017 1.0 02/13/2017 1.1 10/13/2017 2 11/16/2017 3 01/17/2018 4 PI7C9X2G808PR Document Number DS40341 Rev 9-2 Description Preliminary Datasheet (Short-Form) Updated Section 3 Pin Description Updated Section 5.3 Port-Lane Mapping Updated Section 6.1 Physical Layer Circuit Updated Section 6.13 Non-Transparent Bridging Updated Figure 4-1 PI7C9X2G808PR Ball Assignment Updated Section 3 Pin Description Updated Section 6 Functional Description Updated Section 7 EEPROM Interface and System Management/I2C Bus Updated Section 8 Register Description Updated Section 9 Clock Scheme Updated Section 10 Power Management Updated Section 11 IEEE 1149.1 Compatible JTAG Controller Updated Section 12 Electrical and Timing Specifications Removed Section 8.4.76 EEPROM_Scratchpad Updated Section 12.2 DC Specifications Updated Section 8.2.142 Non Transfer Mode Register Updated Section 8.3.111 Non Transfer Mode Register Updated Section 3.4 Miscellaneous Signals (42 BALLS) Updated Figure 6-2 Intelligent Adaptor Architecture Updated Section 8.2.87 NT-UP Port Selection Register Update Section 8.2.88 Hot Plug Configuration Register Updated Section 8.2.142 Non Transfer Mode Register Removed Section 8.2.182 Clock Buffer Control Register Removed Section 8.2.183 Clock Buffer Port Select Register Updated Section 8.3.74 NT-UP Port Selection Register Update Section 8.3.75 Hot Plug Configuration Register Updated Section 8.3.111 NON Transfer Mode Register Removed Section 8.3.161 Clock Buffer Control Register Removed Section 8.3.162 Clock Buffer Port Select Register Updated Section 8.4.36 Link Control 2 Register Added Section 11 Power Sequence Updated Section 8 Register Description Updated Table 13-2 DC Electrical Characteristics Remove “Preliminary” Updated Section 1 Features Updated Section 3.6 Power Pins (75 Balls) Updated Section 8.2 Transparent Mode Configuration Registers Updated Section 13.1 Absolute Maximum Ratings Updated Section 13.2 DC Specifications Added Section 13.4 Operating Ambient Temperature Updated Section 3.1 PCI Express Interface Signals (40 BALLS) Updated Section 3.4 Miscellaneous Signals (45 BALLS) Updated Section 15 Ordering Information Updated Section 13.1 Absolute Maximum Ratings Updated Section 7 EEPROM Interface and System Management/I2C Bus Updated Section 8 Register Description Updated Table 13.2 DC Electrical Characteristics Added Table 13-8 Power Consumption Added Section 14 Thermal Data Updated Section 16 Ordering Information Revision numbering system changed to whole number Updated Section 3.6 Power Pins (75 Balls) Updated Section 3.2 Port Specific Signals (21 Balls) Updated Table 13-1 Absolute Maximum Ratings Updated Section 1 Features Page 3 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR Date Revision Number 05/15/2019 5 8/13/2019 6 05/14/2020 7 12/15/2020 8 08/17/2022 9 PI7C9X2G808PR Document Number DS40341 Rev 9-2 Description Updated Section 8.2.117 PHY PARAMETER 2 REGISTER Updated Section 8.2.118 PHY PARAMETER 3 REGISTER Updated Section 8.2.136 PORT MISC 0 REGISTER Updated Table 12-3 JTAG Boundary Scan Register Definition Updated Table 13-8 Power Consumption Added Figure 15-2 Part Marking Updated Section 16 Ordering Information Updated Section 1 Features Updated Section 3.1 PCI Express Interface Signals (40 Balls) Updated Section 7 EEPROM Interface And System Management/I2c Bus 8.2.114 Switch Operation Mode Register – Offset 850h (Upstream Port Only) Updated 8.2.53 Link Control Register 2 Updated Section 13.1 Absolute Maximum Ratings Update Figure 15-2 Part Marking Updated Section 1 Features Updated Section 3.2 Port Specific Signals (21 Balls) Updated Section 6.1 Physical Layer Circuit Updated Section 8.2.126 EEPROM Control Register Updated Section 16 Ordering Information For Datasheet Status Change Updated Table 9-1 AC Switching and DC Electrical Characteristics for REFCLKP/N Updated Section 2 General Description Removed Section 6.12 Access Control Service Updated Section 8.2.138 PORT MISC 1 REGISTER – OFFSET 8B4h Page 4 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR TABLE OF CONTENTS 1 FEATURES .................................................................................................................................................................... 16 2 GENERAL DESCRIPTION ......................................................................................................................................... 17 3 PIN DESCRIPTION...................................................................................................................................................... 18 3.1 3.2 3.3 3.4 3.5 3.6 4 PIN DESCRIPTION...................................................................................................................................................... 22 4.1 5 PIN LIST OF 196-BALL LBGA ................................................................................................................................. 22 MODE SELECTION AND PORT-LANE MAPPING............................................................................................... 24 5.1 5.2 5.3 6 PCI EXPRESS INTERFACE SIGNALS (40 BALLS) .............................................................................................. 18 PORT SPECIFIC SIGNALS (21 BALLS) ................................................................................................................. 18 EEPROM AND SMBUS/I2C SIGNALS (10 BALLS) ................................................................................................ 19 MISCELLANEOUS SIGNALS (45 BALLS) ............................................................................................................ 19 JTAG BOUNDARY SCAN SIGNALS (5 BALLS)..................................................................................................... 20 POWER PINS (75 BALLS) ....................................................................................................................................... 20 MODE SELECTION ................................................................................................................................................. 24 LANE MAPPING ...................................................................................................................................................... 24 PORT-LANE MAPPING........................................................................................................................................... 24 FUNCTIONAL DESCRIPTION .................................................................................................................................. 26 6.1 PHYSICAL LAYER CIRCUIT ................................................................................................................................. 26 6.1.1 RECEIVER DETECTION .................................................................................................................................. 26 6.1.2 RECEIVER SIGNAL DETECTION .................................................................................................................... 26 6.1.3 RECEIVER EQUALIZATION ............................................................................................................................ 27 6.1.4 TRANSMITTER SWING..................................................................................................................................... 27 6.1.5 DRIVE AMPLITUDE AND DE-EMPHASIS SETTINGS ................................................................................... 27 6.1.6 DRIVE AMPLITUDE ......................................................................................................................................... 28 6.1.7 DRIVE DE-EMPHASIS ..................................................................................................................................... 28 6.1.8 TRANSMITTER ELECTRICAL IDLE LATENCY .............................................................................................. 29 6.2 DATA LINK LAYER (DLL) ..................................................................................................................................... 29 6.3 TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) ............................................................. 30 6.4 ROUTING ................................................................................................................................................................. 30 6.5 TC/VC MAPPING ..................................................................................................................................................... 30 6.6 QUEUE ...................................................................................................................................................................... 30 6.6.1 PH ...................................................................................................................................................................... 31 6.6.2 PD ...................................................................................................................................................................... 31 6.6.3 NPHD ................................................................................................................................................................ 31 6.6.4 CPLH ................................................................................................................................................................. 31 6.6.5 CPLD ................................................................................................................................................................. 31 6.7 TRANSACTION ORDERING .................................................................................................................................. 31 6.8 PORT ARBITRATION ............................................................................................................................................. 32 6.9 VC ARBITRATION .................................................................................................................................................. 32 6.10 FLOW CONTROL .................................................................................................................................................... 32 6.11 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) ............................................................ 33 6.12 NON-TRANSPARENT BRIDGING (NT MODE ONLY) ..................................................................................................... 33 6.12.1 Device Type Identification ................................................................................................................................. 33 6.12.2 Intelligent Adaptor ............................................................................................................................................. 33 6.12.3 Interrupts Request (IRQ) Registers .................................................................................................................... 34 6.12.4 Scratchpad Registers ......................................................................................................................................... 35 6.12.5 NT Base Address Registers ................................................................................................................................ 35 PI7C9X2G808PR Document Number DS40341 Rev 9-2 Page 5 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR 6.12.6 7 Routing ID Translation ...................................................................................................................................... 35 EEPROM INTERFACE AND SYSTEM MANAGEMENT/I2C BUS ..................................................................... 36 7.1 EEPROM INTERFACE............................................................................................................................................. 36 7.1.1 AUTO MODE EEPROM ACCESS..................................................................................................................... 36 7.1.2 EEPROM MODE AT RESET ............................................................................................................................. 36 7.1.3 EEPROM SPACE ADDRESS MAP ................................................................................................................... 36 7.2 SMBUS INTERFACE ............................................................................................................................................... 37 7.2.1 SMBUS BLOCK WRITE .................................................................................................................................... 38 7.2.2 SMBUS BLOCK READ ...................................................................................................................................... 39 7.2.3 CSR READ, USING SMBUS BLOCK READ – BLOCK WRITE PROCESS CALL ........................................... 42 7.3 I2C SLAVE INTERFACE .......................................................................................................................................... 43 7.3.1 I2C REGISTER WRITE ACCESS ....................................................................................................................... 44 7.3.2 I2C REGISTER READ ACCESS ......................................................................................................................... 46 8 REGISTER DESCRIPTION ........................................................................................................................................ 49 8.1 REGISTER TYPES ................................................................................................................................................... 49 8.2 TRANSPARENT MODE CONFIGURATION REGISTERS ................................................................................... 49 8.2.1 VENDOR ID REGISTER – OFFSET 00h .......................................................................................................... 52 8.2.2 DEVICE ID REGISTER – OFFSET 00h............................................................................................................ 52 8.2.3 COMMAND REGISTER – OFFSET 04h ........................................................................................................... 52 8.2.4 PRIMARY STATUS REGISTER – OFFSET 04h ................................................................................................ 53 8.2.5 REVISION ID REGISTER – OFFSET 08h ........................................................................................................ 54 8.2.6 CLASS REGISTER – OFFSET 08h .................................................................................................................... 54 8.2.7 CACHE LINE REGISTER – OFFSET 0Ch ........................................................................................................ 54 8.2.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ............................................................................... 54 8.2.9 HEADER TYPE REGISTER – OFFSET 0Ch..................................................................................................... 54 8.2.10 BASE ADDRESS 0 REGISTER – OFFSET 10h (Upstream Port Only) ............................................................. 54 8.2.11 BASE ADDRESS 1 REGISTER – OFFSET 14h (Upstream Port Only) ............................................................. 55 8.2.12 PRIMARY BUS NUMBER REGISTER – OFFSET 18h ..................................................................................... 55 8.2.13 SECONDARY BUS NUMBER REGISTER – OFFSET 18h ............................................................................... 55 8.2.14 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ........................................................................... 55 8.2.15 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h .......................................................................... 55 8.2.16 I/O BASE ADDRESS REGISTER – OFFSET 1Ch ............................................................................................. 55 8.2.17 I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch ............................................................................................ 56 8.2.18 SECONDARY STATUS REGISTER – OFFSET 1Ch ......................................................................................... 56 8.2.19 MEMORY BASE ADDRESS REGISTER – OFFSET 20h .................................................................................. 56 8.2.20 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h ................................................................................. 57 8.2.21 PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h .................................................... 57 8.2.22 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ................................................... 57 8.2.23 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ........................ 57 8.2.24 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ...................... 57 8.2.25 I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .................................................................. 58 8.2.26 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h................................................................. 58 8.2.27 CAPABILITY POINTER REGISTER – OFFSET 34h ........................................................................................ 58 8.2.28 INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................................................ 58 8.2.29 INTERRUPT PIN REGISTER – OFFSET 3Ch .................................................................................................. 58 8.2.30 BRIDGE CONTROL REGISTER – OFFSET 3Ch ............................................................................................. 58 8.2.31 POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 40h ............................................................ 59 8.2.32 POWER MANAGEMENT DATA REGISTER – OFFSET 44h ........................................................................... 60 8.2.33 PPB SUPPORT EXTENSIONS REGISTER – OFFSET 44h.............................................................................. 60 8.2.34 DATA REGISTER– OFFSET 44h ...................................................................................................................... 60 8.2.35 MSI CAPABILITIES REGISTER – OFFSET 48h .............................................................................................. 60 8.2.36 MESSAGE ADDRESS REGISTER – OFFSET 4Ch ........................................................................................... 61 PI7C9X2G808PR Document Number DS40341 Rev 9-2 Page 6 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR 8.2.37 MESSAGE UPPER ADDRESS REGISTER – OFFSET 50h .............................................................................. 61 8.2.38 MESSAGE DATA REGISTER – OFFSET 54h................................................................................................... 61 8.2.39 PCI EXPRESS CAPABILITIES REGISTER – OFFSET 68h ............................................................................. 61 8.2.40 DEVICE CAPABILITIES REGISTER – OFFSET 6Ch ...................................................................................... 62 8.2.41 DEVICE CONTROL REGISTER – OFFSET 70h .............................................................................................. 62 8.2.42 DEVICE STATUS REGISTER – OFFSET 70h .................................................................................................. 63 8.2.43 LINK CAPABILITIES REGISTER – OFFSET 74h ............................................................................................ 63 8.2.44 LINK CONTROL REGISTER – OFFSET 78h ................................................................................................... 64 8.2.45 LINK STATUS REGISTER – OFFSET 78h ....................................................................................................... 65 8.2.46 SLOT CAPABILITIES REGISTER – OFFSET 7Ch (Downstream Port Only) .................................................. 65 8.2.47 SLOT CONTROL REGISTER – OFFSET 80h (Downstream Port Only) .......................................................... 66 8.2.48 SLOT STATUS REGISTER – OFFSET 80h (Downstream Port Only) .............................................................. 66 8.2.49 DEVICE CAPABILITIES REGISTER 2 – OFFSET 8Ch ................................................................................... 67 8.2.50 DEVICE CONTROL REGISTER 2 – OFFSET 90h ........................................................................................... 67 8.2.51 DEVICE STATUS REGISTER 2 – OFFSET 90h ............................................................................................... 67 8.2.52 LINK CAPABILITIES REGISTER 2 – OFFSET 94h ......................................................................................... 68 8.2.53 LINK CONTROL REGISTER 2 – OFFSET 98h ................................................................................................ 68 8.2.54 LINK STATUS REGISTER 2 – OFFSET 98h .................................................................................................... 68 8.2.55 SLOT CAPABILITIES REGISTER 2 – OFFSET 9Ch ........................................................................................ 68 8.2.56 SLOT CONTROL REGISTER 2 – OFFSET A0h ............................................................................................... 68 8.2.57 SLOT STATUS REGISTER 2 – OFFSET A0h.................................................................................................... 68 8.2.58 SSID/SSVID CAPATILITIES REGISTER – OFFSET A4h ................................................................................. 69 8.2.59 SUBSYSTEM VENDOR ID REGISTER – OFFSET A8h ................................................................................... 69 8.2.60 SUBSYSTEM ID REGISTER – OFFSET A8h .................................................................................................... 69 8.2.61 BAR 0-1 CONFIGURATION REGISTER – OFFSET E4h (Upstream Port Only) ............................................ 69 8.2.62 DEVICE SERIAL NUMBER ENHANCED CAPABILITY HEADER REGISTER – OFFSET 100h ................... 69 8.2.63 DEVICE SERIAL NUMBER LOWER DW REGISTER – OFFSET 104h........................................................... 69 8.2.64 DEVICE SERIAL NUMBER HIGHER DW REGISTER – OFFSET 108h ......................................................... 70 8.2.65 PCI EXPRESS POWER BUDGETING ENHANCED CAPABILITY HEADER REGISTER – OFFSET 138h (Upstream Port Only) ........................................................................................................................................................ 70 8.2.66 DATA SELECT REGISTER – OFFSET 13Ch (Upstream Port Only) ............................................................... 70 8.2.67 POWER BUDGETING DATA REGISTER – OFFSET 140h (Upstream Port Only) ......................................... 70 8.2.68 POWER BUDGET CAPABILITY REGISTER – OFFSET 144h (Upstream Port Only) .................................... 71 8.2.69 PCI EXPRESS VIRTUAL CHANNEL ENHANCED CAPABILITY HEADER REGISTER – OFFSET 148h ..... 71 8.2.70 PORT VC CAPABILITY REGISTER 1 – OFFSET 14Ch ................................................................................... 71 8.2.71 PORT VC CAPABILITY REGISTER 2 – OFFSET 150h ................................................................................... 71 8.2.72 PORT VC CONTROL REGISTER – OFFSET 154h .......................................................................................... 72 8.2.73 PORT VC STATUS REGISTER – OFFSET 154h ............................................................................................. 72 8.2.74 VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 158h ....................................................................... 72 8.2.75 VC RESOURCE CONTROL REGISTER (0) – OFFSET 15Ch .......................................................................... 72 8.2.76 VC RESOURCE STATUS REGISTER (0) – OFFSET 160h.............................................................................. 73 8.2.77 VC RESOURCE CAPABILITY REGISTER (1) – OFFSET 164h ....................................................................... 73 8.2.78 VC RESOURCE CONTROL REGISTER (1) – OFFSET 168h .......................................................................... 73 8.2.79 VC RESOURCE STATUS REGISTER (1) – OFFSET 16Ch ............................................................................. 74 8.2.80 VC ARBITRATION TABLE REGISTER – OFFSET 188h.................................................................................. 74 8.2.81 PORT ARBITRATION TABLE REGISTER (0) and (1) – OFFSET 198h and 1A8h .......................................... 74 8.2.82 ECC ERROR CHECK DISABLE REGISTER – OFFSET 1C8h (Global).......................................................... 75 8.2.83 NT-UP PORT SELECTION REGISTER – OFFSET 1DCh (Global) ................................................................. 75 8.2.84 HOT PLUG CONFIGURATION REGISTER – OFFSET 1E0h ......................................................................... 75 8.2.85 SOFTWARE LANE STATUS REGISTER – OFFSET 1F4h (Global) ................................................................ 76 8.2.86 DE-EMPHASIS AND RATE CONTROL REGISTER – OFFSET 208h (Upstream Port Only) ......................... 77 8.2.87 COMPLIANCE MODE CONTROL REGISTER – OFFSET 20Ch .................................................................... 77 8.2.88 EVEN PORT PHYSICAL LAYER COMMAND AND STATUS REGISTER – OFFSET 220h (Global) ............. 77 8.2.89 ODD PORT PHYSICAL LAYER COMMAND AND STATUS REGISTER – OFFSET 224h (Global) .............. 78 PI7C9X2G808PR Document Number DS40341 Rev 9-2 Page 7 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR 8.2.90 8.2.91 8.2.92 8.2.93 8.2.94 8.2.95 8.2.96 8.2.97 8.2.98 8.2.99 8.2.100 8.2.101 8.2.102 8.2.103 8.2.104 8.2.105 8.2.106 8.2.107 8.2.108 8.2.109 8.2.110 8.2.111 8.2.112 8.2.113 8.2.114 8.2.115 8.2.116 8.2.117 8.2.118 8.2.119 8.2.120 8.2.121 8.2.122 8.2.123 8.2.124 8.2.125 8.2.126 8.2.127 8.2.128 8.2.129 8.2.130 8.2.131 8.2.132 8.2.133 8.2.134 8.2.135 8.2.136 8.2.137 8.2.138 8.2.139 8.2.140 8.2.141 8.2.142 8.2.143 EVEN PORT DISABLE/QUIET/TEST PATTERN RATE REGISTER – OFFSET 230h (Global) ...................... 78 ODD PORT DISABLE/QUIET/TEST PATTERN RATE REGISTER – OFFSET 234h (Global) ....................... 79 LI PM SUBSTATES ENHANCED CAPABILITY HEADER – OFFSET 270h ................................................... 79 L1 PM SUBSTATES CAPABILITY REGISTER – OFFSET 274h ...................................................................... 79 L1 PM SUBSTATES CONTROL 1 REGISTER – OFFSET 278h ....................................................................... 79 L1 PM SUBSTATES CONTROL 2 REGISTER – OFFSET 27Ch ...................................................................... 80 SMBUS CONTROL AND STATUS REGISTER – OFFSET 344h (Upstream Port Only) .................................. 80 DISABLE DOWNSTREAM PORT HOT RESET REGISTER – OFFSET 34Ch (Upstream Port Only) ............. 80 ACS ENHANCED CAPABILITY HEADER REGISTER – OFFSET 520h (Downstream Port Only) ................ 81 ACS CAPABILITY REGISTER – OFFSET 524h (Downstream Port Only) ....................................................... 81 EGRESS CONTROL VECTOR REGISTER – OFFSET 528h (Downstream Port Only) ............................... 81 GPIO 0-15 DIRECTION CONTROL REGISTER – OFFSET 62Ch (Upstream Port Only) .......................... 82 GPIO 16-31 DIRECTION CONTROL REGISTER – OFFSET 630h (Upstream Port Only) ......................... 84 GPIO INPUT DE-BOUNCE REGISTER – OFFSET 638h (Upstream Port Only)........................................ 86 GPIO 0-15 INPUT DATA REGISTER – OFFSET 63Ch (Global)................................................................. 86 GPIO 16-31 INPUT DATA REGISTER – OFFSET 640h (Global) ............................................................... 87 GPIO 0-15 OUTPUT DATA REGISTER – OFFSET 644h (Upstream Port Only) ........................................ 88 GPIO 16-31 OUTPUT DATA REGISTER – OFFSET 648h (Upstream Port Only) ...................................... 89 GPIO 0-31 INTERRUPT POLARITY REGISTER – OFFSET 64Ch (Upstream Port Only).......................... 90 GPIO 0-31 INTERRUPT STATUS REGISTER – OFFSET 650h (Global) .................................................... 90 GPIO 0-31 INTERRUPT MASK REGISTER – OFFSET 654h (Upstream Port Only) .................................. 90 XPIP_CSR 0 REGISTER – OFFSET 844h .................................................................................................... 91 XPIP_CSR 1 REGISTER – OFFSET 848h .................................................................................................... 91 DECODE VGA REGISTER – OFFSET 84Ch................................................................................................ 91 SWITCH OPERATION MODE REGISTER – OFFSET 850h (Upstream Port Only).................................... 91 XPIP_CSR 2 REGISTER – OFFSET 854h .................................................................................................... 92 PHY PARAMETER 1 REGISTER – OFFSET 854h (Upstream Port Only) ................................................... 92 PHY PARAMETER 2 REGISTER – OFFSET 858h ....................................................................................... 92 PHY PARAMETER 3 REGISTER – OFFSET 85Ch ...................................................................................... 93 PHY PARAMETER 4 REGISTER - OFFSET 860h (Upstream Port Only) .................................................... 93 XPIP_CSR 3 REGISTER – OFFSET 864h .................................................................................................... 93 XPIP_CSR 4 REGISTER – OFFSET 868h (Upstream Port Only) ................................................................ 93 XPIP_CSR 5 REGISTER – OFFSET 86Ch .................................................................................................... 94 NON TRANSFER MODE REGISTER – OFFSET 870h (Upstream Port Only) ............................................ 94 OPERATION MODE REGISTER – OFFSET 874h ....................................................................................... 94 DEVICE SPECIFIC POWER MANAGEMENT EVENT– OFFSET 878h (Downstream Port Only) ............. 95 EEPROM CONTROL REGISTER – OFFSET 87Ch (Upstream Port Only).................................................. 95 EEPROM ADDRESS AND DATA REGISTER – OFFSET 880h (Upstream Port Only) .............................. 95 DEBUGOUT CONTROL REGISTER – OFFSET 884h (Upstream Port Only) ............................................. 96 DEBUGOUT DATA REGISTER – OFFSET 888h (Upstream Port Only) ..................................................... 96 LTSSM_CSR REGISTER – OFFSET 88Ch (Downstream Port Only) ........................................................... 96 MAC_CSR REGISTER – OFFSET 890h........................................................................................................ 96 POWER SAVING DISABLE REGISTER – OFFSET 8A4h ............................................................................ 96 TRANSACTION LAYER CSR REGISTER – OFFSET 8A8h .......................................................................... 97 REPLAY TIME-OUT COUNTER REGISTER – OFFSET 8ACh ................................................................... 97 ACKNOWLEDGE LATENCY TIMER REGISTER – OFFSET 8ACh ............................................................ 97 PORT MISC 0 REGISTER – OFFSET 8B0h ................................................................................................. 97 PHY PARAMETER 0 REGISTER – OFFSET 8B0h (Upstream Port Only)................................................... 98 PORT MISC 1 REGISTER – OFFSET 8B4h ................................................................................................. 98 XPIP_CSR 6 REGISTER – OFFSET 8B4h .................................................................................................... 98 XPIP_CSR 7 REGISTER – OFFSET 8B4h .................................................................................................... 98 PORT MISC 2 REGISTER – OFFSET 8B8h ................................................................................................. 98 LED DISPLAY CSR REGISTER – OFFSET 8BCh (Global) ......................................................................... 99 MULTI-CAST ENHANCED CAPABILITY HEADER REGISTER – OFFSET 900h...................................... 99 PI7C9X2G808PR Document Number DS40341 Rev 9-2 Page 8 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR 8.2.144 MULTI-CAST CAPABILITY REGISTER – OFFSET 904h ............................................................................ 99 8.2.145 MULTI-CAST CONTROL REGISTER – OFFSET 904h ................................................................................ 99 8.2.146 MULTI-CAST BASE ADDRESS 0 REGISTER – OFFSET 908h ................................................................. 100 8.2.147 MULTI-CAST BASE ADDRESS 1 REGISTER – OFFSET 90Ch ................................................................. 100 8.2.148 MULTI-CAST RECEIVER REGISTER – OFFSET 910h ............................................................................. 100 8.2.149 MULTI-CAST BLOCK ALL REGISTER – OFFSET 918h ........................................................................... 100 8.2.150 MULTI-CAST BLOCK UNTRANSLATED REGISTER – OFFSET 920h .................................................... 100 8.2.151 EEPROM_SCRATCHPAD REGISTER - OFFSET FB0h ............................................................................ 100 8.2.152 PCI EXPRESS ADVANCED ERROR REPORTING ENHANCED CAPABILITY HEADER REGISTER – OFFSET FB4h ................................................................................................................................................................. 101 8.2.153 UNCORRECTABLE ERROR STATUS REGISTER – OFFSET FB8h ......................................................... 101 8.2.154 UNCORRECTABLE ERROR MASK REGISTER – OFFSET FBCh ............................................................ 101 8.2.155 UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET FC0h ..................................................... 102 8.2.156 CORRECTABLE ERROR STATUS REGISTER – OFFSET FC4h............................................................... 103 8.2.157 CORRECTABLE ERROR MASK REGISTER – OFFSET FC8h .................................................................. 103 8.2.158 ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET FCCh ................................ 103 8.2.159 HEADER LOG REGISTER – OFFSET From FD0h to FDCh..................................................................... 104 8.3 NON TRANSPARENT PORT LINK INTERFACE CONFIGURATION REGISTERS – NT MODE ONLY.......... 105 8.3.1 VENDOR ID REGISTER – OFFSET 00h ........................................................................................................ 108 8.3.2 DEVICE ID REGISTER – OFFSET 00h.......................................................................................................... 108 8.3.3 COMMAND REGISTER – OFFSET 04h ......................................................................................................... 108 8.3.4 PRIMARY STATUS REGISTER – OFFSET 04h .............................................................................................. 108 8.3.5 REVISION ID REGISTER – OFFSET 08h ...................................................................................................... 109 8.3.6 CLASS CODE REGISTER – OFFSET 08h ...................................................................................................... 109 8.3.7 CACHE LINE REGISTER – OFFSET 0Ch ...................................................................................................... 109 8.3.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ............................................................................. 109 8.3.9 HEADER TYPE REGISTER – OFFSET 0Ch................................................................................................... 110 8.3.10 BAR 0 REGISTER – OFFSET 10h ................................................................................................................... 110 8.3.11 BAR 1 REGISTER – OFFSET 14h ................................................................................................................... 110 8.3.12 BAR 2 REGISTER – OFFSET 18h ................................................................................................................... 110 8.3.13 BAR 3 REGISTER – OFFSET 1Ch .................................................................................................................. 110 8.3.14 BAR 4 REGISTER – OFFSET 20h ................................................................................................................... 111 8.3.15 BAR 5 REGISTER – OFFSET 24h ................................................................................................................... 111 8.3.16 SUBSYSTEM VENDOR ID REGISTER – OFFSET 2Ch ................................................................................. 111 8.3.17 SUBSYSTEM ID REGISTER – OFFSET 2Ch .................................................................................................. 111 8.3.18 CAPABILITY POINTER REGISTER – OFFSET 34h ...................................................................................... 112 8.3.19 INTERRUPT LINE REGISTER – OFFSET 3Ch .............................................................................................. 112 8.3.20 INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................................................ 112 8.3.21 POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 40h .......................................................... 112 8.3.22 POWER MANAGEMENT DATA REGISTER – OFFSET 44h ......................................................................... 112 8.3.23 PPB SUPPORT EXTENSIONS – OFFSET 44h............................................................................................... 113 8.3.24 DATA REGISTER – OFFSET 44h ................................................................................................................... 113 8.3.25 MSI CAPABILITIES REGISTER – OFFSET 48h ............................................................................................ 113 8.3.26 MESSAGE ADDRESS REGISTER – OFFSET 4Ch ......................................................................................... 113 8.3.27 MESSAGE UPPER ADDRESS REGISTER – OFFSET 50h ............................................................................ 114 8.3.28 MESSAGE DATA REGISTER – OFFSET 54h................................................................................................. 114 8.3.29 PCI EXPRESS CAPABILITIES REGISTER – OFFSET 68h ........................................................................... 114 8.3.30 DEVICE CAPABILITIES REGISTER – OFFSET 6Ch .................................................................................... 114 8.3.31 DEVICE CONTROL REGISTER – OFFSET 70h ............................................................................................ 115 8.3.32 DEVICE STATUS REGISTER – OFFSET 70h ................................................................................................ 115 8.3.33 LINK CAPABILITIES REGISTER – OFFSET 74h .......................................................................................... 116 8.3.34 LINK CONTROL REGISTER – OFFSET 78h ................................................................................................. 116 8.3.35 LINK STATUS REGISTER – OFFSET 78h ..................................................................................................... 117 8.3.36 LINK CONTROL REGISTER 2 – OFFSET 94h .............................................................................................. 117 PI7C9X2G808PR Document Number DS40341 Rev 9-2 Page 9 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR 8.3.37 8.3.38 8.3.39 8.3.40 8.3.41 8.3.42 8.3.43 8.3.44 8.3.45 8.3.46 8.3.47 8.3.48 8.3.49 8.3.50 8.3.51 8.3.52 8.3.53 8.3.54 8.3.55 8.3.56 8.3.57 8.3.58 8.3.59 8.3.60 8.3.61 8.3.62 8.3.63 8.3.64 8.3.65 8.3.66 8.3.67 8.3.69 8.3.70 8.3.71 8.3.72 8.3.73 8.3.74 8.3.75 8.3.76 8.3.77 8.3.78 8.3.79 8.3.80 8.3.81 8.3.82 8.3.83 8.3.84 8.3.85 8.3.86 8.3.87 8.3.88 8.3.89 8.3.90 8.3.91 LINK CONTROL REGISTER 2 – OFFSET 98h .............................................................................................. 117 LINK STATUS REGISTER 2 – OFFSET 98h .................................................................................................. 118 SSID/SSVID CAPABILITIES REGISTER – OFFSET A4h............................................................................... 118 SUBSYSTEM VENDOR ID REGISTER – OFFSET A8h ................................................................................. 118 SUBSYSTEM ID REGISTER – OFFSET A8h .................................................................................................. 118 VENDOR SPECIFIC CAPABILITIES REGISTER – OFFSET C8h ................................................................ 118 VENDOR SPECIFIC HEADER REGISTER – OFFSET CCh ......................................................................... 118 NT PORT LINK INTERFACE BAR 0-1 CONFIGURATION REGISTER – OFFSET E4h .............................. 119 NT PORT LINK INTERFACE BAR 2 CONFIGURATION REGISTER – OFFSET E8h ................................. 119 NT PORT LINK INTERFACE BAR 2-3 CONFIGURATION REGISTER – OFFSET ECh ............................. 119 NT PORT LINK INTERFACE BAR 4 CONFIGURATION REGISTER – OFFSET F0h ................................. 120 NT PORT LINK INTERFACE BAR 4-5 CONFIGURATION REGISTER – OFFSET F4h .............................. 120 DEVICE SERIAL NUMBER ENHANCED CAPABILITY HEADER REGISTER – OFFSET 100h ................. 120 DEVICE SERIAL NUMBER LOWER DW REGISTER – OFFSET 104h......................................................... 121 DEVICE SERIAL NUMBER HIGHTER DW REGISTER – OFFSET 108h ..................................................... 121 PCI EXPRESS POWER BUDGETING ENHANCED CAPABILITY HEADER REGISTER – OFFSET 138h. 121 DATA SELECT REGISTER – OFFSET 13Ch.................................................................................................. 121 POWER BUDGETING DATA REGISTER – OFFSET 140h ........................................................................... 121 POWER BUDGET CAPABILITY REGISTER – OFFSET 144h ...................................................................... 122 PCI EXPRESS VIRTUAL CHANNEL ENHANCED CAPABILITY HEADER REGISTER – OFFSET 148h ... 122 PORT VC CAPABILITY REGISTER 1 – OFFSET 14Ch ................................................................................. 122 PORT VC CAPABILITY REGISTER 2 – OFFSET 150h ................................................................................. 122 PORT VC CONTROL REGISTER – OFFSET 154h ........................................................................................ 123 VC STATUS REGISTER – OFFSET 154h ....................................................................................................... 123 VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 158h ..................................................................... 123 VC RESOURCE CONTROL REGISTER (0) – OFFSET 15Ch ........................................................................ 123 VC RESOURCE STATUS REGISTER (0) – OFFSET 160h............................................................................. 124 VC RESOURCE CAPABILITY REGISTER (1) – OFFSET 164h ..................................................................... 124 VC RESOURCE CONTROL REGISTER (1) – OFFSET 168h ........................................................................ 124 VC RESOURCE STATUS REGISTER (1) – OFFSET 16Ch ............................................................................ 125 VC ARBITRATION TABLE REGISTER – OFFSET 188h................................................................................ 125 XPIP_CSR 0 REGISTER – OFFSET 844h ...................................................................................................... 126 XPIP_CSR 1 REGISTER – OFFSET 848h ...................................................................................................... 126 DECODE VGA REGISTER – OFFSET 84Ch.................................................................................................. 126 XPIP_CSR 2 REGISTER – OFFSET 854h ...................................................................................................... 126 PHY PARAMETER 2 REGISTER – OFFSET 858h ......................................................................................... 127 PHY PARAMETER 3 REGISTER – OFFSET 85Ch ........................................................................................ 127 XPIP_CSR 3 REGISTER – OFFSET 864h ...................................................................................................... 127 XPIP_CSR 5 REGISTER – OFFSET 86Ch ...................................................................................................... 128 OPERATION MODE REGISTER – OFFSET 874h (Global) .......................................................................... 128 MAC_CSR REGISTER – OFFSET 890h.......................................................................................................... 128 POWER SAVING DISABLE REGISTER – OFFSET 8A4h .............................................................................. 128 TRANSACTION LAYER CSR REGISTER – OFFSET 8A8h ............................................................................ 128 REPLAY TIME-OUT COUNTER REGISTER – OFFSET 8ACh ..................................................................... 129 ACKNOWLEDGE LATENCY TIMER REGISTER – OFFSET 8ACh .............................................................. 129 PORT MISC 0 REGISTER – OFFSET 8B0h ................................................................................................... 129 PORT MISC 1 REGISTER – OFFSET 8B4h ................................................................................................... 129 XPIP_CSR 6 REGISTER – OFFSET 8B4h ...................................................................................................... 130 XPIP_CSR 7 REGISTER – OFFSET 8B4h ...................................................................................................... 130 PORT MISC 2 REGISTER – OFFSET 8B8h ................................................................................................... 130 VENDOR SPECIFIC CAPABILITIES HEADER REGISTER – OFFSET C34h .............................................. 130 VENDOR SPECIFIC HEADER REGISTER – OFFSET C38h ........................................................................ 131 MEMORY BAR 2 ADDRESS TRANSLATION REGISTER – OFFSET C3Ch .................................................. 131 MEMORY BAR 3 ADDRESS TRANSLATION REGISTER – OFFSET C40h .................................................. 131 PI7C9X2G808PR Document Number DS40341 Rev 9-2 Page 10 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR 8.3.92 MEMORY BAR4 ADDRESS TRANSLATION REGISTER – OFFSET C44h ................................................... 131 8.3.93 MEMORY BAR 5 ADDRESS TRANSLATION REGISTER – OFFSET C48h .................................................. 131 8.3.94 VIRTUAL IF IRQ SET REGISTER – OFFSET C4Ch ...................................................................................... 131 8.3.95 VIRTUAL IF IRQ CLEAR REGISTER – OFFSET C50h ................................................................................. 132 8.3.96 VIRTUAL IF IRQ MASK SET REGISTER – OFFSET C54h ........................................................................... 132 8.3.97 VIRTUAL IF IRQ MASK CLEAR REGISTER – OFFSET C58h...................................................................... 132 8.3.98 LINK IF IRQ SET REGISTER – OFFSET C5Ch ............................................................................................. 132 8.3.99 LINK IF IRQ CLEAR REGISTER – OFFSET C60h ........................................................................................ 132 8.3.100 LINK IF IRQ MASK SET REGISTER – OFFST C64h ................................................................................. 132 8.3.101 LINK IF IRQ MASK CLEAR REGISTER – OFFSET C68h ......................................................................... 132 8.3.102 SCRATCHPAD 0 REGISTER – OFFSET C6Ch .......................................................................................... 133 8.3.103 SCRATCHPAD 1 REGISTER – OFFSET C70h .......................................................................................... 133 8.3.104 SCRATHPAD 2 REGISTER – OFFSET C74h ............................................................................................. 133 8.3.105 SCRATCHPAD 3 REGISTER – OFFSET C78h .......................................................................................... 133 8.3.106 SCRATHPAD 4 REGISTER – OFFSET C7Ch ............................................................................................ 133 8.3.107 SCRATCHPAD 5 REGISTER – OFFSET C80h .......................................................................................... 133 8.3.108 SCRATCHPAD 6 REGISTER – OFFSET C84h .......................................................................................... 133 8.3.109 SCRATCHPAD 7 REGISTER – OFFSTE C88h .......................................................................................... 133 8.3.110 VIRTUAL PORT 32-BITS LTT ENTRY 0-7 – OFFSET D94h to DB0h ....................................................... 134 8.3.111 LINK PORT 16-BITS LTT ENTRY 0-31 REGISTER – OFFSET DB4h – DF4h .......................................... 134 8.3.112 FAIL-OVER CSR REGISTER – OFFSET DF4h .......................................................................................... 135 8.3.113 EEPROM_SCRATCHPAD REGISTER – OFFSET FB0h ........................................................................... 135 8.3.114 PCI EXPRESS ADVANCED ERROR REPORTING ENHANCED CAPABILITY HEADER REGISTER – OFFSET FB4h ................................................................................................................................................................. 135 8.3.115 UNCORRECTABLE ERROR STATUS REGISTER – OFFSET FB8h ......................................................... 135 8.3.116 UNCORRECTABLE ERROR MASK REGISTER – OFFSET FBCh ............................................................ 136 8.3.117 UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET FC0h ..................................................... 136 8.3.118 CORRECTABLE ERROR STATUS REGISTER – OFFSET FC4 h.............................................................. 137 8.3.119 CORRECTABLE ERROR MASK REGISTER – OFFSET FC8 h ................................................................. 137 8.3.120 ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET FCCh ................................ 138 8.3.121 HEADER LOG REGISTER – OFFSET From FD0h to FDCh..................................................................... 138 8.4 NON TRANSPARENT PORT VIRTUAL INTERFACE CONFIGURATION REGISTERS – NT MODE ONLY .. 139 8.4.1 VENDOR ID REGISTER – OFFSET 00h ........................................................................................................ 140 8.4.2 DEVICE ID REGISTER – OFFSET 00h.......................................................................................................... 141 8.4.3 COMMAND REGISTER – OFFSET 04h ......................................................................................................... 141 8.4.5 REVISION ID REGISTER – OFFSET 08h ...................................................................................................... 142 8.4.6 CLASS CODE REGISTER – OFFSET 08h ...................................................................................................... 142 8.4.7 CACHE LINE REGISTER – OFFSET 0Ch ...................................................................................................... 142 8.4.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ............................................................................. 142 8.4.9 HEADER TYPE REGISTER – OFFSET 0Ch................................................................................................... 142 8.4.10 BAR 0 REGISTER – OFFSET 10h ................................................................................................................... 143 8.4.11 BAR 1 REGISTER – OFFSET 14h ................................................................................................................... 143 8.4.12 BAR 2 REGISTER – OFFSET 18h ................................................................................................................... 143 8.4.13 BAR 3 REGISTER – OFFSET 1Ch .................................................................................................................. 143 8.4.14 BAR 4 REGISTER – OFFSET 20h ................................................................................................................... 144 8.4.15 BAR 5 REGISTER – OFFSET 24h ................................................................................................................... 144 8.4.16 SUBSYSTEM VENDOR ID REGISTER – OFFSET 2Ch ................................................................................. 144 8.4.17 SUBSYSTEM ID REGISTER – OFFSET 2Ch .................................................................................................. 144 8.4.18 CAPABILITY POINTER REGISTER – OFFSET 34h ...................................................................................... 144 8.4.19 INTERRUPT LINE REGISTER – OFFSET 3Ch .............................................................................................. 145 8.4.20 INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................................................ 145 8.4.21 POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 40h .......................................................... 145 8.4.22 POWER MANAGEMENT DATA REGISTER – OFFSET 44h ......................................................................... 145 8.4.23 PPB SUPPORT EXTENSIONS – OFFSET 44h............................................................................................... 146 PI7C9X2G808PR Document Number DS40341 Rev 9-2 Page 11 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR 8.4.24 8.4.25 8.4.26 8.4.27 8.4.28 8.4.29 8.4.30 8.4.31 8.4.32 8.4.33 8.4.34 8.4.35 8.4.36 8.4.37 8.4.38 8.4.39 8.4.40 8.4.41 8.4.42 8.4.43 8.4.44 8.4.45 8.4.46 8.4.47 8.4.48 8.4.49 8.4.50 8.4.51 8.4.52 8.4.53 8.4.54 8.4.55 8.4.56 8.4.57 8.4.58 8.4.59 8.4.60 8.4.61 8.4.62 8.4.63 8.4.64 8.4.65 8.4.66 8.4.67 8.4.68 8.4.69 8.4.70 8.4.71 8.4.72 8.4.73 8.4.74 8.4.75 9 DATA REGISTER – OFFSET 44h ................................................................................................................... 146 MSI CAPABILITIES REGISTER – OFFSET 48h ............................................................................................ 146 MESSAGE ADDRESS REGISTER – OFFSET 4Ch ......................................................................................... 146 MESSAGE UPPER ADDRESS REGISTER – OFFSET 50h ............................................................................ 146 MESSAGE DATA REGISTER – OFFSET 54h................................................................................................. 147 PCI EXPRESS CAPABILITIES REGISTER – OFFSET 68h ........................................................................... 147 DEVICE CAPABILITIES REGISTER – OFFSET 6Ch .................................................................................... 147 DEVICE CONTROL REGISTER – OFFSET 70h ............................................................................................ 148 DEVICE STATUS REGISTER – OFFSET 70h ................................................................................................ 148 LINK CAPABILITIES REGISTER – OFFSET 74h .......................................................................................... 149 LINK CONTROL REGISTER – OFFSET 78h ................................................................................................. 149 LINK STATUS REGISTER – OFFSET 78h ..................................................................................................... 150 LINK CONTROL REGISTER 2 – OFFSET 98h .............................................................................................. 150 LINK STATUS REGISTER 2 – OFFSET 98h .................................................................................................. 151 SSID/SSVID CAPABILITIES REGISTER – OFFSET A4h............................................................................... 151 SUBSYSTEM VENDOR ID REGISTER – OFFSET A8h ................................................................................. 151 SUBSYSTEM ID REGISTER – OFFSET A8h .................................................................................................. 151 VENDOR SPECIFIC CAPABILITIES REGISTER – OFFSET C8h ................................................................ 151 VENDOR SPECIFIC HEADER REGISTER – OFFSET CCh ......................................................................... 151 NT PORT VIRTUAL INTERFACE BAR 0-1 CONFIGURATION REGISTER – OFFSET D0h ...................... 152 NT PORT VIRTUAL INTERFACE BAR 2 CONFIGURATION REGISTER – OFFSET D4h .......................... 152 NT PORT VIRTUAL INTERFACE BAR 2-3 CONFIGURATION REGISTER – OFFSET D8h ...................... 152 NT PORT VIRTUAL INTERFACE BAR 4 CONFIGURATION REGISTER – OFFSET DCh ......................... 153 NT PORT VIRTUAL INTERFACE BAR 4/5 CONFIGURATION REGISTER – OFFSET E0h ....................... 153 DEVICE SERIAL NUMBER ENHANCED CAPABILITY HEADER REGISTER – OFFSET 100h ................. 153 DEVICE SERIAL NUMBER LOWER DW REGISTER – OFFSET 104h......................................................... 154 DEVICE SERIAL NUMBER HIGHER DW REGISTER – OFFSET 108h ....................................................... 154 VENDOR SPECIFIC ENHANCED CAPABILIY HEADER REGISTER – OFFSET C34h .............................. 154 VENDOR SPECIFIC HEADER REGISTER – OFFSET C38h ........................................................................ 154 MEMORY BAR 2 ADDRESS TRANSLATION REGISTER – OFFSET C3Ch .................................................. 154 MEMORY BAR 3 ADDRESS TRANSLATION REGISTER – OFFSET C40h .................................................. 154 MEMORY BAR4 ADDRESS TRANSLATION REGISTER – OFFSET C44h ................................................... 155 MEMORY BAR 5 ADDRESS TRANSLATION REGISTER – OFFSET C48h .................................................. 155 VIRTUAL IF IRQ SET REGISTER – OFFSET C4Ch ...................................................................................... 155 VIRTUAL IF IRQ CLEAR REGISTER – OFFSET C50h ................................................................................. 155 VIRTUAL IF IRQ MASK SET REGISTER – OFFSET C54h ........................................................................... 155 VIRTUAL IF IRQ MASK CLEAR REGISTER – OFFSET C58h...................................................................... 155 LINK IF IRQ SET REGISTER – OFFSET C5Ch ............................................................................................. 155 LINK IF IRQ CLEAR REGISTER – OFFSET C60h ........................................................................................ 156 LINK IF IRQ MASK SET REGISTER – OFFSET C64h .................................................................................. 156 LINK IF IRQ MASK CLEAR REGISTER – OFFSET C68h ............................................................................. 156 SCRATCHPAD 0 REGISTER – OFFSET C6Ch .............................................................................................. 156 SCRATCHPAD 1 REGISTER – OFFSET C70h .............................................................................................. 156 SCRATHPAD 2 REGISTER – OFFSET C74h ................................................................................................. 156 SCRATCHPAD 3 REGISTER – OFFSET C78h .............................................................................................. 156 SCRATHPAD 4 REGISTER – OFFSET C7Ch ................................................................................................ 157 SCRATCHPAD 5 REGISTER – OFFSET C80h .............................................................................................. 157 SCRATCHPAD 6 REGISTER – OFFSET C84h .............................................................................................. 157 SCRATCHPAD 7 REGISTER – OFFSTE C88h .............................................................................................. 157 VIRTUAL PORT 32-BITS LTT ENTRY 0-7 – OFFSET D94h to DB0h ........................................................... 157 LINK PORT 16-BITS LTT ENTRY 0-31 REGISTER – OFFSET DB4h – DF4h .............................................. 158 FAIL-OVER CSR REGISTER – OFFSET DF4h .............................................................................................. 158 CLOCK SCHEME ...................................................................................................................................................... 159 PI7C9X2G808PR Document Number DS40341 Rev 9-2 Page 12 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR 10 POWER MANAGEMENT ......................................................................................................................................... 160 11 POWER SEQUENCE ................................................................................................................................................. 161 12 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ............................................................................................. 162 12.1 12.2 12.3 12.4 12.5 INSTRUCTION REGISTER ................................................................................................................................... 162 BYPASS REGISTER .............................................................................................................................................. 162 DEVICE ID REGISTER .......................................................................................................................................... 162 BOUNDARY SCAN REGISTER ............................................................................................................................ 163 JTAG BOUNDARY SCAN REGISTER ORDER ................................................................................................... 163 13 ELECTRICAL AND TIMING SPECIFICATIONS ................................................................................................ 168 13.1 13.2 13.3 13.4 13.5 ABSOLUTE MAXIMUM RATINGS ..................................................................................................................... 168 DC SPECIFICATIONS ........................................................................................................................................... 168 AC SPECIFICATIONS ........................................................................................................................................... 168 OPERATING AMBIENT TEMPERATURE .......................................................................................................... 170 POWER CONSUMPTION ...................................................................................................................................... 170 14 THERMAL DATA ...................................................................................................................................................... 171 15 PACKAGE INFORMATION..................................................................................................................................... 172 16 ORDERING INFORMATION................................................................................................................................... 173 PI7C9X2G808PR Document Number DS40341 Rev 9-2 Page 13 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR TABLE OF FIGURES FIGURE 4-1 PI7C9X2G808PR BALL ASSIGNMENT .................................................................................................................... 23 FIGURE 6-1 DRIVER OUTPUT WAVEFORM .................................................................................................................................. 28 FIGURE 6-2 INTELLIGENT ADAPTOR ARCHITECTURE.................................................................................................................. 34 FIGURE 7-1 SMBUS ARCHITECTURE IMPLEMENTATION ............................................................................................................. 37 FIGURE 7-2 SMBUS BLOCK WRITE COMMAND FORMAT, TO WRITE TO A PI7C9X2G808PR REGISTER WITHOUT PEC ............ 38 FIGURE 7-3 SMBUS BLOCK WRITE COMMAND FORMAT, TO WRITE TO A PI7C9X2G808PR REGISTER WITH PEC ................... 38 FIGURE 7-4 SMBUS BLOCK WRITE TO SET UP READ, AND RESULTING READ THAT RETURNS CFG REGISTER VALUE .............. 40 FIGURE 7-5 CSR READ OPERATION USING SMBUS BLOCK READ – BLOCK WRITE PROCESS CALL .......................................... 42 FIGURE 7-6 CSR READ OPERATION USING SMBUS BLOCK READ – BLOCK WRITE PROCESS CALL WITH PEC ......................... 42 FIGURE 7-7 STANDARD DEVICES TO I2C BUS CONNECTION BLOCK DIAGRAM ........................................................................... 43 FIGURE 7-8 I2C WRITE PACKET .................................................................................................................................................. 45 FIGURE 7-9 I2C REGISTER WRITE ACCESS EXAMPLE ................................................................................................................. 45 FIGURE 7-10 I2C WRITE COMMAND PACKET EXAMPLE ............................................................................................................. 46 FIGURE 7-11 I2C READ COMMAND PACKET ............................................................................................................................... 47 FIGURE 7-12 I2C REGISTER READ ACCESS EXAMPLE ................................................................................................................. 48 FIGURE 7-13 I2C READ COMMAND PACKET ............................................................................................................................... 48 FIGURE 11-1 INITIAL POWER-UP SEQUENCE ............................................................................................................................ 161 FIGURE 15-1 PACKAGE OUTLINE DRAWING ............................................................................................................................. 172 FIGURE 15-2 PART MARKING ................................................................................................................................................... 172 PI7C9X2G808PR Document Number DS40341 Rev 9-2 Page 14 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR LIST OF TABLES TABLE 6-1 RECEIVER DETECTION THRESHOLD SETTINGS .......................................................................................................... 26 TABLE 6-2 RECEIVER SIGNAL DETECT THRESHOLD ................................................................................................................... 27 TABLE 6-3 RECEIVER EQUALIZATION SETTINGS ........................................................................................................................ 27 TABLE 6-4 TRANSMITTER SWING SETTINGS ............................................................................................................................... 27 TABLE 6-5 DRIVE AMPLITUDE BASE LEVEL REGISTERS ............................................................................................................ 28 TABLE 6-6 DRIVE AMPLITUDE BASE LEVEL SETTINGS............................................................................................................... 28 TABLE 6-7 DRIVE DE-EMPHASIS BASE LEVEL REGISTER ........................................................................................................... 29 TABLE 6-8 DRIVE DE-EMPHASIS BASE LEVEL SETTINGS ........................................................................................................... 29 TABLE 6-9 SUMMARY OF PCI EXPRESS ORDERING RULES ......................................................................................................... 31 TABLE 7-1 SMBUS ADDRESS PIN CONFIGURATION ................................................................................................................... 37 TABLE 7-2 BYTES FOR SMBUS BLOCK WRITE ........................................................................................................................... 38 TABLE 7-3 SAMPLE SMBUS BLOCK WRITE BYTE SEQUENCE .................................................................................................... 39 TABLE 7-4 BYTES FOR SMBUS BLOCK READ ............................................................................................................................. 40 TABLE 7-5 SMBUS BLOCK WRITE PORTION .............................................................................................................................. 41 TABLE 7-6 SMBUS BLOCK READ PORTION ................................................................................................................................ 41 TABLE 7-7 SMBUS READ COMMAND FOLLOWING REPEAT START FROM MASTER .................................................................. 41 TABLE 7-8 SMBUS RETURN BYTES ............................................................................................................................................ 41 TABLE 7-9 COMMAND FORMAT FOR SMBUS BLOCK READ ....................................................................................................... 42 TABLE 7-10 I2C ADDRESS PIN CONFIGURATION ......................................................................................................................... 43 TABLE 7-11 I2C REGISTER WRITE ACCESS ................................................................................................................................. 44 TABLE 7-12 I2C COMMAND FORMAT FOR WRITE ACCESS.......................................................................................................... 44 TABLE 7-13 I2C COMMAND FORMAT FOR READ ACCESS ........................................................................................................... 46 TABLE 8-1 REGISTER TYPES ....................................................................................................................................................... 49 TABLE 8-2 REGISTER ARRAY LAYOUT FOR VC ARBITRATION ................................................................................................... 74 TABLE 8-3 TABLE ENTRY SIZE IN 4 BITS .................................................................................................................................... 75 TABLE 8-4 REGISTER ARRAY LAYOUT FOR VC ARBITRATION ................................................................................................. 125 TABLE 8-5 TABLE ENTRY SIZE IN 4 BITS .................................................................................................................................. 126 TABLE 8-6 VIRTUAL PORT 32-BITS LTT ENTRY 0-7 REGISTER LOCATIONS ............................................................................ 134 TABLE 8-7 VIRTUAL PORT 32-BITS LTT ENTRY_N (N=0 THROUGH 7) ..................................................................................... 134 TABLE 8-8 LINK PORT 16-BITS LTT ENTRY 0-31 REGISTER LOCATIONS ................................................................................. 134 TABLE 8-9 LINK PORT 16-BITS LTT ENTRY_N_M (N_M 0-1 TO 30-31) .................................................................................... 134 TABLE 8-10 VIRTUAL PORT 32-BITS LTT ENTRY 0-7 REGISTER LOCATIONS .......................................................................... 157 TABLE 8-11 VIRTUAL PORT 32-BITS LTT ENTRY_N (N=0 THROUGH 7) ................................................................................... 157 TABLE 8-12 LINK PORT 16-BITS LTT ENTRY 0-31 REGISTER LOCATIONS ............................................................................... 158 TABLE 8-13 LINK PORT 16-BITS LTT ENTRY_N_M (N_M 0-1 TO 30-31) .................................................................................. 158 TABLE 9-1 AC SWITCHING AND DC ELECTRICAL CHARACTERISTICS FOR REFCLKP/N ......................................................... 159 TABLE 12-1 INSTRUCTION REGISTER CODES ............................................................................................................................ 162 TABLE 12-2 JTAG DEVICE ID REGISTER ................................................................................................................................. 162 TABLE 12-3 JTAG BOUNDARY SCAN REGISTER DEFINITION ................................................................................................... 163 TABLE 13-1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................... 168 TABLE 13-2 DC ELECTRICAL CHARACTERISTICS ..................................................................................................................... 168 TABLE 13-3 PCI EXPRESS INTERFACE - DIFFERENTIAL TRANSMITTER (TX) OUTPUT (5.0 GBPS) CHARACTERISTICS .............. 168 TABLE 13-4 PCI EXPRESS INTERFACE - DIFFERENTIAL TRANSMITTER (TX) OUTPUT (2.5 GBPS) CHARACTERISTICS .............. 169 TABLE 13-5 PCI EXPRESS INTERFACE - DIFFERENTIAL RECEIVER (RX) INPUT (5.0 GBPS) CHARACTERISTICS ........................ 169 TABLE 13-6 PCI EXPRESS INTERFACE - DIFFERENTIAL RECEIVER (RX) INPUT (2.5 GBPS) CHARACTERISTICS ........................ 170 TABLE 13-7 OPERATING AMBIENT TEMPERATURE ................................................................................................................... 170 TABLE 13-8 POWER CONSUMPTION ......................................................................................................................................... 170 TABLE 14-1 THERMAL DATA.................................................................................................................................................... 171 PI7C9X2G808PR Document Number DS40341 Rev 9-2 Page 15 of 173 www.diodes.com August 2022 © 2022 Copyright Diodes Incorporated. All Rights Reserved. PI7C9X2G808PR 1 FEATURES • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 8-lane PCI Express® Gen 2 Switch with 8 PCI Express ports Supports “Cut-through”(Default) as well as “Store and Forward” mode for packet switching 150 ns typical latency for packet routed through Switch without blocking Supports Transparent and Non-Transparent Modes Strapped pins configurable with optional EEPROM, SMBus or I2C Bus SMBus interface support I2C Slave interface support Compliant with System Management (SM) Bus, Version 2.0 Compliant with I2C Bus Specification, Version 2.1 Compliant with PCI Express Base Specification Revision 2.1 Compliant with PCI Express CEM Specification Revision 2.0 Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2 Compliant with Advanced Configuration Power Interface (ACPI) Specification Reliability, Availability and Serviceability Supports Data Poisoning and End-to-End CRC Advanced Error Reporting and Logging Advanced Power Saving Empty downstream ports are set to idle state to minimize power consumption Link Power Management Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power states Active state power management for L0s and L1 states Device State Power Management Supports D0, D3Hot and D3Cold device power states Port Arbitration: Round Robin (RR), Weighted RR and Time-based Weighted RR Extended Virtual Channel capability Two Virtual Channels (VC) and Eight Traffic Class (TC) support Disabled VCs’ buffer is assigned to enabled VCs for resource sharing Independent TC/VC mapping for each port Provides VC arbitration selections: Strict Priority, Round Robin (RR) and Programmable Weighted RR Supports Isochronous Traffic Isochronous traffic class mapped to VC1 only Strict time based credit policing Supports up to 512-byte maximum payload size Programmable driver current and de-emphasis level at each individual port Support Access Control Service (ACS) Support Address Translation (AT) packet for SR-IOV application Support Alternative Routing ID Interpretation (ARI) Support Mutlicast Support Serial Hot Plug Controller Low Power Dissipation: 1.23W typical in L0 normal mode Industrial Temperature Range -40o to 85oC Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative. https://www.diodes.com/quality/product-definitions/ 196-pin LBGA 15mm x 15mm package (ULA) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain