TISP4072F3DR-S

TISP4072F3, TISP4082F3 SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS Copyright © 1997, Power Innovations Limited, UK MARCH 1994 - REVISED SEPTEMBER 1997 TELECOMMUNICATION SYSTEM SECONDARY PROTECTION ● Ion-Implanted Breakdown Region Precise and Stable Voltage Low Voltage Overshoot under Surge T 1 8 R VDRM V(BO) T 2 7 R V V T 3 6 R ‘4072F3 58 72 T 4 5 R ‘4082F3 66 82 DEVICE ● ● D PACKAGE (TOP VIEW) Specified ratings require the connection of pins 1, 2, 3 and 4 for the T terminal. Planar Passivated Junctions Low Off-State Current < 10 µA SL PACKAGE (TOP VIEW) Rated for International Surge Wave Shapes WAVE SHAPE STANDARD ITSP FCC Part 68 8/20 µs ANSI C62.41 70 10/160 µs FCC Part 68 60 10/560 µs FCC Part 68 45 10/700 µs 1 R 2 80 RLM 88 38 FTZ R12 50 VDE 0433 50 CCITT IX K17/K20 50 REA PE-60 35 10/1000 µs T A 2/10 µs 0.5/700 µs MDXXAH MD4XAA device symbol D PACKAGE 3 SL PACKAGE T T 1 2 T 1 Surface Mount and Through-Hole Options PACKAGE PART # SUFFIX Small-outline D Small-outline taped and reeled Single-in-line ● T T 4 ● MDXXAI DR SL 5 6 R 8 7 R R 2 R R SD4XAE Terminals T and R correspond to the alternative line designators of A and B UL Recognized, E132482 description These low voltage symmetrical transient voltage suppressor devices are designed to protect two wire telecommunication applications against transients caused by lightning strikes and a.c. power lines. Offered in two voltage variants to meet battery and protection requirements they are guaranteed to suppress and withstand the listed international lightning surges in both polarities. Transients are initially clipped by breakdown clamping until the voltage rises to the breakover level, which causes the device to crowbar. The high crowbar holding current prevents d.c. latchup as the current subsides. PRODUCT These monolithic protection devices are fabricated in ion-implanted planar structures to ensure precise and matched breakover control and are virtually transparent to the system in normal operation The small-outline 8-pin assignment has been carefully chosen for the TISP series to maximise the inter-pin clearance and creepage distances which are used by standards (e.g. IEC950) to establish voltage withstand ratings. INFORMATION Information is current as of publication date. Products conform to specifications in accordance with the terms of Power Innovations standard warranty. Production processing does not necessarily include testing of all parameters. 1 TISP4072F3, TISP4082F3 SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS MARCH 1994 - REVISED SEPTEMBER 1997 absolute maximum ratings RATING SYMBOL ‘4072F3 Repetitive peak off-state voltage (0°C < TJ < 70°C) VALUE ± 58 VDRM ‘4082F3 UNIT V ± 66 Non-repetitive peak on-state pulse current (see Notes 1, 2 and 3) 1/2 µs (Gas tube differential transient, open-circuit voltage wave shape 1/2 µs) 120 2/10 µs (FCC Part 68, open-circuit voltage wave shape 2/10 µs) 80 8/20 µs (ANSI C62.41, open-circuit voltage wave shape 1.2/50 µs) 70 10/160 µs (FCC Part 68, open-circuit voltage wave shape 10/160 µs) 60 5/200 µs (VDE 0433, open-circuit voltage wave shape 2 kV, 10/700 µs) 0.2/310 µs (RLM 88, open-circuit voltage wave shape 1.5 kV, 0.5/700 µs) 38 5/310 µs (CCITT IX K17/K20, open-circuit voltage wave shape 2 kV, 10/700 µs) 50 5/310 µs (FTZ R12, open-circuit voltage wave shape 2 kV, 10/700 µs) 50 10/560 µs (FCC Part 68, open-circuit voltage wave shape 10/560 µs) 45 10/1000 µs (REA PE-60, open-circuit voltage wave shape 10/1000 µs) 35 Non-repetitive peak on-state current (see Notes 2 and 3) 50 Hz, D Package 1s 4 ITSM SL Package Initial rate of rise of on-state current, A 50 ITSP Linear current ramp, Maximum ramp value < 38 A A rms 6 diT/dt 250 A/µs TJ -40 to +150 °C Tstg -40 to +150 °C Junction temperature Storage temperature range NOTES: 1. Further details on surge wave shapes are contained in the Applications Information section. 2. Initially the TISP must be in thermal equilibrium with 0°C < TJ > Vd the capacitance value is independent on the value of Vd . The capacitance is essentially constant over the range of normal telecommunication frequencies. NORMALISED CAPACITANCE vs RMS AC TEST VOLTAGE 1.05 AIXXAA Normalised Capacitance 1.00 0.95 0.90 0.85 0.80 Normalised to Vd = 100 mV 0.75 DC Bias, VD = 0 0.70 1 10 100 Vd - RMS AC Test Voltage - mV Figure 13. PRODUCT 8 INFORMATION 1000 TISP4072F3, TISP4082F3 SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS MARCH 1994 - REVISED SEPTEMBER 1997 MECHANICAL DATA D008 plastic small-outline package This small-outline package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions. Leads require no additional cleaning or processing when used in soldered assembly. D008 Designation per JEDEC Std 30: PDSO-G8 5,00 (0.197) 4,80 (0.189) 8 7 6 5 1 2 3 4 6,20 (0.244) 5,80 (0.228) 4,00 (0.157) 3,81 (0.150) 7° NOM 3 Places 1,75 (0.069) 1,35 (0.053) 0,50 (0.020) x 45°NOM 0,25 (0.010) 0,203 (0.008) 0,102 (0.004) 0,79 (0.031) 0,28 (0.011) 7° NOM 4 Places 0,51 (0.020) 0,36 (0.014) 8 Places Pin Spacing 1,27 (0.050) (see Note A) 6 Places 5,21 (0.205) 4,60 (0.181) 0,229 (0.0090) 0,190 (0.0075) 4° ± 4° 1,12 (0.044) 0,51 (0.020) ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTES: A. B. C. D. Leads are within 0,25 (0.010) radius of true position at maximum material condition. Body dimensions do not include mold flash or protrusion. Mold flash or protrusion shall not exceed 0,15 (0.006). Lead tips to be planar within ±0,051 (0.002). PRODUCT MDXXAA INFORMATION 9 TISP4072F3, TISP4082F3 SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS MARCH 1994 - REVISED SEPTEMBER 1997 MECHANICAL DATA SL002 2-pin plastic single-in-line package This single-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions. Leads require no additional cleaning or processing when used in soldered assembly. SL002 10,2 (0.400) MAX 4,57 (0.180) MAX 6,60 (0.260) 6,10 (0.240) 8,31 (0.327) MAX Index Dot 12,9 (0.492) MAX 4,267 (0.168) MIN 0,711 (0.028) 0,559 (0.022) 2 Places 1 2 1,500 (0.059) MAX 2 Places 5,08 (0.200) T.P. (see Note A) 0,356 (0.014) 0,203 (0.008) 2 Places ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position. B. Body molding flash of up to 0,15 (0.006) may occur in the package lead plane. PRODUCT 10 INFORMATION MDXXAC TISP4072F3, TISP4082F3 SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS MARCH 1994 - REVISED SEPTEMBER 1997 MECHANICAL DATA D008 tape dimensions D008 Package (8 pin SOIC) Single-Sprocket Tape 4,10 3,90 8,05 7,95 1,60 1,50 2,05 1,95 0,40 0,8 MIN. 5,55 5,45 6,50 6,30 Direction of Feed Embossment Cover 0 MIN. ø 1,5 MIN. Carrier Tape 12,30 11,70 Tape 2,2 2,0 ALL LINEAR DIMENSIONS IN MILLIMETERS NOTES: A. Taped devices are supplied on a reel of the following dimensions:Reel diameter: Reel hub diameter: Reel axial hole: MDXXAT 330 +0,0/-4,0 mm 100 ±2,0 mm 13,0 ±0,2 mm B. 2500 devices are on a reel. PRODUCT INFORMATION 11 TISP4072F3, TISP4082F3 SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS MARCH 1994 - REVISED SEPTEMBER 1997 IMPORTANT NOTICE Power Innovations Limited (PI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to verify, before placing orders, that the information being relied on is current. PI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with PI's standard warranty. Testing and other quality control techniques are utilized to the extent PI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except as mandated by government requirements. PI accepts no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor is any license, either express or implied, granted under any patent right, copyright, design right, or other intellectual property right of PI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. PI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS. Copyright © 1997, Power Innovations Limited PRODUCT 12 INFORMATION