SN74LVC1G126-Q1
SCES467D – JULY 2003 – REVISED AUGUST 2020
SN74LVC1G126-Q1 Single Bus Buffer Gate With 3-State Output
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
Supports 5-V VCC operation
Inputs accept voltages to 5.5 V
Provides down translation to VCC
Low power consumption, 10-μA Max ICC
±24-mA Output drive at 3.3 V
Ioff Supports live insertion, partial-power-down
mode, and back drive protection
Latch-up performance exceeds 100 mA
Per JESD 78, Class II
•
•
Cable modem termination systems
High-speed data acquisition and generation
Motor controls: high-voltage
Power line communication modems
SSDs: Internal or external
Video broadcasting and infrastructure: scalable
platforms
Video broadcasting: IP-based multi-format
transcoders
Video communication systems
3 Description
The SN74LVC1G126-Q1 device is a single line driver
with 3-state output. The output is disabled when the
output-enable input is low.
Device Information
PART NUMBER
PACKAGE (PIN)(1)
BODY SIZE
1P1G126QDBVRQ1
SOT-23 (5)
2.90 mm × 1.60 mm
1P1G126QDRYRQ1
SON (6)
1.00 mm × 1.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
1
OE
2
4
A
Y
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................7
6.7 Operating Characteristics........................................... 7
6.8 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................12
11 Layout........................................................................... 12
11.1 Layout Guidelines................................................... 12
11.2 Layout Example...................................................... 12
12 Device and Documentation Support..........................13
12.1 Receiving Notification of Documentation Updates..13
12.2 Support Resources................................................. 13
12.3 Trademarks............................................................. 13
12.4 Electrostatic Discharge Caution..............................13
12.5 Glossary..................................................................13
13 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
Changes from Revision C (April 2019) to Revision D (August 2020)
Page
• Corrected values in features list......................................................................................................................... 1
• Updated the numbering format for tables, figures and cross-references throughout the document...................1
• Updated Description and Device Information table............................................................................................ 1
• Deleted incorrect history tags from revision C: Changed 1.65-V to 3.6-V VCC to 1.65-V to 5-V VCC operation
and Changed MAX operating temperature to 125°C in Recommended Operating Conditions table................. 2
• Changed ESD ratings table to automotive format.............................................................................................. 4
• Corrected IOH and IOL MAX values in Recommended Operating Conditions table ........................................... 5
• Corrected Electrical Characteristics table...........................................................................................................6
• Removed Switching Characteristics, CL = 15 pF and Switching Characteristics, –40°C to 85°C tables........... 7
• Corrected MAX Switching Characteristics values...............................................................................................7
• Removed unneeded columns in Operating Characteristics table.......................................................................7
• Removed first image and unused rows in table in Parameter Measurement Information section......................8
• Updated Feature Description section ................................................................................................................ 9
• Fixed cross references in Detailed Design Procedure section..........................................................................11
Changes from Revision B (April 2008) to Revision C (April 2019)
Page
• Updated document to new TI data sheet format, removed Ordering Information table, and added Applications
list and Device Information table.........................................................................................................................1
• Added DRY package ......................................................................................................................................... 3
• Added ESD ratings table.................................................................................................................................... 4
• Added Thermal Information table ...................................................................................................................... 5
• Added Feature Description section ....................................................................................................................9
• Added Device Functional Modes section .........................................................................................................10
• Added Application and Implementation section ............................................................................................... 11
• Added Power Supply Recommendations and Layout sections ....................................................................... 12
• Added Device and Documentation Support section and Mechanical, Packaging, and Orderable Information
section.............................................................................................................................................................. 13
2
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5 Pin Configuration and Functions
OE
1
A
5
VCC
2
GND
3
4
OE
1
6
A
2
5
N.C.
GND
3
4
Y
VCC
N.C. is no connection
See all mechanical drawings at the end of this data sheet for
package dimensions.
Y
Figure 5-1. DBV Package 5-Pin SOT-23 Top View
Figure 5-2. DRY Package 6-Pin SON Transparent
Top View
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
DBV
(SOT-23)
DRY
(SON)
A
2
2
I
GND
3
3
—
Ground Pin
NC
—
5
—
No connection
OE
1
1
I
VCC
5
6
—
Power Pin
Y
4
4
O
Y Output
NAME
A Input
OE Enable/Input
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
V
range(2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
VI
Input voltage
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
state(2) (3)
UNIT
VO
Voltage range applied to any output in the high or low
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature range
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
PARAMETER
V(ESD)
(1)
4
Electrostatic
discharge
DEFINITION
Human body model (HBM), per AEC
Q100-002(1)
Charged device model (CDM), per AEC Q100-011
VALUE
±2000
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Operating
Supply voltage
Data retention only
1.65
5.5
VCC = 3 V to 3.6 V
V
2
0.7 × VCC
VCC = 1.65 V to 1.95 V
Low-level input voltage
VI
Input voltage
VO
Output voltage
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
0.3 × VCC
5.5
V
0
VCC
V
–4
VCC = 2.3 V
High-level output current
–8
–16
VCC = 3 V
Low-level output current
Δt/Δv
–24
VCC = 1.65 V
4
VCC = 2.3 V
8
16
VCC = 3 V
Input transition rise or fall rate
(1)
mA
24
VCC = 4.5 V
24
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
mA
–24
VCC = 4.5 V
IOL
V
0
VCC = 1.65 V
IOH
V
1.7
VCC = 4.5 V to 5.5 V
VIL
UNIT
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
MAX
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
ns/V
5
Operating free-air temperature
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
SN74LVC1G126-Q1
THERMAL
METRIC(1)
DBV
DRY
5 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
240.9
279.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
165.8
182.7
°C/W
RθJB
Junction-to-board thermal resistance
143.2
154.5
°C/W
ψJT
Junction-to-top characterization parameter
84.4
31.3
°C/W
ψJB
Junction-to-board characterization parameter
142.5
153.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
–
–
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
VOH
1.65 V to 5.5 V
1.65 V
1.2
2.3 V
1.9
IOH = –16 mA
3V
2.4
3V
2.3
4.5 V
3.8
V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
IOL = 16 mA
3V
0.4
3V
0.55
4.5 V
0.55
VI = 5.5 V or GND
UNIT
V
0 to 5.5 V
±5
μA
Ioff
VI or VO = 5.5 V
0
±10
μA
IOZ
VO = 0 to 5.5 V
3.6 V
10
μA
ICC
VI = 5.5 V or GND
1.65 V to 5.5 V
10
μA
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
3 V to 5.5 V
500
μA
Ci
VI = VCC or GND
(1)
6
MAX
1.65 V to 5.5 V
IOL = 24 mA
A or OE inputs
TYP(1)
VCC – 0.1
IOH = –8 mA
IOL = 100 μA
II
MIN
IOH = –4 mA
IOH = –24 mA
VOL
VCC
IO = 0
3.3 V
4
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
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6.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 7-1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
tdis
PARAMETER
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
Y
1
5.8
1
4.5
ns
OE
Y
1.2
5.8
1
5
ns
OE
Y
1
6
1
4.2
ns
6.7 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Outputs enabled
Power dissipation capacitance
VCC = 3.3 V
VCC = 5 V
TYP
TYP
19
21
3
4
f = 10 MHz
Outputs disabled
UNIT
pF
6.8 Typical Characteristics
14
10
12
VCC = 3 V,
TA = 25°C
tpd – Propagation Delay Time – ns
tpd – Propagation Delay Time – ns
VCC = 3 V,
TA = 25°C
One Output Switching
10
8
6
4
2
One Output Switching
8
6
4
2
0
50
100
150
200
250
300
0
50
CL – Load Capacitance – pF
Figure 6-1. Propagation Delay (Low to High
Transition)
vs Load Capacitance
100
150
200
250
300
CL – Load Capacitance – pF
Figure 6-2. Propagation Delay (High to Low
Transition)
vs Load Capacitance
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
3V
VCC
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
1.5 V
VCC/2
6V
2 × VCC
50 pF
50 pF
500 Ω
500 Ω
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SN74LVC1G126-Q1 device contains a dual buffer gate with output enable control and performs the Boolean
function Y = A.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
8.2 Functional Block Diagram
1
OE
2
4
A
Y
8.3 Feature Description
8.3.1 Balanced CMOS 3-State Outputs
This device includes balanced CMOS 3-State outputs. The three states that these outputs can be in are driving
high, driving low, and high impedance. The term "balanced" indicates that the device can sink and source similar
currents. The drive capability of this device may create fast edges into light loads so routing and load conditions
should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger
currents than the device can sustain without being damaged. It is important for the output power of the device
to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute
Maximum Ratings must be followed at all times.
When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected
to the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor
can be connected to the output to provide a known voltage at the output while it is in the high-impedance state.
The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption
limitations. Typically, a 10 kΩ resistor can be used to meet these requirements.
Unused 3-state CMOS outputs should be left disconnected.
8.3.2 Partial Power Down (Ioff)
This device includes circuitry to disable all outputs when the supply pin is held at 0 V. When disabled, the
outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage
current at each output is defined by the Ioff specification in the Electrical Characteristics table.
8.3.3 Standard CMOS Inputs
This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically
modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst
case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the
maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined
by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this
specification will result in excessive power consumption and could cause oscillations. More details can be found
in Implications of Slow or Floating CMOS Inputs.
Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated
at VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down resistor can
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be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors,
however a 10-kΩ resistor is recommended and will typically meet all requirements.
8.3.4 Clamp Diode Structure
The inputs and outputs to this device have negative clamping diodes only as depicted in Figure 8-1.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
VCC
Device
Logic
Input
Output
-IIK
-IOK
GND
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 8-1. Function Table
INPUTS
10
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G126-Q1 device is a high-drive CMOS device that can be used as an output enabled buffer with
a high output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V, making it ideal
for driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5-V tolerant
allowing it to translate down to VCC.
9.2 Typical Application
Figure 9-1. Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. Outputs can be combined to
produce higher drive but the high drive will also create faster edges into light loads, so routing and load
conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
• For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
• For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
• Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
• Load currents should not exceed 50 mA per output and 100 mA total for the part.
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9.2.3 Application Curves
10
VCC
VCC
VCC
VCC
9
8
1.8 V
2.5 V
3.3 V
5V
ICC (mA)
7
6
5
4
3
2
1
0
0
20
40
Frequency (MHz)
60
80
D003
Figure 9-2. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a
single supply, a 0.1-μF capacitor is recommended. If there are multiple VCC terminals, then 0.01-μF or 0.022-μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Recommended Operating Conditions are rules that must be observed under all circumstances. All
unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The
logic level that should be applied to any particular unused input depends on the function of the device. Generally
they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float
outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs
section of the part when asserted. This will not disable the input section of the I/Os so they also cannot float
when disabled.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 11-1. Layout Diagram
12
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G126-Q1
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
1P1G126QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C26O
1P1G126QDRYRQ1
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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