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SN74CB3Q3305
SCDS141C – OCTOBER 2003 – REVISED NOVEMBER 2015
SN74CB3Q3305 Dual FET Bus Switch
2.5-V/3.3-V Low-Voltage High-Bandwidth Bus Switch
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
(1)
3 Description
(1)
High-Bandwidth Data Path (Up to 500 MHz )
5-V Tolerant I/Os With Device Powered Up or
Powered Down
Low and Flat ON-State Resistance (ron)
Characteristics Over Operating Range
(ron = 3 Ω Typical)
Rail-to-Rail Switching on Data I/O Ports
– 0- to 5-V Switching With 3.3-V VCC
– 0- to 3.3-V Switching With 2.5-V VCC
Bidirectional Data Flow With Near-Zero
Propagation Delay
Low Input/Output Capacitance Minimizes Loading
and Signal Distortion
(Cio(OFF) = 3.5 pF Typical)
Fast Switching Frequency (fOE = 20 MHz
Maximum)
Data and Control Inputs Provide Undershoot
Clamp Diodes
Low Power Consumption (ICC= 0.25 mA Typical)
VCC Operating Range From 2.3 V to 3.6 V
Data I/Os Support 0- to 5-V Signaling Levels (0.8
V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
For additional information regarding the performance
characteristics of the CB3Q family, refer to the TI application
report, CBT-C, CB3T, and CB3Q Signal-Switch Families,
SCDA008.
The SN74CB3Q3305 device is a high-bandwidth FET
bus switch using a charge pump to elevate the gate
voltage of the pass transistor, providing a low and flat
ON-state resistance (ron). The low and flat ON-state
resistance allows for minimal propagation delay and
supports rail-to-rail switching on the data input/output
(I/O) ports. The device also features low data I/O
capacitance to minimize capacitive loading and signal
distortion on the data bus. Specifically designed to
support
high-bandwidth
applications,
the
SN74CB3Q3305 device provides an optimized
interface solution ideally suited for broadband
communications, networking, and data-intensive
computing systems.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry prevents
damaging current backflow through the device when
it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up
or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
Device Information(1)
PART NUMBER
SN74CB3Q3305
PACKAGE
2.00 mm × 3.10 mm
TSSOP (8)
3.00 mm × 6.10 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic, Each FET Switch (SW)
B
A
2 Applications
•
•
•
•
•
•
•
IP Phones: Wired and Wireless
Optical Modules
Optical Networking: Video Over Fiber and EPON
Private Branch Exchange (PBX)
WiMAX and Wireless Infrastructure Equipment
USB, Differential Signal interface
Bus isolation
BODY SIZE (NOM)
VSSOP (8)
VCC
Charge
Pump
EN(1)
(1) EN is the internal enable signal applied to the switch.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74CB3Q3305
SCDS141C – OCTOBER 2003 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
4
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application ................................................... 9
10 Power Supply Recommendations ..................... 10
11 Layout................................................................... 10
11.1 Layout Guidelines ................................................. 10
11.2 Layout Example .................................................... 10
12 Device and Documentation Support ................. 11
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
11
11
11
11
11
13 Mechanical, Packaging, and Orderable
Information ........................................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (October 2009) to Revision C
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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5 Pin Configuration and Functions
PW Package
8-Pin TSSOP
Top View
1OE
1A
1B
GND
1
8
2
7
3
6
4
5
DCU Package
8-Pin VSSOP
Top View
VCC
2OE
2B
2A
1OE
1
8
VCC
1A
2
7
2OE
1B
3
6
2B
GND
4
5
2A
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1A
2
I/O
Channel 1 A port
1B
3
I/O
Channel 1 B port
1OE
1
I
2A
5
I/O
Channel 2 A port
2B
6
I/O
Channel 2 B port
2OE
7
I
GND
4
—
Ground
Vcc
8
—
Power supply
Output Enable for switch 1
Output Enable for switch 2
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
4.6
V
VIN
Control input voltage (2) (3)
–0.5
7
V
VI/O
Switch I/O voltage (2) (3) (4)
–0.5
7
V
IIK
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port clamp current
VI/O < 0
–50
mA
II/O
ON-state switch current (5)
±64
mA
Continuous current through VCC or GND
±100
mA
θJA
Package thermal impedance
Tj
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(5)
(6)
(6)
–65
88
°C/W
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
The package thermal impedance is calculated in accordance with JESD 51-7.
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6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions (1)
VCC
Supply voltage
MIN
MAX
2.3
3.6
VIH
High-level control input
voltage
VCC = 2.3 V to 2.7 V
VIL
Low-level control input
voltage
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
VI/O
Data input/output voltage
TA
Operating free-air temperature
(1)
1.7
VCC = 2.7 V to 3.6 V
2
UNIT
V
V
V
0
5.5
V
–40
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
6.4 Thermal Information
THERMAL METRIC (1)
SN74CB3Q3305
SN74CB3Q3305
DCU (VSSOP)
PW (TSSOP)
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
183
190.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
64.2
74.0
°C/W
RθJB
Junction-to-board thermal resistance
62.5
119.4
°C/W
ψJT
Junction-to-top characterization parameter
4.3
120.0
°C/W
ψJB
Junction-to-board characterization parameter
62.1
117.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
VIK
TEST CONDITIONS
MIN
VCC = 3.6 V,
II = –18 mA
VCC = 3.6 V,
VIN = 0 to 5.5 V
IOZ (3)
VCC = 3.6 V,
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC or GND
Ioff
VCC = 0,
VO = 0 to 5.5 V,
VI = 0
ICC
VCC = 3.6 V,
II/O = 0,
Switch ON or OFF,
VIN = VCC or GND
Control
inputs
IIN
ΔICC (4)
Control
inputs
ICCD (5)
A and B ports open,
Per control VCC = 3.6 V,
input
Control input switching at 50% duty cycle
(1)
(2)
(3)
(4)
(5)
4
TYP (2)
0.25
VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND
0.040
MAX
UNIT
–1.8
V
±1
µA
±1
µA
1
µA
0.7
mA
25
µA
0.045
mA/
MHz
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see
Figure 5).
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
Control
inputs
Cin
TEST CONDITIONS
MIN
TYP (2)
MAX
2.5
3.5
pF
UNIT
VCC = 3.3 V,
VIN = 5.5 V, 3.3 V, or 0
Cio(OFF)
VCC = 3.3 V,
Switch OFF,
VIN = VCC or GND,
VI/O = 5.5 V, 3.3 V, or 0
3.5
5
pF
Cio(ON)
VCC = 3.3 V,
Switch ON,
VIN = VCC or GND,
VI/O = 5.5 V, 3.3 V, or 0
8
10.5
pF
3
8
3.5
9
3
6
3.5
8
VCC = 2.3 V,
TYP at VCC = 2.5 V
ron (6)
VI = 1.7 V, IO = –15 mA
VI = 0, IO = 30 mA
VCC = 3 V
(6)
VI = 0, IO = 30 mA
VI = 2.4 V, IO = –15 mA
Ω
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
FROM
(INPUT)
TO
(OUTPUT)
fOE (1)
OE
A or B
tpd (2)
A or B
B or A
ten
OE
A or B
tdis
OE
A or B
PARAMETER
(1)
(2)
VCC
MIN
MAX
VCC = 2.5 V ± 0.2 V
10
VCC = 3.3 V ± 0.3 V
20
VCC = 2.5 V ± 0.2 V
0.09
VCC = 3.3 V ± 0.3 V
0.15
VCC = 2.5 V ± 0.2 V
1
5
VCC = 3.3 V ± 0.3 V
1
4.5
VCC = 2.5 V ± 0.2 V
1
4.5
VCC = 3.3 V ± 0.3 V
1
5
UNIT
MHz
ns
ns
ns
Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0).
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
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6.7 Typical Characteristics
ron – ON-State Resistance – Ω
16
14
12
VCC = 3.3 V
TA = 25°C
IO = –15 mA
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VI – V
Figure 1. Typical ron vs VI
6
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7 Parameter Measurement Information
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
2 × VCC
Input Generator
VI
S1
RL
VO
50 Ω
50 Ω
VG2
RL
CL
(see Note A)
TEST
VCC
S1
RL
VI
CL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
VCC or GND
VCC or GND
30 pF
50 pF
tPLZ/tPZL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × VCC
2 × VCC
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
tPHZ/tPZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
GND
GND
500 Ω
500 Ω
VCC
VCC
30 pF
50 pF
0.15 V
0.3 V
V∆
VCC
Output
Control
(VIN)
VCC/2
VCC
VCC/2
VCC/2
0V
tPLH
VOH
Output
VCC/2
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC
VCC/2
VCC/2
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
VOL + V∆
VOL
tPZH
tPHL
VCC/2
0V
tPZL
Output
Control
(VIN)
Open
GND
VOH
VCC/2
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Test Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74CB3Q3305 device is organized as two 1-bit switches with separate output-enable (1OE, 2OE) inputs. It
can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is high, the associated 1-bit bus
switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE
is low, the associated 1-bit bus switch is OFF and a high-impedance state exists between the A and B ports.
8.2 Functional Block Diagram
2
3
1A
1OE
1B
SW
1
5
6
2A
2B
SW
7
2OE
Figure 3. Logic Diagram (Positive Logic)
8.3 Feature Description
The device supports High-Bandwidth data path up to 500 MHz . The I/O ports are 5-V tolerant when powered up
or powered down due to IOFF. The charge pump creates low and flat ON-state resistance characteristics over the
whole operating temperature range.
Rail-to-Rail switching on data I/O ports is 0-V to 5-V with 3.3-V VCC or 0-V to 3.3-V with 2.5-V VCC
The data flow is bidirectional with near-zero propagation delay. Reduced input/output capacitance for higher
speed applications. OE can be toggled at the high speeds of 20 MHz for fast switching applications.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74CB3Q3305.
Table 1. Function Table (Each Bus Switch)
8
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
H
B
A port = B port
L
Z
Disconnect
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74CB3Q3305 can be used as bidirectional switch as shown in the application Figure 4 .The master
operates at 5 V and the slave can accept 5 V. With 3 VCC on the device , the two ports can be connected. OE pin
is used to control the chip from Master controller. This is a very generic example and could apply to many
situations. If an application requires 1 bit, tie the OE to low and the ports A and B side to either high or low (not
shown).
9.2 Typical Application
3V
5V
0.1 PF
1
1OE
2
VCC
8
1A
2OE
7
5
2A
2B
6
4
GND
1B
3
MASTER
5V
SLAVE
SN74CB3Q3305
Figure 4. Typical Application of the SN74CB3Q3305
9.2.1 Design Requirements
1. Recommended Input Conditions:
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions (1) .
– Inputs and outputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Absolute Maximum Conditions:
– I/O currents should not exceed ±64 mA per channel.
– Continuos current through GND or VCC should not exceed ±100 mA.
3. Frequency Selection Criterion:
– Maximum frequency tested is 500 MHz.
– Added trace resistance/capacitance can reduce maximum frequency capability; use layout practices as
directed in Layout.
9.2.2 Detailed Design Procedure
The 0.1-µF capacitor should be placed as close as possible to the device.
(1)
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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Typical Application (continued)
9.2.3 Application Curve
12
VCC = 3.3 V
TA = 25°C
A and B Ports Open
10
I CC – mA
8
6
4
One OE Switching
2
0
0
2
4
6
8
10
12
14
16
18
20
OE Switching Frequency − MHz
Figure 5. Typical ICC vs OE Switching Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Absolute Maximum Ratings table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dualsupply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close
to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight
and therefore some traces must turn corners. Figure 6 shows progressively better techniques of rounding
corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 6. Trace Example
10
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• CBT-C, CB3T, and CB3Q Signal-Switch Families, SCDA008
• Implications of Slow or Floating CMOS Inputs, SCBA004
• Selecting the Right Texas Instruments Signal Switch, SZZA030
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
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Product Folder Links: SN74CB3Q3305
11
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
TBD
Call TI
Call TI
-40 to 85
Device Marking
(4/5)
74CB3Q3305DCURE4
ACTIVE
VSSOP
DCU
8
74CB3Q3305DCURG4
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
GARR
SN74CB3Q3305DCUR
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(GARQ ~ GARR)
SN74CB3Q3305PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU305
SN74CB3Q3305PWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU305
SN74CB3Q3305PWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
BU305
SN74CB3Q3305PWRE4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU305
SN74CB3Q3305PWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU305
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
17-Aug-2015
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Dec-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
74CB3Q3305DCURG4
VSSOP
DCU
8
3000
180.0
SN74CB3Q3305DCUR
VSSOP
DCU
8
3000
SN74CB3Q3305PWR
TSSOP
PW
8
2000
SN74CB3Q3305PWR
TSSOP
PW
8
SN74CB3Q3305PWRG4
TSSOP
PW
8
B0
(mm)
K0
(mm)
P1
(mm)
8.4
2.25
3.35
1.05
4.0
180.0
8.4
2.25
3.35
1.05
330.0
12.4
7.0
3.6
1.6
2000
330.0
12.4
7.0
3.6
2000
330.0
12.4
7.0
3.6
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
8.0
Q3
4.0
8.0
Q3
8.0
12.0
Q1
1.6
8.0
12.0
Q1
1.6
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Dec-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74CB3Q3305DCURG4
VSSOP
DCU
8
3000
202.0
201.0
28.0
SN74CB3Q3305DCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
SN74CB3Q3305PWR
TSSOP
PW
8
2000
367.0
367.0
35.0
SN74CB3Q3305PWR
TSSOP
PW
8
2000
364.0
364.0
27.0
SN74CB3Q3305PWRG4
TSSOP
PW
8
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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