SN74CB3Q3305DCUR

SN74CB3Q3305 SCDS141D – OCTOBER 2003 – REVISED SEPTEMBER 2021 SN74CB3Q3305 Dual FET Bus Switch 2.5-V or 3.3-V Low-Voltage High-Bandwidth Bus Switch 1 Features • • • • • • • • • • • • • • 3 Description MHz)1 High-bandwidth data path (up to 500 5-V tolerant I/Os with device powered up or powered down Low and flat ON-state resistance (ron) characteristics over operating range (ron = 3 Ω typical) Supports input voltage beyond supply on data I/O ports – 0 to 5 V switching with 3.3 V VCC – 0 to 3.3 V switching with 2.5 V VCC Bidirectional data flow with near-zero propagation delay Low input or output capacitance minimizes loading and signal distortion (Cio(OFF) = 3.5 pF typical) Fast switching frequency (fOE = 20 MHz maximum) Data and control inputs provide undershoot clamp diodes Low power consumption (ICC = 0.25 mA typical) VCC operating range from 2.3 V to 3.6 V Data I/Os support 0 to 5 V signaling levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V) Control inputs can be driven by TTL or 5 V/3.3 V CMOS outputs Ioff supports partial-power-down mode operation Latch-up performance exceeds 100 mA per JESD 78, Class II 2 Applications • • • • • • • IP phones: wired and wireless Optical modules Optical networking: video over fiber and EPON Private branch exchange (PBX) WiMAX and wireless infrastructure equipment USB, differential signal interface Bus isolation The SN74CB3Q3305 device is a high-bandwidth FET bus switch using a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports switching input voltage beyond the supply on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support highbandwidth applications, the SN74CB3Q3305 device provides an optimized interface solution ideally suited for broadband communications, networking, and dataintensive computing systems. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Device Information(1) PART NUMBER SN74CB3Q3305 (1) PACKAGE BODY SIZE (NOM) VSSOP (8) 2.00 mm × 3.10 mm TSSOP (8) 3.00 mm × 6.10 mm For all available packages, see the orderable addendum at the end of the data sheet. B A VCC Charge Pump EN(1) (1) EN is the internal enable signal applied to the switch. Simplified Schematic, Each FET Switch (SW) 1 For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families, SCDA008. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74CB3Q3305 www.ti.com SCDS141D – OCTOBER 2003 – REVISED SEPTEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions(1) .................... 4 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................5 6.6 Switching Characteristics............................................6 6.7 Typical Characteristics................................................ 6 7 Parameter Measurement Information............................ 7 8 Detailed Description........................................................8 8.1 Overview..................................................................... 8 8.2 Functional Block Diagram........................................... 8 8.3 Feature Description.....................................................8 8.4 Device Functional Modes............................................8 9 Application and Implementation.................................... 9 9.1 Application Information............................................... 9 9.2 Typical Application...................................................... 9 10 Power Supply Recommendations..............................10 11 Layout........................................................................... 10 11.1 Layout Guidelines................................................... 10 11.2 Layout Example...................................................... 10 12 Device and Documentation Support..........................11 12.1 Documentation Support.......................................... 11 12.2 Receiving Notification of Documentation Updates.. 11 12.3 Support Resources................................................. 11 12.4 Trademarks............................................................. 11 12.5 Electrostatic Discharge Caution.............................. 11 12.6 Glossary.................................................................. 11 13 Mechanical, Packaging, and Orderable Information.................................................................... 11 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (October 2015) to Revision D (September 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated data sheet to include inclusive terminology..........................................................................................1 Changes from Revision B (October 2009) to Revision C (October 2015) Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................................................................................................................................................... 1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74CB3Q3305 SN74CB3Q3305 www.ti.com SCDS141D – OCTOBER 2003 – REVISED SEPTEMBER 2021 5 Pin Configuration and Functions 1OE 1A 1B GND 1 8 2 7 3 6 4 5 VCC 2OE 2B 2A 1OE 1 8 VCC 1A 2 7 2OE 1B 3 6 2B GND 4 5 2A Figure 5-2. DCU Package 8-Pin VSSOP Top View Figure 5-1. PW Package 8-Pin TSSOP Top View Table 5-1. Pin Functions PIN NAME NO. TYPE(1) DESCRIPTION 1A 2 I/O Channel 1 A port 1B 3 I/O Channel 1 B port 1OE 1 I 2A 5 I/O Channel 2 A port 2B 6 I/O Channel 2 B port 2OE 7 I Output Enable for switch 2 GND 4 P Ground Vcc 8 P Power supply (1) Output Enable for switch 1 I = input, O = output, I/O = input and output, P = power Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74CB3Q3305 3 SN74CB3Q3305 www.ti.com SCDS141D – OCTOBER 2003 – REVISED SEPTEMBER 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT –0.5 4.6 V VIN Control input voltage(2) (3) –0.5 7 V VI/O Switch I/O voltage(2) (3) (4) –0.5 7 V IIK Control input clamp current VIN < 0 –50 mA II/OK I/O port clamp current VI/O < 0 –50 mA VCC Supply voltage II/O ON-state switch current(5) Continuous current through VCC or GND impedance(6) θJA Package thermal Tj Junction temperature Tstg Storage temperature (1) (2) (3) (4) (5) (6) –65 ±64 mA ±100 mA 88 °C/W 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VI and VO are used to denote specific conditions for VI/O. II and IO are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) UNIT 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) V 1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions(1) MAX 2.3 3.6 Supply voltage VIH High-level control input voltage VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 VIL Low-level control input voltage VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V 0.8 VI/O Data input/output voltage TA Operating free-air temperature (1) 4 MIN VCC UNIT V V V 0 5.5 V –40 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74CB3Q3305 SN74CB3Q3305 www.ti.com SCDS141D – OCTOBER 2003 – REVISED SEPTEMBER 2021 6.4 Thermal Information THERMAL METRIC(1) SN74CB3Q3305 SN74CB3Q3305 DCU (VSSOP) PW (TSSOP) 8 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 183 190.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 64.2 74.0 °C/W RθJB Junction-to-board thermal resistance 62.5 119.4 °C/W ψJT Junction-to-top characterization parameter 4.3 120.0 °C/W ψJB Junction-to-board characterization parameter 62.1 117.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)(1) PARAMETER VIK TEST CONDITIONS VCC = 3.6 V, II = –18 mA VCC = 3.6 V, VIN = 0 to 5.5 V IOZ (3) VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0 VCC = 3.6 V, II/O = 0, Switch ON or OFF, VIN = VCC or GND Control inputs IIN ICC ΔICC (4) Control inputs ICCD (5) A and B ports open, Per control VCC = 3.6 V, input Control input switching at 50% duty cycle Cin Control inputs MIN TYP(2) 0.25 VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND MAX UNIT –1.8 V ±1 µA ±1 µA 1 µA 0.7 mA 25 µA mA/ MHz 0.040 0.045 2.5 3.5 pF VCC = 3.3 V, VIN = 5.5 V, 3.3 V, or 0 Cio(OFF) VCC = 3.3 V, Switch OFF, VIN = VCC or GND, VI/O = 5.5 V, 3.3 V, or 0 3.5 5 pF Cio(ON) VCC = 3.3 V, Switch ON, VIN = VCC or GND, VI/O = 5.5 V, 3.3 V, or 0 8 10.5 pF 3 8 3.5 9 3 6 3.5 8 ron (6) VCC = 2.3 V, TYP at VCC = 2.5 V VCC = 3 V (1) (2) (3) (4) (5) (6) VI = 0, IO = 30 mA VI = 1.7 V, IO = –15 mA VI = 0, IO = 30 mA VI = 2.4 V, IO = –15 mA Ω VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure 9-2). Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74CB3Q3305 5 SN74CB3Q3305 www.ti.com SCDS141D – OCTOBER 2003 – REVISED SEPTEMBER 2021 6.6 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1) FROM (INPUT) TO (OUTPUT) OE A or B A or B B or A ten OE A or B tdis OE A or B PARAMETER fOE (1) tpd (2) (1) (2) VCC MIN MAX VCC = 2.5 V ± 0.2 V 10 VCC = 3.3 V ± 0.3 V 20 VCC = 2.5 V ± 0.2 V 0.09 VCC = 3.3 V ± 0.3 V 0.15 VCC = 2.5 V ± 0.2 V 1 5 VCC = 3.3 V ± 0.3 V 1 4.5 VCC = 2.5 V ± 0.2 V 1 4.5 VCC = 3.3 V ± 0.3 V 1 5 UNIT MHz ns ns ns Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0). The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 6.7 Typical Characteristics ron – ON-State Resistance – Ω 16 14 12 VCC = 3.3 V TA = 25°C IO = –15 mA 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VI – V Figure 6-1. Typical ron vs VI 6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74CB3Q3305 SN74CB3Q3305 www.ti.com SCDS141D – OCTOBER 2003 – REVISED SEPTEMBER 2021 7 Parameter Measurement Information VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VCC Input Generator VI S1 RL VO 50 Ω 50 Ω VG2 RL CL (see Note A) TEST VCC S1 RL VI CL tpd(s) 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω VCC or GND VCC or GND 30 pF 50 pF tPLZ/tPZL 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2 × VCC 2 × VCC 500 Ω 500 Ω GND GND 30 pF 50 pF 0.15 V 0.3 V tPHZ/tPZH 2.5 V ± 0.2 V 3.3 V ± 0.3 V GND GND 500 Ω 500 Ω VCC VCC 30 pF 50 pF 0.15 V 0.3 V V∆ VCC Output Control (VIN) VCC/2 VCC/2 0V tPZL Output Control (VIN) VCC VCC/2 VCC/2 0V tPLH tPHL VCC/2 Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ VCC VCC/2 tPZH VOH Output Open GND VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) VOL + V∆ VOL tPHZ VOH VCC/2 VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 7-1. Test Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74CB3Q3305 7 SN74CB3Q3305 www.ti.com SCDS141D – OCTOBER 2003 – REVISED SEPTEMBER 2021 8 Detailed Description 8.1 Overview The SN74CB3Q3305 device is organized as two 1-bit switches with separate output-enable (1OE and 2OE) inputs. It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is high, the associated 1-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is low, the associated 1-bit bus switch is OFF and a high-impedance state exists between the A and B ports. 8.2 Functional Block Diagram 2 3 1A 1B SW 1 1OE 5 6 2A 2B SW 7 2OE Figure 8-1. Logic Diagram (Positive Logic) 8.3 Feature Description The device supports High-Bandwidth data path up to 500 MHz. The I/O ports are 5 V tolerant when powered up or powered down due to IOFF. The charge pump creates low and flat ON-state resistance characteristics over the whole operating temperature range. Switching input voltage beyond the supply is supported on data I/O ports: 0 V to 5 V with 3.3 V VCC or 0 V to 3.3 V with 2.5 V VCC. The data flow is bidirectional with near-zero propagation delay. Reduced input/output capacitance for higher speed applications. OE can be toggled at the high speeds of 20 MHz for fast switching applications. 8.4 Device Functional Modes Table 8-1 lists the functional modes of the SN74CB3Q3305. Table 8-1. Function Table (Each Bus Switch) 8 INPUT OE INPUT/OUTPUT A FUNCTION H B A port = B port L Z Disconnect Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74CB3Q3305 SN74CB3Q3305 www.ti.com SCDS141D – OCTOBER 2003 – REVISED SEPTEMBER 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information Figure 9-1 shows that the SN74CB3Q3305 can be used as bidirectional switch. The controller operates at 5 V and the peripheral can accept 5 V. Even with a VCC of 3 V on the SN74CB3Q3305, the two ports can be connected to pass the 5 V signal. The controller uses the OE pin control the switch. This is a very generic example and could apply to many situations. For applications that require only 1 bit (for example, one channel), tie the unused OE low and tie the unused ports A and B to either high or low (not shown). 9.2 Typical Application 3V 5V 0.1 F VCC 8 1A 2OE 7 5 2A 2B 6 4 GND 1B 3 1 1OE 2 5V CONTROLLER PERIPHERAL SN74CB3Q3305 Figure 9-1. Typical Application of the SN74CB3Q3305 9.2.1 Design Requirements 1. Recommended Input Conditions: • For specified high and low levels, see VIH and VIL in Section 6.3. • Inputs and outputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC. 2. Absolute Maximum Conditions: • I/O currents should not exceed ±64 mA per channel. • Continuos current through GND or VCC should not exceed ±100 mA. 3. Frequency Selection Criterion: • Maximum frequency tested is 500 MHz. • Added trace resistance/capacitance can reduce maximum frequency capability; use layout practices as directed in Section 11. 9.2.2 Detailed Design Procedure The 0.1 µF capacitor should be placed as close as possible to the device. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74CB3Q3305 9 SN74CB3Q3305 www.ti.com SCDS141D – OCTOBER 2003 – REVISED SEPTEMBER 2021 9.2.3 Application Curve 12 VCC = 3.3 V TA = 25°C A and B Ports Open 10 I CC – mA 8 6 4 One OE Switching 2 0 0 2 4 6 8 10 12 14 16 18 20 OE Switching Frequency − MHz Figure 9-2. Typical ICC vs OE Switching Frequency 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating listed in Section 6.1 table. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1 μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01 μF or 0.022 μF capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual-supply pins operating at different voltages, for example VCC and VDD, a 0.1 µF bypass capacitor is recommended for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 11 Layout 11.1 Layout Guidelines Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 11-1 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections. 11.2 Layout Example BETTER BEST 2W WORST 1W min. W Figure 11-1. Trace Example 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74CB3Q3305 SN74CB3Q3305 www.ti.com SCDS141D – OCTOBER 2003 – REVISED SEPTEMBER 2021 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • Texas Instruments, CBT-C, CB3T, and CB3Q Signal-Switch Families application report • Texas Instruments, Implications of Slow or Floating CMOS Inputs application report • Texas Instruments, Selecting the Right Texas Instruments Signal Switch application report 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74CB3Q3305 11 PACKAGE OPTION ADDENDUM www.ti.com 15-Jun-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 74CB3Q3305DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 GARR SN74CB3Q3305DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (GARQ, GARR) SN74CB3Q3305PW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 BU305 SN74CB3Q3305PWG4 ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 BU305 SN74CB3Q3305PWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 BU305 SN74CB3Q3305PWRE4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 BU305 SN74CB3Q3305PWRG4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 BU305 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of