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SN74CB3T3306
SCDS119C – JANUARY 2003 – REVISED DECEMBER 2015
SN74CB3T3306 Dual FET Bus Switch 2.5-V/3.3-V Low-Voltage Bus Switch
With 5-V Tolerant Level Shifter
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Output Voltage Translation Tracks VCC
Supports Mixed-Mode Signal Operation on All
Data I/O Ports
– 5-V Input Down to 3.3-V Output Level Shift
With 3.3-V VCC
– 5-V/3.3-V Input Down to 2.5-V Output Level
Shift With 2.5-V VCC
5-V Tolerant I/Os With Device Powered Up or
Powered Down
Bidirectional Data Flow With Near-Zero
Propagation Delay
Low ON-State Resistance (ron) Characteristics (ron
= 5 Ω Typical)
Low Input/Output Capacitance Minimizes Loading
(Cio(OFF) = 4.5 pF Typical)
Data and Control Inputs Provide Undershoot
Clamp Diodes
Low Power Consumption (ICC = 20 μA Maximum)
VCC Operating Range From 2.3 V to 3.6 V
Data I/Os Support 0- to 5-V Signaling Levels (0.8
V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
Control Inputs Can Be Driven by TTL or 5-V/3.3-V
CMOS Outputs
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Performance Tested Per JESD 22
– 2000-V Human Body Model (A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Supports Digital Applications:
– Level Translation
– USB Interface
– Bus Isolation
Ideal for Low-Power Portable Equipment
Supports Digital Applications:
– Level Translation
– PCI Interface
– USB Interface
– Memory Interleaving
– Bus Isolation
3 Description
The SN74CB3T3306 device is a high-speed TTLcompatible FET bus switch with low ON-state
resistance (ron), allowing for minimal propagation
delay. The device fully supports mixed-mode signal
operation on all data I/O ports by providing voltage
translation that tracks VCC. The SN74CB3T3306
device supports systems using 5-V TTL, 3.3-V
LVTTL, and 2.5-V CMOS switching standards, as well
as user-defined switching levels (see Figure 5).
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74CB3T3306DCT
SSOP (8)
2.95 mm × 2.80 mm
SN74CB3T3306DCU
VSSOP (8)
2.30 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
B
A
VG(1)
Control
Circuit
EN(2)
(1) Gate voltage (VG) is approximately equal to VCC + VT when the switch is ON
and VI > VCC + VT.
(2) EN is the internal enable signal applied to the switch.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74CB3T3306
SCDS119C – JANUARY 2003 – REVISED DECEMBER 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagrams ....................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 12
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 2012) to Revision C
•
2
Page
Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table,
Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................................... 1
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5 Pin Configuration and Functions
DCT or DCU Package
8-Pin SSOP or VSSOP
Top View
1OE
1A
1B
GND
1
8
2
7
3
6
4
5
VCC
2OE
2B
2A
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1OE
1
I
1A
2
I/O
Active-low enable for switch 1
Switch 1 A terminal
1B
3
I/O
Switch 1 B terminal
GND
4
—
Ground
2A
5
I/O
Switch 2 A terminal
2B
6
I/O
Switch 2 B terminal
2OE
7
I
VCC
8
—
Active-low enable for switch 1
Supply voltage pin
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.5
7
V
VIN
Control input voltage
(2) (3)
–0.5
7
V
VI/O
Switch I/O voltage (2) (3) (4)
–0.5
7
V
IIK
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port clamp current
VI/O < 0
–50
mA
II/O
ON-state switch current (5)
±128
mA
Continuous current through VCC or GND
±100
mA
150
°C
150
°C
Supply voltage (2)
VCC
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(5)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
+2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
+1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
VIH
VIL
Supply voltage
High-level control input voltage
Low-level control input voltage
VI/O
Data input and output voltage
TA
Operating free-air temperature
(1)
4
MIN
MAX
UNIT
2.3
3.6
VCC = 2.3 V to
2.7 V
V
1.7
5.5
VCC = 2.7 V to
3.6 V
2
5.5
VCC = 2.3 V to
2.7 V
0
0.7
VCC = 2.7 V to
3.6 V
0
0.8
0
5.5
V
–40
85
°C
V
V
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74CB3T3306
THERMAL METRIC (1)
DCT (SSOP)
DCU (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
182.6
209.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
113.2
75.5
°C/W
RθJB
Junction-to-board thermal resistance
95.1
88.9
°C/W
ψJT
Junction-to-top characterization parameter
39.2
6.4
°C/W
ψJB
Junction-to-board characterization parameter
94.1
88.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
VIK
TEST CONDITIONS
MIN
TYP (2) MAX
VCC = 3 V, II = –18 mA
(see Figure 9 and Figure 1)
VOH
IIN
Control inputs
VCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND
Ioff
VCC = 0, VO = 0 to 5.5 V, VI = 0
VI = 0 to 0.7 V
Control inputs
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
Cin
Control inputs
VCC = 3.3 V, VIN = VCC or GND
µA
–40
VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND
ΔICC (4)
±10
VI = 0.7 V to VCC – 0.7 V
IOZ (3)
VCC = 3.6 V, II/O = 0,
Switch ON or OFF, VIN = VCC or GND
V
±20
VCC = 3.6 V, Switch ON,
VIN = VCC or GND
ICC
–1.2
VI = VCC – 0.7 V to 5.5 V
II
±5
µA
10
µA
VI = VCC or GND
20
VI = 5.5 V
20
300
µA
pF
4.5
pF
Cio(ON)
VCC = 3.3 V, Switch ON,
VIN = VCC or GND
VI/O = 5.5 V or 3.3 V
VI/O = GND
15
VCC = 2.3 V, TYP at VCC = 2.5 V,
VI = 0
IO = 24 mA
5
8
IO = 16 mA
5
8
IO = 64 mA
5
7
IO = 32 mA
5
7
(1)
(2)
(3)
(4)
(5)
µA
3
Cio(OFF)
VCC = 3 V, VI = 0
µA
±10
VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF,
VIN = VCC or GND
ron (5)
UNIT
4
pF
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
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6.6 Switching Characteristics
over recommended operating free-air temperature range unless otherwise noted (see Figure 4)
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
ten
OE
A or B
tdis
OE
A or B
PARAMETER
tpd (1)
TEST CONDITIONS
MIN
MAX
UNIT
VCC = 2.5 V ± 0.2 V
0.15
ns
VCC = 3.3 V
± 0.3 V
0.25
ns
VCC = 2.5 V ± 0.2 V
1
8.5
ns
VCC = 3.3 V
± 0.3 V
1
6.5
ns
1
9
ns
VCC = 2.5 V ± 0.2 V
(1)
VCC = 3.3 V
± 0.3 V
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
6.7 Typical Characteristics
3.5
4.0
VCC = 2.3 V ~ 3.6 V
VI = 5.5 V
TA = 85°C
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VOH - Output Voltage High - V
VOH - Output Voltage High - V
4.0
3.5
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = 25°C
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
2.5
VCC - Supply Voltage - V
Figure 1. VOH vs Supply Voltage
2.7
2.9
3.1
3.3
3.5
3.7
VCC - Supply Voltage - V
Figure 2. VOH vs Supply Voltage
V
- Output Voltage High - V
OH
4.0
3.5
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = -40°C
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VCC - Supply Voltage - V
Figure 3. VOH vs Supply Voltage
6
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7 Parameter Measurement Information
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
2 × VCC
Input Generator
VI
S1
RL
VO
50 Ω
50 Ω
VG2
RL
CL
(see Note A)
TEST
VCC
S1
RL
VI
CL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V or GND
5.5 V or GND
30 pF
50 pF
tPLZ/tPZL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × VCC
2 × VCC
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
tPHZ/tPZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V
5.5 V
30 pF
50 pF
0.15 V
0.3 V
V∆
VCC
Output
Control
(VIN)
VCC/2
VCC
VCC/2
VCC/2
0V
tPLH
VOH
Output
VCC/2
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC
VCC/2
VCC/2
VOL
tPHZ
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
VOL + V∆
VOL
tPZH
tPHL
VCC/2
0V
tPZL
Output
Control
(VIN)
Open
GND
VOH
VCC/2
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Test Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74CB3T3306 device is organized as two 1-bit bus switches with separate ouput-enable (1OE, 2OE)
inputs. It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit
bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B
ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging
current will not backflow through the device when it is powered down. The SN74CB3T3306 device has isolation
during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Figure 5. Typical DC Voltage-Translation Characteristics
8
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8.2 Functional Block Diagrams
2
1A
1OE
3
1B
SW
1
5
2A
6
SW
2B
7
2OE
Figure 6. Functional Block Diagram, SN74CB3T3306
B
A
VG(1)
Control
Circuit
EN(2)
(1) Gate voltage (VG) is approximately equal to VCC + VT when the switch is ON
and VI > VCC + VT.
(2) EN is the internal enable signal applied to the switch.
Figure 7. Simplified Schematic, Each FET Switch (SW)
8.3 Feature Description
The SN74CB3T3306 is ideal for low-power portable equipment. Power consumption is low by design, ICC =
20 μA, On-state resistance is low (ron = 5 Ω) It has bidirectional data flow with near zero propagation delay. The
devices minimizes loading due to the low input/output capacitance Cio(OFF) = 4.5 pF Typ. Operating VCC range
from 2.3 V to 3.6 V. The output tracks VCC.Data and control inputs provide undershoot clamp diodes. Control
inputs can be driven by TTL or 5-V/3.3-V CMOS outputs. It supports mixed-mode signal operation on all data I/O
ports. Data I/Os support 0- to 5-V signaling levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V). The device is
protected from damaging current, Ioff supports partial shutdown which prevents the current from flowing back
through the device when it is powered down. In addition, it has 5-V tolerant I/Os with device powered up or
powered down. The device is latch-up resistant with 250 mA exceeding the JESD 17 standard, providing
protection from destruction due to latch-up. This device is protected against electrostatic discharge. It is tested
per JESD 22 using 2000-V Human-Body Model (A114-B, Class II), and 1000-V Charged-Device Model (C101).
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8.4 Device Functional Modes
Table 1 lists the functional modes for the SN74CB3T3306.
Table 1. Function Table
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
A port = B port
H
Hi-Z
Disconnect
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This application is specifically to connect a 5-V bus to a 3.3 V device. Ideally, set VCC to 3.3 V. It is assumed that
communication in this particular application is one-directional, going from the bus controller to the device.
9.2 Typical Application
1
Bus
Controller
2
3
5
6
7
4
8
0.1 µF
Figure 8. Typical Application Diagram
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits.
Because this design is for down-translating voltage, no pull-up resistors are required.
9.2.2 Detailed Design Procedure
1. Recommended Input conditions
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions
– Inputs are overvoltage tolerant allowing them to go as high as 7 V at any valid VCC
2. Recommend output conditions
– Load currents should not exceed 128 mA on each channel
10
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Typical Application (continued)
9.2.3 Application Curves
4.0
VCC = 2.3 V
IO = 1 µA
TA = 25°C
3.0
V - Output Voltage - V
O
V - Output Voltage - V
O
4.0
2.0
1.0
0.0
VCC = 3 V
IO = 1 µA
TA = 25°C
3.0
2.0
1.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VI - Input Voltage - V
Figure 9. Data Output Voltage vs Data Input Voltage
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VI - Input Voltage - V
Figure 10. Data Output Voltage vs Data Input Voltage
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight
and therefore some traces must turn corners. Figure 11 shows progressively better techniques of rounding
corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.
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11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 11. Trace Example
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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Copyright © 2003–2015, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3306
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
74CB3T3306DCURG4
Package Package Pins
Type Drawing
VSSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DCU
8
3000
180.0
8.4
2.25
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.35
1.05
4.0
8.0
Q3
SN74CB3T3306DCTR
SM8
DCT
8
3000
180.0
13.0
3.35
4.5
1.55
4.0
12.0
Q3
SN74CB3T3306DCUR
VSSOP
DCU
8
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
SN74CB3T3306DCUR
VSSOP
DCU
8
3000
180.0
9.0
2.25
3.4
1.0
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jul-2020
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74CB3T3306DCURG4
VSSOP
DCU
8
3000
202.0
201.0
28.0
SN74CB3T3306DCTR
SM8
DCT
8
3000
182.0
182.0
20.0
SN74CB3T3306DCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
SN74CB3T3306DCUR
VSSOP
DCU
8
3000
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
DCT0008A
SSOP - 1.3 mm max height
SCALE 3.500
SMALL OUTLINE PACKAGE
C
4.25
TYP
3.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
2X
1.95
3.15
2.75
NOTE 3
4
5
8X
B
2.9
2.7
NOTE 4
SEE DETAIL A
0.30
0.15
0.13
1.3
1.0
C A B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.1
0.0
0.6
0.2
DETAIL A
TYPICAL
4220784/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DCT0008A
SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE
8X (1.1)
SYMM
(R0.05)
TYP
1
8
8X (0.4)
SYMM
6X (0.65)
5
4
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220784/C 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCT0008A
SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE
8X (1.1)
SYMM
1
8
8X (0.4)
SYMM
6X (0.65)
5
4
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4220784/C 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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