74GTLPH16945VRE4

SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • • Member of the Texas Instruments Widebus™ Family TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant Medium-Drive GTLP Outputs (50 mA) LVTTL Outputs (–24 mA/24 mA) GTLP Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on A-Port Data Inputs Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II SCES292D – OCTOBER 1999 – REVISED JUNE 2005 DGG OR DGV PACKAGE (TOP VIEW) 1DIR 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2DIR 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1B1 1B2 GND 1B3 1B4 BIAS VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VREF 2B5 2B6 GND 2B7 2B8 2OE DESCRIPTION/ORDERING INFORMATION The SN74GTLPH16945 is a medium-drive, 16-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It is partitioned as two 8-bit transceivers. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing ( VCC. The package thermal impedance is calculated in accordance with JESD 51-7. 5 SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES292D – OCTOBER 1999 – REVISED JUNE 2005 Recommended Operating Conditions (1) (2) (3) (4) VCC BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK Input clamp current IOH High-level output current IOL Low-level output current ?t/?V Input transition rise or fall rate ?t/?VCC Power-up ramp rate TA Operating free-air temperature (1) (2) (3) (4) 6 MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 B port VTT Except B port B port Except B port VCC 5.5 VREF + 0.05 VREF – 0.05 Except B port V V V 2 B port V 0.8 V –18 mA A port –24 mA A port 24 B port 50 Outputs enabled 10 ns/V µs/V 20 –40 mA 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable but, generally, GND is connected first. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current drain. SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES292D – OCTOBER 1999 – REVISED JUNE 2005 Electrical Characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port VCC = 3.15 V, II = –18 mA VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC – 0.2 IOH = –12 mA 2.4 IOH = –24 mA 2 VCC = 3.15 V VCC = 3.15 V to 3.45 V, A port VOL VCC = 3.15 V VCC = 3.15 V to 3.45 V, B port II Control inputs IOZH (2) IOZL (2) A port B port MIN TYP (1) MAX TEST CONDITIONS VCC = 3.15 V VCC = 3.45 V, VCC = 3.45 V –1.2 UNIT V V IOL = 100 µA 0.2 IOL = 12 mA 0.4 IOL = 24 mA 0.5 IOL = 100 µA 0.2 IOL = 10 mA 0.2 IOL = 40 mA 0.4 IOL = 50 mA 0.55 VI = 0 or 5.5 V ±10 VO = VCC 10 VO = 1.5 V 10 –10 V µA µA µA A and B ports VCC = 3.45 V, VO = GND (3) A port VCC = 3.15 V, VI = 0.8 V 75 µA IBHH (4) A port VCC = 3.15 V, VI = 2 V –75 µA IBHLO (5) A port VCC = 3.45 V, VI = 0 to VCC 500 µA (6) A port VCC = 3.45 V, VI = 0 to VCC –500 IBHL IBHHO ICC A or B port Cio (1) (2) (3) (4) (5) (6) (7) 50 Outputs low 50 Outputs disabled 50 VCC = 3.45 V, One A-port or control input at VCC – 0.6 V, Other A-port or control inputs at VCC or GND ?ICC (7) Ci VCC = 3.45 V, IO = 0, VI (A-port or control input) = VCC or GND, VI (B port) = VTT or GND µA Outputs high mA 1.5 mA pF Control inputs VI = 3.15 V or 0 4.5 5 A port VO = 3.15 V or 0 7.5 9 B port VO = 1.5 V or 0 7.5 9 pF All typical values are at VCC = 3.3 V, TA = 25°C. For I/O ports, the parameters IOZH and IOZL include the input leakage current. The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and then raising it to VILmax. The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and then lowering it to VIHmin. An external driver must source at least IBHLO to switch this node from low to high. An external driver must sink at least IBHHO to switch this node from high to low. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Hot-Insertion Specifications for A Port over recommended operating free-air temperature range PARAMETER Ioff TEST CONDITIONS MIN MAX UNIT 10 µA OE = 0 ±30 µA OE = 0 ±30 µA VCC = 0, BIAS VCC = 0, VI or VO = 0 to 5.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, 7 SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES292D – OCTOBER 1999 – REVISED JUNE 2005 Live-Insertion Specifications for B Port over recommended operating free-air temperature range PARAMETER Ioff TEST CONDITIONS MIN MAX µA VO = 0.5 V to 1.5 V, OE = 0 ±30 µA VO = 0.5 V to 1.5 V, OE = 0 ±30 µA 5 mA 10 µA BIAS VCC = 0, VI or VO = 0 to 1.5 V IOZPU VCC = 0 to 1.5 V, BIAS VCC = 0, IOZPD VCC = 1.5 V to 0, BIAS VCC = 0, ICC (BIAS VCC) VCC = 0 to 3.15 V VCC = 3.15 V to 3.45 V UNIT 10 VCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0 to 1.5 V VO VCC = 0, BIAS VCC = 3.3 V, IO = 0 IO VCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V 0.95 1.05 V µA –1 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) PARAMETER tPLH tPHL ten tdis A B OE B Rise time, B outputs (20% to 80%) tf Fall time, B outputs (80% to 20%) tPHL ten tdis 8 TO (OUTPUT) tr tPLH (1) FROM (INPUT) B A OE A All typical values are at VCC = 3.3 V, TA = 25°C. MIN TYP (1) MAX 2.1 6.3 2.1 6.3 2 6.9 2 6.9 2.5 UNIT ns ns ns 2.1 ns 2.1 5.3 2.1 5.3 0.3 5.7 0.3 5.7 ns ns SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES292D – OCTOBER 1999 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 1.5 V 6V Open GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω 25 Ω From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND Test Point LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1V Output 1V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) 1V 0V tPLH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) tPLZ 3V 1.5 V VOL + 0.3 V VOL tPZH VOH Output 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V 1.5 V tPZL 1.5 V 1V Input 3V Output Control Output Waveform 2 S1 at GND (see Note B) tPHZ VOH 1.5 V VOH − 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 9 SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES292D – OCTOBER 1999 – REVISED JUNE 2005 Distributed-Load Backplane Switching Characteristics The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC load, to help the designer better understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more information. 38 Ω 0.25” ZO = 70 Ω 2” Conn. 1” Conn. 2” Conn. Conn. 1” 1” 0.25” 1” Rcvr Rcvr Rcvr Slot 2 Slot 9 Slot 10 Drvr Slot 1 Figure 2. Medium-Drive Test Backplane 1.5 V 19 Ω From Output Under Test LL = 19 nH Test Point CL = 9 pF Figure 3. Medium-Drive RLC Network 10 38 Ω 1.5 V 1.5 V SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES292D – OCTOBER 1999 – REVISED JUNE 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3) PARAMETER tPLH tPHL ten tdis (1) FROM (INPUT) TO (OUTPUT) A B OE B TYP (1) 4.3 4.3 5 4.4 UNIT ns ns tr Rise time, B outputs (20% to 80%) 1 ns tf Fall time, B outputs (80% to 20%) 2 ns All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. 11 PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74GTLPH16945GRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74GTLPH16945VRE4 ACTIVE TVSOP DGV 48 TBD Call TI Call TI 74GTLPH16945VRG4 ACTIVE TVSOP DGV 48 TBD Call TI Call TI SN74GTLPH16945GR ACTIVE TSSOP DGG 48 Green (RoHS & no Sb/Br) Samples (Requires Login) 74GTLPH16945GRE4 2000 (3) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74GTLPH16945GR Package Package Pins Type Drawing TSSOP DGG 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.8 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74GTLPH16945GR TSSOP DGG 48 2000 346.0 346.0 41.0 Pack Materials-Page 2 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. 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