ADC10D020CIVS

ADC10D020 www.ti.com SNAS143D – SEPTEMBER 2001 – REVISED MARCH 2013 ADC10D020 Dual 10-Bit, 20 MSPS, 150 mW A/D Converter Check for Samples: ADC10D020 FEATURES DESCRIPTION • • • • • The ADC10D020 is a dual low power, high performance CMOS analog-to-digital converter that digitizes signals to 10 bits resolution at sampling rates up to 30 MSPS while consuming a typical 150 mW from a single 3.0V supply. No missing codes is ensured over the full operating temperature range. The unique two stage architecture achieves 9.5 Effective Bits over the entire Nyquist band at 20 MHz sample rate. An output formatting choice of offset binary or 2's complement coding and a choice of two gain settings eases the interface to many systems. Also allowing great flexibility of use is a selectable 10bit multiplexed or 20-bit parallel output mode. An offset correction feature minimizes the offset error. 1 2 • • • Internal Sample-and-Hold Internal Reference Capability Dual Gain Settings Offset Correction Selectable Offset Binary or 2's Complement Output Multiplexed or Parallel Output Bus Single +2.7V to 3.6V Operation Power Down and Standby Modes APPLICATIONS • • • • • • Digital Video CCD Imaging Portable Instrumentation Communications Medical Imaging Ultrasound KEY SPECIFICATIONS • • • • • • • • • • • Resolution 10 Bits Conversion Rate 20 MSPS ENOB 9.5 Bits (typ) DNL 0.35 LSB (typ) Conversion Latency Parallel Outputs 2.5 Clock Cycles Multiplexed Outputs, I Data Bus 2.5 Clock Cycles Multiplexed Outputs, Q Data Bus 3 Clock Cycles PSRR 90 dB Power Consumption—Normal Operation 150 mW (typ) Power Down Mode VA or VD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. In the 48-pin TQFP, θJA is 76°C/W, so PDMAX = 1,645 mW at 25°C and 855 mW at the maximum operating ambient temperature of 85°C. Note that the power dissipation of this device under normal operation will typically be about 170 mW (150 mW quiescent power + 20 mW due to 1 LVTTL load on each digital output). The values for maximum power dissipation listed above will be reached only when the ADC10D020 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 Texas Instruments Linear Data Book, for other methods of soldering surface mount devices. Operating Ratings (1) (2) −40°C ≤ TA ≤ +85°C Operating Temperature Range VA, VD Supply Voltage +2.7V to +3.6V VDR Supply Voltage VIN Differential Voltage Range VCM Input Common Mode Range +1.5V to VD GAIN = Low ±VREF/2 GAIN = High ±VREF GAIN = Low VREF/4 to (VA–VREF/4) GAIN = High VREF/2 to (VA–VREF/2) VREF Voltage Range 0.8V to 1.5V −0.3V to (VA +0.3V) Digital Input Pins Voltage Range (1) (2) (5) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC10D020 5 ADC10D020 SNAS143D – SEPTEMBER 2001 – REVISED MARCH 2013 www.ti.com Converter Electrical Characteristics The following specifications apply for VA = VD = VDR = +3.0 VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN (a.c. coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1). Symbol Parameter Conditions Typical (2) Limits (3) Units (Limits) STATIC CONVERTER CHARACTERISTICS INL Integral Non-Linearity DNL Differential Non-Linearity ±0.65 ±1.8 LSB (max) ±0.35 +1.2 −1.0 LSB (max) LSB (min) 10 Bits −5 +10 −16 LSB (max) LSB (min) +0.5 +2.0 −1.5 LSB (max) LSB (min) −4 +6 −14 %FS (max) %FS (min) 9.0 Bits (min) Resolution with No Missing Codes Without Offset Correction VOFF Offset Error With Offset Correction GE Gain Error DYNAMIC CONVERTER CHARACTERISTICS ENOB SINAD SNR THD HS2 HS3 SFDR (1) (2) (3) 6 Effective Number of Bits Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Second Harmonic Third Harmonic Spurious Free Dynamic Range fIN = 1.0 MHz, VIN = FSR −0.1 dB 9.5 fIN = 4.7 MHz, VIN = FSR −0.1 dB 9.5 fIN = 9.5 MHz, VIN = FSR −0.1 dB 9.5 Bits fIN = 19.5 MHz, VIN = FSR −0.1 dB 9.5 Bits fIN = 1.0 MHz, VIN == FSR −0.1 dB 59 fIN = 4.7 MHz, VIN = FSR −0.1 dB 59 fIN = 9.5 MHz, VIN = FSR −0.1 dB 59 dB fIN = 19.5 MHz, VIN = FSR −0.1 dB 59 dB fIN = 1.0 MHz, VIN = FSR −0.1 dB 59 fIN = 4.7 MHz, VIN = FSR −0.1 dB 59 fIN = 9.5 MHz, VIN = FSR −0.1 dB 59 dB fIN = 19.5 MHz, VIN = FSR −0.1 dB 59 dB fIN = 1.0 MHz, VIN = FSR −0.1 dB −73 dB fIN = 4.7 MHz, VIN = FSR −0.1 dB −73 fIN = 9.5 MHz, VIN = FSR −0.1 dB −73 dB fIN = 19.5 MHz, VIN = FSR −0.1 dB −73 dB fIN = 1.0 MHz, VIN = FSR −0.1 dB −84 dB fIN = 4.7 MHz, VIN = FSR −0.1 dB −92 dB fIN = 9.5 MHz, VIN = FSR −0.1 dB −87 dB fIN = 19.5 MHz, VIN = FSR −0.1 dB −87 dB fIN = 1.0 MHz, VIN = FSR −0.1 dB −80 dB fIN = 4.7 MHz, VIN = FSR −0.1 dB −78 dB fIN = 9.5 MHz, VIN = FSR −0.1 dB −78 dB fIN = 19.5 MHz, VIN = FSR −0.1 dB −78 dB fIN = 1.0 MHz, VIN = FSR −0.1 dB 76 dB fIN = 4.7 MHz, VIN = FSR −0.1 dB 75 dB fIN = 9.5 MHz, VIN = FSR −0.1 dB 75 dB fIN = 19.5 MHz, VIN = FSR −0.1 dB 74 dB Bits dB 56 dB (min) dB 56 −62 dB (min) dB (min) The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device. However, errors in the A/D conversion can occur if the input goes beyond the limits given in these tables. See Figure 2 Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Performance is ensured only at VREF = 1.0V and a clock duty cycle of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are performed and limits specified with clock low and high levels of 0.3V and VD − 0.3V, respectively. Submit Documentation Feedback Copyright © 2001–2013, Texas Instruments Incorporated Product Folder Links: ADC10D020 ADC10D020 www.ti.com SNAS143D – SEPTEMBER 2001 – REVISED MARCH 2013 Converter Electrical Characteristics (continued) The following specifications apply for VA = VD = VDR = +3.0 VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN (a.c. coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1). Symbol IMD FPBW Parameter Conditions Intermodulation Distortion fIN1 < 4.9 MHz, VIN = FSR −6.1 dB fIN2 < 5.1 MHz, VIN = FSR −6.1 dB Overrange Output Code (VIN+−VIN−) > 1.1V Underrange Output Code (VIN+−VIN−) < −1.1V Typical (2) Limits (3) 65 Units (Limits) dB 1023 0 Full Power Bandwidth 140 MHz INTER-CHANNEL CHARACTERISTICS Crosstalk 1 MHz input to tested channel, 4.75 MHz input to other channel −90 dB Channel - Channel Aperture Delay Match fIN = 8 MHz 8.5 ps 0.03 %FS Gain Pin = AGND 1 VP-P Gain Pin = VA 2 VP-P Clock High 6 pF Channel - Channel Gain Matching REFERENCE AND ANALOG CHARACTERISTICS VIN Analog Differential Input Range CIN Analog Input Capacitance (each input) 3 pF RIN Analog Differential Input Resistance 27 kΩ VREF Reference Voltage 1.0 IREF Reference Input Current