ADC3421IRTQR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 ADC342x Quad-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converter 1 Features 3 Description • • • • • • The ADC342x are a high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. 1 • • • • • • Quad Channel 12-Bit Resolution Single Supply: 1.8 V Serial LVDS Interface Flexible Input Clock Buffer with Divide-by-1, -2, -4 SNR = 70.2 dBFS, SFDR = 87 dBc at fIN = 70 MHz Ultra-Low Power Consumption: – 98 mW/Ch at 125 MSPS Channel Isolation: 105 dB Internal Dither and Chopper Support for Multi-Chip Synchronization Pin-to-Pin Compatible with 14-Bit Version Package: VQFN-56 (8 mm × 8 mm) 2 Applications • • • • • • • • • • Multi-Carrier, Multi-Mode Cellular Base Stations Radar and Smart Antenna Arrays Munitions Guidance Motor Control Feedback Network and Vector Analyzers Communications Test Equipment Nondestructive Testing Microwave Receivers Software-Defined Radios (SDRs) Quadrature and Diversity Radio Receivers Device Information(1) PART NUMBER ADC342x PACKAGE VQFN (56) BODY SIZE (NOM) 8.00 mm × 8.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. space space space space space space Spectrum at 10-MHz IF (SFDR = 97 dBc, SNR = 70.4 dBFS, SINAD = 70.4 dBFS, THD = 98 dBc, HD2 = 95 dBc, HD3 = 97 dBc) 0 -10 -20 Amplitude (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D201 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 1 1 1 2 3 3 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 6 Electrical Characteristics: General ............................ 6 Electrical Characteristics: ADC3421, ADC3422 ....... 7 Electrical Characteristics: ADC3423, ADC3424 ....... 7 AC Performance: ADC3421...................................... 8 AC Performance: ADC3422.................................... 10 AC Performance: ADC3423.................................. 12 AC Performance: ADC3424.................................. 14 Digital Characteristics ........................................... 16 Timing Requirements: General ............................. 16 Timing Requirements: LVDS Output..................... 17 Typical Characteristics: ADC3421 ........................ 18 Typical Characteristics: ADC3422 ........................ 23 Typical Characteristics: ADC3423 ........................ 28 Typical Characteristics: ADC3424 ........................ 33 7.19 Typical Characteristics: Common ......................... 38 7.20 Typical Characteristics: Contour ........................... 39 8 Parameter Measurement Information ................ 39 9 Detailed Description ............................................ 41 8.1 Timing Diagrams ..................................................... 39 9.1 9.2 9.3 9.4 9.5 9.6 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 41 41 42 46 47 51 10 Applications and Implementation...................... 66 10.1 Application Information.......................................... 66 10.2 Typical Applications .............................................. 67 11 Power Supply Recommendations ..................... 69 12 Layout................................................................... 70 12.1 Layout Guidelines ................................................. 70 12.2 Layout Example .................................................... 70 13 Device and Documentation Support ................. 71 13.1 13.2 13.3 13.4 13.5 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 71 71 71 71 71 14 Mechanical, Packaging, and Orderable Information ........................................................... 71 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (July 2014) to Revision A • 2 Page Released to production........................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 5 Device Comparison Table INTERFACE Serial LVDS JESD204B RESOLUTION (Bits) 25 MSPS 50 MSPS 80 MSPS 125 MSPS 160 MSPS 12 ADC3421 ADC3422 ADC3423 ADC3424 — 14 ADC3441 ADC3442 ADC3443 ADC3444 — 12 — ADC34J22 ADC34J23 ADC34J24 ADC34J25 14 — ADC34J42 ADC34J43 ADC34J44 ADC34J45 6 Pin Configuration and Functions DB0M DB0P DB1M DB1P DVDD DCLKM DCLKP FCLKM FCLKP DVDD DC0M DC0P DC1M DC1P RTQ Package VQFN-56 Top View 56 55 54 53 52 51 50 49 48 47 46 45 44 43 DA0M 4 39 DD1P DVDD 5 38 DVDD AVDD 6 37 PDN AVDD 7 GND Pad 36 AVDD INAM 8 (Back Side) 35 INDM INAP 9 34 INDP AVDD 10 33 AVDD AVDD 11 32 AVDD INBP 12 31 INCP INBM 13 30 INCM AVDD 14 29 AVDD 17 18 19 20 21 Copyright © 2014–2015, Texas Instruments Incorporated 22 23 24 25 26 27 28 AVDD 16 CLKP 15 VCM DD1M SYSREFM 40 SYSREFP 3 RESET DA0P AVDD DD0P CLKM 41 AVDD 2 SDOUT DA1M SEN DD0M SDATA 42 SCLK 1 AVDD DA1P Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 3 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com Pin Functions PIN NAME I/O NO. DESCRIPTION AVDD 6, 7, 10, 11, 14, 15, 20, 23, 28, 29, 32, 33, 36 I Analog 1.8-V power supply CLKM 21 I Negative differential clock input for the ADC CLKP 22 I Positive differential clock input for the ADC DA0M 4 O Negative serial LVDS output for wire-0 of channel A DA0P 3 O Positive serial LVDS output for wire-0 of channel A DA1M 2 O Negative serial LVDS output for wire-1 of channel A DA1P 1 O Positive serial LVDS output for wire-1 of channel A DB0M 56 O Negative serial LVDS output for wire-0 of channel B DB0P 55 O Positive serial LVDS output for wire-0 of channel B DB1M 54 O Negative serial LVDS output for wire-1 of channel B DB1P 53 O Positive serial LVDS output for wire-1 of channel B DC0M 46 O Negative serial LVDS output for wire-0 of channel C DC0P 45 O Positive serial LVDS output for wire-0 of channel C DC1M 44 O Negative serial LVDS output for wire-1 of channel C DC1P 43 O Positive serial LVDS output for wire-1 of channel C DD0M 42 O Negative serial LVDS output for wire-0 of channel D DD0P 41 O Positive serial LVDS output for wire-0 of channel D DD1M 40 O Negative serial LVDS output for wire-1 of channel D DD1P 39 O Positive serial LVDS output for wire-1 of channel D DCLKM 51 O Negative bit clock output DCLKP 50 O Positive bit clock output DVDD 5, 38, 47, 52 I Digital 1.8-V power supply FCLKM 49 O Negative frame clock output FCLKP 48 O Positive frame clock output GND PowerPAD™ I Ground, 0 V INAM 8 I Negative differential analog input for channel A INAP 9 I Positive differential analog input for channel A INBM 13 I Negative differential analog input for channel B INBP 12 I Positive differential analog input for channel B INCM 30 I Negative differential analog input for channel C INCP 31 I Positive differential analog input for channel C INDM 35 I Negative differential analog input for channel D INDP 34 I Positive differential analog input for channel D PDN 37 I Power-down control. This pin can be configured via the SPI. This pin has an internal 150-kΩ pulldown resistor. RESET 24 I Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor. SCLK 16 I Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor. SDATA 17 I Serial interface data input. This pin has an internal 150-kΩ pulldown resistor. SDOUT 19 O Serial interface data output SEN 18 I Serial interface enable; active low. This pin has an internal 150-kΩ pullup resistor to AVDD. SYSREFM 26 I Negative external SYSREF input SYSREFP 25 I Positive external SYSREF input VCM 27 O Common-mode voltage for analog inputs 4 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Analog supply voltage range, AVDD –0.3 2.1 V Digital supply voltage range, DVDD V Voltage applied to input pins Temperature –0.3 2.1 INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM –0.3 min (1.9, AVDD + 0.3) CLKP, CLKM –0.3 AVDD + 0.3 SYSREFP, SYSREFM –0.3 AVDD + 0.3 SCLK, SEN, SDATA, RESET, PDN –0.3 3.9 Operating free-air, TA –40 85 Operating junction, TJ 125 Storage, Tstg (1) V –65 ºC 150 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings V(ESD) (1) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Electrostatic discharge VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions (1) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage range 1.7 1.8 1.9 V DVDD Digital supply voltage range 1.7 1.8 1.9 V ANALOG INPUT VID Differential input voltage VIC Input common-mode voltage For input frequencies < 450 MHz 2 For input frequencies < 600 MHz 1 VPP VCM ± 0.025 V CLOCK INPUT Input clock frequency Sampling clock frequency Sine wave, ac-coupled Input clock amplitude (differential) Input clock duty cycle 15 (2) 0.2 125 (3) 1.5 LPECL, ac-coupled 1.6 LVDS, ac-coupled 0.7 35% Input clock common-mode voltage MSPS 50% VPP 65% 0.95 V DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to GND 3.3 pF RLOAD Single-ended load resistance 100 Ω (1) (2) (3) After power-up, use only the RESET pin to reset the device for the first time; see the Register Initialization section for details. See Table 3 for details. With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 5 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 7.4 Thermal Information ADC342x THERMAL METRIC (1) RTQ (VQFN) UNIT 56 PINS RθJA Junction-to-ambient thermal resistance 25.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 9.5 °C/W RθJB Junction-to-board thermal resistance 3.4 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 3.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics: General Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT 2.0 VPP ri Differential input full-scale Input resistance Differential at dc 6.6 kΩ ci Input capacitance Differential at dc 3.7 pF VOC(VCM) VCM common-mode voltage output 0.95 VCM output current capability V 10 mA Input common-mode current Per analog input pin 1.5 µA/MSPS Analog input bandwidth (3 dB) 50-Ω differential source driving 50-Ω termination across INP and INM 540 MHz DC ACCURACY EO Offset error αEO Temperature coefficient of offset error –25 EG(REF) Gain error as a result of internal reference inaccuracy alone EG(CHAN) Gain error of channel alone α(EGCHAN) Temperature coefficient of EG(CHAN) 25 ± 0.024 –2 2 –2 ±0.008 mV mV/°C %FS %FS Δ%FS/Ch CHANNEL-TO-CHANNEL ISOLATION fIN = 10 MHz fIN = 100 MHz Crosstalk (1) fIN = 200 MHz fIN = 230 MHz fIN = 300 MHz (1) 6 Near channel 105 Far channel 105 Near channel 95 Far channel 105 Near channel 94 Far channel 105 Near channel dB 92 Far channel 105 Near channel 85 Far channel 105 Crosstalk is measured with a –1-dBFS input signal on the aggressor channel and no input on the victim channel. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 7.6 Electrical Characteristics: ADC3421, ADC3422 Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3421 PARAMETER MIN TYP ADC clock frequency ADC3422 MAX MIN TYP 25 Resolution 12 MAX UNIT 50 MSPS 12 Bits 1.8-V analog supply current 54 71 71 90 mA 1.8-V digital supply current 45 71 56 90 mA 177 240 228 305 mW 5 17 5 17 mW 34 75 35 75 mW Total power dissipation Global power-down dissipation Standby power-down dissipation 7.7 Electrical Characteristics: ADC3423, ADC3424 Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3423 PARAMETER MIN TYP ADC clock frequency ADC3424 MAX MIN TYP 80 Resolution 12 1.8-V analog supply current 1.8-V digital supply current Total power dissipation Global power-down dissipation Standby power-down dissipation Copyright © 2014–2015, Texas Instruments Incorporated MAX UNIT 125 MSPS 12 92 107 Bits 119 145 mA 68 100 98 145 mA 288 365 391 475 mW 5 17 5 17 mW 40 88 43 103 mW Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 7 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 7.8 AC Performance: ADC3421 Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3421 (fS = 25 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz SNR Signal-to-noise ratio (full Nyquist band) Noise spectral density (averaged across Nyquist zone) NSD (1) 70.9 fIN = 70 MHz 70.4 70.6 fIN = 100 MHz 70.3 70.5 fIN = 170 MHz 69.7 69.9 fIN = 230 MHz 68.9 69.1 fIN = 10 MHz 70.2 70.5 fIN = 20 MHz 70.1 70.3 fIN = 70 MHz 69.8 70.0 fIN = 100 MHz 69.6 69.8 fIN = 170 MHz 69.2 69.3 fIN = 230 MHz 68.3 68.5 fIN = 10 MHz –141.5 –141.7 fIN = 20 MHz –141.3 –139.5 –141.5 fIN = 70 MHz –141.0 –141.2 fIN = 100 MHz –140.9 –141.1 fIN = 170 MHz –140.3 –140.5 fIN = 230 MHz –139.5 –139.7 71 71.1 70.8 70.9 Effective number of bits 67.9 fIN = 70 MHz 69.5 70 fIN = 100 MHz 70.5 70.7 fIN = 170 MHz 69.6 69.8 fIN = 230 MHz 68.7 68.7 fIN = 10 MHz 11.5 11.5 11.4 11.4 fIN = 70 MHz 11.4 11.4 fIN = 100 MHz 11.4 11.4 fIN = 170 MHz 11.3 11.3 fIN = 230 MHz 11.1 11.1 93 90 91 85 fIN = 70 MHz 93 88 fIN = 100 MHz 85 82 fIN = 170 MHz 86 85 fIN = 230 MHz 82 82 fIN = 20 MHz ENOB (1) 11 fIN = 10 MHz fIN = 20 MHz SFDR (1) 8 Spurious-free dynamic range TYP 71.1 fIN = 20 MHz Signal-to-noise and distortion ratio MIN 70.7 68.9 fIN = 10 MHz SINAD (1) DITHER OFF MAX 70.9 fIN = 20 MHz Signal-to-noise ratio (from 1-MHz offset) TYP 84 MAX UNIT dBFS dBFS dBFS/Hz dBFS Bits dBc Reported from a 1-MHz offset. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 AC Performance: ADC3421 (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3421 (fS = 25 MSPS) DITHER ON PARAMETER TEST CONDITIONS TYP 93 92 84 100 94 fIN = 70 MHz 93 92 fIN = 100 MHz 94 93 fIN = 170 MHz 86 85 fIN = 230 MHz 86 82 96 90 91 85 fIN = 70 MHz 93 88 fIN = 100 MHz 85 82 fIN = 170 MHz 89 89 fIN = 230 MHz 82 82 fIN = 10 MHz 99 92 fIN = 10 MHz fIN = 20 MHz HD2 Second-order harmonic distortion fIN = 10 MHz fIN = 20 MHz HD3 Third-order harmonic distortion fIN = 20 MHz Non HD2, HD3 Spurious-free dynamic range (excluding HD2, HD3) IMD3 Total harmonic distortion Two-tone, third-order intermodulation distortion 84 MIN TYP 98 91 96 92 fIN = 100 MHz 95 93 fIN = 170 MHz 92 90 fIN = 230 MHz 97 91 fIN = 10 MHz 90 86 90 83 fIN = 70 MHz 89 85 fIN = 100 MHz 84 80 fIN = 170 MHz 84 83 fIN = 230 MHz 80 79 fIN1 = 45 MHz, fIN2 = 50 MHz –98 –98 fIN1 = 185 MHz, fIN2 = 190 MHz –91 –91 Copyright © 2014–2015, Texas Instruments Incorporated 87 MAX fIN = 70 MHz fIN = 20 MHz THD DITHER OFF MIN 81 MAX UNIT dBc dBc dBc dBc dBFS Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 9 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 7.9 AC Performance: ADC3422 Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3422 (fS = 50 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz SNR Signal-to-noise ratio (full Nyquist band) Noise spectral density (averaged across Nyquist zone) NSD (1) 71 fIN = 70 MHz 70.5 70.7 fIN = 100 MHz 70.4 70.6 fIN = 170 MHz 69.8 70.1 fIN = 230 MHz 68.8 69 fIN = 10 MHz 70.2 70.4 fIN = 20 MHz 69.8 70.0 fIN = 70 MHz 69.7 69.9 fIN = 100 MHz 69.8 70.1 fIN = 170 MHz 69.3 69.5 fIN = 230 MHz 68.2 68.4 fIN = 10 MHz –144.6 –144.8 fIN = 20 MHz –144.4 –142.7 –144.6 fIN = 70 MHz –144.3 –144.5 fIN = 100 MHz –144.2 –144.4 fIN = 170 MHz –143.6 –143.9 fIN = 230 MHz –142.6 –142.8 70.8 71 70.7 70.9 fIN = 70 MHz 70.3 70.6 fIN = 100 MHz 70.6 70.8 fIN = 170 MHz 69.7 69.9 fIN = 230 MHz 68.6 68.8 fIN = 10 MHz 11.5 11.5 11.4 11.5 fIN = 70 MHz 11.4 11.5 fIN = 100 MHz 11.4 11.5 fIN = 170 MHz 11.3 11.3 fIN = 230 MHz 11.1 11.1 90 92 95 90 fIN = 70 MHz 93 92 fIN = 100 MHz 87 87 fIN = 170 MHz 87 86 fIN = 230 MHz 83 83 fIN = 20 MHz ENOB (1) Effective number of bits 67.9 11 fIN = 10 MHz fIN = 20 MHz SFDR (1) 10 Spurious-free dynamic range TYP 70.8 fIN = 20 MHz Signal-to-noise and distortion ratio MIN 70.6 68.9 fIN = 10 MHz SINAD (1) DITHER OFF MAX 70.8 fIN = 20 MHz Signal-to-noise ratio (from 1-MHz offset) TYP 82 MAX UNIT dBFS dBFS/Hz dBFS Bits dBc Reported from a 1-MHz offset. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 AC Performance: ADC3422 (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3422 (fS = 50 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz Second-order harmonic distortion 95 fIN = 70 MHz 93 92 fIN = 100 MHz 94 92 fIN = 170 MHz 87 86 fIN = 230 MHz 85 83 90 92 94 92 fIN = 70 MHz 94 92 fIN = 100 MHz 87 87 fIN = 170 MHz 88 89 fIN = 230 MHz 83 88 fIN = 10 MHz 99 93 fIN = 20 MHz Non HD2, HD3 Spurious-free dynamic range (excluding HD2, HD3) IMD3 Total harmonic distortion Two-tone, third-order intermodulation distortion 82 99 93 fIN = 70 MHz 98 92 fIN = 100 MHz 95 94 fIN = 170 MHz 96 89 fIN = 230 MHz 96 90 fIN = 10 MHz 88 87 89 89 fIN = 70 MHz 90 87 fIN = 100 MHz 86 85 fIN = 170 MHz 84 83 fIN = 230 MHz 81 81 fIN1 = 45 MHz, fIN2 = 50 MHz –95 –95 fIN1 = 185 MHz, fIN2 = 190 MHz –88 –88 fIN = 20 MHz THD TYP 92 fIN = 20 MHz Third-order harmonic distortion MIN 98 83 fIN = 10 MHz HD3 DITHER OFF MAX 95 fIN = 20 MHz HD2 TYP Copyright © 2014–2015, Texas Instruments Incorporated 87 79 MAX UNIT dBc dBc dBc dBc dBFS Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 11 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 7.10 AC Performance: ADC3423 Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3423 (fS = 80 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz SNR Signal-to-noise ratio (full Nyquist band) Noise spectral density (averaged across Nyquist zone) NSD (1) SINAD 70.7 fIN = 100 MHz 70.3 70.5 fIN = 170 MHz 70.1 70.3 fIN = 230 MHz 69.6 69.9 fIN = 10 MHz 70.3 70.5 fIN = 70 MHz 70.1 70.4 fIN = 100 MHz 69.9 70.2 fIN = 170 MHz 69.7 69.9 fIN = 230 MHz 69.3 69.6 fIN = 10 MHz –146.6 –146.8 fIN = 70 MHz –146.4 –144.6 –146.6 fIN = 100 MHz –146.2 –146.4 fIN = 170 MHz –146.0 –146.2 fIN = 230 MHz –145.5 –145.8 70.7 70.8 70.3 70.4 fIN = 100 MHz 70.4 70.7 fIN = 170 MHz 70 70.2 fIN = 230 MHz 69.5 69.7 11.5 11.5 11.4 11.4 fIN = 100 MHz 11.4 11.5 fIN = 170 MHz 11.3 11.4 fIN = 230 MHz 11.3 11.3 90 90 91 90 fIN = 100 MHz 93 93 fIN = 170 MHz 88 86 fIN = 230 MHz 87 85 67.7 fIN = 10 MHz fIN = 70 MHz ENOB (1) Effective number of bits 11 fIN = 10 MHz fIN = 70 MHz SFDR (1) 12 Spurious-free dynamic range TYP 70.9 fIN = 70 MHz Signal-to-noise and distortion ratio MIN 70.5 68.7 fIN = 10 MHz (1) DITHER OFF MAX 70.7 fIN = 70 MHz Signal-to-noise ratio (from 1-MHz offset) TYP 81 MAX UNIT dBFS dBFS/Hz dBFS Bits dBc Reported from a 1-MHz offset. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 AC Performance: ADC3423 (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3423 (fS = 80 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz Second-order harmonic distortion Third-order harmonic distortion 92 fIN = 100 MHz 97 93 fIN = 170 MHz 88 86 fIN = 230 MHz 87 85 fIN = 10 MHz 90 90 91 90 fIN = 100 MHz 93 99 fIN = 170 MHz 96 93 fIN = 230 MHz 87 87 99 94 98 93 fIN = 100 MHz 94 94 fIN = 170 MHz 95 92 fIN = 230 MHz 94 91 fIN = 10 MHz 88 86 fIN = 70 MHz Spurious-free dynamic range (excluding HD2, HD3) fIN = 70 MHz THD IMD3 Total harmonic distortion Two-tone, third-order intermodulation distortion TYP 91 81 81 fIN = 10 MHz Non HD2, HD3 MIN 96 fIN = 70 MHz HD3 DITHER OFF MAX 94 fIN = 70 MHz HD2 TYP 86 89 86 fIN = 100 MHz 91 90 fIN = 170 MHz 87 84 fIN = 230 MHz 84 82 fIN1 = 45 MHz, fIN2 = 50 MHz –97 –97 fIN1 = 185 MHz, fIN2 = 190 MHz –92 –92 Copyright © 2014–2015, Texas Instruments Incorporated 78 MAX UNIT dBc dBc dBc dBc dBFS Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 13 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 7.11 AC Performance: ADC3424 Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3424 (fS = 125 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz SNR Signal-to-noise ratio (full Nyquist band) Noise spectral density (averaged across Nyquist zone) NSD (1) SINAD 70.6 fIN = 100 MHz 70.1 70.4 fIN = 170 MHz 69.8 70.3 fIN = 230 MHz 69.2 69.9 fIN = 10 MHz 70.3 70.5 fIN = 70 MHz 70.1 70.4 fIN = 100 MHz 70.0 70.2 fIN = 170 MHz 69.6 70.1 fIN = 230 MHz 69.0 69.7 fIN = 10 MHz –148.4 –148.6 fIN = 70 MHz –148.2 –145.9 –148.5 fIN = 100 MHz –148.0 –148.3 fIN = 170 MHz –147.7 –148.2 fIN = 230 MHz –147.1 –147.8 70.5 70.6 70.3 70.5 fIN = 100 MHz 70.1 70.5 fIN = 170 MHz 69.7 70.1 fIN = 230 MHz 68.6 69.1 11.4 11.4 11.4 11.4 fIN = 100 MHz 11.4 11.4 fIN = 170 MHz 11.3 11.4 fIN = 230 MHz 11.2 11.3 93 89 94 90 fIN = 100 MHz 90 87 fIN = 170 MHz 86 85 fIN = 230 MHz 81 80 67 fIN = 10 MHz fIN = 70 MHz ENOB (1) Effective number of bits 10.8 fIN = 10 MHz fIN = 70 MHz SFDR (1) 14 Spurious-free dynamic range TYP 70.7 fIN = 70 MHz Signal-to-noise and distortion ratio MIN 70.3 68 fIN = 10 MHz (1) DITHER OFF MAX 70.5 fIN = 70 MHz Signal-to-noise ratio (from 1-MHz offset) TYP 80 MAX UNIT dBFS dBFS/Hz dBFS Bits dBc Reported from a 1-MHz offset. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 AC Performance: ADC3424 (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. ADC3424 (fS = 125 MSPS) DITHER ON PARAMETER TEST CONDITIONS MIN fIN = 10 MHz Second-order harmonic distortion Third-order harmonic distortion 91 fIN = 100 MHz 90 91 fIN = 170 MHz 86 85 fIN = 230 MHz 81 80 fIN = 10 MHz 96 88 95 89 fIN = 100 MHz 97 90 fIN = 170 MHz 93 87 fIN = 230 MHz 87 86 100 93 99 94 fIN = 100 MHz 94 93 fIN = 170 MHz 95 92 fIN = 230 MHz 94 90 fIN = 10 MHz 90 85 fIN = 70 MHz Spurious-free dynamic range (excluding HD2, HD3) fIN = 70 MHz THD IMD3 Total harmonic distortion Two-tone, third-order intermodulation distortion TYP 92 80 81 fIN = 10 MHz Non HD2, HD3 MIN 94 fIN = 70 MHz HD3 DITHER OFF MAX 93 fIN = 70 MHz HD2 TYP 86 90 85 fIN = 100 MHz 88 86 fIN = 170 MHz 85 82 fIN = 230 MHz 80 78 fIN1 = 45 MHz, fIN2 = 50 MHz 95 95 fIN1 = 185 MHz, fIN2 = 190 MHz 89 89 Copyright © 2014–2015, Texas Instruments Incorporated 77 MAX UNIT dBc dBc dBc dBc dBFS Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 15 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 7.12 Digital Characteristics The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN) VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels VIL Low-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels IIH High-level input current Low-level input current IIL RESET, SDATA, SCLK, PDN SEN (1) 1.3 V 0.4 V VHIGH = 1.8 V 10 µA VHIGH = 1.8 V 0 µA RESET, SDATA, SCLK, PDN VLOW = 0 V 0 µA SEN VLOW = 0 V 10 µA DIGITAL INPUTS (SYSREFP, SYSREFM) VIH High-level input voltage 1.3 V VIL Low-level input voltage 0.5 V Common-mode voltage for SYSREF 0.9 V DIGITAL OUTPUTS (CMOS Interface, SDOUT) VOH High-level output voltage VOL Low-level output voltage DVDD – 0.1 DVDD V 0 0.1 V DIGITAL OUTPUTS (LVDS Interface) VODH High-level output differential voltage With an external 100-Ω termination 280 350 460 mV VODL Low-level output differential voltage With an external 100-Ω termination –460 –350 –280 mV VOCM Output common-mode voltage (1) 1.05 V SEN has an internal 150-kΩ pullup resistor to AVDD. SPI pins (SEN, SCLK, SDATA) can be driven by 1.8 V or 3.3 V CMOS buffers. 7.13 Timing Requirements: General Typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C. tA Aperture delay MIN TYP MAX UNIT 1.24 1.44 1.64 ns Aperture delay matching between two channels of the same device ±70 Aperture delay variation between two devices at same temperature and supply voltage tJ Aperture jitter Wake-up time: ps 130 fS rms Time to valid data after exiting standby power-down mode 35 200 µs Time to valid data after exiting global power-down mode (in this mode, both channels power down) 85 450 µs 2-wire mode (default) 9 Clock cycles 1-wire mode 8 Clock cycles ADC latency (1): tSU_SYSREF tH_SYSREF SYSREF reference time: ps ±150 Setup time for SYSREF referenced to input clock rising edge 1000 ps Hold time for SYSREF referenced to input clock rising edge 100 ps (1) Overall latency = ADC latency + tPDI. 16 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 7.14 Timing Requirements: LVDS Output (1) (2) Typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, 6x Serialization (2-Wire Mode), CLOAD = 3.3 pF (3), and RLOAD = 100 Ω (4), unless otherwise noted.. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C. MIN TYP tSU Data setup time: data valid to zero-crossing of differential output clock (CLKOUTP – CLKOUTM) (5) MAX 0.43 0.5 ns tHO Data hold time: zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data becoming invalid (5) 0.48 0.58 ns Clock propagation delay: input clock falling edge cross-over to 1-wire mode frame clock rising edge cross-over 2-wire mode (15 MSPS < sampling frequency < 125 MSPS) 2.7 4.5 tPDI tDELAY Delay time 6.5 0.44 × tS + tDELAY 3 4.5 UNIT ns ns 5.9 ns LVDS bit clock duty cycle: duty cycle of differential clock (CLKOUTP – CLKOUTM) 49% tFALL, tRISE Data fall time, data rise time: rise time measured from –100 mV to 100 mV, 15 MSPS ≤ Sampling frequency ≤ 125 MSPS 0.11 ns tCLKRISE, tCLKFALL Output clock rise time, output clock fall time: rise time measured from –100 mV to 100 mV, 15 MSPS ≤ Sampling frequency ≤ 125 MSPS 0.11 ns (1) (2) (3) (4) (5) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Timing parameters are ensured by design and characterization and are not tested in production. CLOAD is the effective external single-ended load capacitance between each output pin and ground. RLOAD is the differential load resistance between the LVDS output pair. Data valid refers to a logic high of 100 mV and a logic low of –100 mV. Table 1. LVDS Timing at Lower Sampling Frequencies: 6X Serialization (2-Wire Mode) SETUP TIME (tSU, ns) HOLD TIME (tHO, ns) SAMPLING FREQUENCY (MSPS) MIN TYP MIN TYP 25 2.61 3.06 2.75 3.12 40 1.69 1.9 1.8 1.98 60 1.11 1.23 1.18 1.31 80 0.81 0.89 0.88 0.97 100 0.6 0.68 0.68 0.77 MAX MAX Table 2. LVDS Timings at Lower Sampling Frequencies: 12X Serialization (1-Wire Mode) SAMPLING FREQUENCY (MSPS) SETUP TIME (tSU, ns) MIN TYP 25 1.3 40 0.76 50 HOLD TIME (tHO, ns) MIN TYP 1.48 1.32 1.57 0.88 0.79 0.97 0.57 0.68 0.61 0.77 60 0.42 0.55 0.45 0.62 70 0.35 0.44 0.4 0.51 80 0.26 0.35 0.35 0.43 Copyright © 2014–2015, Texas Instruments Incorporated MAX Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 MAX 17 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 7.15 Typical Characteristics: ADC3421 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -70 -80 -90 -100 -110 -110 -120 2.5 5 7.5 Frequency (MHz) 10 0 12.5 2.5 D801 SFDR = 95 dBc, SNR = 71 dBFS, SINAD = 71 dBFS, THD = 94 dBc, HD2 = 106 dBc, HD3 = 95 dBc 5 7.5 Frequency (MHz) 10 12.5 D802 SFDR = 90 dBc, SNR = 71.2 dBFS, SINAD = 71.1 dBFS, THD = 89 dBc, HD2 = 90 dBc, HD3 = 106 dBc Figure 1. FFT for 10-MHz Input Signal (Dither On) Figure 2. FFT for 10-MHz Input Signal (Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) -60 -100 0 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 2.5 5 7.5 Frequency (MHz) 10 12.5 0 2.5 D803 SFDR = 92 dBc, SNR = 70.5 dBFS, SINAD = 70.3 dBFS, THD = 91 dBc, HD2 = 105 dBc, HD3 = 92 dBc 5 7.5 Frequency (MHz) 10 12.5 D804 SFDR = 91 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS, THD = 88 dBc, HD2 = 91 dBc, HD3 = 101 dBc Figure 3. FFT for 70-MHz Input Signal (Dither On) Figure 4. FFT for 70-MHz Input Signal (Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) -50 -90 -120 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 2.5 5 7.5 Frequency (MHz) 10 12.5 D805 SFDR = 87 dBc, SNR = 69.8 dBFS, SINAD = 69.7 dBFS, THD = 85 dBc, HD2 = 90 dBc, HD3 = 87 dBc Figure 5. FFT for 170-MHz Input Signal (Dither On) 18 -40 Submit Documentation Feedback 0 2.5 5 7.5 Frequency (MHz) 10 12.5 D806 SFDR = 85 dBc, SNR = 70 dBFS, SINAD = 69.8 dBFS, THD = 86 dBc, HD2 = 85 dBc, HD3 = 92 dBc Figure 6. FFT for 170-MHz Input Signal (Dither Off) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 Typical Characteristics: ADC3421 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -60 -70 -80 -90 -100 -100 -110 -110 -120 0 2.5 5 7.5 Frequency (MHz) 10 12.5 0 2.5 D807 SFDR = 77 dBc, SNR = 68.2 dBFS, SINAD = 67.7 dBFS, THD = 75 dBc, HD2 = 77 dBc, HD3 = 83 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 10 12.5 D808 Figure 8. FFT for 270-MHz Input Signal (Dither Off) 0 -40 5 7.5 Frequency (MHz) SFDR = 75 dBc, SNR = 68.4 dBFS, SINAD = 67.5 dBFS, THD = 74 dBc, HD2 = 75 dBc, HD3 = 80 dBc Figure 7. FFT for 270-MHz Input Signal (Dither On) Amplitude (dBFS) -50 -90 -120 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 2.5 5 7.5 Frequency (MHz) 10 12.5 0 2.5 D809 SFDR = 67 dBc, SNR = 66.4 dBFS, SINAD = 66.4 dBFS, THD = 93 dBc, HD2 = 67 dBc, HD3 = 88 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 12.5 D810 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 10 Figure 10. FFT for 450-MHz Input Signal (Dither Off) 0 -40 5 7.5 Frequency (MHz) SFDR = 66 dBc, SNR = 66.5 dBFS, SINAD = 66.5 dBFS, THD = 87 dBc, HD2 = 66 dBc, HD3 = 93 dBc Figure 9. FFT for 450-MHz Input Signal (Dither On) Amplitude (dBFS) -40 -120 0 2.5 5 7.5 Frequency (MHz) 10 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 90, each tone at = –7 dBFS Figure 11. FFT for Two-Tone Input Signal (–7 dBFS at 46 MHz and 50 MHz) Copyright © 2014–2015, Texas Instruments Incorporated 12.5 D811 0 2.5 5 7.5 Frequency (MHz) 10 12.5 D812 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 105, each tone at = –36 dBFS Figure 12. FFT for Two-Tone Input Signal (–36 dBFS at 46 MHz and 50 MHz) Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 19 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics: ADC3421 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 2.5 5 7.5 Frequency (MHz) 10 12.5 0 2.5 5 7.5 Frequency (MHz) D813 fIN1 = 184.5 MHz, fIN2 = 189.5 MHz, IMD3 = 91, each tone at = –7 dBFS 10 12.5 D814 fIN1 = 184.5 MHz, fIN2 = 189.5 MHz, IMD3 = 98 dBFS, each tone at –36 dBFS Figure 13. FFT for Two-Tone Input Signal (–7 dBFS at 185 MHz and 190 MHz) Figure 14. FFT for Two-Tone Input Signal (–36 dBFS at 185 MHz and 190 MHz) -85 -85 Two-Tone IMD (dBFS) Two-Tone IMD (dBFS) -90 -95 -100 -90 -95 -100 -105 -110 -35 -31 -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -105 -35 -7 -31 D815 Figure 15. Intermodulation Distortion vs Input Amplitude (46 MHz and 50 MHz) -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -7 D816 Figure 16. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz) 72 100 Dither_EN Dither_DIS 71 Dither_EN Dither_DIS 95 SFDR (dBc) SNR (dBFS) 90 70 69 68 85 80 75 70 67 65 66 60 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D801 D817 Figure 17. Signal-to-Noise Ratio vs Input Frequency 20 Submit Documentation Feedback 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D818 Figure 18. Spurious-Free Dynamic Range vs Input Frequency Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 Typical Characteristics: ADC3421 (continued) 71.5 200 71 160 70.5 120 70 80 69.5 40 SNR (dBFS) -50 -40 -30 Amplitude (dBFS) -20 -10 71 150 70 100 69 50 68 -70 0 -60 72 250 SNR (dBFS) SFDR (dBc) SFDR (dBFS) 200 0 0 -60 -50 D819 Figure 19. Performance vs Input Amplitude (30 MHz) 78 -40 -30 Amplitude (dBFS) -20 -10 D820 Figure 20. Performance vs Input Amplitude (170 MHz) 105 76 88 76 100 74 95 72 90 70 85 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) SNR (dBFS) SNR SFDR SFDR (dBc) SNR (dBFS) SNR SFDR 68 0.85 80 1.1 74 86 72 84 70 82 68 80 66 0.85 D821 Figure 21. Performance vs Input Common-Mode Voltage (30 MHz) 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) 78 1.1 D822 Figure 22. Performance vs Input Common-Mode Voltage (170 MHz) 72 95 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 93 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V 71.6 91 SNR (dBFS) SFDR (dBc) 0 SFDR (dBc) SNR (dBFS) 72 69 -70 73 280 SNR (dBFS) SFDR (dBc) 240 SFDR (dBFS) SFDR (dBc,dBFS) 72.5 SFDR (dBc,dBFS) Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 89 AVDD = 1.85 V AVDD = 1.9 V 71.2 70.8 87 70.4 85 83 -40 -15 10 35 Temperature (°C) 60 85 D823 Figure 23. Spurious-Free Dynamic Range vs AVDD Supply and Temperature (30 MHz) Copyright © 2014–2015, Texas Instruments Incorporated 70 -40 -15 10 35 Temperature (°C) 60 85 D824 Figure 24. Signal-to-Noise Ratio vs AVDD Supply and Temperature (30 MHz) Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 21 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics: ADC3421 (continued) Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 72 92 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 91 71.6 SNR (dBFS) 90 SFDR (dBc) DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V DVDD = 1.9 V 89 DVDD = 1.85 V DVDD = 1.9 V 71.2 70.8 88 70.4 87 10 35 Temperature (°C) 60 70 -40 85 Figure 25. Spurious-Free Dynamic Range vs DVDD Supply and Temperature (30 MHz) 92 72 88 71 84 70 80 69 76 68 72 67 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 2 68 2.2 70.9 94 70.7 92 45 50 55 60 Input Clock Duty Cycle (%) 65 90 70 D829 Figure 29. Performance vs Clock Duty Cycle (30 MHz) 22 Submit Documentation Feedback SNR (dBFS) 96 40 70 64 60 61 50 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 2 40 2.2 D828 90 SNR SFDR 70.4 SFDR (dBc) SNR (dBFS) 71.1 35 67 Figure 28. Performance vs Clock Amplitude (150 MHz) SNR SFDR 70.5 30 80 70.6 100 98 90 70 58 0.2 Figure 27. Performance vs Clock Amplitude (40 MHz) 71.3 D826 100 D827 71.5 85 SNR SFDR 73 SNR (dBFS) SNR (dBFS) 73 60 76 100 SNR SFDR 96 74 10 35 Temperature (°C) Figure 26. Signal-to-Noise Ratio vs DVDD Supply and Temperature (30 MHz) SFDR (dBc) 75 -15 D825 SFDR (dBc) -15 88 70.2 86 70 84 69.8 82 69.6 80 69.4 30 35 40 45 50 55 60 Input Clock Duty Cycle (%) 65 SFDR (dBc) 86 -40 78 70 D830 Figure 30. Performance vs Clock Duty Cycle (150 MHz) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 7.16 Typical Characteristics: ADC3422 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -60 -70 -80 -90 -100 -100 -110 -110 -120 0 5 10 15 Frequency (MHz) 20 0 25 5 D601 SFDR = 89 dBc, SNR = 70.9 dBFS, SINAD = 70.8 dBFS, THD = 88 dBc, HD2 = 110 dBc, HD3 = 89 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 20 25 D602 Figure 32. FFT for 10-MHz Input Signal (Dither Off) 0 -40 10 15 Frequency (MHz) SFDR = 85 dBc, SNR = 71.2 dBFS, SINAD = 70.9 dBFS, THD = 83 dBc, HD2 = 92 dBc, HD3 = 85 dBc Figure 31. FFT for 10-MHz Input Signal (Dither On) Amplitude (dBFS) -50 -90 -120 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 5 10 15 Frequency (MHz) 20 25 0 5 D603 SFDR = 101 dBc, SNR = 70.6 dBFS, SINAD = 70.5 dBFS, THD = 98 dBc, HD2 = 106 dBc, HD3 = 101 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 20 25 D604 Figure 34. FFT for 70-MHz Input Signal (Dither Off) 0 -40 10 15 Frequency (MHz) SFDR = 90 dBc, SNR = 70.8 dBFS, SINAD = 70.6 dBFS, THD = 87 dBc, HD2 = 91 dBc, HD3 = 90 dBc Figure 33. FFT for 70-MHz Input Signal (Dither On) Amplitude (dBFS) -40 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 5 10 15 Frequency (MHz) 20 25 D605 SFDR = 86 dBc, SNR = 69.9 dBFS, SINAD = 69.8 dBFS, THD = 85 dBc, HD2 = 93 dBc, HD3 = 86 dBc Figure 35. FFT for 170-MHz Input Signal (Dither On) Copyright © 2014–2015, Texas Instruments Incorporated 0 5 10 15 Frequency (MHz) 20 25 D606 SFDR = 85 dBc, SNR = 70.1 dBFS, SINAD = 70 dBFS, THD = 86 dBc, HD2 = 85 dBc ,HD3 = 112 dBc Figure 36. FFT for 170-MHz Input Signal (Dither Off) Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 23 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics: ADC3422 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -70 -80 -90 -100 -110 -110 -120 5 10 15 Frequency (MHz) 20 25 0 5 D607 SFDR = 75 dBc, SNR = 69 dBFS, SINAD = 67.9 dBFS, THD = 74 dBc, HD2 = 75 dBc, HD3 = 81 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 20 25 D608 Figure 38. FFT for 270-MHz Input Signal (Dither Off) 0 -40 10 15 Frequency (MHz) SFDR = 75 dBc, SNR = 69.2 dBFS, SINAD = 67.9 dBFS, THD = 73 dBc, HD2 = 75 dBc, HD3 = 81 dBc Figure 37. FFT for 270-MHz Input Signal (Dither On) Amplitude (dBFS) -60 -100 0 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 5 10 15 Frequency (MHz) 20 25 0 5 D609 SFDR = 68 dBc, SNR = 67.2 dBFS, SINAD = 67.1 dBFS, THD = –86 dBc, HD2 = 75 dBc, HD3 = 73 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 20 25 D610 Figure 40. FFT for 450-MHz Input Signal (Dither Off) 0 -40 10 15 Frequency (MHz) SFDR = 68 dBc, SNR = 67.5 dBFS, SINAD = 67.4 dBFS, THD = –87 dBc, HD2 = –68 dBc, HD3 = –87 dBc Figure 39. FFT for 450-MHz Input Signal (Dither On) Amplitude (dBFS) -50 -90 -120 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 5 10 15 Frequency (MHz) 20 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 102 dBFS, each tone at –7 dBFS Figure 41. FFT for Two-Tone Input Signal (–7 dBFS at 46 MHz and 50 MHz) 24 -40 Submit Documentation Feedback 25 D611 0 5 10 15 Frequency (MHz) 20 25 D612 fIN1 = 46.3 MHz, fIN2 = 50.3 MHz, IMD3 = 110 dBFS, each tone at –36 dBFS Figure 42. FFT for Two-Tone Input Signal (–36 dBFS at 46 MHz and 50 MHz) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 Typical Characteristics: ADC3422 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 5 10 15 Frequency (MHz) 20 25 0 5 fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 95 dBFS, each tone at –7 dBFS 25 D614 Figure 44. FFT for Two-Tone Input Signal (–36 dBFS at 185 MHz and 190 MHz) -80 -80 -85 -85 Two-Tone IMD (dBFS) Two-Tone IMD (dBFS) 20 fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 105 dBFS, each tone at –36 dBFS Figure 43. FFT for Two-Tone Input Signal (–7 dBFS at 185 MHz and 190 MHz) -90 -95 -100 -105 -110 -35 10 15 Frequency (MHz) D613 -90 -95 -100 -105 -31 -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -110 -35 -7 -31 D615 Figure 45. Intermodulation Distortion vs Input Amplitude (46 MHz and 50 MHz) -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -7 D616 Figure 46. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz) 72 100 Dither_EN Dither_DIS Dither_EN Dither_DIS 95 71 SFDR (dBc) SNR (dBFS) 90 70 69 85 80 75 70 68 65 67 60 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D617 Figure 47. Signal-to-Noise Ratio vs Input Frequency Copyright © 2014–2015, Texas Instruments Incorporated 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D618 Figure 48. Spurious-Free Dynamic Range vs Input Frequency Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 25 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics: ADC3422 (continued) 71 160 70.5 120 70 80 69.5 -60 -50 -40 -30 Amplitude (dBFS) -20 -10 71 240 SNR SFDR SFDR 200 70.5 160 70 120 69.5 80 40 69 40 0 68.5 -70 0 0 -60 -50 D619 Figure 49. Performance vs Input Amplitude (30 MHz) 78 -40 -30 Amplitude (dBFS) -20 -10 D620 Figure 50. Performance vs Input Amplitude (170 MHz) 96 76 88 76 94 74 92 72 90 70 88 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) SNR (dBFS) SNR SFDR SFDR (dBc) SNR (dBFS) SNR SFDR 68 0.85 86 1.1 74 86 72 84 70 82 68 80 66 0.85 D621 Figure 51. Performance vs Input Common-Mode Voltage (30 MHz) 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) 78 1.1 D622 Figure 52. Performance vs Input Common-Mode Voltage (170 MHz) 71.5 96 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 94 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V 71.1 92 SNR (dBFS) SFDR (dBc) 0 SFDR (dBc) 69 -70 71.5 SNR (dBFS) 71.5 240 SNR (dBFS) SFDR (dBc) SFDR (dBFS) 200 SFDR (dBc,dBFS) SNR (dBFS) 72 SFDR (dBc,dBFS) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 90 AVDD = 1.85 V AVDD = 1.9 V 70.7 70.3 88 69.9 86 84 -40 -15 10 35 Temperature (°C) 60 85 D623 Figure 53. Spurious-Free Dynamic Range vs AVDD Supply and Temperature (30 MHz) 26 Submit Documentation Feedback 69.5 -40 -15 10 35 Temperature (°C) 60 85 D624 Figure 54. Signal-to-Noise Ratio vs AVDD Supply and Temperature (30 MHz) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 Typical Characteristics: ADC3422 (continued) Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 74 94 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 73 SFDR (dBc) SFDR (dBc) 92 DVDD = 1.85 V DVDD = 1.9 V 90 88 DVDD = 1.85 V DVDD = 1.9 V 72 71 70 86 69 -15 10 35 Temperature (°C) 60 68 -40 85 74 96 SNR SFDR 71 87 70 84 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 2 78 2.2 76 99 SNR SFDR 96 74 93 72 90 70 87 68 84 66 81 64 78 62 75 60 0.2 0.4 D627 Figure 57. Performance vs Clock Amplitude (40 MHz) 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 90 70.7 88 70.5 86 65 84 70 D629 Figure 59. Performance vs Clock Duty Cycle (30 MHz) Copyright © 2014–2015, Texas Instruments Incorporated SNR (dBFS) 70.9 45 50 55 60 Input Clock Duty Cycle (%) D628 70.6 SFDR (dBc) 92 40 72 2.2 90 SNR SFDR 71.1 35 2 Figure 58. Performance vs Clock Amplitude (150 MHz) 94 SNR SFDR SNR (dBFS) 85 81 71.3 70.3 30 60 70.4 88 70.2 86 70 84 69.8 82 69.6 30 35 40 45 50 55 60 Input Clock Duty Cycle (%) 65 SFDR (dBc) 69 SNR (dBFS) 90 SFDR (dBc) SNR (dBFS) 78 93 72 68 0.2 10 35 Temperature (°C) Figure 56. Signal-to-Noise Ratio vs DVDD Supply and Temperature (30 MHz) Figure 55. Spurious-Free Dynamic Range vs DVDD Supply and Temperature (30 MHz) 73 -15 D625 SFDR (dBc) 84 -40 80 70 D630 Figure 60. Performance vs Clock Duty Cycle (150 MHz) Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 27 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 7.17 Typical Characteristics: ADC3423 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -70 -80 -90 -100 -110 -110 -120 8 16 24 Frequency (MHz) 32 0 40 8 D401 SFDR = 89 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS, THD = 89 dBc, HD2 = 108 dBc, HD3 = 89 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 32 40 D402 Figure 62. FFT for 10-MHz Input Signal (Dither Off) 0 -40 16 24 Frequency (MHz) SFDR = 84 dBc, SNR = 70.9 dBFS, SINAD = 70.7 dBFS, THD = 83 dBc, HD2 = 92 dBc, HD3 = 84 dBc Figure 61. FFT for 10-MHz Input Signal (Dither On) Amplitude (dBFS) -60 -100 0 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 8 16 24 Frequency (MHz) 32 40 0 8 D403 SFDR = 92 dBc, SNR = 70.5 dBFS, SINAD = 70.4 dBFS, THD = 91 dBc, HD2 = 112 dBc, HD3 = 92 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 40 D404 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 32 Figure 64. FFT for 70-MHz Input Signal (Dither Off) 0 -40 16 24 Frequency (MHz) SFDR = 86 dBc, SNR = 70.7 dBFS, SINAD = 70.5 dBFS, THD = 84 dBc, HD2 = 92 dBc, HD3 = 86 dBc Figure 63. FFT for 70-MHz Input Signal (Dither On) Amplitude (dBFS) -50 -90 -120 -120 0 8 16 24 Frequency (MHz) 32 40 D405 SFDR = 87 dBc, SNR = 70.2 dBFS, SINAD = 70.1 dBFS, THD = 93 dBc, HD2 = 102 dBc, HD3 = 87 dBc Figure 65. FFT for 170-MHz Input Signal (Dither On) 28 -40 Submit Documentation Feedback 0 8 16 24 Frequency (MHz) 32 40 D406 SFDR = 86 dBc, SNR = 70.5 dBFS, SINAD = 70.4 dBFS, THD = 88 dBc, HD2 = 86 dBc, HD3 = 97 dBc Figure 66. FFT for 170-MHz Input Signal (Dither Off) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 Typical Characteristics: ADC3423 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -60 -70 -80 -90 -100 -100 -110 -110 -120 0 8 16 24 Frequency (MHz) 32 0 40 8 D407 SFDR = 76 dBc, SNR = 69.2 dBFS, SINAD = 68.3 dBFS, THD = 75 dBc, HD2 = 76 dBc, HD3 = 81 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 32 40 D408 Figure 68. FFT for 270-MHz Input Signal (Dither Off) 0 -40 16 24 Frequency (MHz) SFDR = 75 dBc, SNR = 69.5 dBFS, SINAD = 68.4 dBFS, THD = 75 dBc, HD2 = 75 dBc, HD3 = 82 dBc Figure 67. FFT for 270-MHz Input Signal (Dither On) Amplitude (dBFS) -50 -90 -120 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 8 16 24 Frequency (MHz) 32 40 0 8 D409 SFDR = 68 dBc, SNR = 67.5 dBFS, SINAD = 67.1 dBFS, THD = 77 dBc, HD2 = 68 dBc, HD3 = 89 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 32 40 D410 Figure 70. FFT for 450-MHz Input Signal (Dither Off) 0 -40 16 24 Frequency (MHz) SFDR = 67 dBc SNR = 67.7 dBFS, SINAD = 67.3 dBFS, THD = 77 dBc, HD2 = 67 dBc, HD3 = 84 dBc Figure 69. FFT for 450-MHz Input Signal (Dither On) Amplitude (dBFS) -40 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 8 16 24 Frequency (MHz) 32 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 98 dBFS, each tone at –7 dBFS Figure 71. FFT for Two-Tone Input Signal (–7 dBFS at 46 MHz and 50 MHz) Copyright © 2014–2015, Texas Instruments Incorporated 40 D411 0 8 16 24 Frequency (MHz) 32 40 D412 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 105 dBFS, each tone at –36 dBFS Figure 72. FFT for Two-Tone Input Signal (–36 dBFS at 46 MHz and 50 MHz) Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 29 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics: ADC3423 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 8 16 24 Frequency (MHz) 32 40 0 8 16 24 Frequency (MHz) D413 32 D414 fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 105 dBFS, each tone at –36 dBFS Figure 73. FFT FOR Two-Tone Input Signal (–7 dBFS at 185 MHz and 190 MHz) Figure 74. FFT FOR Two-Tone Input Signal (–36 dBFS at 185 MHz and 190 MHz) -80 -85 Two-Tone IMD (dBFS) -90 -95 -100 -105 -110 -35 -90 -95 -100 -105 -31 -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -110 -35 -7 -31 D415 Figure 75. Intermodulation Distortion vs Input Amplitude (46 MHz and 50 MHz) -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -7 D416 Figure 76. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz) 72 100 Dither_EN Dither_DIS Dither_EN Dither_DIS 95 71 90 SFDR (dBc) SNR (dBFS) 40 fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 90 dBFS, each tone at –7 dBFS -85 Two-Tone IMD (dBFS) -40 70 69 85 80 68 75 67 70 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D417 Figure 77. Signal-to-Noise Ratio vs Input Frequency 30 Submit Documentation Feedback 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D418 Figure 78. Spurious-Free Dynamic Range vs Input Frequency Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 Typical Characteristics: ADC3423 (continued) 71 160 70.5 120 70 80 69.5 40 71 180 SNR (dBFS) SFDR (dBc) 160 SFDR (dBFS) 140 70.5 120 70 100 71.5 69.5 80 69 60 68.5 40 0 -60 -50 -40 -30 Amplitude (dBFS) -20 -10 68 -70 0 20 -60 -50 D419 Figure 79. Performance vs Input Amplitude (30 MHz) 76 -40 -30 Amplitude (dBFS) -20 -10 D421 D420 Figure 80. Performance vs Input Amplitude (170 MHz) 92 76 90 74 90 72 88 70 86 68 84 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) SNR (dBFS) SNR SFDR SFDR (dBc) SNR (dBFS) SNR SFDR 66 0.85 82 1.1 88 72 86 70 84 68 82 D421 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) 80 1.1 D422 Figure 82. Performance vs Input Common-Mode Voltage (170 MHz) 95 71 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 70.8 SNR (dBFS) 93 SFDR (dBc) 74 66 0.85 Figure 81. Performance vs Input Common-Mode Voltage (30 MHz) 91 89 87 85 -40 0 SFDR (dBc) 69 -70 72 SNR (dBFS) 71.5 240 SNR (dBFS) SFDR (dBc) SFDR (dBFS) 200 SFDR (dBc,dBFS) SNR (dBFS) 72 SFDR (dBc,dBFS) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. AVDD = 1.85 V AVDD = 1.9 V 70.6 70.4 70.2 -15 10 35 Temperature (°C) 60 85 D423 Figure 83. Spurious-Free Dynamic Range vs AVDD Supply and Temperature (170 MHz) Copyright © 2014–2015, Texas Instruments Incorporated 70 -40 -15 10 35 Temperature (°C) 60 85 D424 Figure 84. Signal-to-Noise Ratio vs AVDD Supply and Temperature (170 MHz) Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 31 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics: ADC3423 (continued) Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 100 71.5 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 71.1 SNR (dBFS) 92 88 84 DVDD = 1.85 V DVDD = 1.9 V 70.7 70.3 69.9 -15 10 35 Temperature (°C) 60 69.5 -40 85 -15 D425 Figure 85. Spurious-Free Dynamic Range vs DVDD Supply and Temperature (170 MHz) 76 10 35 Temperature (°C) 105 74 99 70 96 68 93 2 SNR (dBFS) 72 SFDR (dBc) SNR (dBFS) 102 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 96 72 92 70 88 68 84 66 80 64 0.2 90 2.2 0.4 D427 Figure 87. Performance vs Clock Amplitude (40 MHz) 71.3 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 88 70.7 86 70.5 84 65 82 70 D429 Figure 89. Performance vs Clock Duty cycle (30 MHz) 32 Submit Documentation Feedback SNR (dBFS) 70.9 45 50 55 60 Input Clock Duty Cycle (%) D428 70.8 SFDR (dBc) SNR (dBFS) 90 40 76 2.2 92 SNR SFDR 71.1 35 2 Figure 88. Performance vs Clock Amplitude (150 MHz) 92 SNR SFDR 70.3 30 D426 SNR SFDR 74 0.4 85 Figure 86. Signal-to-Noise Ratio vs DVDD Supply and Temperature (170 MHz) SNR SFDR 66 0.2 60 SFDR (dBc) 80 -40 70.6 90 70.4 88 70.2 86 70 84 69.8 30 35 40 45 50 55 60 Input Clock Duty Cycle (%) 65 SFDR (dBc) SFDR (dBc) 96 DVDD = 1.85 V DVDD = 1.9 V 82 70 D430 Figure 90. Performance vs Clock Duty Cycle (150 MHz) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 7.18 Typical Characteristics: ADC3424 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 12.5 25 37.5 Frequency (MHz) 50 0 62.5 SFDR = 97 dBc, SNR = 70.4 dBFS, SINAD = 70.4 dBFS, THD = 98 dBc, HD2 = 95 dBc, HD3 = 97 dBc 50 62.5 D202 Figure 92. FFT for 10-MHz Input Signal (Chopper On, Dither Off) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) 25 37.5 Frequency (MHz) SFDR = 91 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS, THD = 86 dBc, HD2 = 92 dBc, HD3 = 91 dBc Figure 91. FFT for 10-MHz Input Signal (Chopper On, Dither On) -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 0 12.5 D203 SFDR = 99 dBc, SNR = 70.3 dBFS, SINAD = 70.3 dBFS, THD = 95 dBc, HD2 = 103 dBc, HD3 = 99 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 62.5 D204 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 50 Figure 94. FFT for 70-MHz Input Signal (Dither Off) 0 -40 25 37.5 Frequency (MHz) SFDR = 91 dBc, SNR = 70.6 dBFS, SINAD = 70.6 dBFS, THD = 87 dBc, HD2 = 91 dBc, HD3 = 95 dBc Figure 93. FFT for 70-MHz Input Signal (Dither On) Amplitude (dBFS) 12.5 D201 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D205 SFDR = 86 dBc, SNR = 69.8 dBFS, SINAD = 69.8 dBFS, THD = 91 dBc, HD2 = 86 dBc, HD3 = 101 dBc Figure 95. FFT for 170-MHz Input Signal (Dither On) Copyright © 2014–2015, Texas Instruments Incorporated 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D206 SFDR = 85 dBc, SNR = 70.3 dBFS, SINAD = 70.2 dBFS, THD = 88 dBc, HD2 = 99 dBc, HD3 = 85 dBc Figure 96. FFT for 170-MHz Input Signal (Dither Off) Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 33 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics: ADC3424 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -70 -80 -90 -100 -110 -110 -120 12.5 25 37.5 Frequency (MHz) 50 62.5 0 12.5 D207 SFDR = 76 dBc, SNR = 68.94 dBFS, SINAD = 68.4 dBFS, THD = 75 dBc, HD2 = 76 dBc, HD3 = 81 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 50 62.5 D208 Figure 98. FFT for 270-MHz Input Signal (Dither Off) 0 -40 25 37.5 Frequency (MHz) SFDR = 76 dBc, SNR = 69.3 dBFS, SINAD = 68.6 dBFS, THD = 75 dBc, HD2 = 76 dBc, HD3 = 82 dBc Figure 97. FFT for 270-MHz Input Signal (Dither On) Amplitude (dBFS) -60 -100 0 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 0 12.5 D209 SFDR = 71 dBc, SNR = 67.2 dBFS, SINAD = 66.5 dBFS, THD = 74 dBc, HD2 = 71 dBc, HD3 = 79 dBc -10 -20 -20 -30 -30 Amplitude (dBFS) 0 -10 -50 -60 -70 -80 50 62.5 D210 Figure 100. FFT for 450-MHz Input Signal (Dither Off) 0 -40 25 37.5 Frequency (MHz) SFDR = 69 dBc, SNR = 67.8 dBFS, SINAD = 66.8 dBFS, THD = 73 dBc, HD2 = 77 dBc, HD3 = 69 dBc Figure 99. FFT for 450-MHz Input Signal (Dither On) Amplitude (dBFS) -50 -90 -120 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 100 dBFS, each tone at –7 dBFS Figure 101. FFT for Two-Tone Input Signal (–7 dBFS at 46 MHz and 50 MHz) 34 -40 Submit Documentation Feedback D211 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D212 fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 99 dBFS, each tone at –36 dBFS Figure 102. FFT for Two-Tone Input Signal (–36 dBFS at 46 MHz and 50 MHz) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 Typical Characteristics: ADC3424 (continued) 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. -40 -50 -60 -70 -80 -60 -70 -80 -90 -100 -100 -110 -110 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 0 12.5 25 37.5 Frequency (MHz) D213 50 62.5 D214 fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 86 dBFS, each tone at –7 dBFS fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 102 dBFS, each tone at –36 dBFS Figure 103. FFT for Two-Tone Input Signal (–7 dBFS at 185 MHz and 190 MHz) Figure 104. FFT for Two-Tone Input Signal (–36 dBFS at 185 MHz and 190 MHz) -80 -80 -85 -85 Two-Tone IMD (dBFS) Two-Tone IMD (dBFS) -50 -90 -120 -90 -95 -100 -105 -110 -35 -90 -95 -100 -105 -31 -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -110 -35 -7 -31 D215 Figure 105. Intermodulation Distortion vs Input Amplitude (46 MHz and 50 MHz) -27 -23 -19 -15 Each Tone Amplitude (dBFS) -11 -7 D216 Figure 106. Intermodulation Distortion vs Input Amplitude (185 MHz and 190 MHz) 100 72 Dither_EN Dither_DIS Dither_EN Dither_DIS 95 SFDR (dBc) 71 SNR (dBFS) -40 70 69 90 85 80 68 75 70 67 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D217 Figure 107. Signal-to-Noise Ratio vs Input Frequency Copyright © 2014–2015, Texas Instruments Incorporated 0 50 100 150 200 250 Frequency (MHz) 300 350 400 D218 Figure 108. Spurious-Free Dynamic Range vs Input Frequency Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 35 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com Typical Characteristics: ADC3424 (continued) 71 160 70.5 120 70 80 69.5 40 71 180 SNR (dBFS) SFDR (dBc) 160 SFDR (dBFS) 140 70.5 120 70 100 71.5 69.5 80 69 60 68.5 40 0 -60 -50 -40 -30 Amplitude (dBFS) -20 -10 68 -70 0 20 -60 -50 D219 Figure 109. Performance vs Input Amplitude (30 MHz) 76 -40 -30 Amplitude (dBFS) -20 -10 D220 Figure 110. Performance vs Input Amplitude (170 MHz) 96 76 88 74 94 72 92 70 90 68 88 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) SNR (dBFS) SNR SFDR SFDR (dBc) SNR (dBFS) SNR SFDR 66 0.85 86 1.1 86 72 84 70 82 68 80 66 0.85 0.9 0.95 1 1.05 Input Common-Mode Voltage (V) 78 1.1 D222 Figure 112. Performance vs Input Common-Mode Voltage (170 MHz) 94 72.5 AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V AVDD = 1.85 V AVDD = 1.9 V AVDD = 1.7 V AVDD = 1.75 V AVDD = 1.8 V 71.7 SFDR (dBc) 92 SFDR (dBc) 74 D221 Figure 111. Performance vs Input Common-Mode Voltage (30 MHz) 90 88 86 AVDD = 1.85 V AVDD = 1.9 V 70.9 70.1 69.3 84 -40 -15 10 35 Temperature (°C) 60 85 D223 Figure 113. Spurious-Free Dynamic Range vs AVDD Supply and Temperature (170 MHz) 36 0 SFDR (dBc) 69 -70 72 SNR (dBFS) 71.5 240 SNR (dBFS) SFDR (dBc) SFDR (dBFS) 200 SFDR (dBc,dBFS) SNR (dBFS) 72 SFDR (dBc,dBFS) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. Submit Documentation Feedback 68.5 -40 -15 10 35 Temperature (°C) 60 85 D224 Figure 114. Signal-to-Noise Ratio vs AVDD Supply and Temperature (170 MHz) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 Typical Characteristics: ADC3424 (continued) Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 71.5 94 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V 71.1 SNR (dBFS) 90 88 70.7 70.3 69.9 86 -15 10 35 Temperature (°C) 60 69.5 -40 85 Figure 115. Spurious-Free Dynamic Range vs DVDD Supply and Temperature (170 MHz) 72.5 73 60 85 D226 105 SNR SFDR 100 72 95 71 95 71 90 70 90 70.5 85 69 85 70 80 68 80 SNR (dBFS) 71.5 SFDR (dBc) SNR (dBFS) 10 35 Temperature (°C) Figure 116. Signal-to-Noise Ratio vs DVDD Supply and Temperature (170 MHz) 105 SNR SFDR 100 72 -15 D225 69.5 75 67 75 69 70 66 70 68.5 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) 2 65 0.2 65 2.2 0.4 D227 Figure 117. Performance vs Clock Amplitude (40 MHz) 71.5 0.6 0.8 1 1.2 1.4 1.6 1.8 Differential Clock Amplitude (Vpp) Figure 118. Performance vs Clock Amplitude (150 MHz) 92 70.3 90 69.9 88 45 50 55 60 Input Clock Duty Cycle (%) 65 86 70 D229 Figure 119. Performance vs Clock Duty Cycle (30 MHz) Copyright © 2014–2015, Texas Instruments Incorporated SNR (dBFS) 70.7 SFDR (dBc) 94 40 D228 90 SNR SFDR 71.1 35 65 2.2 70.5 96 SNR SFDR 69.5 30 2 SFDR (dBc) 84 -40 SNR (dBFS) DVDD = 1.85 V DVDD = 1.9 V 70.3 87.5 70.1 85 69.9 82.5 69.7 80 69.5 30 35 40 45 50 55 60 Input Clock Duty Cycle (%) 65 SFDR (dBc) SFDR (dBc) 92 DVDD = 1.7 V DVDD = 1.75 V DVDD = 1.8 V DVDD = 1.85 V DVDD = 1.9 V 77.5 70 D230 Figure 120. Performance vs Clock Duty Cycle (150 MHz) Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 37 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 7.19 Typical Characteristics: Common Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted. 0 -5 Amplitude (dBFS) -10 PSRR (dB) -15 -20 -25 -30 -35 -40 -45 -50 0 50 100 150 200 250 Frequency of Signal on Supply (MHz) 0 300 -25 Amplitude (dBFS) -30 -35 CMRR (dB) -40 -45 -50 -55 -60 -65 -70 62.5 D002 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 300 12.5 D003 fIN = 30 MHz, AIN = –1 dBFS, test signal amplitude = 50 mVPP Figure 123. Common-Mode Rejection Ratio vs Test Signal Frequency 25 37.5 Frequency (MHz) 50 62.5 D004 fIN = 170.1 MHz, fCMRR = 5 MHz, ACMRR = 50 mVPP, SINAD = 69.66 dBFS, SFDR = 75 dBc Figure 124. Common-Mode Rejection Ratio Spectrum 320 400 Analog Power Digital Power Total Power Analog Power Digital Power Total Power 280 Power Consumption (mW) 360 Power Consumption (mW) 50 Figure 122. Power-Supply Rejection Ratio Spectrum -20 320 280 240 200 160 240 200 160 120 80 120 80 5 15 25 35 45 55 65 75 85 95 105 115 125 Sampling Speed (MSPS) D009 Figure 125. Power vs Sampling Frequency (Two-Wire Mode) 38 25 37.5 Frequency (MHz) fIN = 30.1 MHz, fPSRR = 3 MHz, APSRR = 50 mVPP, SINAD = 58.51 dBFS, SFDR = 60 dBc Figure 121. Power-Supply Rejection Ratio vs Test Signal Frequency 50 100 150 200 250 Frequency of Input Common-Mode Signal (MHz) 12.5 D001 fIN = 30 MHz, AIN = –1 dBFS, test signal amplitude = 50 mVPP 0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 Submit Documentation Feedback 40 10 20 30 40 50 60 Sampling Speed (MSPS) 70 80 D010 Figure 126. Power vs Sampling Frequency (One-Wire Mode) Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 7.20 Typical Characteristics: Contour Typical values are at TA= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc when chopper is disabled and from fS / 2 when is chopper enabled, unless otherwise noted. 120 120 85 89 77 81 73 110 70.5 100 Sampling Frequency, MSPS Sampling Frequency, MSPS 110 69 90 80 85 70 89 73 81 77 69 60 50 40 50 81 85 100 70 150 77 73 67.5 68 90 80 70 70.5 69.5 70 68.5 69 67.5 68 60 50 30 69 200 250 300 Input Frequency, MHz 75 68.5 69 40 85 89 30 69.5 70 100 350 80 400 450 85 66 Figure 127. Spurious-Free Dynamic Range (SFDR) 100 66.5 69.5 70 70.5 50 67 150 68.5 69 68 200 250 300 Input Frequency, MHz 67.5 68 68.5 69 67.5 67 66.5 350 400 450 69.5 70 70.5 Figure 128. Signal-to-Noise Ratio (SNR) 8 Parameter Measurement Information 8.1 Timing Diagrams DAn_P DBn_P Logic 0 VODL = -350 mV Logic 1 (1) VODH = +350 mV (1) DAn_M DBn_M VOCM GND (1) With an external 100-Ω termination. Figure 129. Serial LVDS Output Voltage Levels Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 39 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com Timing Diagrams (continued) CLKIN FCLK DCLK 1-Wire (12x Serialization) Dx0P Dx0M D 9 D 10 D 11 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 0 DCLK Dx0P Dx0M Dx1P Dx1M D 5 D 0 D 1 D 2 D 3 D 4 D 5 D 0 D 11 D 6 D 7 D 8 D 9 D 10 D 11 D 6 SAMPLE N-1 2-Wire (6x Serialization) SAMPLE N+1 SAMPLE N Figure 130. Output Timing Diagram DCLK t HO Dx0P Dx0M t SU Figure 131. Setup and Hold Time 40 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9 Detailed Description 9.1 Overview The ADC342x are a high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS to 125-MSPS, analog-todigital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x family supports a serial low-voltage differential signaling (LVDS) interface in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. 9.2 Functional Block Diagram INAP INAM 12-Bit ADC Digital Encoder and Serializer INBP INBM 12-Bit ADC Digital Encoder and Serializer CLKP CLKM DA0P DA0M DA1P DA1M DB0P DB0M DB1P DB1M Bit Clock DCLKP DCLKM Frame Clock FCLKP FCLKM Divide by 1,2,4 PLL SYSREFP SYSREFM INCP INCM 12-Bit ADC Digital Encoder and Serializer INDP INDM 12-Bit ADC Digital Encoder and Serializer Copyright © 2014–2015, Texas Instruments Incorporated DC1P DC1M DD0P DD0M DD1P DD1M SDOUT SDATA SCLK Configuration Registers SEN Common Mode RESET VCM DC0P DC0M Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 41 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 9.3 Feature Description 9.3.1 Analog Inputs The ADC342x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-Ω source driving 50-Ω termination between INP and INM). 9.3.2 Clock Input The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC342x can be driven by the transformercoupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 132, Figure 133, and Figure 134. See Figure 135 for details regarding the internal clock buffer. 0.1 mF 0.1 mF Zo CLKP Differential Sine-Wave Clock Input CLKP RT Typical LVDS Clock Input 0.1 mF 100 W CLKM Device 0.1 mF Zo NOTE: RT = termination resistor, if necessary. CLKM Figure 132. Differential Sine-Wave Clock Driving Circuit Zo Device Figure 133. LVDS Clock Driving Circuit 0.1 mF CLKP 150 W Typical LVPECL Clock Input 100 W Zo 0.1 mF CLKM Device 150 W Figure 134. LVPECL Clock Driving Circuit 42 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 Clock Buffer LPKG 2 nH 20 Ÿ CLKP CBOND 1 pF 5 kŸ CEQ CEQ RESR 100 Ÿ 0.95 V CEQ LPKG 2 nH 5 kŸ 20 Ÿ CLKM CBOND 1 pF RESR 100 Ÿ NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer. Figure 135. Internal Clock Buffer A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 136. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. 0.1 mF CMOS Clock Input CLKP 0.1 mF CLKM Device Figure 136. Single-Ended Clock Driving Circuit 9.3.2.1 SNR and Clock Jitter The signal-to-noise ratio of the ADC is limited by three different factors, as shown in Equation 1. Quantization noise (typically 74 dB for a 12-bit ADC) and thermal noise limit SNR at low input frequencies, and the clock jitter sets SNR for higher input frequencies. SNRADC[dBc] § 20 ˜ log ¨10 ¨ © SNR Quantizatoin Noise 20 · ¸ ¸ ¹ 2 § ¨10 ¨ © SNR Thermal Noise 20 · ¸ ¸ ¹ 2 § ¨10 ¨ © SNR Jitter 20 · ¸ ¸ ¹ 2 (1) The SNR limitation resulting from sample clock jitter can be calculated with Equation 2. SNRJitter [dBc] 20 ˜ log( 2S ˜ f in ˜ TJitter ) Copyright © 2014–2015, Texas Instruments Incorporated (2) Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 43 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com The total clock jitter (TJitter) has two components: the internal aperture jitter (130 fs for the device) which is set by the noise of the clock input buffer and the external clock. TJitter can be calculated with Equation 3. TJitter (TJitter , Ext .Clock _ Input ) 2 (TAperture _ ADC ) 2 (3) External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input; a faster clock slew rate improves the ADC aperture jitter. The devices have a typical thermal noise of 72.7 dBFS and internal aperture jitter of 130 fs. The SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 137. 71.0 70.5 70.0 SNR (dBFS) 69.5 69.0 68.5 68.0 67.5 67.0 66.5 Ext Clock Jitter 35 fs 50 fs 100 fs 150 fs 200 fs 66.0 65.5 65.0 10 100 Input Frequency (MHz) 1000 D036 D001 Figure 137. SNR vs Frequency for Different Clock Jitter 9.3.3 Digital Output Interface The devices offer two different output format options, thus making interfacing to a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) easy. Each option can be easily programmed using the serial interface, as shown in Table 3. The output interface options are: • One-wire, 1x frame clock, 12x serialization with the DDR bit clock and • Two-wire, 1x frame clock, 6x serialization with the DDR bit clock. Table 3. Interface Rates INTERFACE OPTIONS One-wire Two-wire (Default after Reset) (1) SERIALIZATION RECOMMENDED SAMPLING FREQUENCY (MSPS) MINIMUM MAXIMUM BIT CLOCK FREQUENCY (MHz) FRAME CLOCK FREQUENCY (MHz) SERIAL DATA RATE PER WIRE (Mbps) 90 15 180 480 80 960 60 20 120 375 125 750 15 12x 80 20 (1) 6x 125 Use the LOW SPEED ENABLE register bits for low speed operation; see Table 21. 9.3.3.1 One-Wire Interface: 12x Serialization In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of every frame clock, starting with the LSB. The data rate is 12x sample frequency (12x serialization). 44 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9.3.3.2 Two-Wire Interface: 6x Serialization The two-wire interface is recommended for sampling frequencies above 65 MSPS. The output data rate is 6x sample frequency because six data bits are output every clock cycle on each differential pair. Each ADC sample is sent over the two wires with the six MSBs on Dx1P, Dx1M and the six LSBs on Dx0P, Dx0M, as shown in Figure 138. CLKIN FCLK DCLK 1-Wire (12x Serialization) Dx0P Dx0M D 9 D 10 D 11 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 0 DCLK Dx0P Dx0M Dx1P Dx1M SAMPLE N-1 D 5 D 0 D 1 D 2 D 3 D 4 D 5 D 0 D 11 D 6 D 7 D 8 D 9 D 10 D 11 D 6 SAMPLE N 2-Wire (6x Serialization) SAMPLE N+1 Figure 138. Output Timing Diagram Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 45 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 9.4 Device Functional Modes 9.4.1 Input Clock Divider The devices are equipped with an internal divider on the clock input. The clock divider allows operation with a faster input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed for operation with a 125-MHz clock and the divide-by-2 option supports a maximum input clock of 250 MHz and the divide-by-4 option provides a maximum input clock frequency of 500 MHz. 9.4.2 Chopper Functionality 0 0 -20 -20 -40 -40 Attenuation (dB) Attenuation (dB) The devices are equipped with an internal chopper front-end. Enabling the chopper function swaps the ADC noise spectrum by shifting the 1/f noise from dc to fS / 2. Figure 139 shows the noise spectrum with the chopper off and Figure 140 shows the noise spectrum with the chopper on. This function is especially useful in applications requiring good ac performance at low input frequencies or in dc-coupled applications. The chopper can be enabled via SPI register writes and is recommended for input frequencies below 30 MHz. The chopper function creates a spur at fS / 2 that must be filtered out digitally. -60 -80 -100 -60 -80 -100 -120 -120 0 10 20 30 40 Frequency (MHz) 50 60 0 10 D016 fS = 125 MSPS, SNR = 70.4 dBFS, fIN = 10 MHz, SFDR = 98 dBc 20 30 40 Frequency (MHz) 50 60 D017 fS = 125 MSPS, SNR = 70.4 dBFS, fIN = 10 MHz, SFDR = 97 dBc Figure 139. Chopper Off Figure 140. Chopper On 9.4.3 Power-Down Control The power-down functions of the ADC342x can be controlled either through the parallel control pin (PDN) or through an SPI register setting (see register 15h). The PDN pin can also be configured via SPI to a global powerdown or standby functionality, as shown in Table 4. Table 4. Power-Down Modes FUNCTION 46 POWER CONSUMPTION (mW) WAKE-UP TIME (µs) Global power-down 5 85 Standby 45 35 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9.4.4 Internal Dither Algorithm 0 0 -10 -10 -20 -20 -30 -30 Amplitude (dBFS) Amplitude (dBFS) The ADC342x use an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm can be turned off by using the DIS DITH CHx registers bits. Figure 141 and Figure 142 show the effect of using dither algorithms. -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 12.5 25 37.5 Frequency (MHz) 50 0 62.5 12.5 D201 SFDR = 95 dBc, SNR = 70.4 dBFS, SINAD = 70.4 dBFS, THD = 98 dBc, HD2 = 95 dBc, HD3 = 97 dBc 25 37.5 Frequency (MHz) 50 62.5 D202 SFDR = 91 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS, THD = 86 dBc, HD2 = 92 dBc, HD3 = 91 dBc Figure 141. FFT for 10-MHz Input Signal (Chopper On, Dither On) Figure 142. FFT for 10-MHz Input Signal (Chopper On, Dither Off) 9.4.5 Summary of Performance Mode Registers Table 5 lists the location, value, and functions of performance mode registers in the device. Table 5. Performance Modes MODE REGISTER SETTINGS DESCRIPTION Special modes Registers 139 (bit 3), 239 (bit 3), 439 (bit 3), and 539 (bit 3) Always write 1 for best performance Disable dither Registers 1 (bits 7:0), 134 (bits 5 and 3), 234 (bits 5 and 3), 434 (bits 5 and 3), and 534 (bits 5 and 3) Disable dither to improve SNR Disable chopper Registers 122 (bit 1), 222 (bit 1), 422 (bit 1), and 522 (bit 1) High IF modes Registers 11Dh (bit 1), 21Dh (bit 1), 41Dh (bit 1), 51Dh (bit 1), 308h (bits 7-6) and 608h (bits 7-6) Disable chopper (shifts 1/f noise floor at dc) Improves HD3 by a couple of dB for IF > 100 MHz 9.5 Programming The ADC342x can be configured using a serial programming interface, as described in this section. 9.5.1 Serial Interface The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 47 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com Programming (continued) 9.5.1.1 Register Initialization After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 143. If required, the serial interface registers can be cleared during operation either: 1. Through a hardware reset, or 2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low. 9.5.1.1.1 Serial Register Write The device internal register can be programmed with these steps: 1. Drive the SEN pin low, 2. Set the R/W bit to 0 (bit A15 of the 16-bit address), 3. Set bit A14 in the address field to 1, 4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be written, and 5. Write the 8-bit data that are latched in on the SCLK rising edge. Figure 143 and Table 6 show the timing requirements for the serial register write operation. Register Address [13:0] SDATA R/W 1 A13 A12 A11 A1 Register Data [7:0] A0 D7 D6 D5 D4 =0 D3 D2 D1 D0 tDH tSCLK tDSU SCLK tSLOADS tSLOADH SEN RESET Figure 143. Serial Register Write Timing Diagram Table 6. Serial Interface Timing (1) MIN TYP UNIT 20 MHz fSCLK SCLK frequency (equal to 1 / tSCLK) tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDSU SDIO setup time 25 ns tDH SDIO hold time 25 ns (1) 48 > dc MAX Typical values are at 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, and AVDD = DVDD = 1.8 V, unless otherwise noted. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9.5.1.1.2 Serial Register Readout The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin. This readback mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. The procedure to read the contents of the serial registers is as follows: 1. Drive the SEN pin low. 2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers. 3. Set bit A14 in the address field to 1. 4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read. 5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin. 6. The external controller can latch the contents at the SCLK rising edge. 7. To enable register writes, reset the R/W register bit to 0. When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 144 shows a timing diagram of the serial register read operation. Data appear on the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 145. Register Data: 'RQ¶W &DUH Register Address [13:0] SDATA R/W 1 A13 A12 A11 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 =1 Register Read Data [7:0] SDOUT D7 D6 D5 D4 D3 D2 SCLK SEN Figure 144. Serial Register Read Timing Diagram SCLK tSD_DELAY SDOUT Figure 145. SDOUT Timing Diagram Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 49 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 9.5.2 Register Initialization After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 146 and Table 7. Power Supplies t1 RESET t2 t3 SEN Figure 146. Initialization of Serial Registers after Power-Up Table 7. Power-Up Timing MIN t1 Power-on delay from power-up to active high RESET pulse t2 t3 TYP MAX UNIT 1 ms Reset pulse duration: active high RESET pulse duration 10 ns Register write delay from RESET disable to SEN active 100 ns If required, the serial interface registers can be cleared during operation either: 1. Through hardware reset, or 2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low. 50 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9.6 Register Maps Table 8. Register Map Summary REGISTER ADDRESS, A[13:0] (Hex) REGISTER DATA 7 Register 01h 6 5 DIS DITH CHA 4 3 DIS DITH CHB 2 1 DIS DITH CHC 0 DIS DITH CHD Register 03h 0 0 0 0 0 0 0 ODD EVEN Register 04h 0 0 0 0 0 0 0 FLIP WIRE Register 05h 0 0 0 0 0 0 0 1W-2W RESET Register 06h 0 0 0 0 0 0 TEST PATTERN EN Register 07h 0 0 0 0 0 0 0 OVR ON LSB Register 09h 0 0 0 0 0 0 ALIGN TEST PATTERN DATA FORMAT Register 0Ah CHA TEST PATTERN CHB TEST PATTERN Register 0Bh CHC TEST PATTERN 0 CHD TEST PATTERN Register 0Eh CUSTOM PATTERN[11:4] Register 0Fh CUSTOM PATTERN[3:0] 0 0 Register 13h 0 0 0 0 0 0 Register 15h CHA PDN CHB PDN CHC PDN CHD PDN STANDBY GLOBAL PDN 0 0 Register 25h 0 0 LOW SPEED ENABLE 0 CONFIG PDN PIN 0 0 0 0 LVDS SWING Register 27h CLK DIV 0 Register 11Dh 0 0 0 0 0 0 HIGH IF MODE0 Register 122h 0 0 0 0 0 0 DIS CHOP CHA 0 Register 134h 0 0 DIS DITH CHA 0 DIS DITH CHA 0 0 0 Register 139h 0 0 0 0 SP1 CHA 0 0 0 0 Register 21Dh 0 0 0 0 0 0 HIGH IF MODE1 Register 222h 0 0 0 0 0 0 DIS CHOP CHD 0 Register 234h 0 0 DIS DITH CHD 0 DIS DITH CHD 0 0 0 Register 239h 0 0 0 0 SP1 CHD 0 0 0 0 0 0 0 0 0 0 Register 308 HIGH IF MODE Register 41Dh 0 0 0 0 0 0 HIGH IF MODE2 Register 422h 0 0 0 0 0 0 DIS CHOP CHB 0 Register 434h 0 0 DIS DITH CHB 0 DIS DITH CHB 0 0 0 Register 439h 0 0 0 0 SP1 CHB 0 0 0 0 Register 51Dh 0 0 0 0 0 0 HIGH IF MODE3 Register 522h 0 0 0 0 0 0 DIS CHOP CHC 0 Register 534h 0 0 DIS DITH CHC 0 DIS DITH CHC 0 0 0 Register 539h 0 0 0 0 SP1 CHC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDN SYSREF Register 608h Register 70Ah HIGH IF MODE 0 0 Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 51 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 9.6.1 Serial Register Description 9.6.1.1 Register 01h (address = 01h) Figure 147. Register 01h 7 6 5 DIS DITH CHA R/W-0h 4 3 DIS DITH CHB R/W-0h 2 DIS DITH CHC R/W-0h 1 0 DIS DITH CHD R/W-0h LEGEND: R/W = Read/Write; -n = value after reset Table 9. Register 01h Field Descriptions Bit Field Type Reset Description 7-6 DIS DITH CHA R/W 0h These bits enable or disable the on-chip dither. Control this bit along with bits 5 and 3 of register 134h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 5-4 DIS DITH CHB R/W 0h These bits enable or disable the on-chip dither. Control this bit along with bits 5 and 3 of register 434h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 3-2 DIS DITH CHC R/W 0h These bits enable or disable the on-chip dither. Control this bit along with bits 5 and 3 of register 534h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 1-0 DIS DITH CHD R/W 0h These bits enable or disable the on-chip dither. Control this bit along with bits 5 and 3 of register 234h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 9.6.1.2 Register 03h (address = 03h) Figure 148. Register 03h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 ODD EVEN R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 10. Register 03h Field Descriptions Bit Field Type Reset Description 7-6 0 W 0h Must write 0. ODD EVEN R/W 0h This bit selects the bit sequence on the output wires (in 2-wire mode only). 0 = Bits 0, 1, 2, and so forth appear on wire-0; bits 7, 8, 9, and so forth appear on wire-1. 1 = Bits 0, 2, 4, and so forth appear on wire-0; bits 1, 3, 5, and so forth appear on wire-1. 0 52 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9.6.1.3 Register 04h (address = 04h) Figure 149. Register 04h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 FLIP WIRE R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 11. Register 04h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0. FLIP WIRE R/W 0h This bit flips the data on the output wires. Valid only in two wire configuration. 0 = Default 1 = Data on output wires is flipped. Pin D0x becomes D1x, and vice versa. 0 9.6.1.4 Register 05h (address = 05h) Figure 150. Register 05h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 1W-2W R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 12. Register 05h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0. 1W-2W R/W 0h This bit transmits output data on either one or two wires. 0 = Output data are transmitted on two wires (Dx0P, Dx0M and Dx1P, Dx1M) 1 = Output data are transmitted on one wire (Dx0P, Dx0M). In this mode, the recommended fS is less than 80 MSPS. 0 9.6.1.5 Register 06h (address = 06h) Figure 151. Register 06h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 TEST PATTERN EN R/W-0h 0 RESET R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 13. Register 06h Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1 TEST PATTERN EN R/W 0h This bit enables test pattern selection for the digital outputs. 0 = Normal output 1 = Test pattern output enabled 0 RESET R/W 0h This bit applies a software reset. This bit resets all internal registers to the default values and selfclears to 0. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 53 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 9.6.1.6 Register 07h (address = 07h) Figure 152. Register 07h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 OVR ON LSB R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 14. Register 07h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0. OVR ON LSB R/W 0h This bit provides OVR information on the LSB bits. 0 = Output data bit 0 functions as the LSB of the 12-bit data 1 = Output data bit 0 carries the overrange (OVR) information 0 9.6.1.7 Register 09h (address = 09h) Figure 153. Register 09h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 ALIGN TEST PATTERN R/W-0h 0 DATA FORMAT R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 15. Register 09h Field Descriptions 54 Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1 ALIGN TEST PATTERN R/W 0h This bit aligns the test patterns across the outputs of both channels. 0 = Test patterns of both channels are free running 1 = Test patterns of both channels are aligned 0 DATA FORMAT R/W 0h This bit selects th digital output data format. 0 = Twos complement 1 = Offset binary Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9.6.1.8 Register 0Ah (address = 0Ah) Figure 154. Register 0Ah 7 6 5 CHA TEST PATTERN R/W-0h 4 3 2 1 CHB TEST PATTERN R/W-0h 0 LEGEND: R/W = Read/Write; -n = value after reset Table 16. Register 0Ah Field Descriptions Bit Field Type Reset Description 7-4 CHA TEST PATTERN R/W 0h These bits control the test pattern for channel A after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 101010101010 and 010101010101 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits 0110 = Deskew pattern: data are AAAh 1000 = PRBS pattern: data are a sequence of pseudo random numbers 1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, and 599 Others = Do not use 3-0 CHB TEST PATTERN R/W 0h These bits control the test pattern for channel B after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 101010101010 and 010101010101 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095 0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits 0110 = Deskew pattern: data are AAAh 1000 = PRBS pattern: data are a sequence of pseudo random numbers 1001 = 8-point sine-wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, and 599 Others = Do not use Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 55 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 9.6.1.9 Register 0Bh (address = 0Bh) Figure 155. Register 0Bh 7 6 5 CHC TEST PATTERN R/W-0h 4 3 2 1 CHD TEST PATTERN R/W-0h 0 LEGEND: R/W = Read/Write; -n = value after reset Table 17. Register 0Bh Field Descriptions Bit Field Type Reset Description 7-4 CHC TEST PATTERN R/W 0h These bits control the test pattern for channel C after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 101010101010 and 010101010101. 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095. 0110 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 1000 = Deskew pattern: data are AAAh. 1010 = PRBS pattern: data are a sequence of pseudo random numbers. 1011 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use 3-0 CHD TEST PATTERN R/W 0h These bits control the test pattern for channel D after the TEST PATTERN EN bit is set. 0000 = Normal operation 0001 = All 0's 0010 = All 1's 0011 = Toggle pattern: data alternate between 101010101010 and 010101010101. 0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 4095. 0110 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register bits. 1000 = Deskew pattern: data are AAAh. 1010 = PRBS pattern: data are a sequence of pseudo random numbers. 1011 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a sine-wave: 0, 599, 2048, 3496, 4095, 3496, 2048, 599. Others = Do not use 9.6.1.10 Register 0Eh (address = 0Eh) Figure 156. Register 0Eh 7 6 5 4 3 CUSTOM PATTERN[11:4] R/W-0h 2 1 0 LEGEND: R/W = Read/Write; -n = value after reset Table 18. Register 0Eh Field Descriptions 56 Bit Field Type Reset Description 7-0 CUSTOM PATTERN[11:4] R/W 0h These bits set the 12-bit custom pattern (bits 11-4) for all channels. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9.6.1.11 Register 0Fh (address = 0Fh) Figure 157. Register 0Fh 7 6 5 CUSTOM PATTERN[3:0] R/W-0h 4 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 19. Register 0Fh Field Descriptions Bit Field Type Reset Description 7-4 CUSTOM PATTERN[3:0] R/W 0h These bits set the 12-bit custom pattern (bits 3-0) for all channels. 3-0 0 W 0h Must write 0. 9.6.1.12 Register 13h (address = 13h) Figure 158. Register 13h 7 0 W-0h 6 0 R/W-0h 5 0 R/W-0h 4 0 W-0h 3 0 R/W-0h 2 0 R/W-0h 1 0 LOW SPEED ENABLE W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 20. Register 13h Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1-0 LOW SPEED ENABLE R/W 0h Enables low speed operation in 1-wire and 2-wire mode. Depending upon sampling frequency, write this bit as per Table 21. Table 21. LOW SPEED ENABLE Register Settings Across fS fS, MSPS REGISTER BIT LOW SPEED ENABLE MIN MAX 1-WIRE MODE 2-WIRE MODE 25 125 00 00 20 25 10 11 15 20 10 Not supported Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 57 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 9.6.1.13 Register 15h (address = 15h) Figure 159. Register 15h 7 6 5 4 3 2 1 CHA PDN CHB PDN CHC PDN CHD PDN STANDBY GLOBAL PDN 0 W-0h R/W-0h R/W-0h W-0h R/W-0h R/W-0h W-0h 0 CONFIG PDN PIN R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 22. Register 15h Field Descriptions Bit Field Type Reset Description 7 CHA PDN W 0h 0 = Normal operation 1 = Power-down channel A 6 CHB PDN R/W 0h 0 = Normal operation 1 = Power-down channel B 5 CHC PDN R/W 0h 0 = Normal operation 1 = Power-down channel C 4 CHD PDN W 0h 0 = Normal operation 1 = Power-down channel D 3 STANDBY R/W 0h The ADCs of both channels enter standby. 0 = Normal operation 1 = Standby 2 GLOBAL PDN R/W 0h 0 = Normal operation 1 = Global power-down 1 0 W 0h Must write 0. 0 CONFIG PDN PIN R/W 0h This bit configures the PDN pin as either a global power-down or standby pin. 0 = Logic high voltage on the PDN pin sends the device into global power-down 1 = Logic high voltage on the PDN pin sends the device into standby 9.6.1.14 Register 25h (address = 25h) Figure 160. Register 25h 7 6 5 4 3 2 1 0 LVDS SWING R/W-0h LEGEND: R/W = Read/Write; -n = value after reset Table 23. Register 25h Field Descriptions 58 Bit Field Type Reset Description 7-0 LVDS SWING R/W 0h These bits control the swing of the LVDS outputs (including the data output, bit clock, and frame clock). Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9.6.1.15 Register 27h (address = 27h) Figure 161. Register 27h 7 6 CLK DIV R/W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 24. Register 27h Field Descriptions Bit Field Type Reset Description 7-6 CLK DIV R/W 0h These bits select the internal clock divider for the input sampling clock. 00 = Divide-by-1 01 = Divide-by-1 10 = Divide-by-2 11 = Divide-by-4 5-0 0 W 0h Must write 0. 9.6.1.16 Register 11Dh (address = 11Dh) Figure 162. Register 11Dh 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 HIGH IF MODE0 R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 25. Register 11Dh Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1 HIGH IF MODE0 0 0 Set the HIGH IF MODE[7:0] bits together to 1111. Improves HD3 by a couple of dB for IF > 100 MHz. W 0h Must write 0. 9.6.1.17 Register 122h (address = 122h) Figure 163. Register 122h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 DIS CHOP CHA R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 26. Register 122h Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1 DIS CHOP CHA R/W 0h This bit disables the chopper. Set this bit to shift the 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc 0 0 W 0h Must write 0. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 59 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 9.6.1.18 Register 134h (address = 134h) Figure 164. Register 134h 7 0 W-0h 6 0 W-0h 5 DIS DITH CHA R/W-0h 4 0 W-0h 3 DIS DITH CHA R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 27. Register 134h Field Descriptions Bit Field Type Reset Description 7-6 0 W 0h Must write 0. 5 DIS DITH CHA R/W 0h Set this bit along with bits 7 and 6 of register 01h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 4 0 W 0h Must write 0. 3 DIS DITH CHA R/W 0h Set this bit along with bits 7 and 6 of register 01h. 00 = Default 11 = Dither is disabled for channel A. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 0 W 0h Must write 0. 2-0 9.6.1.19 Register 139h (address = 139h) Figure 165. Register 139h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 SP1 CHA R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 28. Register 139h Field Descriptions Bit Field Type Reset Description 7-4 0 W 0h Must write 0. SP1 CHA R/W 0h This bit sets the special mode for best performance on channel A. Always write 1 after reset. 0 W 0h Must write 0. 3 2-0 9.6.1.20 Register 21Dh (address = 21Dh) Figure 166. Register 21Dh 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 HIGH IF MODE1 R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 29. Register 21Dh Field Descriptions 60 Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1 HIGH IF MODE1 R/W 0h Set the HIGH IF MODE[7:0] bits together to 1111. Improves HD3 by a couple of dB for IF > 100 MHz. 0 0 W 0h Must write 0. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9.6.1.21 Register 222h (address = 222h) Figure 167. Register 222h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 DIS CHOP CHD R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 30. Register 222h Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1 DIS CHOP CHD R/W 0h This bit disables the chopper. Set this bit to shift the 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc 0 0 W 0h Must write 0. 9.6.1.22 Register 234h (address = 234h) Figure 168. Register 234h 7 0 W-0h 6 0 W-0h 5 DIS DITH CHD R/W-0h 4 0 W-0h 3 DIS DITH CHD R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 31. Register 234h Field Descriptions Bit Field Type Reset Description 7-6 0 W 0h Must write 0. 5 DIS DITH CHD R/W 0h Set this bit with bits 1 and 0 of register 01h. 00 = Default 11 = Dither is disabled for channel D. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 4 0 W 0h Must write 0. 3 DIS DITH CHD R/W 0h Set this bit with bits 1 and 0 of register 01h. 00 = Default 11 = Dither is disabled for channel D. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 0 W 0h Must write 0. 2-0 Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 61 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 9.6.1.23 Register 239h (address = 239h) Figure 169. Register 239h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 SP1 CHD R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 32. Register 239h Field Descriptions Bit Field Type Reset Description 7-4 0 W 0h Must write 0. SP1 CHD R/W 0h This bit sets the special mode for best performance on channel D. Always write 1 after reset. 0 W 0h Must write 0. 3 2-0 9.6.1.24 Register 308h (address = 308h) Figure 170. Register 308h 7 6 HIGH IF MODE W-0h W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 33. Register 308h Field Descriptions Bit Field Type Reset Description 7-6 HIGH IF MODE R/W 0h Set the HIGH IF MODE[7:0] bits together to FFh. Improves HD3 by a couple of dB for IF > 100 MHz. 5-0 0 W 0h Must write 0. 9.6.1.25 Register 41Dh (address = 41Dh) Figure 171. Register 41Dh 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 HIGH IF MODE2 R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 34. Register 41Dh Field Descriptions 62 Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1 HIGH IF MODE2 R/W 0h Set the HIGH IF MODE[7:0] bits together to FFh. Improves HD3 by a couple of dB for IF > 100 MHz. 0 0 W 0h Must write 0. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9.6.1.26 Register 422h (address = 422h) Figure 172. Register 422h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 DIS CHOP CHB R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 35. Register 422h Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1 DIS CHOP CHB R/W 0h This bit disables the chopper. Set this bit to shift the 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc 0 0 W 0h Must write 0. 9.6.1.27 Register 434h (address = 434h) Figure 173. Register 434h 7 0 W-0h 6 0 W-0h 5 DIS DITH CHB R/W-0h 4 0 W-0h 3 DIS DITH CHB R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 36. Register 434h Field Descriptions Bit Field Type Reset Description 7-6 0 W 0h Must write 0. 5 DIS DITH CHB R/W 0h Set this bit with bits 5 and 4 of register 01h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 4 0 W 0h Must write 0. 3 DIS DITH CHB R/W 0h Set this bit with bits 5 and 4 of register 01h. 00 = Default 11 = Dither is disabled for channel B. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 0 W 0h Must write 0. 2-0 Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 63 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 9.6.1.28 Register 439h (address = 439h) Figure 174. Register 439h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 SP1 CHB R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 37. Register 439h Field Descriptions Bit Field Type Reset Description 7-4 0 W 0h Must write 0. SP1 CHB R/W 0h This bit sets the special mode for best performance on channel B. Always write 1 after reset. 0 W 0h Must write 0. 3 2-0 9.6.1.29 Register 51Dh (address = 51Dh) Figure 175. Register 51Dh 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 HIGH IF MODE3 R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 38. Register 51Dh Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1 HIGH IF MODE3 R/W 0h Set the HIGH IF MODE[7:0] bits together to FFh. Improves HD3 by a couple of dB for IF > 100 MHz. 0 0 W 0h Must write 0. 9.6.1.30 Register 522h (address = 522h) Figure 176. Register 522h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 DIS CHOP CHC R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 39. Register 522h Field Descriptions 64 Bit Field Type Reset Description 7-2 0 W 0h Must write 0. 1 DIS CHOP CHC R/W 0h This bit disables the chopper. Set this bit to shift the 1/f noise floor at dc. 0 = 1/f noise floor is centered at fS / 2 (default) 1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc 0 0 W 0h Must write 0. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 9.6.1.31 Register 534h (address = 534h) Figure 177. Register 534h 7 0 W-0h 6 0 W-0h 5 DIS DITH CHC R/W-0h 4 0 W-0h 3 DIS DITH CHC R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 40. Register 534h Field Descriptions Bit Field Type Reset Description 7-6 0 W 0h Must write 0. 5 DIS DITH CHC R/W 0h Set this bit with bits 3 and 2 of register 01h. 00 = Default 11 = Dither is disabled for channel C. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 4 0 W 0h Must write 0. 3 DIS DITH CHC R/W 0h Set this bit with bits 3 and 2 of register 01h. 00 = Default 11 = Dither is disabled for channel C. In this mode, SNR typically improves by 0.2 dB at 70 MHz. 0 W 0h Must write 0. 2-0 9.6.1.32 Register 539h (address = 539h) Figure 178. Register 539h 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 SP1 CHC R/W-0h 2 0 W-0h 1 0 W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 41. Register 539h Field Descriptions Bit Field Type Reset Description 7-4 0 W 0h Must write 0. SP1 CHC R/W 0h This bit sets the special mode for best performance on channel C. Always write 1 after reset. 0 W 0h Must write 0. 3 2-0 9.6.1.33 Register 608h (address = 608h) Figure 179. Register 608h 7 6 HIGH IF MODE W-0h W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 R/W-0h 0 0 W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 42. Register 608h Field Descriptions Bit Field Type Reset Description 7-6 HIGH IF MODE R/W 0h Set the HIGH IF MODE[7:0] bits together to FFh. Improves HD3 by a couple of dB for IF > 100 MHz. 5-0 0 W 0h Must write 0. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 65 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 9.6.1.34 Register 70Ah (address = 70Ah) Figure 180. Register 70Ah 7 0 W-0h 6 0 W-0h 5 0 W-0h 4 0 W-0h 3 0 W-0h 2 0 W-0h 1 0 W-0h 0 PDN SYSREF R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 43. Register 70Ah Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0. PDN SYSREF R/W 0h If the SYSREF pins are not used in the system, the SYSREF buffer must be powered down by setting this bit. 0 = Normal operation 1 = Powers down the SYSREF buffer 0 10 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC inputs. When designing the dc driving circuits, the ADC input impedance must be considered. Figure 181 and Figure 182 show the impedance (Zin = Rin || Cin) across the ADC input pins. 6 Differential Capacitance, Cin (pF) Differential Resistance, Rin (kOhm) 10 1 0.1 4 3 2 1 0.01 0 100 200 300 400 500 600 700 Frequency (MHz) 800 900 1000 Figure 181. Differential Input Resistance, RIN 66 5 Submit Documentation Feedback D024 0 100 200 300 400 500 600 700 Frequency (MHz) 800 900 1000 D025 D001 Figure 182. Differential Input Capacitance, CIN Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 10.2 Typical Applications 10.2.1 Driving Circuit Design: Low Input Frequencies 39 nH 0.1 PF INP 0.1 PF 50 Ÿ 0.1 PF 50 Ÿ 25 Ÿ 22 pF 25 Ÿ 50 Ÿ 50 Ÿ INM 1:1 1:1 0.1 PF 39 nH VCM Device Figure 183. Driving Circuit for Low Input Frequencies 10.2.1.1 Design Requirements For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in series with each input pin can be kept to damp out ringing caused by package parasitic. The drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched impedance to the source. 10.2.1.2 Detailed Design Procedure A typical application involving using two back-to-back coupled transformers is illustrated in Figure 183. The circuit is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used with the series inductor (39 nH), this combination helps absorb the sampling glitches. 10.2.1.3 Application Curve Figure 184 shows the performance obtained by using the circuit shown in Figure 183. 0 -10 -20 Amplitude (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D201 SFDR = 97 dBc, SNR = 70.4 dBFS, SINAD = 70.4 dBFS, THD = 98 dBc, HD2 = 95 dBc, HD3 = 97 dBc Figure 184. Performance FFT at 10 MHz (Low Input Frequency) Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 67 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com Typical Applications (continued) 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz 0.1 PF 10 Ÿ INP 0.1 PF 0.1 PF 15 Ÿ 25 Ÿ 56 nH 10 pF 25 Ÿ 15 Ÿ INM 1:1 1:1 10 Ÿ 0.1 PF VCM Device Figure 185. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz) 10.2.2.1 Design Requirements See the Design Requirements section for further details. 10.2.2.2 Detailed Design Procedure When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize performance, as shown in Figure 185. 10.2.2.3 Application Curve Figure 186 shows the performance obtained by using the circuit shown in Figure 185. 0 -10 -20 Amplitude (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D205 SFDR = 86 dBc, SNR = 69.8 dBFS, SINAD = 69.8 dBFS, THD = 91 dBc, HD2 = 86 dBc, HD3 = 101 dBc Figure 186. Performance FFT at 170 MHz (Mid Input Frequency) 68 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 Typical Applications (continued) 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz 0.1 PF 0.1 PF 10 Ÿ INP 0.1 PF 25 Ÿ 25 Ÿ INM 1:1 1:1 10 Ÿ 0.1 PF VCM Device Figure 187. Driving Circuit for High Input Frequencies (fIN > 230 MHz) 10.2.3.1 Design Requirements See the Design Requirements section for further details. 10.2.3.2 Detailed Design Procedure For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 187. 10.2.3.3 Application Curve Figure 188 shows the performance obtained by using the circuit shown in Figure 187. 0 -10 -20 Amplitude (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 12.5 25 37.5 Frequency (MHz) 50 62.5 D209 SFDR = 71 dBc, SNR = 67.2 dBFS, SINAD = 66.5 dBFS, THD = 74 dBc, HD2 = 71 dBc, HD3 = 79 dBc Figure 188. Performance FFT at 450 MHz (High Input Frequency) 11 Power Supply Recommendations The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply requirements during device power-up. AVDD and DVDD can power up in any order. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 69 ADC3421, ADC3422, ADC3423, ADC3424 SBAS673A – JULY 2014 – REVISED OCTOBER 2015 www.ti.com 12 Layout 12.1 Layout Guidelines The ADC342x EVM layout can be used as a reference layout to obtain the best performance. A layout diagram of the EVM top layer is provided in Figure 189. Some important points to remember during laying out the board are: 1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the package level. To minimize crosstalk onboard, the analog inputs must exit the pin out in opposite directions, as shown in the reference layout of Figure 189 as much as possible. 2. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to minimize coupling between them. This configuration is also maintained on the reference layout of Figure 189 as much as possible. 3. Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, the digital output traces must not be kept parallel to the analog input traces because this configuration can result in coupling from digital outputs to analog inputs and degrade performance. All digital output traces to the receiver [such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] must be matched in length to avoid skew among outputs. 4. At each power-supply pin (AVDD and DVDD), keep a 0.1-µF decoupling capacitor close to the device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF capacitors can be kept close to the supply source. 12.2 Layout Example Analog Input Routing Sampling Clock Routing ADC34xx Digital Output Routing Figure 189. Typical Layout of the ADC342x Board 70 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 ADC3421, ADC3422, ADC3423, ADC3424 www.ti.com SBAS673A – JULY 2014 – REVISED OCTOBER 2015 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 44. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ADC3421 Click here Click here Click here Click here Click here ADC3422 Click here Click here Click here Click here Click here ADC3423 Click here Click here Click here Click here Click here ADC3424 Click here Click here Click here Click here Click here 13.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.3 Trademarks E2E is a trademark of Texas Instruments. PowerPAD is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ADC3421 ADC3422 ADC3423 ADC3424 71 PACKAGE OPTION ADDENDUM www.ti.com 20-Jan-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADC3421IRTQR ACTIVE QFN RTQ 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3421 ADC3421IRTQT ACTIVE QFN RTQ 56 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3421 ADC3422IRTQR ACTIVE QFN RTQ 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3422 ADC3422IRTQT ACTIVE QFN RTQ 56 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3422 ADC3423IRTQR ACTIVE QFN RTQ 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3423 ADC3423IRTQT ACTIVE QFN RTQ 56 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3423 ADC3424IRTQR ACTIVE QFN RTQ 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3424 ADC3424IRTQT ACTIVE QFN RTQ 56 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ3424 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 20-Jan-2017 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADC3421IRTQR QFN RTQ 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 ADC3421IRTQT QFN RTQ 56 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 ADC3422IRTQR QFN RTQ 56 2000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 ADC3422IRTQT QFN RTQ 56 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 ADC3423IRTQR QFN RTQ 56 2000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 ADC3423IRTQT QFN RTQ 56 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 ADC3424IRTQR QFN RTQ 56 2000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 ADC3424IRTQT QFN RTQ 56 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC3421IRTQR QFN RTQ 56 2000 336.6 336.6 28.6 ADC3421IRTQT QFN RTQ 56 250 213.0 191.0 55.0 ADC3422IRTQR QFN RTQ 56 2000 336.6 336.6 28.6 ADC3422IRTQT QFN RTQ 56 250 213.0 191.0 55.0 ADC3423IRTQR QFN RTQ 56 2000 336.6 336.6 28.6 ADC3423IRTQT QFN RTQ 56 250 213.0 191.0 55.0 ADC3424IRTQR QFN RTQ 56 2000 336.6 336.6 28.6 ADC3424IRTQT QFN RTQ 56 250 213.0 191.0 55.0 Pack Materials-Page 2 IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you (individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of this Notice. 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