ADC3541, ADC3542
SBAS840B – JULY 2020 – REVISED APRIL 2022
ADC354x 14-bit, 10-MSPS to 65-MSPS, Low-noise, Ultra-low Power ADC
1 Features
3 Description
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•
•
The ADC3541, ADC3542 and ADC3543 (ADC354x)
family of devices are low-noise, ultra-low power,
14-bit, 10 to 65-MSPS, high-speed analog-todigital converters (ADCs). Designed for low power
consumption, these devices deliver a noise spectral
density of –155 dBFS/Hz. The ADC354x offers great
dc precision together with IF sampling support,
which make these devices an excellent choice for a
wide range of applications. High-speed control loops
benefit from the short latency of only one clock cycle.
The ADC consumes only 79 mW at 65 MSPS, and
the power consumption scales very well with lower
sampling rates.
•
•
•
•
•
•
•
•
•
•
•
14-bit 10/25/65 MSPS ADC
Noise floor: –155 dBFS/Hz
Ultra-low power with optimized power scaling:
35 mW (10 MSPS) to 84 mW (65 MSPS)
Latency: 1 clock cycle
INL: ±0.6 LSB; DNL: ±0.1 LSB
Reference: external or internal
Input Bandwidth: 900 MHz (3-dB)
Industrial temperature range: –40°C to +105°C
On-chip digital filter (optional)
– Decimation by 2, 4, 8, 16, 32
– 32-bit NCO
SDR/DDR and Serial CMOS interface
Small footprint: 40-WQFN (5 mm × 5 mm) package
Single 1.8-V supply
Spectral Performance (fIN = 10 MHz):
– SNR: 79.0 dBFS
– SFDR: 87 dBc HD2, HD3
– SFDR: 99 dBFS Worst Spur
Spectral Performance (fIN = 64 MHz):
– SNR: 78.0 dBFS
– SFDR: 70 dBc HD2, HD3
– SFDR: 91 dBFS Worst Spur
The ADC354x uses an SDR, DDR or a serial
CMOS interface to output the data offering the lowest
power digital interface, together with the flexibility
to minimize the number of digital interconnects.
These devices are a pin-to-pin compatible family with
different speed grades. These devices support the
extended industrial temperature range of –40°C to
+105⁰C.
Package Information
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
High-speed data acquisition
Industrial monitoring
Thermal imaging
Imaging and sonar
Software defined radio
Power quality analysis
Communications infrastructure
High-speed control loops
Instrumentation
Smart grids
Spectroscopy
Radar
(1)
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
ADC354x
WQFN (40)
5.00 mm × 5.00 mm
For all available packages, see the package option
addendum at the end of the data sheet.
Device Comparison
(1)
PART NUMBER
RESOLUTION
SAMPLING RATE
ADC3544(1)
14 bit
125 MSPS
ADC3543(1)
14 bit
65 MSPS
ADC3542
14 bit
25 MSPS
ADC3541
14 bit
10 MSPS
Product Preview
REFBUF
1.2V REF
Digital Downconverter
VREF
NCO
ADC
14bit
AIN
N
DCLK
VCM
0.95V
Dig I/F
CMOS
CLK
ADC354x Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
D0..15
ADC3541, ADC3542
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SBAS840B – JULY 2020 – REVISED APRIL 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics - Power Consumption......... 6
6.6 Electrical Characteristics - DC Specifications............. 7
6.7 Electrical Characteristics - AC Specifications
ADC3541.......................................................................9
6.8 Electrical Characteristics - AC Specifications
ADC3542.....................................................................10
6.9 Electrical Characteristics - AC Specifications
ADC3543..................................................................... 11
6.10 Timing Requirements.............................................. 12
6.11 Typical Characteristics: ADC3541...........................14
6.12 Typical Characteristics: ADC3542.......................... 17
6.13 Typical Characteristics: ADC3543.......................... 21
7 Parameter Measurement Information.......................... 26
8 Detailed Description......................................................28
8.1 Overview................................................................... 28
8.2 Functional Block Diagram......................................... 28
8.3 Feature Description...................................................29
8.4 Device Functional Modes..........................................53
8.5 Programming............................................................ 54
8.6 Register Map.............................................................56
9 Application Information Disclaimer............................. 70
9.1 Application Information............................................. 70
9.2 Typical Application.................................................... 70
9.3 Initialization Set Up................................................... 73
10 Power Supply Recommendations..............................74
11 Layout........................................................................... 76
11.1 Layout Guidelines................................................... 76
11.2 Layout Example...................................................... 76
12 Device and Documentation Support..........................77
12.1 Receiving Notification of Documentation Updates..77
12.2 Support Resources................................................. 77
12.3 Trademarks............................................................. 77
12.4 Electrostatic Discharge Caution..............................77
12.5 Glossary..................................................................77
13 Mechanical, Packaging, and Orderable
Information.................................................................... 77
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2020) to Revision B (February 2022)
Page
• Changed the data sheet From: Advanced Information To: Production data....................................................... 1
2
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5 Pin Configuration and Functions
Figure 5-1. RSB Package, 40-Pin WQFN
(Top View)
Table 5-1. Pin Descriptions
PIN
NAME
NO.
I/O
DESCRIPTION
INPUT/REFERENCE
AINM
14
I
Negative analog input
AINP
13
I
Positive analog input
REFBUF
4
I
1.2-V external voltage reference input for use with internal reference buffer. Internal 100 kΩ
pull-up resistor to AVDD. This pin is also used to configure default operating conditions.
REFGND
3
I
Reference ground input, 0 V
VCM
9
O
Common-mode voltage output for the analog inputs, 0.95 V
VREF
2
I
External voltage reference input, 1.6 V.
CLKM
7
I
Negative differential sampling clock input for the ADC
CLKP
6
I
Positive differential sampling clock input for the ADC
PDN/SYNC
1
I
Power down, synchronization input. This pin can be configured via the SPI interface. Active
high. This pin has an internal 21 kΩ pull-down resistor.
RESET
10
I
Hardware reset; active high. This pin has an internal 21 kΩ pull-down resistor.
SCLK
40
I
Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO
39
I
Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
SEN
17
I
Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.
CLOCK
CONFIGURATION
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Table 5-1. Pin Descriptions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
DIGITAL INTERFACE
DCLK
26
O
CMOS output for data bit clock.
D0
38
O
SDR CMOS output used with 18 bit output (configured via output bit formatter). This
becomes the LSB. When not used it can be left unconnected.
See Section 8.3.5.4 and Section 8.3.5.5 on how to change the output resolution and output
bit mapping.
D1
37
O
SDR CMOS output used with 16 bit output (configured via output bit formatter). This
becomes the LSB. When not used it can be left unconnected.
D2
36
O
SDR CMOS output for data bit D0 (14 bit LSB).
D3/
DCLKIN
35
I/O
SDR CMOS output for data bit D1. Used as DCLKIN for serial CMOS output modes.
D4
34
O
SDR CMOS output for data bit D2.
D5
33
O
SDR CMOS output for data bit D3.
D6
32
O
SDR CMOS output for data bit D4.
D7
30
O
SDR CMOS output for data bit D5.
D8
29
O
SDR CMOS output for data bit D6.
D9
28
O
SDR CMOS output for data bit D7.
D10
27
O
SDR CMOS output for data bit D8.
D11/ Serial
Lane 0
24
O
SDR CMOS output for data bit D9. DDR CMOS output for data bits D6/D13 (MSB). Lane 0
in serial CMOS output mode.
D12/
Serial Lane 1
23
O
SDR CMOS output for data bit D10. DDR CMOS output for data bits D5/D12. Lane 1 in
serial CMOS output mode.
D13
22
O
SDR CMOS output for data bit D11.
DDR CMOS output for data bits D4/D11.
D14
21
O
SDR CMOS output for data bit D12.
DDR CMOS output for data bits D3/D10.
D15
20
O
CMOS output for data bit D13 (MSB).
DDR CMOS output for data bits D2/D9.
D16/ FCLK
19
O
SDR CMOS output used with 16 bit output (configured via output bit formatter). This
becomes the MSB. When not used it can be left unconnected.
DDR CMOS output for data bits D1/D8. Frame clock output in serial CMOS output mode.
D17
18
O
SDR CMOS output used with 18 bit output (configured via output bit formatter). This
becomes the MSB. When not used it can be left unconnected.
DDR CMOS output for data bits D0/D7 (LSB).
AVDD
5,8,11,16
I
Analog 1.8-V power supply
GND
POWER SUPPLY
4
12,15
I
Ground, 0 V
IOGND
25
I
Ground, 0 V for digital interface
IOVDD
31
I
1.8-V power supply for digital interface
PowerPAD™
--
--
Connect to ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
MIN
MAX
Supply voltage range, AVDD, IOVDD
–0.3
2.1
V
Supply voltage range, GND, IOGND, REFGND
–0.3
0.3
V
AINP/M, CLKP/M, VREF, REFBUF
–0.3
MIN(2.1, AVDD+0.3)
PDN, RESET, SCLK, SEN, SDIO
–0.3
MIN(2.1, AVDD+0.3)
D3 (DCLKIN)
–0.3
MIN(2.1, IOVDD+0.3)
V
105
°C
150
°C
Voltage applied
to input pins
TEST CONDITIONS
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
Electrostatic discharge
pins(1)
UNIT
2500
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
V
1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply
voltage range IOVDD(1)
1.75
1.8
1.85
V
1.75
1.8
1.85
V
TA
Operating free-air temperature
–40
105
°C
TJ
Operating junction temperature
105(2)
°C
AVDD(1)
(1)
(2)
Measured to GND.
Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
6.4 Thermal Information
ADC354x
THERMAL METRIC(1)
RSB (QFN)
UNIT
40 Pins
RΘJA
Junction-to-ambient thermal resistance
30.7
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
16.4
°C/W
RΘJB
Junction-to-board thermal resistance
10.5
°C/W
ΨJT
Junction-to-top characterization parameter
0.2
°C/W
ΨJB
Junction-to-board characterization parameter
10.5
°C/W
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
2.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics - Power Consumption
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external 1.6V reference, 5 pF
output load, and –1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC3541 - 10 MSPS
IAVDD
Analog supply current
IIOVDD
I/O supply
PDIS
Power dissipation(1)
IIOVDD
External reference
current(1)
SDR CMOS
External reference, SDR CMOS
I/O supply current(1)
15.5
mA
4
35
DDR CMOS
4
Serial CMOS 2-wire
5
Serial CMOS 1-wire
6
mW
mA
4x complex decimation, Serial CMOS
2-wire
6.5
20
31
mA
6
13
mA
ADC3542 - 25 MSPS
IAVDD
Analog supply current
External reference
IIOVDD
I/O supply current(1)
SDR CMOS
PDIS
Power
IIOVDD
dissipation(1)
External reference, SDR CMOS
I/O supply current(1)
46
DDR CMOS
6
Serial CMOS 2-wire
7
4x complex decimation, Serial CMOS
2-wire
10
External reference
35
SDR CMOS
11
External reference, SDR CMOS
84
DDR CMOS
11
8x complex decimation, Serial CMOS
2-wire
16
mW
mA
ADC3543 - 65 MSPS
IAVDD
Analog supply current
current(1)
IIOVDD
I/O supply
PDIS
Power dissipation(1)
IIOVDD
I/O supply current(1)
mA
mW
mA
MISCELLANEOUS
Internal reference, additional analog supply current
IAVDD
PDIS
(1)
6
2
External 1.2V reference (REFBUF), additional analog supply current
0.3
Single ended clock input, reduces
analog supply current by
0.7
Power consumption in global power
down mode
Enabled via SPI
Default power down mask, internal
reference
5
Default power down mask, external
reference
9
mA
mW
Measured with full-scale sine wave input signal at specified sample rate, with ~ 5 pF loading on each CMOS output pin.
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6.6 Electrical Characteristics - DC Specifications
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external 1.6V reference, 5 pF
output load, and –1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
No missing codes
PSRR
MIN
TYP
MAX
14
FIN = 1 MHz
UNIT
bits
38
dB
ADC3541 - 10 MSPS: DC ACCURACY
DNL
Differential nonlinearity
FIN = 1.1 MHz
± 0.2
± 0.85
LSB
INL
Integral nonlinearity
FIN = 1.1 MHz
± 0.6
± 2.1
LSB
VOS_ERR
Offset error
12
130
LSB
VOS_DRIFT
Offset drift over temperature
GAINERR
Gain error
External 1.6 V reference
GAINDRIFT
Gain drift over temperature
External 1.6 V reference
GAINERR
Gain error
Internal reference
GAINDRIFT
Gain drift over temperature
Internal reference
0.01
LSB/ºC
1
Transition Noise
%FSR
25
ppm/ºC
-2.3
%FSR
151
ppm/ºC
0.45
LSBRMS
ADC3542 - 25 MSPS: DC ACCURACY
DNL
Differential nonlinearity
FIN = 1.1 MHz
± 0.2
± 0.85
LSB
INL
Integral nonlinearity
FIN = 1.1 MHz
± 0.6
± 2.1
LSB
VOS_ERR
Offset error
12
130
LSB
VOS_DRIFT
Offset drift over temperature
GAINERR
Gain error
External 1.6 V reference
GAINDRIFT
Gain drift over temperature
External 1.6 V reference
GAINERR
Gain error
Internal reference
GAINDRIFT
Gain drift over temperature
Internal reference
-0.01
-0.2
Transition Noise
LSB/ºC
1
%FSR
31
ppm/ºC
-2.8
%FSR
151
ppm/ºC
0.45
LSBRMS
ADC3543 - 65 MSPS: DC ACCURACY
DNL
Differential nonlinearity
FIN = 5 MHz
± 0.1
LSB
INL
Integral nonlinearity
FIN = 5 MHz
± 0.6
LSB
VOS_ERR
Offset error
VOS_DRIFT
Offset drift over temperature
GAINERR
Gain error
External 1.6 V reference
1.4
%FSR
GAINDRIFT
Gain drift over temperature
External 1.6 V reference
25
ppm/ºC
GAINERR
Gain error
Internal reference
0.8
%FSR
GAINDRIFT
Gain drift over temperature
Internal reference
96
ppm/ºC
0.45
LSBRMS
Transition Noise
5.9
LSB
0.02
LSB/ºC
ADC ANALOG INPUT (AINP/M)
FS
Input full scale
VCM
Input common mode voltage
Default, differential
2.25
RIN
Differential input resistance
FIN = 100 kHz
8
kΩ
CIN
Differential input capacitance
FIN = 100 kHz
7
pF
VOCM
Output common mode voltage
0.95
V
BW
Analog input bandwidth (-3dB)
900
MHz
0.9
0.95
Vpp
1.0
V
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6.6 Electrical Characteristics - DC Specifications (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external 1.6V reference, 5 pF
output load, and –1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal Voltage Reference
VREF
Internal reference voltage
VREF Output Impedance
1.6
V
8
Ω
1.2
V
Reference Input Buffer (REFBUF)
External reference voltage
External voltage reference (VREF)
VREF
1.6
V
Input Current
External voltage reference
0.3
mA
Input impedance
5.3
kΩ
Clock Input (CLKP/M)
Input clock frequency
0.5
VID
Differential input voltage
1
VCM
Input common mode voltage
RIN
Single ended input resistance to common mode
CIN
Single ended input capacitance
65
MHz
3.6
Vpp
0.9
V
5
kΩ
1.5
Clock duty cycle
40
50
pF
60
%
Digital Inputs (RESET, PDN, SCLK, SEN, SDIO)
VIH
High level input voltage
VIL
Low level input voltage
IIH
High level input current
IIL
Low level input current
CI
Input capacitance
1.4
0.4
90
-150
150
90
1.5
V
uA
pF
Digital Output (SDOUT)
VOH
High level output voltage
ILOAD = -400 uA
VOL
Low level output voltage
ILOAD = 400 uA
IOVDD
– 0.1
IOVDD
V
0.1
CMOS Interface (D0:D17)
Output data rate
8
per CMOS output pin
VOH
High level output voltage
ILOAD = -400 uA
VOL
Low level output voltage
ILOAD = 400 uA
VIH
High level input voltage
VIL
Low level input voltage
Input clock (Serial CMOS)
250
IOVDD
– 0.1
IOVDD
MHz
V
0.1
IOVDD
– 0.1
IOVDD
V
0.1
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6.7 Electrical Characteristics - AC Specifications ADC3541
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 10 MSPS, external reference, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external
1.6V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC3541: 10 MSPS
NSD
Noise Spectral Density
SNR
Signal to noise ratio
fIN = 1.1 MHz, AIN = -20 dBFS
-146.5
fIN = 1.1 MHz
SINAD
fIN = 4.9 MHz
Signal to noise and distortion ratio
79.0
76.0
79.0
fIN = 1.1 MHz
79.0
76.0
fIN = 9.9 MHz
THD
Effective number of bits
fIN = 4.9 MHz
Total Harmonic Distortion (First five
harmonics)
Non HD2,3
Spur free dynamic range including
second and third harmonic distortion
Spur free dynamic range (excluding
HD2 and HD3)
12.8
fIN = 1.1 MHz
90
79
fIN = 4.9 MHz
Two tone inter-modulation distortion
94
95
87
fIN = 1.1 MHz
99
f1 = 3 MHz, f2 = 4 MHz, AIN = -7 dBFS/
tone
dBc
93
85
fIN = 9.9 MHz
fIN = 4.9 MHz
bit
87
fIN = 1.1 MHz
fIN = 9.9 MHz
IMD3
12.8
fIN = 9.9 MHz
fIN = 4.9 MHz
dBFS
12.8
12.3
fIN = 9.9 MHz
SFDR
79.0
dBFS
79.0
fIN = 1.1 MHz
ENOB
79.0
fIN = 9.9 MHz
fIN = 4.9 MHz
dBFS/Hz
90
100
dBc
dBFS
100
92
dBc
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6.8 Electrical Characteristics - AC Specifications ADC3542
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 25 MSPS, external reference, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external
1.6V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC3542: 25 MSPS
NSD
Noise Spectral Density
fIN = 1.1 MHz, AIN = -20 dBFS
-150.7
fIN = 1.1 MHz
fIN = 5 MHz
SNR
Signal to noise ratio
Signal to noise and distortion ratio
79.0
76.0
79.0
fIN = 20 MHz
79.0
fIN = 40 MHz
78.5
fIN = 1.1 MHz
79.0
76.0
79.0
fIN = 20 MHz
79.0
fIN = 40 MHz
78.5
fIN = 5 MHz
Effective number of bits
Total Harmonic Distortion (First five
harmonics)
THD
SFDR
Spur free dynamic range including
second and third harmonic distortion
12.8
12.8
fIN = 40 MHz
12.8
fIN = 1.1 MHz
90
79
94
fIN = 20 MHz
91
fIN = 40 MHz
88
fIN = 1.1 MHz
93
85
Non HD2,3
IMD3
10
Two tone inter-modulation distortion
95
fIN = 20 MHz
93
fIN = 40 MHz
89
103
103
fIN = 20 MHz
102
fIN = 40 MHz
99
f1 = 3 MHz, f2 = 4 MHz, AIN = -7 dBFS/
tone
95
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dBc
101
90
fIN = 10 MHz
f1 = 10 MHz, f2 = 12 MHz, AIN = -7
dBFS/tone
dBc
97
fIN = 10 MHz
fIN = 5 MHz
bit
95
fIN = 10 MHz
fIN = 1.1 MHz
Spur free dynamic range (excluding
HD2 and HD3)
12.8
fIN = 20 MHz
fIN = 5 MHz
dBFS
12.8
12.3
fIN = 10 MHz
fIN = 5 MHz
dBFS
79.0
fIN = 10 MHz
fIN = 1.1 MHz
ENOB
79.0
fIN = 10 MHz
fIN = 5 MHz
SINAD
dBFS/Hz
dBFS
dBc
101
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6.9 Electrical Characteristics - AC Specifications ADC3543
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, external reference, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external
1.6V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC3543: 65 MSPS
NSD
Noise Spectral Density
fIN = 1.1 MHz, AIN = -20 dBFS
-154.7
fIN = 1.1 MHz
fIN = 5 MHz
SNR
Signal to noise ratio
79.0
77.0
79.0
fIN = 20 MHz
79.0
fIN = 40 MHz
78.5
fIN = 64 MHz
78.0
fIN = 1.1 MHz
SINAD
Signal to noise and distortion ratio
Effective number of bits
79.0
fIN = 20 MHz
79.0
fIN = 40 MHz
78.5
fIN = 64 MHz
78.0
Total Harmonic Distortion (First five
harmonics)
12.8
fIN = 20 MHz
12.8
fIN = 40 MHz
12.5
fIN = 64 MHz
12.0
Spur free dynamic range including
second and third harmonic distortion
Non HD2,3
IMD3
Spur free dynamic range (excluding
HD2 and HD3)
Two tone inter-modulation distortion
89
84
fIN = 20 MHz
86
fIN = 40 MHz
82
fIN = 64 MHz
78
fIN = 1.1 MHz
95
88
87
fIN = 20 MHz
88
fIN = 40 MHz
85
fIN = 64 MHz
80
fIN = 1.1 MHz
100
93
dBc
90
fIN = 10 MHz
fIN = 5 MHz
bit
88
84
fIN = 10 MHz
fIN = 5 MHz
SFDR
12.8
fIN = 10 MHz
fIN = 5 MHz
dBFS
12.8
12.4
fIN = 1.1 MHz
THD
79.0
fIN = 10 MHz
fIN = 5 MHz
dBFS
79.0
76.2
fIN = 1.1 MHz
ENOB
79.0
fIN = 10 MHz
fIN = 5 MHz
dBFS/Hz
dBc
101
fIN = 10 MHz
99
fIN = 20 MHz
97
fIN = 40 MHz
96
fIN = 64 MHz
91
f1 = 10 MHz, f2 = 12 MHz, AIN = -7
dBFS/tone
92
dBFS
dBc
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6.10 Timing Requirements
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, and –1-dBFS differential input,
unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
ADC Timing Specifications
tAD
Aperture delay
0.85
tA
Aperture jitter
Square wave clock with fast edges
tJ
Jitter on DCLKIN
Serial CMOS output mode
Recory time from +6 dB overload condition
Signal conversion period, referenced to
sampling clock falling edge
tCONV
1
FS = 10 Msps
-TS/2
FS = 25 Msps
-TS/2
FS = 65 Msps
-TS/4
FS = 10 Msps
+TS ×
1/5
FS = 25 Msps
+TS ×
3/8
FS = 65 Msps
+TS ×
5/8
Bandgap reference enabled, single ended
clock
Time to valid data after coming out of power
down. Internal reference.
Wake up
time
tS,SYNC
Setup time for SYNC input signal
tH,SYNC
Hold time for SYNC input signal
ADC
Latency
Bandgap reference enabled, differential clock
14
Bandgap reference disabled, single ended
clock
1.6
Bandgap reference disabled, differential clock
1.6
12
1.13
Bandgap reference disabled, differential clock
1.13
500
Sampling
Clock
Period
Sampling
Clock
Period
us
ms
us
ms
ps
600
SDR CMOS
1
DDR CMOS
1
Serialized CMOS: 2-wire
2
Clock
cycles
1
Real decimation by 2
21
Complex decimation by 2
22
Real or complex decimation by 4, 8, 16, 32
23
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Clock
cycle
14
Bandgap reference disabled, single ended
clock
Referenced to sampling clock rising edge
Signal input to data output
14.6
Bandgap reference enabled, differential clock
Serialized CMOS: 1-wire
Add.
Latency
14.6
Bandgap reference enabled, single ended
clock
Time to valid data after coming out of power
down. External 1.6V reference.
fs
± 50 ps (pk-pk)
SNR within 1 dB of expected value
Signal acquisition period, referenced to
sampling clock falling edge
tACQ
180
ns
Output
clock
cycles
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6.10 Timing Requirements (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to
TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, and –1-dBFS differential input,
unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
3
5
7
UNIT
Interface Timing - SDR CMOS
tPD
tCD
tDV
Propagation delay: sampling clock falling edge to DCLK rising edge
DCLK rising edge to output data delay
Fout = 10 MSPS
-0.3
-0.2
DCLK rising edge to output data delay
Fout = 25 MSPS
-0.3
-0.2
DCLK rising edge to output data delay
Fout = 65 MSPS
-0.3
-0.2
Data valid, SDR CMOS
Fout = 10 MSPS
99.9
99.9
Data valid, SDR CMOS
Fout = 25 MSPS
39.9
39.9
Data valid, SDR CMOS
Fout = 65 MSPS
15.1
15.3
3
5
ns
ns
ns
Interface Timing - DDR CMOS
tPD
tCD
tDV
Propagation delay: sampling clock falling edge to DCLK rising edge
DCLK rising edge to output data delay
Fout = 10 MSPS
-0.3
-0.2
DCLK rising edge to output data delay
Fout = 25 MSPS
-0.4
-0.2
DCLK rising edge to output data delay
Fout = 65 MSPS
-0.4
-0.2
Data valid, DDR CMOS
Fout = 10 MSPS
49.5
49.9
Data valid, DDR CMOS
Fout = 25 MSPS
19.6
19.8
Data valid, DDR CMOS
Fout = 65 MSPS
7.4
7.5
7
ns
ns
ns
Interface Timing - SERIAL CMOS
tPD
tCD
tDV
Propagation delay: sampling clock falling
edge to DCLK rising edge
DCLK rising edge to output data delay,
2-wire serial CMOS
DCLK rising edge to output data delay,
1-wire serial CMOS
Data valid, 2-wire serial CMOS
Data valid, 1-wire serial CMOS
Delay between sampling clock falling edge to
2+
3+
4+
DCLKIN falling edge < 2.5ns.
TDCLK TDCLK TDCLK
TDCLK = DCLK period
+
+
+
tCDCLK = Sampling clock falling edge to
tCDCLK tCDCLK tCDCLK
DCLKIN falling edge
Delay between sampling clock falling edge to
DCLKIN falling edge >= 2.5ns.
2+
3+
4+
TDCLK = DCLK period
tCDCLK tCDCLK tCDCLK
tCDCLK = Sampling clock falling edge to
DCLKIN falling edge
Fout = 10 MSPS, D11/12 = 70 MBPS
0.04
0.18
Fout = 25 MSPS, D11/12 = 175 MBPS
0.01
0.18
Fout = 10 MSPS, D11 = 140 MBPS
0.05
0.19
Fout = 10 MSPS, D11/12 = 70 MBPS
13.4
13.8
Fout = 25 MSPS, D11/12 = 175 MBPS
5.2
5.5
Fout = 10 MSPS, D11 = 140 MBPS
6.2
6.8
ns
ns
ns
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK(SCLK) Serial clock frequency
tSU(SEN)
SEN to rising edge of SCLK
tH(SEN)
SEN from rising edge of SCLK
tSU(SDIO)
SDIO to rising edge of SCLK
tH(SDIO)
SDIO from rising edge of SCLK
20
MHz
10
9
ns
17
9
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
t(OZD)
SDIO tri-state to driven
3.9
10.8
t(ODZ)
SDIO data to tri-state
3.4
14
t(OD)
SDIO valid from falling edge of SCLK
3.9
10.8
ns
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6.11 Typical Characteristics: ADC3541
Typical values at TA = 25 °C, ADC sampling rate = 10 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD =
1.8 V, 65k FFT, 1.6 V external reference, 5 pF load capacitance, unless otherwise noted.
SNR = 79.3 dBFS, SFDR = 85 dBc, Non HD23 = 97 dBFS
Figure 6-1. Single Tone FFT at FIN = 1.1 MHz
AIN = - 7 dBFS/tone, IMD3 = 94 dBc
Figure 6-2. Two Tone FFT at FIN = 3,4 MHz
AIN = -20 dBFS/tone, IMD3 = 87 dBc
Figure 6-3. Two Tone FFT at FIN = 3,4 MHz
spacer
Figure 6-4. AC Performance vs Input Frequency
spacer
FIN = 1.1 MHz
Figure 6-5. ENOB vs Input Frequency
14
Figure 6-6. AC Performance vs Input Amplitude
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6.11 Typical Characteristics: ADC3541 (continued)
FIN = 1.1 MHz
Differential (Diff) vs Single ended (SE) clock, FIN = 1.1 MHz
Figure 6-7. AC Performance vs Sampling Rate
Figure 6-8. AC Performance vs Clock Amplitude
FIN = 1.1 MHz
FIN = 1.1 MHz
Figure 6-9. AC Performance vs AVDD
Figure 6-10. AC Performance vs VCM vs Temperature
FIN = 1.1 MHz
FIN = 1.1 MHz
Figure 6-11. INL vs Code
Figure 6-12. DNL vs Code
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6.11 Typical Characteristics: ADC3541 (continued)
Figure 6-13. DC Histogram
Pulse Input = 1 MHz
Figure 6-14. Pulse Response
13
25
IAVDD , ADC3541/42
IIOVDD, SDR
IIOVDD, DDR
20
Bypass
/4 real
/8 real
/32 real
IIOVDD, 2-w
IIOVDD, 1-w
/2 real
/4 complex
/8 complex
/32 complex
Current (mA)
Current (mA)
10.5
15
10
8
5.5
5
3
0
5
10
15
Sampling Rate (MSPS)
20
5
25
10
15
Sampling Rate (MSPS)
20
25
FIN = 1 MHz, 2-w serial CMOS
FIN = 1 MHz
Figure 6-16. IIOVDD Current vs Decimation
Figure 6-15. Current vs Sampling Rate
12
SDR, 5 pF
SDR, 15 pF
SDR, 22 pF
DDR, 5 pF
DDR, 15 pF
DDR, 22 pF
Current (mA)
10
8
6
4
2
5
10
15
Sampling Rate (MSPS)
20
25
FIN = 1 MHz
Figure 6-17. IIOVDD Current vs Output Load
16
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6.12 Typical Characteristics: ADC3542
Typical values at TA = 25 °C, ADC sampling rate = 25 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD =
1.8 V, 65k FFT, 1.6 V external reference, 5 pF load capacitance, unless otherwise noted.
SNR = 79.4 dBFS, SFDR = 89 dBc, Non HD23 = 99 dBFS
Figure 6-18. Single Tone FFT at FIN = 1.1 MHz
AIN = -10 dBFS, SNR = 79.9 dBFS, SFDR = 98 dBc, Non
HD23 = 93 dBFS
SNR = 79.3 dBFS, SFDR = 99 dBc, Non HD23 = 99 dBFS
Figure 6-19. Single Tone FFT at FIN = 10 MHz
SNR = 78.6 dBFS, SFDR = 88 dBc, Non HD23 = 98 dBFS
Figure 6-21. Single Tone FFT at FIN = 40 MHz
Figure 6-20. Single Tone FFT at FIN = 10 MHz
AIN = -7 dBFS/tone, IMD3 = 90 dBc
Figure 6-22. Two Tone FFT at FIN = 3, 4 MHz
AIN = -20 dBFS/tone, IMD3 = 87 dBc
Figure 6-23. Two Tone FFT at FIN = 3, 4 MHz
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6.12 Typical Characteristics: ADC3542 (continued)
0
-20
Amplitude (dBFS)
-40
-60
-80
-100
-120
-140
0
5
Input Frequency (MHz)
10
12.5
AIN = -7 dBFS/tone, IMD3 = 100 dBc
Figure 6-24. Two Tone FFT at FIN = 10, 12 MHz
Figure 6-25. AC Performance vs Input Frequency
Figure 6-26. ENOB vs Input Frequency
FIN = 5 MHz
Figure 6-27. AC Performance vs Input Amplitude
FIN = 1.1 MHz
Differential (Diff) vs Single ended (SE) clock, FIN = 5 MHz
Figure 6-28. AC Performance vs Sampling Rate
18
Figure 6-29. AC Performance vs Clock Amplitude
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6.12 Typical Characteristics: ADC3542 (continued)
FIN = 1.1 MHz
FIN = 1.1 MHz
Figure 6-30. AC Performance vs AVDD
Figure 6-31. AC Performance vs VCM vs Temperature
FIN = 1.1 MHz
FIN = 1.1 MHz
Figure 6-32. INL vs Code
Figure 6-33. DNL vs Code
Figure 6-34. DC Histogram
Pulse Input = 1 MHz
Figure 6-35. Pulse Response
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6.12 Typical Characteristics: ADC3542 (continued)
13
25
IAVDD , ADC3541/42
IIOVDD, SDR
IIOVDD, DDR
20
Bypass
/4 real
/8 real
/32 real
IIOVDD, 2-w
IIOVDD, 1-w
/2 real
/4 complex
/8 complex
/32 complex
Current (mA)
Current (mA)
10.5
15
10
8
5.5
5
3
0
5
10
15
Sampling Rate (MSPS)
20
5
25
10
15
Sampling Rate (MSPS)
20
25
FIN = 1 MHz, 2-w serial CMOS
FIN = 1 MHz
Figure 6-37. IIOVDD Current vs Decimation
Figure 6-36. Current vs Sampling Rate
12
SDR, 5 pF
SDR, 15 pF
SDR, 22 pF
DDR, 5 pF
DDR, 15 pF
DDR, 22 pF
Current (mA)
10
8
6
4
2
5
10
15
Sampling Rate (MSPS)
20
25
FIN = 1 MHz
Figure 6-38. IIOVDD Current vs Output Load
20
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6.13 Typical Characteristics: ADC3543
Typical values at TA = 25 °C, ADC sampling rate = 65 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD =
1.8 V, 65k FFT, 1.6 V external reference, 5 pF load capacitance, unless otherwise noted.
SNR = 79.3 dBFS, SFDR = 91 dBc, Non HD23 = 100 dBFS
Figure 6-39. Single Tone FFT at FIN = 1.1 MHz
AIN = -10 dBFS, SNR = 79.7 dBFS, SFDR = 93 dBc, Non
HD23 = 105 dBFS
SNR = 79.2 dBFS, SFDR = 87 dBc, Non HD23 = 102 dBFS
Figure 6-40. Single Tone FFT at FIN = 10 MHz
SNR = 78.5 dBFS, SFDR = 85 dBc, Non HD23 = 97 dBFS
Figure 6-42. Single Tone FFT at FIN = 40 MHz
Figure 6-41. Single Tone FFT at FIN = 10 MHz
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6.13 Typical Characteristics: ADC3543 (continued)
SNR = 78.0 dBFS, SFDR = 69 dBc, Non HD23 = 94 dBFS
Figure 6-43. Single Tone FFT at FIN = 64 MHz
AIN = -7 dBFS/tone, IMD3 = 100 dBc
Figure 6-45. Two Tone FFT at FIN = 10, 12 MHz
AIN = -7 dBFS/tone, IMD3 = 89 dBc
Figure 6-47. Two Tone FFT at FIN = 35,40 MHz
22
SNR = 77.1 dBFS, SFDR = 77 dBc, Non HD23 = 87 dBFS
Figure 6-44. Single Tone FFT at FIN = 100 MHz
AIN = -20 dBFS/tone, IMD3 = 93 dBc
Figure 6-46. Two Tone FFT at FIN = 10, 12 MHz
spacer
Figure 6-48. AC Performance vs Input Frequency
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6.13 Typical Characteristics: ADC3543 (continued)
FIN = 5 MHz
spacer
Figure 6-49. ENOB vs Input Frequency
FIN = 5 MHz
Figure 6-50. AC Performance vs Input Amplitude
Differential (Diff) vs Single ended (SE) clock, FIN = 5 MHz
Figure 6-51. AC Performance vs Sampling Rate
Figure 6-52. AC Performance vs Clock Amplitude
FIN = 5 MHz
FIN = 5 MHz
Figure 6-53. AC Performance vs AVDD
Figure 6-54. AC Performance vs VCM vs Temperature
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6.13 Typical Characteristics: ADC3543 (continued)
FIN = 5 MHz
FIN = 5 MHz
Figure 6-55. INL vs Code
Figure 6-56. DNL vs Code
Figure 6-57. DC Histogram
Pulse Input = 1 MHz
Figure 6-58. Pulse Response
FIN = 5 MHz
FIN = 5 MHz
Figure 6-59. AC Performance vs Clock Duty Cycle
24
Figure 6-60. Current vs Sampling Rate
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6.13 Typical Characteristics: ADC3543 (continued)
FIN = 5 MHz, 2-w serial CMOS
Figure 6-61. IIOVDD Current vs Decimation
FIN = 5 MHz, DDC Bypass
Figure 6-62. IIOVDD Current vs Output Interface
FIN = 5 MHz, DDC Bypass
Figure 6-63. IIOVDD Current vs Output Load
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7 Parameter Measurement Information
Sample N
Input Signal
Sample N+1
tAD
tPD
Sampling
Clock
tACQ
tCONV
tCD
TDCLK
DCLK
tDV
D2..15
Sample N
Sample N-1
Figure 7-1. Timing Diagram: SDR CMOS
Sample N
Input Signal
Sample N+1
tAD
tPD
Sampling
Clock
tACQ
tCONV
tCD
TDCLK
DCLK
tDV
D13
D6
D13
D6
D13
D12
D12
D5
D12
D5
D12
D16/
FCLK
D8
D1
D8
D1
D8
D17
D7
D0
D7
D0
D7
...
D11
Sample N-2
Sample N-1
Sample N
Figure 7-2. Timing Diagram: DDR CMOS (default bit mapper)
26
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Sample N
Input Signal
Sample N+1
tAD
tPD
Sampling
Clock
tACQ
tCONV
tCDCLK
DCLKIN
(D3)
DCLK
tCD
TDCLK
FCLK
tDV
D12
D13
D11
D9
D7
D5
D3
D1
D13
D11
D9
D7
D5
D3
D1
D11
D12
D10
D8
D6
D4
D2
D0
D12
D10
D8
D6
D4
D2
D0
Sample N-2
Sample N-1
Figure 7-3. Timing Diagram: Serial CMOS 2-wire (default bit mapper)
Sample N
Input Signal
Sample N+1
tAD
tPD
Sampling
Clock
tACQ
tCONV
tCDCLK
DCLKIN
(D3)
DCLK
tCD
TDCLK
FCLK
tDV
D11
D2
D1
D0
D13
Sample N-2
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Sample N-1
Figure 7-4. Timing Diagram: Serial CMOS 1-wire (default bit mapper)
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8 Detailed Description
8.1 Overview
The ADC354x is a low noise, ultra-low power 14-bit high-speed ADC family supporting sampling rates from 10 to
65 Msps. It offers good DC precision together with IF sampling support which makes it suited for a wide range of
applications. The ADC354x is equipped with an on-chip internal reference option but it also supports the use of
an external, high precision 1.6 V voltage reference or an external 1.2 V reference which is buffered and gained
up internally. Because of the inherent low latency architecture, the digital output result is available after only one
clock cycle. Single ended as well as differential input signaling is supported.
An optional programmable digital down converter enables external anti-alias filter relaxation as well as output
data rate reduction. The digital filter provides a 32-bit programmable NCO and supports both real or complex
decimation.
The ADC354x family uses a SDR or DDR as well as a 2-wire or 1-wire serial CMOS interface to output the data
offering lowest power digital interface together with the flexibility to minimize the number of digital interconnects.
The ADC354x includes a digital output formatter which supports output resolutions from 14 to 20-bit. The device
is part of a pin-to-pin compatible family with different speed grades.
The device features and control options can be set up either through pin configurations or via SPI register writes.
8.2 Functional Block Diagram
REFBUF
1.2V REF
Digital Downconverter
VREF
NCO
ADC
14bit
AIN
N
FCLK
DCLKIN
VCM
0.95V
Dig I/F
CMOS
DCLK
D0..15
CLK
28
SCLK
SEN
SDIO
PDN/SYNC
RESET
Control
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8.3 Feature Description
8.3.1 Analog Input
The analog inputs of ADC354x are intended to be driven differentially. Both AC coupling and DC coupling of the
analog inputs is supported. The analog inputs are designed for an input common mode voltage of 0.95 V which
must be provided externally on each input pin. DC-coupled input signals must have a common mode voltage that
meets the device input common mode voltage range.
The equivalent input network diagram is shown in Figure 8-1. All four sampling switches, on-resistance shown in
red, are in same position (open or closed) simultaneously.
AVDD
Sampling Switch
xINP/
xINM
1
2 nH
0.32 pF
125
24
1.4 pF
0.15 pF
0.6 pF
0.6 pF
GND
GND
GND
6.4 pF
7
GND
GND
GND
5
0.7 pF
GND
1.6 pF
GND
GND
Figure 8-1. Equivalent Input Network
8.3.1.1 Analog Input Bandwidth
Figure 8-2 shows the analog full power input bandwidth of the ADC with a 50 Ω differential termination. The
-3 dB bandwidth is approximately 900 MHz and the useful input bandwidth with good AC performance is
approximately 120 MHz.
The equivalent input resistance RIN and input capacitance CIN vs frequency are shown in Figure 8-3.
Normalized Gain Response (dB)
0
-1
-2
-3
-4
-5
-6
10
100
Input Frequency (MHz)
1000
ADC3
Figure 8-2. ADC Analog Input bandwidth response
Figure 8-3. Equivant RIN, CIN vs Input Frequency
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8.3.1.2 Analog Front End Design
The ADC354x is an unbuffered ADC and thus a passive kick-back filter is recommended to absorb the glitch
from the sampling operation. Depending on if the input is driven by a balun or a differential amplifier with low
output impedance, a termination network may be needed. Additionally a passive DC bias circuit is needed in
AC-coupled applications which can be combined with the termination network.
8.3.1.2.1 Sampling Glitch Filter Design
The front end sampling glitch filter is designed to optimize the SNR and HD3 performance of the ADC. The filter
performance is dependent on input frequency and therefore the following filter designs are recommended for
different input frequency ranges as shown in Figure 8-4 and Figure 8-5.
33
10
180nH
100 pF
Termination
33
180nH
10
Figure 8-4. Sampling glitch filter example for input frequencies from DC to 30 MHz
33
10
120nH
100pF
82 pF
Termination
33
10
120nH
100pF
Figure 8-5. Sampling glitch filter example for input frequencies from 30 to 70 MHz
8.3.1.2.2 Single Ended Input
The ADC can be configured to operate with single ended input instead of differential using just the positive signal
input. This operating mode must be enabled via SPI register write (address 0xE). The single ended signal is
connected to the negative ADC input and both the positive and negative input need to be biased to VCM as
shown in Figure 8-6.
0.56V
0V
-0.56V
C
INM
0.56V
VCM
-0.56V
INM
R
VCM
VCM
INP
C
VCM
INP
C
Figure 8-6. Single ended analog input: AC coupled (left) and DC coupled (right)
The signal swing is now reduced by 6-dB (single ended input with 1.125 Vpp vs differential 2.25 Vpp), and the
resulting SNR is reduced by 3-dB.
30
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8.3.1.2.3 Analog Input Termination and DC Bias
Depending on the input drive circuitry, a termination network and/or DC biasing needs to be provided.
8.3.1.2.3.1 AC-Coupling
The ADC354x requires external DC bias using the common mode output voltage (VCM) of the ADC together
with the termination network as shown in Figure 8-7. The termination is located within the glitch filter network.
When using a balun on the input, the termination impedance has to be adjusted to account for the turns ratio of
the transformer. When using an amplifier, the termination impedance can be adjusted to optimize the amplifier
performance.
Glitch Filter
Termination
33
1 uF
10
180nH
25
100 pF
VCM
0.1 …F
33
25
1 uF
VCM
180nH
10
Figure 8-7. AC-Coupling: termination network provides DC bias (glitch filter example for DC - 30 MHz)
8.3.1.2.3.2 DC-Coupling
In DC coupled applications the DC bias needs to be provided from the fully differential amplifier (FDA) using
VCM output of the ADC as shown in Figure 8-8. The glitch filter in this case is located between the anti-alias filter
and the ADC. No termination may be needed if amplifier is located close to the ADC or if the termination is part
of the anti-alias filter.
Glitch Filter
33
10
180nH
AAF (Anti
Alias Filter)
100 pF
33
VCM
180nH
10
Figure 8-8. DC-Coupling: DC bias provided by FDA (glitch filter example for DC - 30 MHz)
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8.3.1.3 Auto-Zero Feature
The ADC354x includes an internal auto-zero front end amplifier circuit which improves the 1/f flicker noise. This
auto-zero feature is enabled by default for the ADC3541/2 and can be enabled using SPI register writes for the
ADC3543 (register 0x11, D0). The following 4M point FFTs compare auto-zero feature enabled vs disabled.
32
Figure 8-9. FS = 10 MSPS, FIN = 1.1 MHz
Figure 8-10. FS = 10 MSPS, FIN = 1.1 MHz
Figure 8-11. FS = 25 MSPS, FIN = 1.1 MHz
Figure 8-12. FS = 25 MSPS, FIN = 1.1 MHz
Figure 8-13. FS = 65 MSPS, FIN = 5 MHz
Figure 8-14. FS = 65 MSPS, FIN = 5 MHz
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8.3.2 Clock Input
In order to maximize the ADC SNR performance, the external sampling clock should be low jitter and differential
signaling with a high slew rate. This is especially important in IF sampling applications. For less jitter sensitive
applications, the ADC354x provides the option to operate with single ended signaling which saves additional
power consumption.
8.3.2.1 Single Ended vs Differential Clock Input
The ADC354x can be operated using a differential or a single ended clock input where the single ended clock
consumes less power consumption. However clock amplitude impacts the ADC aperture jitter and consequently
the SNR. For maximum SNR performance, a large clock signal with fast slew rates needs to be provided.
•
•
Differential Clock Input: The clock input can be AC coupled externally. The ADC354x provides internal biasing
for that use case.
Single Ended Clock Input: This mode needs to be configured using SPI register (0x0E, D2 and D0) or with
the REFBUF pin. In this mode there is no internal clock biasing and thus the clock input needs to be DC
coupled around a 0.9V center. The unused input needs to be AC coupled to ground.
1.8V
CLKP
CLKP
+
0.9V
5kO
0V
VCM
0.9V
CLKM
5kO
CLKM
-
Figure 8-15. External and internal connection using differential (left) and single ended (right) clock input
8.3.2.2 Signal Acquisition Time Adjust
The ADC354x includes a register (DLL PDN (0x11, D2) which increases the signal acquisition time window for
clock rates below 40 MSPS from 25% to 50% of the clock period. Increasing the sampling time provides a longer
time for the driving amplifier to settle out the signal which can improve the SNR performance of the system.
Note
This register needs to be set for the 65 MSPS speed grade (ADC3543) when operating at sampling
rates below 40 MSPS. For the 10 and 25 MSPS device speed grades the sampling time is already set
to TS/2.
When powering down the DLL, the acquisition time will track the clock duty cycle (50% is recommended).
Table 8-1. Acquisition time vs DLL PDN setting
SAMPLING CLOCK FS (MSPS)
DLL PDN (0x11, D2)
ACQUISITION TIME (tACQ)
65
0
TS / 4
≤ 40
1
TS / 2
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8.3.3 Voltage Reference
The ADC354x provides three different options for supplying the voltage reference to the ADC. An external 1.6
V reference can be directly connected to the VREF input; a voltage 1.2 V reference can be connected to the
REFBUF input using the internal gain buffer or the internal 1.2 V reference can be enabled to generate a 1.6V
reference voltage. For best performance, the reference noise should be filtered by connecting a 10 uF and a 0.1
uF ceramic bypass capacitor to the VREF pin. The internal reference circuitry of the ADC354x is shown in Figure
8-16.
Note
The voltage reference mode can be selected using SPI register writes or by using the REFBUF pin
(default) as a control pin (Section 8.5.1). If the REFBUF pin is not used for configuration, the REFBUF
pin should be connected to AVDD (even though the REFBUF pin has a weak internal pullup to AVDD)
and the voltage reference option has to be selected using the SPI interface.
AINP
AINM
VCM
0.95V
VREF
(1.6V)
x1.33
REFBUF
(1.2V)
VREF1.2
REFGND
Figure 8-16. Different voltage reference options for ADC354x
8.3.3.1 Internal voltage reference
The 1.6 V reference for the ADC can be generated internal using the on-chip 1.2V reference along with the
internal gain buffer. A 10 uF and a 0.1 uF ceramic bypass capacitor (CVREF) should be connected between the
VREF and REFGND pins as close to the pins as possible.
xINP
xINM
VCM
0.95V
VREF
(1.6V)
x1.33
CVREF
REFBUF
(1.6V)
VREF1.2
REFGND
Figure 8-17. Internal reference
34
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8.3.3.2 External voltage reference (VREF)
For highest accuracy and lowest temperature drift, the VREF input can be directly connected to an external 1.6 V
reference. A 10 uF and a 0.1 uF ceramic bypass capacitor (CVREF) connected between the VREF and REFGND
pins and placed as close to the pins as possible is recommended. The load current from the external reference
is about 1 mA.
Note: The internal reference is also used for other functions inside the device, therefore the reference amplifier
should only be powered down in power down state but not during normal operation.
xINP
xINM
VCM
0.95V
VREF
(1.6V)
Reference
1.6V
CVREF
REFBUF
(1.2V)
x1.33
VREF1.2
REFGND
Figure 8-18. External 1.6 V reference
8.3.3.3 External voltage reference with internal buffer (REFBUF)
The ADC354x is equipped with an on-chip reference buffer that also includes gain to generate the 1.6V
reference voltage from an external 1.2 V reference. A 10 uF and a 0.1 uF ceramic bypass capacitor (CVREF)
between the VREF and REFGND pins and a 10 uF and a 0.1 uF ceramic bypass capacitor (CREFBUF) between
the REFBUF and REFGND pins are recommended. Both capacitors should be placed as close to the pins as
possible. The load current from the external reference is less than 100 uA.
xINP
xINM
VCM
0.95V
VREF
(1.6V)
REFBUF
(1.2V)
Reference
1.2V
x1.33
VREF1.2
CREFBUF
CVREF
REFGND
Figure 8-19. External 1.2 V reference using internal reference buffer
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8.3.4 Digital Down Converter
The ADC354x includes an optional on-chip digital down conversion (DDC) decimation filter that can be enabled
via SPI register setting. It supports complex decimation by 2, 4, 8, 16 and 32 using a digital mixer and a
32-bit numerically controlled oscillator (NCO) as shown in Figure 8-20. Furthermore it supports a mode with real
decimation where the complex mixer is bypassed (NCO should be set to 0 for lowest power consumption) and
the digital filter acts as a low pass filter.
Internally the decimation filter calculations are performed with a 20-bit resolution in order to avoid any SNR
degradation due to quantization noise. The output formatter (Section 8.3.5.4) truncates to the selected resolution
prior to outputting the data on the digital interface.
NCO
32bit
Filter
I
Q
ADC
N
I
Q
Digital
Interface
SYNC
Figure 8-20. Internal Digital Decimation Filter
36
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8.3.4.1 Digital Filter Operation
The complex decimation operation is illustrated with an example in Figure 8-21. First the input signal (and the
negative image) are frequency shifted by the NCO frequency as shown on the left. Next a digital filter is applied
(centered around 0 Hz) and the output data rate is decimated - in this example the output data rate FS,OUT =
FS/8 with a Nyquist zone of FS/16. During the complex mixing the spectrum (signal and noise) is split into real
and complex parts and thus the amplitude is reduced by 6-dB. In order to compensate this loss, there is a 6-dB
digital gain option in the decimation filter block that can be enabled via SPI write.
Input Signal
(Alias)
-FIN + FNCO
Shifted Input
Signal (Alias)
Shifted Input Signal
Negative Image
Input Signal
Negative Image
Decimation
by 8
FIN + FNCO
0
-FS/2
FS/2
FNCO
-FS/2
-FS/16
0
FS/16
FS/2
NCO Tuning Range
Figure 8-21. Complex decimation illustration
The real decimation operation is illustrated with an example in Figure 8-22. There is no frequency shift
happening and only the real portion of the complex digital filter is exercised. The output data rate is decimated a decimation of 8 would result in an output data rate FS,OUT = FS/8 with a Nyquist zone of FS/16.
During the real mixing the spectrum (signal and noise) amplitude is reduced by 3-dB. In order to compensate this
loss, there is a 3-dB digital gain option in the decimation filter block that can be enabled via SPI write.
Input Signal
Decimation by
32
Decimation by
16
Decimation by 2
Decimation by 4
Decimation by 8
FS/32
FS/16
FS/8
FS/4
FS/2
FS/64
Figure 8-22. Real decimation illustration
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8.3.4.2 FS/4 Mixing with Real Output
In this mode, the output after complex decimation gets mixed with FS/4 (FS = output data rate in this case).
Instead of a complex output with the input signal centered around 0 Hz, the output is transmitted as a real output
at twice the data rate and the signal is centered around FS/4 (Fout/4) as illustrated in Figure 8-23.
In this example, complex decimation by 8 is used. The output data is transmitted as a real output with an output
rate of Fout = FS'/4 (FS' = ADC sampling rate). The input signal is now centered around FS/4 (Fout/4) or FS'/16.
FIN
FNCO
- FIN + FNCO
-FIN + FNCO + FS/4
/8
FS/4 mix
Fout/4 mix
Complex
Decimation /8
0
0
FS/2
0
)6¶/2
FS/16
)6¶/2
FS/8
Figure 8-23. FS/4 Mixing with real output
8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
The decimation block is equipped with a 32-bit NCO and a digital mixer to fine tune the frequency placement
prior to the digital filtering. The oscillator generates a complex exponential sequence of:
ejωn (default) or e–jωn
(1)
where: frequency (ω) is specified as a signed number by the 32-bit register setting
The complex exponential sequence is multiplied with the real input from the ADC to mix the desired carrier to
a frequency equal to fIN + fNCO. The NCO frequency can be tuned from –FS/2 to +FS/2 and is processed as a
signed, 2s complement number. After programming a new NCO frequency, the MIXER RESTART register bit or
SYNC pin has to be toggled for the new frequency to get active. Additionally the ADC354x provides the option
via SPI to invert the mixer phase.
The NCO frequency setting is set by the 32-bit register value given and calculated as:
NCO frequency = 0 to + FS/2: NCO = fNCO × 232 / FS
NCO frequency = -FS/2 to 0: NCO = (fNCO + FS) × 232 / FS
where:
• NCO = NCO register setting (decimal value)
• fNCO = Desired NCO frequency (MHz)
• FS = ADC sampling rate (MSPS)
The NCO programming is further illustrated with this example:
•
•
•
ADC sampling rate FS = 65 MSPS
Input signal fIN = 10 MHz
Desired output frequency fOUT = 0 MHz
For this example there are four ways to program the NCO and achieve the desired output frequency as shown in
Table 8-2.
Table 8-2. NCO value calculations example
Alias or negative image
fNCO
NCO Value
fIN = –10 MHz
fNCO = 10 MHz
660764199
fIN = 10 MHz
fNCO = –10 MHz
3634203097
fIN = 10 MHz
fNCO = 10 MHz
660764199
fIN = –10 MHz
fNCO = –10 MHz
3634203097
38
Mixer Phase
as is
inverted
Frequency translation for fOUT
fOUT = fIN + fNCO = –10 MHz +10 MHz = 0 MHz
fOUT = fIN + fNCO = 10 MHz + (–10 MHz) = 0 MHz
fOUT = fIN – fNCO = 10 MHz – 10 MHz = 0 MHz
fOUT = fIN – fNCO = –10 MHz – (–10 MHz) = 0 MHz
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8.3.4.4 Decimation Filter
The ADC354x supports complex decimation by 2, 4, 8, 16 and 32 with a pass-band bandwidth of ~ 80% and
a stopband rejection of at least 85 dB. Table 8-3 gives an overview of the pass-band bandwidth of the different
decimation settings with respect to ADC sampling rate FS. In real decimation mode the output bandwidth is half
of the complex bandwidth.
Table 8-3. Decimation Filter Summary and Maximum Available Output Bandwidth
REAL/COMPLEX
DECIMATION
Complex
Real
DECIMATION
SETTING N
OUTPUT RATE
OUTPUT
BANDWIDTH
OUTPUT RATE
(FS = 65 MSPS)
OUTPUT BANDWIDTH
(FS = 65 MSPS)
2
FS / 2 complex
4
FS / 4 complex
0.8 × FS / 2
32.5 MSPS complex
26 MHz
0.8 × FS / 4
16.25 MSPS complex
8
13 MHz
FS / 8 complex
0.8 × FS / 8
8.125 MSPS complex
6.5 MHz
16
FS / 16 complex
0.8 × FS / 16
4.0625 MSPS complex
3.25 MHz
32
FS / 32 complex
0.8 × FS / 32
2.03125 MSPS complex
1.625 MHz
2
FS / 2 real
0.4 × FS / 2
32.5 MSPS
13 MHz
4
FS / 4 real
0.4 × FS / 4
16.25 MSPS
6.5 MHz
8
FS / 8 real
0.4 × FS / 8
8.125 MSPS
3.25 MHz
16
FS / 16 real
0.4 × FS / 16
4.0625 MSPS
1.625 MHz
32
FS / 32 real
0.4 × FS / 32
2.03125 MSPS
0.8125 MHz
The decimation filter responses are normalized to the ADC sampling clock frequency FS and illustrated in Figure
8-25 to Figure 8-34. They are interpreted as follows:
Each figure contains the filter pass-band, transition band(s) and alias or stop-band(s) as shown in Figure 8-24.
The x-axis shows the offset frequency (after the NCO frequency shift) normalized to the ADC sampling rate FS.
For example, in the divide-by-4 complex setup, the output data rate is FS / 4 complex with a Nyquist zone of FS /
8 or 0.125 × F S. The transition band (colored in blue) is centered around 0.125 × FS and the alias transition band
is centered at 0.375 × FS. The stop-bands (colored in red), which alias on top of the pass-band, are centered at
0.25 × FS and 0.5 × FS. The stop-band attenuation is greater than 85 dB.
0
Passband
Transition Band
Alias Band
Attn Spec
-20
Filter
Transition
Bands
Amplitude (dB)
-40
Bands that alias on top
of signal band
Pass Band
-60
-80
-100
-120
0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency (Fs)
Figure 8-24. Interpretation of the Decimation Filter Plots
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0
Passband
Transition Band
Alias Band
Attn Spec
-40
Amplitude (dB)
Amplitude (dB)
-20
-60
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Normalized Frequency (Fs)
Passband
Transition Band
Alias Band
Attn Spec
0
0.025
0.05
0.075
0.1
0.125
0.15
0.175
0.2
0.225
0.25
Normalized Frequency (Fs)
Decb
Figure 8-25. Decimation by 2 complex frequency
response
Decb
Figure 8-26. Decimation by 2 complex passband
ripple response
0
0
Passband
Transition Band
Alias Band
Attn Spec
-20
Passband
Transition Band
Alias Band
Attn Spec
-0.01
-0.02
-0.03
-40
Amplitude (dB)
Amplitude (dB)
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.1
-60
-80
-0.04
-0.05
-0.06
-0.07
-0.08
-100
-0.09
-120
-0.1
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Normalized Frequency (Fs)
0
Figure 8-27. Decimation by 4 complex frequency
response
Amplitude (dB)
Amplitude (dB)
-40
-60
-80
-100
-120
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Normalized Frequency (Fs)
0.4
0.45
0.5
0.04
0.05
0.06
0.07
0.08
0.09
-0.08
-0.081
-0.082
-0.083
-0.084
-0.085
-0.086
-0.087
-0.088
-0.089
-0.09
-0.091
-0.092
-0.093
-0.094
-0.095
-0.096
-0.097
-0.098
-0.099
-0.1
0.1
0.11
0.12
Decb
Passband
Transition Band
Alias Band
Attn Spec
0
0.006
0.012
0.018
0.024
0.03
0.036
0.042
Normalized Frequency (Fs)
Decb
Figure 8-29. Decimation by 8 complex frequency
response
40
0.03
Figure 8-28. Decimation by 4 complex passband
ripple response
Passband
Transition Band
Alias Band
Attn Spec
0
0.02
Normalized Frequency (Fs)
0
-20
0.01
Decb
0.048
0.054
0.06
Decb
Figure 8-30. Decimation by 8 complex passband
ripple response
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-0.1
0
Passband
Transition Band
Alias Band
Attn Spec
-0.12
-0.13
-40
Amplitude (dB)
Amplitude (dB)
-20
Passband
Transition Band
Alias Band
Attn Spec
-0.11
-60
-80
-0.14
-0.15
-0.16
-0.17
-0.18
-100
-0.19
-120
-0.2
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Normalized Frequency (Fs)
0
0.006
0.009
0.012
0.015
0.018
0.021
0.024
0.027
0.03
Normalized Frequency (Fs)
Figure 8-31. Decimation by 16 complex frequency
response
Decb
Figure 8-32. Decimation by 16 complex passband
ripple response
-0.2
0
Passband
Transition Band
Alias Band
Attn Spec
-20
Passband
Transition Band
Alias Band
Attn Spec
-0.205
-0.21
-0.215
-40
Amplitude (dB)
Amplitude (dB)
0.003
Decb
-60
-80
-0.22
-0.225
-0.23
-0.235
-0.24
-100
-0.245
-120
-0.25
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Normalized Frequency (Fs)
0.45
0.5
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
Normalized Frequency (Fs)
Decb
Figure 8-33. Decimation by 32 complex frequency
response
0.016
0.018
0.02
Decb
Figure 8-34. Decimation by 32 complex passband
ripple response
8.3.4.5 SYNC
The PDN/SYNC pin can be used to synchronize multiple devices using an external SYNC signal. The PDN/
SYNC pin can be configured via SPI (SYNC EN bit) from power down to synchronization functionality and is
latched in by the rising edge of the sampling clock as shown in Figure 8-35.
CLK
tS,SYNC
tH,SYNC
SYNC
Figure 8-35. External SYNC timing diagram
The synchronization signal is only required when using the decimation filter - either using the SPI SYNC register
or the PDN/SYNC pin. It resets internal clock dividers used in the decimation filter and aligns the internal clocks
as well as I and Q data within the same sample. If no SYNC signal is given, the internal clock dividers is not
be synchronized, which can lead to a fractional delay across different devices. The SYNC signal also resets the
NCO phase and loads the new NCO frequency (same as the MIXER RESTART bit).
When trying to resynchronize during operation, the SYNC toggle should occur at 64*K clock cycles, where K is
an integer. This provids the phase continuity of the clock divider.
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8.3.4.6 Output Formatting with Decimation
8.3.4.6.1 Parallel CMOS
In parallel CMOS mode, the ADC354x device supports complex decimation output with DDR CMOS interface
and real output with SDR and DDR CMOS interface as shown in Figure 8-36 (complex decimation) and Figure
8-37 (real decimation). In this illustration the output format is selected to 16-bit.
D16..1
DCLK
DCLK
D16
(MSB)
D15
...
D3
D2
D1
Sample
NI
Sample
NQ
Figure 8-36. Output Data Format in Complex Decimation (default bit mapper)
Table 8-4 illustrates the output interface data rate along with the corresponding DCLK frequency based on
complex decimation setting (N).
Furthermore the table shows an actual lane rate example with complex decimation by 4.
Table 8-4. Parallel CMOS Data Rate Examples with Complex Decimation
REAL/COMPLEX
DECIMATION
DECIMATION
SETTING
Complex
42
ADC SAMPLING RATE
DCLK
DOUT (MHz)
N
FS
FS x 2 / N
FS x 4 / N
4
65 MHz
32.5 MHz
65 MHz
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SDR
DDR CMOS
D17..10
D16..1
DCLK
DCLK
DCLK
DCLK
D16
(MSB)
D10
D7
D15
D7
D15
D15
D11
D6
D14
D6
D14
...
...
D3
D15
D2
D10
D2
D10
D2
D16
D1
D9
D1
D9
D1
D17
D0
D8
D0
D8
Sample
A0
Sample
A1
Sample
A0
Sample
A1
Figure 8-37. Output Data Format in Real Decimation (default bit mapper)
Table 8-4 illustrates the output interface data rate along with the corresponding DCLK frequency based on real
decimation setting (M).
Furthermore the table shows an actual lane rate example with complex decimation by 4.
Table 8-5. Parallel CMOS Data Rate Examples with Decimation
REAL/COMPLEX
DECIMATION
DECIMATION
SETTING
ADC SAMPLING RATE
M
FS
Real
4
65 MHz
SDR/DDR
CMOS
SDR
DDR
SDR
DDR
DCLK
FS / M
16.25 MHz
DOUT
FS / M
FS x 2 / M
16.25 MHz
32.5 MHz
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8.3.4.6.2 Serialized CMOS Interface
In serialized CMOS mode, the ADC354x device supports complex decimation output Figure 8-38 and real
decimation output Figure 8-39. The examples are shown for 16-bit output for 2-wire (8x serialization) and 1-wire
(16x serialization).
FCLK
D12
AI
D15
AI
D13
AI
D11
AI
D9
AI
D7
AI
D5
AI
D3
AI
D1
AQ
D15
AQ
D13
AQ
D11
AQ
D9
AQ
D7
AQ
D5
AQ
D3
AQ
D1
D11
AI
D14
AI
D12
AI
D10
AI
D8
AI
D6
AI
D4
AI
D2
AI
D0
AQ
D14
AQ
D12
AQ
D10
AQ
D8
AQ
D6
AQ
D4
AQ
D2
AQ
D0
2-Wire
8x Serialization
DCLK
FCLK
1-Wire
16x Serialization
D11
AI
AQ
DCLK
Figure 8-38. Output Data Format in Complex Decimation
Table 8-6 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK
frequencies based on output resolution (R), number of serial CMOS lanes (L) and complex decimation setting
(N).
Furthermore the table shows an actual lane rate example for the 2- and 1- wire interface, 16-bit output resolution
and complex decimation by 16.
Table 8-6. Serial CMOS Lane Rate Examples with Complex Decimation and 16-bit Output Resolution
44
DECIMATION
SETTING
ADC SAMPLING
RATE
OUTPUT
RESOLUTION
# of WIRES
FCLK
DCLKIN, DCLK
DOUT
N
FS
R
L
FS / N
[DOUT] / 2
FS x 2 x R / L / N
16
65 MSPS
16
2
1
4.0625 MHz
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65 MHz
65 MHz
130 MHz
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FCLK
D12
A0
D15
A0
D13
A0
D11
A0
D9
A0
D7
A0
D5
A0
D3
A0
D1
A1
D15
A1
D13
A1
D11
A1
D9
A1
D7
A1
D5
A1
D3
A1
D1
D11
A0
D14
A0
D12
A0
D10
A0
D8
A0
D6
A0
D4
A0
D2
A0
D0
A1
D14
A1
D12
A1
D10
A1
D8
A1
D6
A1
D4
A1
D2
A1
D0
2-Wire
8x Serialization
DCLK
FCLK
1-Wire
16x Serialization
D11
A0
A1
DCLK
Figure 8-39. Output Data Format in Real Decimation
Table 8-7 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK
frequencies based on output resolution (R), number of serial CMOS lanes (L) and real decimation setting (M).
Furthermore the table shows an actual lane rate example for the 2- and 1-wire interface, 16-bit output resolution
and real decimation by 16.
Table 8-7. Serial CMOS Lane Rate Examples with Real Decimation and 16-bit Output Resolution
DECIMATION
SETTING
ADC SAMPLING
RATE
OUTPUT
RESOLUTION
# of WIRES
FCLK
DCLKIN, DCLK
DOUT
M
FS
R
L
FS / M / 2 (L = 2)
FS / M (L = 1)
[DOUT] / 2
FS x R / L / M
16
65 MSPS
16
2
2.03125 MHz
16.25 MHz
32.5 MHz
1
4.0625 MHz
32.5 MHz
65 MHz
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8.3.5 Digital Interface
The ADC354x family supports two different CMOS output modes - parallel SDR/DDR output and serialized
CMOS output formats.
8.3.5.1 Parallel CMOS Output
The low power CMOS interface supports single data rate (SDR) and double data rate (DDR) output options. In
SDR and DDR output mode the output clock is generated inside the ADC354x. The different interface options
are configured using SPI register writes.
8.3.5.2 Serialized CMOS output
In this mode the output data is serialized and transmitted over 2 or 1 wires. Due to CMOS output speed limitation
this mode is only available for reduced output data rates. This mode is similar to the multi-SPI interface.
8.3.5.2.1 SDR Output Clocking
The ADC354x provides a SDR output clocking option for all serial CMOS output modes (including decimation)
which is enabled using the SPI interface. In serial CMOS mode by default the data is output on rising and falling
edge of DCLK. In SDR clocking mode, DCLKIN has to be twice as fast as the default DCLKIN so that the output
data are clocked out only on DCLK rising edge.
Internally DCLKIN is divided by 2 for data processing and this operation can add 1 extra clock cycle latency to
the ADC latency.
Latency (2 clock cycles)
Sample N
Sample N+1
Sample N+2
Sample N+3
Sample N+4
Sample N+5
Sample N+6
tAD
tPD
Continous
Clock
DCLKIN
DCLKIN
SDR
DCLK
DCLK
SDR
tCD
FCLK
D12
D11
Sample N-1
Sample N
Sample N+1
Sample N+2
Figure 8-40. SDR Output Clocking
46
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8.3.5.3 Output Data Format
The output data can be configured to two's complement (default) or offset binary formatting using SPI register
writes (register 0x8F and 0x92). Table 8-8 provides an overview for minimum and maximum output codes for the
two formatting options. The actual output resolution is set by the output bit mapper.
Table 8-8. Overview of minimum and maximum output codes vs resolution for different formatting
Two's Complement (default)
RESOLUTION (BIT)
14
VIN,MAX
0x1FFF
0
16
18
0x7FFF
0x1FFFF
0x0000
VIN,MIN
0x2000
Offset Binary
20
14
16
18
20
0x7FFFF
0x3FFF
0xFFFF
0x3FFFF
0xFFFFF
0x2000
0x8000
0x20000
0x80000
0x00000
0x8000
0x20000
0x80000
0x0000
0x00000
8.3.5.4 Output Formatter
The digital output interface utilizes a flexible output bit mapper Figure 8-41. The bit mapper takes the 14-bit
output directly from the ADC or from digital filter block and reformats it to a resolution of 14, 16, 18 or 20-bit. With
parallel output format the maximum output resolution supported is 16-bit. With serial CMOS output the output
serialization factor gets adjusted accordingly for 2- and 1-wire interface mode. The maximum output data rate
can not be exceeded independently of output resolution and serialization factor.
Output
Formatter
14/16/18/
20-bit
NCO
TEST
PATTERN
N
DIG
I/F
Output
Bit Mapper
Figure 8-41. Interface output bit mapper
Table 8-9 provides an overview for the resulting serialization factor depending on output resolution and output
modes. Note that the DCLKIN frequency needs to be adjusted accordingly as well. Changing the output
resolution to 16-bit, 2-wire mode for example would result in DCLKIN = FS * 4 instead of * 3.5.
The output bit mapper can be used for bypass and decimation filter.
Table 8-9. Serialization factor vs output resolution for different output modes
OUTPUT
RESOLUTION
14-bit (default)
16-bit
18-bit
20-bit
Interface
SERIALIZATION
FCLK
DCLKIN
DCLK
D0/D1
2-Wire
7x
FS/2
FS* 3.5
FS* 3.5
FS* 7
1-Wire
14x
FS
FS* 7
FS* 7
FS* 14
2-Wire
8x
FS/2
FS* 4
FS* 4
FS* 8
1-Wire
16x
FS
FS* 8
FS* 8
FS* 16
2-Wire
9x
FS/2
FS* 4.5
FS* 4.5
FS* 9
1-Wire
18x
FS
FS* 9
FS* 9
FS* 18
2-Wire
10x
FS/2
FS* 5
FS* 5
FS* 10
1-Wire
20x
FS
FS* 10
FS* 10
FS* 20
The programming sequence to change the output interface and/or resolution from default settings is shown in
Section 8.3.5.6.
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8.3.5.5 Output Bit Mapper
The output bit mapper allows to change the output bit order for any selected interface mode.
NCO
N
TEST
PATTERN
DIG
I/F
Output
Formatter
14/16/18/
20-bit
Output
Bit Mapper
Figure 8-42. Output Bit Mapper
It is a two step process to change the output bit mapping and assemble the output data bus:
1. In parallel interface mode, the maximum output resolution is 18-bit, in serial interface mode the maximum
output resolution is 20-bit. Each output bit of either channel has a unique identifier bit as shown in the Table
8-10. The MSB starts with bit D19 – depending on output resolution chosen the LSB would be D6 (14-bit) to
D0 (20-bit). The ‘previous sample’ is only needed in 2-w mode.
2. The bit mapper is then used to assemble the output sample. The following sections detail how to remap both
a parallel and a serial output format.
Table 8-10. Unique identifier of each data bit
48
Bit
Previous sample (2w only)
Current sample
D19 (MSB)
0x2D
0x6D
D18
0x2C
0x6C
D17
0x27
0x67
D16
0x26
0x66
D15
0x25
0x65
D14
0x24
0x64
D13
0x1F
0x5F
D12
0x1E
0x5E
D11
0x1D
0x5D
D10
0x1C
0x5C
D9
0x17
0x57
D8
0x16
0x56
D7
0x15
0x55
D6
0x14
0x54
D5
0x0F
0x4F
D4
0x0E
0x4E
D3
0x0D
0x4D
D2
0x0C
0x4C
D1
0x07
0x47
D0 (LSB)
0x06
0x46
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In parallel SDR mode, a data bit (with unique identifier) needs to be assigned to each output pin using the
register addresses as shown in Figure 8-43. The example on the right shows the 14-bit output data bus
remapped to reverse order to where the MSB starts on pin D2 instead of pin D15.
DCLK
D2
D13 (0x3B, 0x6D)
D3
D12 (0x3C, 0x6C)
D4
D11 (0x3D, 0x67)
D5
D10 (0x3E, 0x66)
D6
D9 (0x3F, 0x65)
D7
D8 (0x40, 0x64)
D8
D7 (0x41, 0x5F)
D9
D6 (0x42, 0x5E)
D10
D5 (0x43, 0x5D)
D11
D4 (0x4A, 0x5C)
D12
D3 (0x49, 0x57)
D13
D2 (0x48, 0x56)
D14
D1 (0x47, 0x55)
D15
D0 (0x46, 0x54)
Figure 8-43. SDR output mapping (left) and example (right)
In parallel DDR mode, a data bit (with unique identifier) needs to be assigned to each output pin for both the
rising and the falling edge of the DCLK using the register addresses as shown on the left of Figure 8-44. D9 and
D10 are used for 16 and 18-bit output. The example on the right shows the 14-bit output data bus remapped to
where the MSB starts on D17 instead of D11.
DCLK
D11
D0 (0x72, 0x54)
D7 (0x4A, 0x5F)
D12
D1 (0x71, 0x55)
D8 (0x49, 0x64)
D13
D2 (0x70, 0x56)
D9 (0x48, 0x65)
D14
D3 (0x6F, 0x57)
D10 (0x47, 0x66)
D15
D4 (0x6E, 0x5C) D11 (0x46, 0x67)
D16
D5 (0x6D, 0x5D) D12 (0x45, 0x6C)
D17
D6 (0x6C, 0x5E) D13 (0x44, 0x6D)
Figure 8-44. DDR output timing mapping (left) and example (right)
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In the serial output mode, a data bit (with unique identifier) needs to be assigned to each location within the
serial output stream. There are a total of 40 addresses (0x39 to 0x60). When using complex decimation, the
output bit mapper is applied to both the “I” and the “Q” sample.
2-wire mode: in this mode both the current and the previous sample have to be used in the address space as
shown in Figure 8-45 below. The address order is different for 14/18-bit and 16/20-bit. Note: there are unused
addresses between samples for resolution less than 20-bit (grey back ground), which can be skipped if not used.
14-bit
16-bit 18-bit 20-bit
14-bit
16-bit 18-bit 20-bit
0x5F 0x60 0x5D 0x5E 0x5B 0x5C 0x59 0x5A 0x57 0x58 0x55 0x56 0x53 0x54 0x51 0x52 0x4F 0x50 0x4D 0x4E
0x60 0x5F 0x5E 0x5D 0x5C 0x5B 0x5A 0x59 0x58 0x57 0x56 0x55 0x54 0x53 0x52 0x51 0x50 0x4F 0x4E 0x4D
D12
14/18-bit
16/20-bit
D11
14/18-bit 0x4B 0x4C 0x49 0x4A 0x47 0x48 0x45 0x46 0x43 0x44 0x41 0x42 0x3F 0x40 0x3D 0x3E 0x3B 0x3C 0x39 0x3A
16/20-bit 0x4C 0x4B 0x4A 0x49 0x48 0x47 0x46 0x45 0x44 0x43 0x42 0x41 0x40 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39
Previous Sample
Current Sample
Figure 8-45. 2-wire output bit mapper
In the following example (Figure 8-46), the 16-bit 2-wire serial output is reordered to where pin D12 carries the 8
MSB and pin D11 carries 8 LSBs.
D12
D11
D19A
(0x60
0x2D)
D11A
(0x4C
0x1D)
D18A
(0x5F
0x2C)
D10A
(0x4B
0x1C)
D17A
(0x5E
0x27)
D9A
(0x4A
0x17)
Previous Sample
D16A
D15A
(0x5D
(0x5C
0x26)
0x25)
D8A
D7A
(0x49
(0x48
0x16)
0x15)
D14A
(0x5B
0x24)
D6A
(0x47
0x14)
D13A
(0x5A
0x1F)
D5A
(0x46
0x0F)
D12A
(0x59
0x1E)
D4A
(0x45
0x0E)
D19A
(0x56
0x6D)
D11A
(0x42
0x5D)
D18A
(0x55
0x6C)
D10A
(0x41
0x5C)
D17A
(0x54
0x67)
D9A
(0x40
0x57)
Current Sample
D16A
D15A
(0x53
(0x52
0x66)
0x65)
D8A
D7A
(0x39
(0x38
0x56)
0x55)
D14A
(0x51
0x64)
D6A
(0x37
0x54)
D13A
(0x50
0x5F)
D5A
(0x36
0x4F)
D12A
(0x4F
0x5E)
D4A
(0x35
0x4E)
Figure 8-46. Example: 2-wire output mapping
1-wire mode: Only the ‘current’ sample needs to programmed in the address space.
14-bit
D11
(default)
16-bit
18-bit
20-bit
0x4C 0x4B 0x4A 0x49 0x48 0x47 0x46 0x45 0x44 0x43 0x42 0x41 0x40 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39
Figure 8-47. 1-wire output bit mapping
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8.3.5.6 Output Interface/Mode Configuration
The following sequence summarizes all the relevant registers for changing the output interface and/or enabling
the decimation filter. Steps 1 and 2 must come first since the E-Fuse load reset the SPI writes, the remaining
steps can come in any order.
Table 8-11. Configuration steps for changing interface or decimation
STEP
FEATURE
ADDRESS
DESCRIPTION
Select the output interface bit mapping depending on resolution and output interface.
Output Resolution
1
14-bit
0x07
SDR
DDR
2-wire
0xC8
0xA9
18-bit
N/A
N/A
0x2B
20-bit
N/A
N/A
0x4B
16-bit
1-wire
0x2B
0x4B
0x6C
Load the output interface bit mapping using the E-fuse loader (0x13, D0). Program register 0x13
to 0x01, wait ~ 1ms so that bit mapping is loaded properly followed by 0x13 0x00
2
0x13
3
0x0A/B/C
Power down relevant CMOS output buffers to avoid contention.
4
0x18
For serial CMOS modes, DCLKIN EN (D4) needs to be enabled.
In serial CMOS, configure the FCLK registers based on bypass/decimation and # of lanes used.
Bypass/Decimation
5
0x19
Output
Interface
Bypass/ Real Decimation
Complex Decimation
SCMOS
FCLK SRC
(D7)
FCLK DIV
(D4)
2-wire
0
1
1-wire
0
0
2-wire
1
0
1-wire
1
0
6
0x1B
Select the output interface resolution using the bit mapper (D5-D3).
7
0x1F
For serial CMOS modes, DCLKIN EN (D6) and DCLK OB EN (D4) need to be enabled.
In serial CMOS, select the FCLK pattern for decimation for proper duty cycle output of the FCLK.
Decimation
0x20
0x21
0x22
8
Real Decimation
Output
Resolution
2-wire
14-bit
0xFE000
16-bit
0xFF000
18-bit
0xFF800
20-bit
0xFFC00
use default
14-bit
Complex Decimation
1-wire
16-bit
0xFFFFF
18-bit
20-bit
9
0x39..0x72
Change output bit mapping if desired. This also works with the default interface selection.
10
0x24
Enable the decimation filter
11
0x25
Configure the decimation filter
12
0x2A/B/C/D
Program the NCO frequency for complex decimation (can be skipped for real decimation)
Configure the complex output data stream (set both bits to 0 for real decimation)
Decimation
Filter
13
0x27
14
0x26
Serial CMOS
OP-Order (D4)
Q-Delay (D3)
2-wire
1
0
1-wire
0
1
Set the mixer gain and toggle the mixer reset bit to update the NCO frequency.
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8.3.5.6.1 Configuration Example
The following is a step by step programming example to configure the ADC354x to complex decimation by 8 with
1-wire serial CMOS and 16-bit output.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
0x07 (address) 0x6C (load bit mapper configuration for 16-bit output with 1-wire serial CMOS)
0x13 0x01, wait 1 ms, 0x13 0x00 (load e-fuse)
0x0A 0xFF, 0x0B 0xFF, 0x0C 0xFD (power down unused CMOS output buffers to avoid contention)
0x18 0x10 (DCLKIN EN for serial CMOS mode)
0x19 0x82 (configure FCLK)
0x1B 0x88 (select 16-bit output resolution)
0x1F 0x50 (DCLKIN EN for serial CMOS mode)
0x20 0xFF, 0x21 0xFF, 0x22 0x0F (configure FCLK pattern)
0x24 0x06 (enable decimation filter)
0x25 0x30 (configure complex decimation by 8)
0x2A/B/C/D (program NCO frequency)
0x27/0x2E 0x08 (configure Q-delay register bit)
0x26 0xAA (set digital mixer gain to 6-dB and toggle the mixer update)
8.3.6 Test Pattern
In order to enable in-circuit testing of the digital interface, the following test patterns are supported and enabled
via SPI register writes (0x14/0x15/0x16). The test pattern generator is located after the decimation filter as
shown in Figure 8-48. In decimation mode (real and complex), the test patterns replace the output data of the
DDC - however channel A controls the test patterns for both channels.
NCO
N
TEST
PATTERN
Output
Formatter
14/16/18/
20-bit
DIG
I/F
Output
Bit Mapper
Figure 8-48. Test Pattern Generator
•
•
52
RAMP Pattern: The step size is set in the CUSTOM PAT register according to the native ADC resolution.
When selecting a higher output resolution then the additional LSBs will still be 0 in RAMP pattern mode.
– 00001: 18-bit output resolution
– 00100: 16-bit output resolution
– 10000: 14-bit output resolution
Custom Pattern: Configured in the CUSTOM PAT register
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8.4 Device Functional Modes
8.4.1 Normal operation
In normal operating mode, the entire ADC full scale range gets converted to a digital output with 14-bit
resolution. The output is available in as little as 1 clock cycle on the digital CMOS outputs.
8.4.2 Power Down Options
A global power down mode can be enabled via SPI as well as using the power down pin (PDN/SYNC). There is
an internal pull-down 21 kΩ resistor on the PDN/SYNC input pin and the pin is active high - so the pin needs to
be pulled high externally to enter global power down mode.
The SPI register map provides the capability to enable/disable individual blocks directly or via PDN pin mask in
order to trade off power consumption vs wake up time as shown in Table 8-12.
REFBUF
1.2V REF
Digital Downconverter
VREF
NCO
AIN
ADC
N
Dig I/F
CLK
Figure 8-49. Power Down Configurations
Table 8-12. Overview of Power Down Options
Function/ Register
PDN
via SPI
Mask for
Global PDN
Feature Default
Power
Impact
Wake-up
time
ADC
Yes
-
Enabled
Reference gain amplifier
Yes
Enabled
~ 0.4 mA
~3 us
Should only be powered down in power
down state.
Internal 1.2V reference
Yes
External ref
~ 1-3.5 mA
~3 ms
Internal/external reference selection is
available through SPI and REFBUF pin.
Comment
ADC is included in Global PDN
automatically
Yes
Differential
clock
~ 1 mA
n/a
Single ended clock input saves ~ 1 mA
compared to differential.
Some programmability is available
through the REFBUF pin.
Depending on output interface mode,
unused output drivers can be powered
down for maximum power savings
Clock buffer
Yes
Output interface drivers
Yes
-
Enabled
varies
n/a
Decimation filter
Yes
-
Disabled
see electrical
table
n/a
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8.5 Programming
The device is primarily configured and controlled using the serial programming interface (SPI) however it can
operate in a default configuration without requiring the SPI interface. Furthermore the power down function as
well as internal/external reference configuration is possible via pin control (PDN/SYNC and REFBUF pin).
Note
The power down command (via PIN or SPI) only goes in effect with the ADC sampling clock present.
After initial power up, the default operating configuration for each device is shown in Table 8-13.
Table 8-13. Default device configuration after power up
Feature
ADC3541
ADC3542
Signal Input
ADC3543
Differential
Auto-zero
Enabled
Enabled
Clock Input
Disabled
Differential
Reference
External
Decimation
DDC bypass
Interface
SDR CMOS
Output Format
2s compliment
8.5.1 Configuration using PINs only
The ADC voltage reference can be selected using the REFBUF pin. Even though there is an internal 100 kΩ
pull-up resistor to AVDD, the REFBUF pin should be set to a voltage externally and not left floating.
Table 8-14. REFBUF voltage levels control voltage reference selection
REFBUF VOLTAGE
VOLTAGE REFERENCE OPTION
CLOCKING OPTION
Digital Interface
> 1.7 V (Default)
External reference
Differential clock input
SDR CMOS
1.2 V (1.15-1.25V)
External 1.2 V input on REFBUF pin using internal
gain buffer
Differential clock input
SDR CMOS
0.5 - 0.7V
Internal reference
Differential clock input
SDR CMOS
< 0.1V
Internal reference
Single ended clock input
Serial CMOS 2-wire
8.5.2 Configuration Using the SPI Interface
The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock) and SDIO (serial interface data input/output) pins. Serially shifting
bits into the device is enabled when SEN is low. Serial data input are latched at every SCLK rising edge when
SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low.
When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples
of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 12 MHz
down to low speeds (of a few hertz) and also with a non-50 % SCLK duty cycle.
8.5.2.1 Register Write
The internal registers can be programmed following these steps:
1.
2.
3.
4.
Drive the SEN pin low
Set the R/W bit to 0 (bit A15 of the 16-bit address) and bits A[14:12] in address field to 0.
Initiate a serial interface cycle by specifying the address of the register (A[11:0]) whose content is written and
Write the 8-bit data that are latched in on the SCLK rising edges
Figure 8-50 show the timing requirements for the serial register write operation.
54
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Register Address
R/W
SDIO
0
0
0
0
A11
A10
A9
A8
A7
A6
A5
A4
Register Data
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tH,SDIO
tSCLK
tS,SDIO
SCLK
tS,SEN
tH,SEN
SEN
RESET
Figure 8-50. Serial Register Write Timing Diagram
8.5.2.2 Register Read
The device includes a mode where the contents of the internal registers can be read back using the SDIO pin.
This readback mode can be useful as a diagnostic check to verify the serial interface communication between
the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:
1. Drive the SEN pin low
2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers. Set A[14:12] in address
field to 0.
3. Initiate a serial interface cycle specifying the address of the register (A[11:0]) whose content must be read
4. The device launches the contents (D[7:0]) of the selected register on the SDIO pin on SCLK falling edge
5. The external controller can capture the contents on the SCLK rising edge
Register Address
R/W
SDIO
1
0
0
0
A11
A10
A9
A8
A7
A6
A5
A4
Register Data
tOZD
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tOD
SCLK
tODZ
SEN
Figure 8-51. Serial Register Read Timing Diagram
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8.6 Register Map
Table 8-15. Register Map Summary
REGISTER
ADDRESS
REGISTER DATA
A[11:0]
D7
0x00
0
0x07
0x08
D6
D5
D4
0
0
OP IF MAPPER
0
0
PDN CLKBUF
D2
0
0
0
0
OP IF EN
PDN
REFAMP
0
0x0A
CMOS OB DIS [7:0]
0x0B
CMOS OB DIS [15:8]
0x0C
D1
D0
0
RESET
OP IF SEL
PDN A
1
PDN
GLOBAL
MASK
REFAMP
MASK BG
DIS
0
CMOS OB DIS [23:16]
0x0D
0
0
MASK
REFSYS A
0x0E
SYNC PIN
EN
SPI SYNC
SPI SYNC EN
0
REF CTRL
0x11
0
0
SE A
0
0
DLL PDN
0
AZ EN
0x13
0
0
0
0
0
0
0
E-FUSE LD
0
MASK
CLKBUF
0x14
CUSTOM PAT [7:0]
0x15
CUSTOM PAT [15:8]
0x16
0
0
0
0x18
0
0
0
0
0x19
FCLK SRC
0
0x1B
MAPPER EN
20B EN
0x1E
0
0
0x1F
LOW DR EN
DCLKIN EN
TEST PAT A
0
0
FCLK DIV
0
0
FCLK EN
0
0
0
0
0
0
0
0
2X DCLK
0
0
0
CMOS DCLK DEL
DCLK OB EN
FCLK PAT [7:0]
FCLK PAT [15:8]
0x22
0
0
0
0
0x24
0
0
0
0
0x25
0
0x27
FCLK PAT [19:16]
DECIMATION
0
0
0
DIG BYP
DDC EN
0
REAL OUT
0
0
MIX PHASE
MIX RES A
FS/4 MIX A
0
0
0
0
0
OP ORDER A
Q-DEL A
FS/4 MIX PH
A
0
0
0
FORMAT A
0
0x2A
NCO A [7:0]
0x2B
NCO A [15:8]
0x2C
NCO A [23:16]
0x2D
NCO A [31:24]
0x39..0x72
0x8F
CUSTOM PAT [17:16]
0
BIT MAPPER RES
0
SE CLK EN
0
0x21
MIX GAIN A
REF SEL
DCLKIN EN
0x20
0x26
56
D3
OUTPUT BIT MAPPER
0
0
0
0
0
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8.6.1 Detailed Register Description
Figure 8-52. Register 0x00
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
RESET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-16. Register 0x00 Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
R/W
0
Must write 0
RESET
R/W
0
This bit resets all internal registers to the default values and self
clears to 0.
0
Figure 8-53. Register 0x07
7
6
5
4
3
0
OP IF EN
R/W-0
R/W-0
R/W-0
OP IF MAPPER
R/W-0
R/W-0
2
1
0
OP IF SEL
R/W-0
R/W-0
R/W-0
Table 8-17. Register 0x07 Field Descriptions
Bit
Field
Type
Reset
Description
7-5
OP IF MAPPER
R/W
000
This register contains the proper output interface bit mapping for
the different interfaces. The interface bit mapping is internally
loaded from e-fuses and also requires a fuse load command to
go into effect (0x13, D0). Register 0x07 along with the E-Fuse
Load (0x13, D0) needs to be loaded first in the programming
sequence since the E-Fuse load resets the SPI writes.
After initial reset the default output interface variant is loaded
automatically from fuse internally. However when reading back
this register reads 000 until a value is written using SPI.
001: 2-wire, 18 and 14-bit
010: 2-wire, 16-bit
011: 1-wire
100: 0.5-wire
101: DDR
110: SDR
4
0
R/W
0
Must write 0
3
OP IF EN
R/W
0
Enables changing the default output interface mode (D2-D0).
2-0
OP IF SEL
R/W
000
Selects the output interface mode. OP IF EN (D3) needs to
be enabled also.After initial reset the default output interface is
loaded automatically from fuse internally. However when reading
back this register reads 000 until a value is written using SPI.
000: SDR CMOS
001: DDR CMOS
011: 2-wire
100: 1-wire
101: 0.5-wire
others: not used
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Figure 8-54. Register 0x08
7
6
5
4
3
2
1
0
0
0
PDN CLKBUF
PDN REFAMP
0
PDN A
1
PDN GLOBAL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-18. Register 0x08 Field Descriptions
58
Bit
Field
Type
Reset
Description
7-6
0
R/W
0
Must write 0
5
PDN CLKBUF
R/W
0
Powers down sampling clock buffer
0: Clock buffer enabled
1: Clock buffer powered down
4
PDN REFAMP
R/W
0
Powers down internal reference gain amplifier
0: REFAMP enabled
1: REFAMP powered down
3
0
R/W
0
Must write 0
2
PDN A
R/W
0
Powers down ADC channel A
0: ADC channel A enabled
1: ADC channel A powered down
1
1
R/W
1
Must write 1
0
PDN GLOBAL
R/W
0
Global power down via SPI
0: Global power disabled
1: Global power down enabled. Power down mask (register
0x0D) determines which internal blocks are powered down.
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Figure 8-55. Register 0x0A, B, C
7
6
5
4
3
2
1
0
R/W-0
R/W-0
R/W-0
CMOS OB DIS [23:0]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-19. Register 0x0A/B/C Field Descriptions
Bit
Field
Type
Reset
Description
7:0
CMOS OB DIS [23:0]
R/W
0
These register bits power down the individual CMOS output
buffers. See Table 8-20 for the actual bit to pin mapping. Unused
pins should be powered down (ie set to 1) for maximum power
savings.
There is a separate control to enable the DCLKIN buffer in
register 0x1F (D6) and 0x18 (D4). DCLK output buffer is
powered down using register 0x1F (D4).
NOTE: When using serial CMOS interface the CMOS output
buffer (D3) has to be powered down because it shares the pin
with DCLKIN.
0: Output buffer enabled
1: Output buffer powered down
Table 8-20. Output buffer enable bit mapping vs output interface mode
ADDRESS (HEX)
0x0A
BIT
PIN NAME
SDR CMOS
DDR CMOS
SCMOS 2-w
SCMOS 1-w
D7
D7
D7
D7
-
-
D6
-
-
-
-
-
D5
-
-
-
-
-
D4
D4
D4
-
-
-
D3
D3
D3
-
DCLKIN
DCLKIN
D2
D2
D2
-
-
-
D1
D1
D1
-
-
-
D0
D0
D0
-
-
-
Register setting
0x0B
0x60
0x7F
0xFF
0xFF
D7
D13
D13
-
-
-
D6
D14
D14
-
-
-
D5
D15
D15
-
-
-
D4
FCLK
-
-
FCLK
FCLK
D3
-
-
-
-
-
D2
-
-
-
-
-
D1
-
-
-
-
-
D0
D8
Register setting
0x0C
D8
D8
-
-
0x1E
0xFE
0xEF
0xEF
D7
D10
D10
D10
-
-
D6
D9
D9
D9
-
-
D5
D6
D6
D6
-
-
D4
D5
D5
D5
-
-
D3
-
-
-
-
-
D2
-
-
-
-
-
D1
D11
D11
D11
D11
D11
D0
D12
Register setting
D12
D12
D12
-
0x0C
0x0C
0xFC
0xFD
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Figure 8-56. Register 0x0D (PDN GLOBAL MASK)
7
6
5
4
0
0
MASK REFSYS
A
0
3
R/W-0
R/W-0
R/W-0
R/W-0
2
1
MASK CLKBUF MASK REFAMP MASK BG DIS
R/W-0
R/W-0
R/W-0
0
0
R/W-0
Table 8-21. Register 0x0D Field Descriptions
Bit
60
Field
Type
Reset
Description
7
0
R/W
0
Must write 0
6
0
R/W
0
Must write 0
5
MASK REFSYS A
R/W
0
Global power down mask control for internal bias currents, ADC
channel A.
0: Internal bias currents will get powered down when global
power down is exercised.
1: Internal bias currents will NOT get powered down when global
power down is exercised.
4
0
R/W
0
Must write 0
3
MASK CLKBUF
R/W
0
Global power down mask control for sampling clock input buffer.
0: Clock buffer will get powered down when global power down
is exercised.
1: Clock buffer will NOT get powered down when global power
down is exercised.
2
MASK REFAMP
R/W
0
Global power down mask control for reference amplifier.
0: Reference amplifier will get powered down when global power
down is exercised.
1: Reference amplifier will NOT get powered down when global
power down is exercised.
1
MASK BG DIS
R/W
0
Global power down mask control for internal 1.2V bandgap
voltage reference. Setting this bit reduces power consumption
in global power down mode but increases the wake up time. See
the power down option overview.
0: Internal 1.2V bandgap voltage reference will NOT get
powered down when global power down is exercised.
1: Internal 1.2V bandgap voltage reference will get powered
down when global power down is exercised.
0
0
R/W
0
Must write 0
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Figure 8-57. Register 0x0E
7
6
5
4
3
SYNC PIN EN
SPI SYNC
SPI SYNC EN
0
REF CTL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
2
1
REF SEL
R/W-0
0
SE CLK EN
R/W-0
R/W-0
Table 8-22. Register 0x0E Field Descriptions
Bit
Field
Type
Reset
Description
7
SYNC PIN EN
R/W
0
This bit controls the functionality of the SYNC/PDN pin.
0: SYNC/PDN pin exercises global power down mode when pin
is pulled high.
1: SYNC/PDN pin issues the SYNC command when pin is
pulled high.
6
SPI SYNC
R/W
0
Toggling this bit issues the SYNC command using the SPI
register write. SYNC using SPI must be enabled as well (D5).
This bit doesn't self reset to 0.
0: Normal operation
1: SYNC command issued.
5
SPI SYNC EN
R/W
0
This bit enables synchronization using SPI instead of the
SYNC/PDN pin.
0: Synchronization using SPI register bit disabled.
1: Synchronization using SPI register bit enabled.
4
0
R/W
0
Must write 0
3
REF CTL
R/W
0
This bit determines if the REFBUF pin controls the voltage
reference selection or the SPI register (D2-D1).
0: The REFBUF pin selects the voltage reference option.
1: Voltage reference is selected using SPI (D2-D1) and single
ended clock using D0.
2-1
REF SEL
R/W
00
Selects of the voltage reference option. REF CTRL (D3) must be
set to 1.
00: Internal reference
01: External voltage reference (1.2V) using internal reference
buffer (REFBUF)
10: External voltage reference
11: not used
SE CLK EN
R/W
0
Selects single ended clock input and powers down the
differential sampling clock input buffer. REF CRTL (D3) must be
set to 1.
0: Differential clock input
1: Single ended clock input
0
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Figure 8-58. Register 0x11
7
6
5
4
3
2
1
0
0
0
SE A
0
0
DLL PDN
0
AZ EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-23. Register 0x11 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
R/W
0
Must write 0
SE A
R/W
0
This bit enables single ended analog input, channel A. In this
mode the SNR reduces by 3-dB.
0: Differential input
1: Single ended input.
0
R/W
0
Must write 0
2
DLL PDN
R/W
0
This register applies ONLY to the ADC3543. It powers down
the internal DLL, which is used to adjust the sampling time.
This register must be enabled when operating at sampling rates
below 40 MSPS. When DLL PDN bit is enabled the sampling
time is directly dependent on sampling clock duty cycle (with a
50/50 duty the sampling time is TS/2).
0: Sampling time is TS/ 4
1: Sampling time is TS/2 (only for sampling rates below 40
MSPS).
1
0
R/W
0
Must write 0
0
AZ EN
R/W
0/1
This bit enables the internal auto-zero circuitry. It is enabled by
default for the ADC3541/42 and disabled for the ADC3543.
0: Auto-zero disabled
1: Auto-zero enabled
5
4-3
Figure 8-59. Register 0x13
7
6
5
4
3
2
0
0
0
0
0
0
1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
0
E-FUSE LD
R/W-0
R/W-0
Table 8-24. Register 0x13 Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
R/W
0
Must write 0
E-FUSE LD
R/W
0
This register bit loads the internal bit mapping for different
interfaces. After setting the interface in register 0x07, this EFUSE LD bit needs to be set to 1 and reset to 0 for loading to go
into effect. Register 0x07 along with the E-Fuse Load (0x13, D0)
needs to be loaded first in the programming sequence since the
E-Fuse load resets the SPI writes.
0: E-FUSE LOAD set
1: E-FUSE LOAD reset
0
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Figure 8-60. Register 0x14/15/16
7
6
5
4
3
2
1
0
CUSTOM PAT [7:0]
CUSTOM PAT [15:8]
0
0
0
R/W-0
R/W-0
R/W-0
TEST PAT A
R/W-0
R/W-0
CUSTOM PAT [17:16]
R/W-0
R/W-0
R/W-0
Table 8-25. Register 0x14, 15, 16 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CUSTOM PAT [17:0]
R/W
00000000
This register is used for two purposes:
•
•
It sets the constant custom pattern starting from MSB
It sets the RAMP pattern increment step size.
00001: Ramp pattern for 18-bit ADC
00100: Ramp pattern for 16-bit ADC
10000: Ramp pattern for 14-bit ADC
7-5
0
R/W
0
Must write 0.
4-2
TEST PAT A
R/W
000
Enables test pattern output mode for channel A (NOTE: The test
pattern is set prior to the bit mapper and is based on native
resolution of the ADC starting from the MSB). These work in
either output format.
000: Normal output mode (test pattern output disabled)
010: Ramp pattern: need to set proper increment using
CUSTOM PAT register
011: Constant Pattern using CUSTOM PAT [17:0] in register
0x14/15/16.
others: not used
Figure 8-61. Register 0x18
7
6
5
4
3
2
1
0
0
0
0
DCLKIN EN
0
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-26. Register 0x18 Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
R/W
0
Must write 0
DCLKIN EN
R/W
0
This bit enables the DCLKIN clock input buffer for serial CMOS
modes. Also DCLKIN EN (0x1F, D6) needs to be set as well.
0: DCLKIN buffer powered down.
1: DCLKIN buffer enabled.
0
R/W
0
Must write 0
4
3-0
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Figure 8-62. Register 0x19
7
6
5
4
3
2
1
0
FCLK SRC
0
0
FCLK DIV
0
0
FCLK EN
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-27. Register 0x19 Field Descriptions
Bit
Field
Type
Reset
Description
FCLK SRC
R/W
0
User has to select if FCLK signal comes from ADC or from DDC
block. Here real decimation is treated same as bypass mode
0: FCLK generated from ADC. FCLK SRC set to 0 for DDC
bypass and real decimation mode
1: FCLK generated from DDC block. In complex decimation
mode only this bit needs to be set for 2-w and 1-w output
interface mode.
0
R/W
0
Must write 0
FCLK DIV
R/W
0
This bit needs to be set to 1 for 2-w output mode in bypass
mode only (non decimation).
0: All output interface modes except 2-w bypass mode..
1: 2-w output interface mode.
0
R/W
0
Must write 0
1
FCLK EN
R/W
0
This bit enables FCLK output for CMOS output.
0: Data output pin is used for parallel output data.
1: Data output pin is used for FCLK output in serialized CMOS
mode.
0
0
R/W
0
Must write 0
7
6-5
4
3-2
Table 8-28. Configuration of FCLK SRC and FCLK DIV Register Bits vs Serial Interface
BYPASS/DECIMATION
Decimation Bypass/ Real Decimation
Complex Decimation
64
SERIAL INTERFACE
FCLK SRC
FCLK DIV
2-wire
0
1
1-wire
0
0
2-wire
1
0
1-wire
1
0
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Figure 8-63. Register 0x1B
7
6
5
MAPPER EN
20B EN
R/W-0
R/W-0
4
3
BIT MAPPER RES
R/W-0
R/W-0
R/W-0
2
1
0
0
0
0
R/W-0
R/W-0
R/W-0
Table 8-29. Register 0x1B Field Descriptions
Bit
Field
Type
Reset
Description
7
MAPPER EN
R/W
0
This bit enables changing the resolution of the output (including
output serialization factor) in bypass mode only.
0: Output bit mapper disabled.
1: Output bit mapper enabled.
6
20B EN
R/W
0
This bit enables 20-bit output resolution which can be useful
for high decimation settings so that quantization noise doesn't
impact the ADC performance.
0: 20-bit output resolution disabled.
1: 20-bit output resolution enabled.
5-3
BIT MAPPER RES
R/W
000
Sets the output resolution using the bit mapper. MAPPER EN bit
(D6) needs to be enabled when operating in bypass mode..
000: 18 bit
001: 16 bit
010: 14 bit
all others, n/a
2-0
0
R/W
0
Must write 0
Table 8-30. Register Settings for Output Bit Mapper vs Operating Mode
BYPASS/
DECIMATION
OUTPUT RESOLUTION
MAPPER EN (D7)
Decimation Bypass
Resolution Change
1
Real Decimation
000: 18-bit
001: 16-bit
010: 14-bit
0
Resolution Change (default 18-bit)
Complex Decimation
BIT MAPPER RES (D5-D3)
0
Figure 8-64. Register 0x1E
7
6
5
4
3
2
1
0
0
0
CMOS DCLK DEL
0
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-31. Register 0x1E Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
R/W
0
Must write 0
5-4
CMOS DCLK DEL
R/W
00
These bits adjust the output timing of CMOS DCLK output.
00: no delay
01: DCLK advanced by 50 ps
10: DCLK delayed by 50 ps
11: DCLK delayed by 100 ps
3-0
0
R/W
0
Must write 0
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Figure 8-65. Register 0x1F
7
6
5
4
3
2
1
0
LOW DR EN
DCLKIN EN
0
DCLK OB EN
2X DCLK
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-32. Register 0x1F Field Descriptions
Bit
Field
Type
Reset
Description
7
LOW DR EN
R/W
0
This bit impacts the output drive strength of the CMOS output
buffers. This bit can be enabled at slow speeds in order to save
power consumption but it will also degrade the rise and fall
times.
0: Low drive strength disabled.
1: Low drive strength enabled.
6
DCLKIN EN
R/W
0
This bit enables the DCLKIN clock input buffer for serial CMOS
modes. Also DCLKIN EN (0x18, D4) needs to be set as well.
0: DCLKIN buffer powered down.
1: DCLKIN buffer enabled.
5
0
R/W
0
Must write 0
4
DCLK OB EN
R/W
1
This bit enables DCLK output buffer.
0: DCLK output buffer powered down.
1: DCLK output buffer enabled.
3
2X DCLK
R/W
0
This bit enables SDR output clocking with serial CMOS mode.
When this mode is enabled, DCLKIN required is twice as fast
and data is output only on rising edge of DCLK.
0: Normal operation with data output on DCLK rising and falling
edge.
1: 2x DCLK mode enabled with data output on DCLK rising edge
only.
0
R/W
0
Must write 0
2-0
Figure 8-66. Register 0x20/21/22
7
6
5
4
3
2
1
0
FCLK PAT [7:0]
FCLK PAT [15:8]
0
0
0
0
FCLK PAT [19:16]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-33. Register 0x20, 21, 22 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FCLK PAT [19:0]
R/W
0xFFC00
These bits can adjust the duty cycle of the FCLK. In decimation
bypass mode the FCLK pattern gets adjusted automatically for
the different output resolutions. Table 8-34 shows the proper
FCLK pattern values for 1-wire in real/complex decimation.
Table 8-34. FCLK Pattern for different resolution based on interface
DECIMATION
REAL DECIMATION
OUTPUT RESOLUTION
16-bit
0xFF000
14-bit
66
1-WIRE
0xFE000
18-bit
COMPLEX DECIMATION
2-WIRE
14-bit
Use Default
0xFF800
0xFFFFF
16-bit
0xFFFFF
18-bit
0xFFFFF
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Figure 8-67. Register 0x24
7
6
5
4
3
2
1
0
0
0
0
0
0
DIG BYP
DDC EN
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-35. Register 0x24 Field Descriptions
Bit
Field
Type
Reset
Description
7-3
0
R/W
0
Must write 0
2
DIG BYP
R/W
0
This bit needs to be set to enable digital features block which
includes decimation.
0: Digital feature block bypassed - lowest latency
1: Data path includes digital features
1
DDC EN
R/W
0
Enables internal decimation filter
0: DDC disabled.
1: DDC enabled.
0
0
R/W
0
Must write 0
To output
interface
DDC
N
DECIMATION
DIG BYP
Figure 8-68. Register control for digital features
Figure 8-69. Register 0x25
7
6
0
5
4
DECIMATION
R/W-0
R/W-0
R/W-0
R/W-0
3
2
1
0
REAL OUT
0
0
MIX PHASE
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-36. Register 0x25 Field Descriptions
Bit
7
6-4
3
2-1
0
Field
Type
Reset
Description
0
R/W
0
Must write 0
DECIMATION
R/W
000
Complex decimation setting.
000: Bypass mode (no decimation)
001: Decimation by 2
010: Decimation by 4
011: Decimation by 8
100: Decimation by 16
101: Decimation by 32
others: not used
REAL OUT
R/W
0
This bit selects real output decimation. In this mode, the
decimation filter is a low pass filter and no complex mixing is
performed to reduce power consumption. For maximum power
savings the NCO in this case should be set to 0.
0: Complex decimation
1: Real decimation
0
R/W
0
Must write 0
MIX PHASE
R/W
0
This bit used to invert the NCO phase
0: NCO phase as is.
1: NCO phase inverted.
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Figure 8-70. Register 0x26
7
6
MIX GAIN A
R/W-0
R/W-0
5
4
3
2
1
0
MIX RES A
FS/4 MIX A
0
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-37. Register 0x26 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
MIX GAIN A
R/W
00
This bit applies a 0, 3 or 6-dB digital gain to the output of digital
mixer to compensate for the mixing loss for channel A.
00: no digital gain added
01: 3-dB digital gain added
10: 6-dB digital gain added
11: not used
5
MIX RES A
R/W
0
Toggling this bit resets the NCO phase of channel A and loads
the new NCO frequency. This bit does not self reset.
4
FS/4 MIX A
R/W
0
Enables FS/4 mixing for DDC A (complex decimation only).
0: FS/4 mixing disabled.
1: FS/4 mixing enabled.
0
R/W
0
Must write 0
3-0
Figure 8-71. Register 0x27
7
6
5
4
3
2
1
0
0
0
0
OP ORDER A
Q-DEL A
FS/4 MIX PH A
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-38. Register 0x27 Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
R/W
0
Must write 0
4
OP ORDER A
R/W
0
Swaps the I and Q output order for channel A
0: Output order is I[n], Q[n]
1: Output order is swapped: Q[n], I[n]
3
Q-DEL A
R/W
0
This delays the Q-sample output of channel A by one.
0: Output order is I[n], Q[n]
1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]
2
FS/4 MIX PH A
R/W
0
Inverts the mixer phase for channel A when using FS/4 mixer
0: Mixer phase is non-inverted
1: Mixer phase is inverted
0
R/W
0
Must write 0
1-0
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Figure 8-72. Register 0x2A/2B/2C/2D
7
6
5
4
3
2
1
0
R/W-0
R/W-0
R/W-0
R/W-0
NCO A [7:0]
NCO A [15:8]
NCO A [23:16]
NCO A [31:24]
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-39. Register 0x2A/2B/2C/2D Field Descriptions
Bit
Field
Type
Reset
Description
7-0
NCO A [31:0]
R/W
0
Sets the 32 bit NCO value for decimation filter channel A. The
NCO value is fNCO× 232/FS
In real decimation these registers are automatically set to 0.
Figure 8-73. Register 0x39...0x72
7
6
5
4
3
R/W-0
R/W-0
R/W-0
R/W-0
2
1
0
R/W-0
R/W-0
R/W-0
OUTPUT BIT MAPPER
R/W-0
Table 8-40. Register 0x39...0x72 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
OUTPUT BIT MAPPER
R/W
0
These registers are used to reorder the output data bus. See the
Section 8.3.5.5 on how to program it.
Figure 8-74. Register 0x8F
7
6
5
4
3
2
1
0
0
0
0
0
0
0
FORMAT A
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-41. Register 0x8F Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
R/W
0
Must write 0
1
FORMAT A
R/W
0
This bit sets the output data format for channel A. Digital bypass
register bit (0x24, D2) needs to be enabled as well.
0: 2s complement
1: Offset binary
0
0
R/W
0
Must write 0
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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
A spectrum analyzer is a typical frequency domain application for the ADC354x and its front end circuitry is
similar to several other systems such as software defined radio (SDR), sonar, radar or communications. Some
applications require frequency coverage including DC or near DC (that is, sonar) so it is included in this example.
9.2 Typical Application
Figure 9-1. Typical configuration for a spectrum analyzer with DC support
9.2.1 Design Requirements
Frequency domain applications cover a wide range of frequencies from low input frequencies at or near DC in
the 1st Nyquist zone to undersampling in higher Nyquist zones. If very low input frequency is supported then the
input has to be DC coupled and the ADC driven by a fully differential amplifier (FDA). If low frequency support is
not needed, then AC coupling and use of a balun may be more suitable.
The internal reference is used since DC precision is not needed. However, the ADC AC performance is highly
dependent on the quality of the external clock source. If in-band interferers can be present, then the ADC
SFDR performance is a key care about. A higher ADC sampling rate is desirable in order to relax the external
anti-aliasing filter – an internal decimation filter can be used to reduce the digital output rate afterwards.
Table 9-1. Design key care-abouts
FEATURE
DESCRIPTION
Signal Bandwidth
DC to 20 MHz
Input Driver
Single ended to differential signal conversion and DC coupling
Clock Source
External clock with low jitter
When designing the amplifier/filter driving circuit, the ADC input full-scale voltage needs to be taken into
consideration. For example, the ADC354x input full-scale is 2.25 Vpp. When factoring in ~ 1 dB for insertion
loss of the filter, then the amplifier needs to deliver close to 2.5 Vpp. The amplifier distortion performance will
70
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degrade with a larger output swing and considering the ADC common mode input voltage the amplifier may not
be able to deliver the full swing. The ADC354x provides an output common mode voltage of 0.95 V, and the
device can only swing within 250 mV of the negative supply. A unipolar 3.3 V amplifier power supply limits the
maximum voltage swing to ~ 2.8 V pp. Additionally, input voltage protection diodes may be needed to protect the
ADC from over-voltage events.
Table 9-2. Output voltage swing of THS4541 vs power supply
DEVICE
MIN OUTPUT VOLTAGE
MAX SWING WITH 3.3 V/ 0 V SUPPLY
THS4541
VS- + 250 mV
2.8 Vpp
9.2.2 Detailed Design Procedure
9.2.2.1 Input Signal Path
Depending on desired input signal frequency range, the device provides a low power options to drive the ADC
inputs. Table 9-3 provides a comparison between the device and the power consumption vs usable frequency
trade off.
Table 9-3. Fully Differential Amplifier Options
DEVICE
CURRENT (IQ) PER CHANNEL
USABLE FREQUENCY RANGE
THS4561
0.8 mA
< 3 MHz
THS4551
1.4 mA
< 10 MHz
THS4541
10 mA
< 70 MHz
The low pass filter design (topology, filter order) is driven by the application itself. However, when designing the
low pass filter, the optimum load impedance for the amplifier should be taken into consideration as well. Between
the low pass filter and the ADC input the sampling glitch filter must be added as well as shown in Section
8.3.1.2.1. In this example, the DC - 30 MHz glitch filter is selected.
9.2.2.2 Sampling Clock
Applications operating with low input frequencies (such as DC to 20 MHz) typically are less sensitive to
performance degradation due to clock jitter. The internal ADC aperture jitter improves with faster rise and fall
times (i.e. square wave vs sine wave). Table 9-4 provides an overview of the estimated SNR performance of
the ADC354x based on different amounts of jitter of the external clock source. The SNR is estimated based on
ADC354x thermal noise of 79 dBFS and input signal at -1dBFS.
Table 9-4. ADC SNR performance across vs input frequency for different amounts of external clock jitter
INPUT FREQUENCY
TJ,EXT = 100 fs
TJ,EXT = 250 fs
TJ,EXT = 500 fs
TJ,EXT = 1 ps
5 MHz
79.0
78.9
78.9
78.8
10 MHz
78.9
78.9
78.7
78.0
20 MHz
78.9
78.6
78.0
75.9
Termination of the clock input should be considered for long clock traces.
9.2.2.3 Voltage Reference
The ADC354x is configured to internal reference operation by applying 0.6 V to the REFBUF pin.
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9.2.3 Application Curves
0
0
-20
-20
-40
-40
Amplitude (dBFS)
Amplitude (dBFS)
The following FFT plots show the performance of THS4541 driving the ADC354x operated at 65 MSPS with a
full-scale input at -1 dBFS with input frequencies at 1, 5, 10 and 20 MHz.
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
0
10
20
Input Frequency (MHz)
30
0
10
20
Input Frequency (MHz)
30
ADC3
ADC3
SNR = 78.7 dBFS, SFDR = 90 dBc
SNR = 78.6 dBFS, SFDR = 96 dBc
Figure 9-3. Single Tone FFT at FIN = 5 MHz
0
0
-20
-20
-40
-40
Amplitude (dBFS)
Amplitude (dBFS)
Figure 9-2. Single Tone FFT at FIN = 1 MHz
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
0
10
20
Input Frequency (MHz)
30
0
10
20
Input Frequency (MHz)
30
ADC3
SNR = 78.0 dBFS, SFDR = 92 dBc
Figure 9-4. Single Tone FFT at FIN = 10 MHz
72
ADC3
SNR = 75.9 dBFS, SFDR = 81 dBc
Figure 9-5. Single Tone FFT at FIN = 20 MHz
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9.3 Initialization Set Up
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin, as shown in Figure 9-6.
1. Apply AVDD and IOVDD (no specific sequence required). After AVDD is applied, the internal bandgap
reference powers up and settle out in ~ 2 ms.
2. Configure REFBUF pin (pull high or low even if configured via SPI later on) and apply the sampling clock.
3. Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses
and the internal power up capacitor calibration is initiated. The calibration takes approximately 200000 clock
cycles.
4. Begin programming using SPI interface.
AVDD
IOVDD
t1
REFBUF
Ext VREF
CLK
t3
t2
RESET
SEN
Figure 9-6. Initialization of serial registers after power up
Table 9-5. Power-up timing
MIN
t1
Power-on delay: delay from power up and logic level of REFBUF pin to
RESET rising edge
t2
RESET pulse width
t3
Delay from RESET disable to SEN active
2
TYP
MAX
UNIT
ms
1
us
~ 200000
clock cycles
9.3.1 Register Initialization During Operation
If required, the serial interface registers can be cleared and reset to default settings during operation either:
•
•
through a hardware reset or
by applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 0x00)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
After hardware or software reset the wait time is also ~ 200000 clock cycles before the SPI registers can be
programmed.
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10 Power Supply Recommendations
The ADC354x requires two different power-supplies. The AVDD rail provides power for the internal analog
circuits and the ADC itself while the IOVDD rail powers the digital interface and the internal digital circuits like
decimation filter or output interface mapper. Power sequencing is not required.
The AVDD power supply must be low noise in order to achieve data sheet performance. In applications
operating near DC, the 1/f noise contribution of the power supply needs to be considered as well. The ADC
is designed for very good PSRR which aides with the power supply filter design.
Figure 10-1. Power supply rejection ratio (PSRR) vs frequency
There are two recommended power-supply architectures:
1. Step down using high-efficiency switching converters, followed by a second stage of regulation using a low
noise LDO to provide switching noise reduction and improved voltage accuracy.
2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach
provides the best efficiency, but care must be taken to ensure switching noise is minimized to prevent
degraded ADC performance.
TI WEBENCH® Power Designer can be used to select and design the individual power-supply elements
needed: see the WEBENCH® Power Designer
Recommended switching regulators for the first stage include the TPS62821, and similar devices.
Recommended low dropout (LDO) linear regulators include the TPS7A4701, TPS7A90, LP5901, and similar
devices.
For the switch regulator only approach, the ripple filter must be designed with a notch frequency that aligns with
the switching ripple frequency of the DC/DC converter. Note the switching frequency reported from WEBENCH®
and design the EMI filter and capacitor combination to have the notch frequency centered as needed. Figure
10-2 and Figure 10-3 illustrate the two approaches.
AVDD and IOVDD supply voltages should not be shared in order to prevent digital switching noise from coupling
into the analog signal chain.
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FB
2.1V
DC/DC
Regulator
5V-12V
FB
1.8V
AVDD
LDO
10uF 10uF 0.1uF
47uF
47uF
GND
GND
GND
FB
IOVDD
10uF 10uF 0.1uF
FB = Ferrite bead filter
GND
Figure 10-2. Example: LDO Linear Regulator Approach
5V-12V
1.8V
DC/DC
Regulator
EMI FILTER
FB
AVDD
10uF 10uF 10uF
10uF 10uF 0.1uF
GND
GND
FB
IOVDD
10uF 10uF 0.1uF
GND
Ripple filter notch frequency to match switching frequency of the DC/DC regulator
FB = Ferrite bead filter
Figure 10-3. Example Switcher-Only Approach
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11 Layout
11.1 Layout Guidelines
There are several critical signals which require specific care during board design:
1. Analog input and clock signals
• Traces should be as short as possible and vias should be avoided where possible to minimize impedance
discontinuities.
• Traces should be routed using loosely coupled 100-Ω differential traces.
• Differential trace lengths should be matched as close as possible to minimize phase imbalance and HD2
degradation.
2. Digital output interface
• A 20 ohm series isolation resistor should be used on each CMOS output and placed close the digital
output. This isolation resistor limits the output current into the capacitive load and thus minimizes the
switching noise inside the ADC. When driving longer distances a buffer should be used. The resistor
value should be optimized for the desired output data rate.
3. Voltage reference
• The bypass capacitor should be placed as close to the device pins as possible and connected between
VREF and REFGND – on top layer avoiding vias.
• Depending on configuration an additional bypass capacitor between REFBUF and REFGND may be
recommended and should also be placed as close to pins as possible on top layer.
4. Power and ground connections
• Provide low resistance connection paths to all power and ground pins.
• Use power and ground planes instead of traces.
• Avoid narrow, isolated paths which increase the connection resistance.
• Use a signal/ground/power circuit board stackup to maximize coupling between the ground and power
plane.
11.2 Layout Example
The following screen shot shows the top layer of the ADC354x EVM.
•
•
•
Signal and clock inputs are routed as differential signals on the top layer avoiding vias.
CMOS output interface lanes with isolation resistor and digital buffer.
Bypass caps are close to the VREF pin on the top layer avoiding vias.
Bypass caps on VREF close
to the pins on top layer
Isolation resistors on CMOS
output pins
Clock routing
without vias
Analog inputs on
top layer (no vias)
Figure 11-1. Layout example: top layer of ADC354x EVM
76
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SBAS840B – JULY 2020 – REVISED APRIL 2022
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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18-May-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ADC3541IRSBR
ACTIVE
WQFN
RSB
40
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AZ3541
Samples
ADC3541IRSBT
ACTIVE
WQFN
RSB
40
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AZ3541
Samples
ADC3542IRSBR
ACTIVE
WQFN
RSB
40
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AZ3542
Samples
ADC3542IRSBT
ACTIVE
WQFN
RSB
40
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
AZ3542
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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