ADS7955-Q1
SLAS814 – DECEMBER 2011
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10-Bit, 1 MSPS, 8-Channel, Single-Ended, MicroPower, Serial Interface ADC
Check for Samples: ADS7955-Q1
FEATURES
DESCRIPTION
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The ADS7955-Q1 is a
analog-to-digital converter.
1
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Qualified for Automotive Applications
1-MHz Sample Rate Serial Devices
10-Bit Resolution
Zero Latency
20-MHz Serial Interface
Analog Supply Range: 2.7 to 5.25 V
I/O Supply Range: 1.7 to 5.25 V
Two SW Selectable Unipolar, Input Ranges: 0
to 2.5V and 0 to 5V
Auto and Manual Modes for Channel Selection
8-Channel Device can Share 16 Channel
Device Footprint
Two Programmable Alarm Levels per Channel
Four Individually Configurable GPIOs for
TSSOP Package Devices
Typical Power Dissipation: 14.5 mW (+VA = 5
V, +VBD = 3 V) at 1 MSPS
Power-Down Current (1 μA)
Input Bandwidth (47 MHz at 3 dB)
30-Pin TSSOP Package
APPLICATIONS
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PLC / IPC
Battery Powered Systems
Medical Instrumentation
Digital Power Supplies
Touch Screen Controllers
High-Speed Data Acquisition Systems
High-Speed Closed-Loop Systems
10-bit
multichannel
The device includes a capacitor based SAR A/D
converter with inherent sample and hold.
The device accepts a wide analog supply range from
2.7V to 5.25V. Very low power consumption makes
this device suitable for battery-powered and isolated
power supply applications.
A wide 1.7V to 5.25V I/O supply range facilitates a
glue-less interface with the most commonly used
CMOS digital hosts.
The serial interface is controlled by CS and SCLK for
easy connection with microprocessors and DSP.
The input signal is sampled with the falling edge of
CS. It uses SCLK for conversion, serial data output,
and reading serial data in. The device allows auto
sequencing of preselected channels or manual
selection of a channel for the next conversion cycle.
There are two software selectable input ranges (0V 2.5V and 0V - 5V), four individually configurable
GPIOs, and two programmable alarm thresholds per
channel. These features make the device suitable for
most data acquisition applications.
The device offers an attractive power-down feature.
This is extremely useful for power saving when the
device is operated at lower conversion speeds.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
ADS7955-Q1
SLAS814 – DECEMBER 2011
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ADS7955-Q1 BLOCK DIAGRAM
REF
MXO AINP
Ch0
Ch1
+VA
AGND
ADC
Ch2
SDO
Compare
Alarm
Threshold
Control Logic
&
Sequencing
Ch n*
GPIO
BDGND
SDI
SCLK
CS
VBD
NOTE: n* is number of channels (16,12,8, or 4) depending on the device from the ADS79XX product family.
NOTE: 4 number of GPIO are available in TSSOP package device.
ORDERING INFORMATION - 10-BIT
TA
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY (LSB)
NO MISSING
CODES AT
RESOLUTION
(BIT)
NUMBER OF
CHANNELS
PACKAGE
ORDERABLE PART
NUMBER
TOP-SIDE MARKING
–40°C to 125°C
±0.5
±0.5
10
8
30 pin TSSOP - DBT
ADS7955QDBTRQ1
ADS7955Q1
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
–0.3 to +VA +0.3
V
+VA to AGND, +VBD to BDGND
–0.3 to +7.0
V
Digital input voltage to BDGND
–0.3 to (7.0)
V
AINP or CHn to AGND
–0.3 to (+VA + 0.3)
V
Operating temperature range
–40 to 125
°C
Storage temperature range
–65 to 150
°C
150
°C
Digital output to BDGND
Junction temperature
Power dissipation
(TJ Max–TA)/θJA
DBT packaged versions rated for MSL3 260C per JSTD-020 specifications
Human Body Model (HBM) ESD, Class H2 per Q100-002
2
kV
200
V
Maximum withstand voltage > 500 to ≤ to 750 V
with corner pins > 750
V
Machine Model (MM) ESD, Class M2 per Q100-003
Charged Device Model (CDM) ESD, Class C3B2 per Q100-011
Latch up (per JESD78)
(1)
2
Class I
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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THERMAL INFORMATION
ADS7955-Q1
THERMAL METRIC (1)
DBT
UNITS
30 PINS
Junction-to-ambient thermal resistance (2)
θJA
89.83
(3)
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
43.13
ψJT
Junction-to-top characterization parameter (5)
0.77
ψJB
Junction-to-board characterization parameter (6)
42.52
θJCbot
Junction-to-case (bottom) thermal resistance (7)
22.94
(1)
(2)
(3)
(4)
(5)
(6)
(7)
22.94
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
ELECTRICAL CHARACTERISTICS
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input span (1)
Range 1
0
Vref
Range 2 while 2Vref ≤ +VA
0
2*Vref
Range 1
–0.20
VREF
+0.20
Range 2 while 2Vref ≤ +VA
–0.20
2*VREF
+0.20
Absolute input range
Input capacitance
Input leakage current
TA = 125°C
V
V
15
ρF
61
nA
10
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
10
Bits
Integral linearity
–0.5
±0.2
0.5
LSB (2)
Differential linearity
–0.5
±0.2
0.5
LSB
Offset error (3)
–1.5
±0.5
1.5
LSB
–1
±0.1
1
Gain error
Range 1
±0.1
Range 2
LSB
SAMPLING DYNAMICS
Conversion time
20 MHz SCLK
Acquisition time
Maximum throughput rate
800
325
nSec
nSec
20 MHz SCLK
1.0
MHz
Aperture delay
5
nsec
Step response
150
nsec
Over voltage recovery
150
nsec
(1)
(2)
(3)
Ideal input span; does not include gain or offset error.
LSB means Least Significant Bit.
Measured relative to an ideal full-scale input
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ELECTRICAL CHARACTERISTICS (continued)
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
Total harmonic distortion (4)
100 kHz
Signal-to-noise ratio
100 kHz
60
Signal-to-noise + distortion
100 kHz
60
Spurious free dynamic range
100 kHz
Full power bandwidth
At –3 dB
Channel-to-channel crosstalk
–80
dB
dB
82
dB
47
MHz
Any off-channel with 100kHz, Full-scale input to
channel being sampled with DC input.
–95
From previously sampled to channel with 100kHz,
Full-scale input to channel being sampled with DC
input.
–85
dB
EXTERNAL REFERENCE INPUT
Vref reference voltage at REFP
2.0
Reference resistance
2.5
3.0
100
V
kΩ
ALARM SETTING
Higher threshold range
000
FFC
Hex
Lower threshold range
000
FFC
Hex
DIGITAL INPUT/OUTPUT
Logic family
CMOS
VIH
Logic level
0.7*(+VBD)
VIL
+VBD = 5 V
0.8
VIL
+VBD = 3 V
0.4
V
VOH
At Isource = 200 μA
VOL
At Isink = 200 μA
Data format MSB first
Vdd-0.2
0.4
MSB First
POWER SUPPLY REQUIREMENTS
+VA supply voltage
2.7
3.3
5.25
V
+VBD supply voltage
1.7
3.3
5.25
V
At +VA = 2.7 to 3.6 V and 1MHz throughput
Supply current (normal mode)
1.8
At +VA = 2.7 to 3.6 V static state
1
mA
At +VA = 4.7 to 5.25 V and 1 MHz throughput
2.3
3
mA
At +VA = 4.7 to 5.25 V static state
1.1
1.5
mA
Power-down state supply current
+VBD supply current
mA
1.05
+VA = 5.25V, fs = 1MHz
1
μA
1
mA
μSec
Power-up time
1
Invalid conversions after power up or
reset
1 Numbers
TEMPERATURE RANGE
–40
Specified performance
(4)
4
125
°C
Calculated on the first nine harmonics of the input frequency.
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TIMING REQUIREMENTS (see Figure 7 and Figure 8)
All specifications typical at –40°C to 125°C, +VA = 2.7 V to 5.25 V (unless otherwise specified)
TEST CONDITIONS (1)
PARAMETER
tconv
tq
td1
tsu1
td2
Conversion time
Minimum quiet sampling time needed from bus
3-state to start of next conversion
Delay time, CS low to first data (DO–15) out
Setup time, CS low to first rising edge of SCLK
Delay time, SCLK falling to SDO next data bit valid
(2)
MIN
td3
Hold time, SCLK falling to SDO data bit valid
Delay time, 16th SCLK falling edge to SDO 3-state
16
+VBD = 3 V
16
+VBD = 5 V
16
+VBD = 1.8 V
40
+VBD = 3 V
40
+VBD = 5 V
40
38
+VBD = 3 V
27
+VBD = 5 V
17
+VBD = 1.8 V
8
+VBD = 3 V
6
+VBD = 5 V
4
th2
tw1
td4
twh
twl
Setup time, SDI valid to rising edge of SCLK
Hold time, rising edge of SCLK to SDI valid
Pulse duration CS high
Delay time CS high to SDO 3-state
Pulse duration SCLK high
Pulse duration SCLK low
Frequency SCLK
(1)
(2)
UNIT
SCLK
ns
+VBD = 1.8 V
ns
ns
+VBD = 1.8 V
35
+VBD = 3 V
27
ns
17
+VBD = 1.8 V
7
+VBD = 3 V
5
+VBD = 5 V
3
ns
+VBD = 1.8 V
26
+VBD = 3 V
22
+VBD = 5 V
tsu2
MAX
+VBD = 1.8 V
+VBD = 5 V
th1
TYP
ns
13
+VBD = 1.8 V
2
+VBD = 3 V
3
+VBD = 5 V
4
+VBD = 1.8 V
12
+VBD = 3 V
10
+VBD = 5 V
6
+VBD = 1.8 V
20
+VBD = 3 V
20
+VBD = 5 V
20
ns
ns
ns
+VBD = 1.8 V
24
+VBD = 3 V
21
+VBD = 5 V
12
+VBD = 1.8 V
20
+VBD = 3 V
20
+VBD = 5 V
20
+VBD = 1.8 V
20
+VBD = 3 V
20
+VBD = 5 V
20
ns
ns
ns
+VBD = 1.8 V
20
+VBD = 3 V
20
+VBD = 5 V
20
MHz
1.8V specifications apply from 1.7V to 1.9V, 3V specifications apply from 2.7V to 3.6V, 5V specifications apply from 4.75V to 5.25V.
With 50-pF load
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DEVICE INFORMATION
PIN CONFIGURATION (TOP VIEW)
GPIO2
1
30
GPIO1
GPIO3
2
29
REFM
REFP
3
28
GPIO0
+VBD
4
27
BDGND
+VA
5
26
SDO
AGND
MXO
6
25
7
24
SDI
SCLK
AINP
8
23
CS
AINM
9
22
AGND
AGND
CH7
10
21
+VA
11
20
CH0
CH6
12
19
CH5
13
18
CH1
CH2
CH4
14
17
CH3
NC
15
16
NC
TERMINAL FUNCTIONS - TSSOP PACKAGE
DEVICE NAME
ADS7955-Q1
PIN NAME
I/O
FUNCTION
4
REFP
I
Reference input
3
REFM
I
Reference ground
8
AINP
I
Signal input to ADC
9
AINM
I
ADC input ground
Multiplexer output
PIN NO.
REFERENCE
ADC ANALOG INPUT
MULTIPLEXER
7
MXO
O
20
Ch0
I
19
Ch1
I
18
Ch2
I
17
Ch3
I
14
Ch4
I
13
Ch5
I
12
Ch6
I
11
Ch7
I
-
Ch8
I
-
Ch9
I
-
Ch10
I
-
Ch11
I
-
Ch12
I
-
Ch13
I
-
Ch14
I
-
Ch15
I
Analog channels for multiplexer
DIGITAL CONTROL SIGNALS
6
23
CS
I
Chip select input
24
SCLK
I
Serial clock input
25
SDI
I
Serial data input
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TERMINAL FUNCTIONS - TSSOP PACKAGE (continued)
DEVICE NAME
ADS7955-Q1
PIN NAME
I/O
SDO
O
FUNCTION
PIN NO.
26
Serial data output
GENERAL PURPOSE INPUTS / OUTPUTS: These pins have programmable dual functionality. Refer to Table 8 for functionality
programming
29
30
GPIO0
I/O
General purpose input or output
High alarm or
High/Low alarm
O
Active high output indicating high alarm or high/low alarm depending on
programming
GPIO1
I/O
General purpose input or output
Low alarm
O
Active high output indicating low alarm
1
GPIO2
I/O
General purpose input or output
Range
I
2
GPIO3
I/O
PD
I
Selects range: High -> Range 2 / Low -> Range 1
General purpose input or output
Active low power down input
POWER SUPPLY AND GROUND
5, 21
+VA
—
Analog power supply
6, 10, 22
AGND
—
Analog ground
28
+VBD
—
Digital I/O supply
27
BDGND
—
Digital ground
—
—
Pins internally not connected, do not float these pins
NC PINS
15, 16
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TYPICAL CHARATERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
STATIC SUPPLY CURRENT
vs
SUPPLY VOLTAGE
3.5
1.5
2.5
2
1.5
+VA - Supply Current - mA
3
1.3
1.2
1.1
1
3.4
4.1
4.8
+VA - Supply Voltage - V
0.9
2.7
5.5
3.2
3
2.8
2.6
2.4
2.2
3.4
4.1
4.8
+VA - Supply Voltage - V
2
-40
5.5
15
70
TA - Free-Air Temperature - °C
Figure 1.
Figure 2.
Figure 3.
STATIC SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SAMPLE RATE
SUPPLY CURRENT
vs
SAMPLE RATE
1.115
No Powerdown,
TA = 25°C
+VA - Supply Current - mA
1.105
1.1
1.095
1.09
1.085
1.08
125
2.5
2.5
VDD = 5.5 V
1.11
With Powerdown,
TA = 25°C
5V
2
+VA - Supply Current - mA
1
2.7
fS = 1 MSPS,
VDD = 5.5 V
3.4
TA = 25°C
1.4
+VA - Supply Current - mA
+VA - Supply Current - mA
fS = 1 MSPS,
TA = 25°C
+VA - Supply Current - mA
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
2.7 V
1.5
1
0.5
2
5V
1.5
2.7 V
1
0.5
1.075
1.07
-40
Figure 4.
8
0
0
15
70
TA - Free-Air Temperature - °C
125
0
200
400
600
800
fS - Sample Rate - KSPS
1000
Figure 5.
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0
100
200
300
400
fS - Sample Rate - KSPS
500
Figure 6.
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DETAILED DESCRIPTION
DEVICE OPERATION
The ADS7955-Q1 is a 10-bit 8-channel device. Figure 7 and Figure 8 show device operation timing. Device
operation is controlled with CS, SCLK, and SDI. The device outputs its data on SDO.
Frame n
Frame n + 1
CS
1
3
5
9
7
11
13
15 16
1
3
5
9
7
11
13
15 16
SCLK
SDO
Top 4 Bit
SDI
Top 4 Bit
12-Bit Conversion Result
16-Bit I/P Word
16-Bit I/P Word
Mux Chan Change
MUX
12-Bit Conversion Result
Mux Chan Change
Analog I/P Settling After Chan Change
Sampling
Instance
Acquisition
Acquisition Phase tacq
Conversion
Conversion Phase tcnv
Conversion Phase
GPO
Data Written (through SDI) in Frame n – 1
Data Written (through SDI) in Frame n
GPI
GPI status is latched in on CS falling
edge and transferred to SDO frame n
Figure 7. Device Operation Timing Diagram
Each frame begins with the falling edge of CS. With the falling edge of CS, the input signal from the selected
channel is sampled, and the conversion process is initiated. The device outputs data while the conversion is in
progress. The 16-bit data word contains a 4-bit channel address, followed by a 12-bit conversion result in MSB
first format. There is an option to read the GPIO status instead of the channel address. (Refer to Table 1,
Table 2, and Table 5 for more details.)
The device selects a new multiplexer channel on the second SCLK falling edge. The acquisition phase starts on
the fourteenth SCLK rising edge. On the next CS falling edge the acquisition phase will end, and the device
starts a new frame.
The TSSOP packaged device has four General Purpose IO (GPIO) pins, QFN versions have only one GPIO.
These four pins can be individually programmed as GPO or GPI. It is also possible to use them for preassigned
functions, refer to Table 10. GPO data can be written into the device through the SDI line. The device refreshes
the GPO data on the CS falling edge as per the SDI data written in previous frame.
Similarly the device latches GPI status on the CS falling edge and outputs the GPI data on the SDO line (if GPI
read is enabled by writing DI04=1 in the previous frame) in the same frame starting with the CS falling edge.
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a
1/t Throughput (Single Frame)
CS
tw1
tsu1
SCLK
1
td1
SDO
3
2
4
th1
DO15
DO-14
5
6
14
15
16
td3
td2
DO-13
DO-12
DO-11
MSB
DO-10
MSB-1
DO-2
LSB
DO-1
DO-0
tq
tsu2
SDI
DI-15
DI-14
DI-13
DI-12
DI-11
DI-10
DI-2
DI-1
DI-0
th2
Figure 8. Serial Interface Timing Diagram for 10-Bit Devices
The falling edge of CS clocks out DO-15 (first bit of the four bit channel address), and remaining address bits are
clocked out on every falling edge of SCLK until the third falling edge. The conversion result MSB is clocked out
on the 4th SCLK falling edge and LSB on the 15th/13th/11th falling edge respectively for the 10-bit device. On
the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 16th falling edge
of SCLK.
The device reads a sixteen bit word on the SDI pin while it outputs the data on the SDO pin. SDI data is latched
on every rising edge of SCLK starting with the 1st clock as shown in Figure 8.
CS can be asserted (pulled high) only after 16 clocks have elapsed.
The device has two (high and low) programmable alarm thresholds per channel. If the input crosses these limits;
the device flags out an alarm on GPIO0/GPIO1 depending on the GPIO program register settings (refer to
Table 10). The alarm is asserted (under the alarm conditions) on the 12th falling edge of SCLK in the same
frame when a data conversion is in progress. The alarm output is reset on the 10th falling edge of SCLK in the
next frame.
The device offers a power-down feature to save power when not in use. There are two ways to powerdown the
device. It can be powered down by writing DI05 = 1 in the mode control register (refer to Table 1, Table 2, and
Table 5); in this case the device powers down on the 16th falling edge of SCLK in the next data frame. Another
way to powerdown the device is through GPIO in the case of the TSSOP packaged device. GPIO3 can act as
the PD input (refer to Table 10, to assign this functionality to GPIO3). This is an asynchronous and active low
input. The device powers down instantaneously after GPIO3 (PD) = 0. The device will power up again on the CS
falling edge with DI05 = 0 in the mode control register and GPIO3 (PD) = 1.
CHANNEL SEQUENCING MODES
There are three modes for channel sequencing, namely Manual mode, Auto-1 mode, Auto-2 mode. Mode
selection is done by writing into the control register (refer to Table 1, Table 2, and Table 5). A new multiplexer
channel is selected on the second falling edge of SCLK (as shown in Figure 7) in all three modes.
Manual mode: When configured to operate in Manual mode, the next channel to be selected is programmed in
each frame and the device selects the programmed channel in the next frame. On powerup or after reset the
default channel is 'Channel-0' and the device is in Manual mode.
Auto-1 mode: In this mode the device scans pre-programmed channels in ascending order. A new multiplexer
channel is selected every frame on the second falling edge of SCLK. There is a separate ‘program register’ for
pre-programming the channel sequence. Table 3 and Table 4 show Auto-1 ‘program register’ settings.
Once programmed the device retains ‘program register’ settings until the device is powered down, reset, or
reprogrammed. It is allowed to exit and re-enter the Auto-1 mode any number of times without disturbing
‘program register’ settings.
The Auto-1 program register is reset to FFFF/FFF/FF/F hex for the 8 channel device upon device powerup or
reset; implying the device scans all channels in ascending order.
10
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Auto-2 mode: In this mode the user can configure the program register to select the last channel in the scan
sequence. The device scans all channels from channel 0 up to and including the last channel in ascending order.
The multiplexer channel is selected every frame on the second falling edge of SCLK. There is a separate
‘program register’ for pre-programming of the last channel in the sequence (multiplexer depth). Table 6 lists the
‘Auto-2 prog’ register settings for selection of the last channel in the sequence.
Once programmed the device retains program register settings until the device is powered down, reset, or
reprogrammed. It is allowed to exit and re-enter Auto-2 mode any number of times, without disturbing the
‘program register’ settings.
On powerup or reset the bits D9-D6 of the Auto-2 program register are reset to 7 hex for the 8 channel device;
implying the device scans all channels in ascending order.
DEVICE PROGRAMMING AND MODE CONTROL
The following section describes device programming and mode control. These devices feature two types of
registers to configure and operate the devices in different modes. These registers are referred as ‘Configuration
Registers’. There are two types of ‘Configuration Registers’ namely ‘Mode control registers’ and ‘Program
registers’.
Mode Control Register
A ‘Mode control register’ is configured to operate the device in one of three channel sequencing modes, namely
Manual mode, Auto-1 Mode, Auto-2 Mode. It is also used to control user programmable features like range
selection, device power-down control, GPIO read control, and writing output data into the GPIO.
Program Registers
The 'Program registers’ are used for device configuration settings and are typically programmed once on
powerup or after device reset. There are different program registers such as ‘Auto-1 mode programming’ for
pre-programming the channel sequence, ‘Auto-2 mode programming’ for selection of the last channel in the
sequence, ‘Alarm programming’ for all 16 channels (8 channels) and GPIO for individual pin configuration as GPI
or GPO or a pre-assigned function.
DEVICE POWER-UP SEQUENCE
The device power-up sequence is shown in Figure 9. Manual mode is the default power-up channel sequencing
mode and Channel-0 is the first channel by default. As explained previously, these devices offer Program
Registers to configure user programmable features like GPIO, Alarm, and to pre-program the channel sequence
for Auto modes. At ‘powerup or on reset’ these registers are set to the default values listed in Table 1 to
Table 10. It is recommended to program these registers on powerup or after reset. Once configured; the device
is ready to use in any of the three channel sequencing modes namely Manual, Auto-1, and Auto-2.
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Device power up or reset
Device operation in manual mode, Channel 0;
SDO Invalid in first frame
CS
First frame
CS
Auto 1 register program (note 1)
CS
Auto 2 register program (note 1)
CS
Alarm register program (note 1)
CS
GPIO register program (note 1)
Operation in manual mode
CS
CS
Operation in Auto 1 mode
CS
Operation in Auto 2 mode
(1)
The device continues its operation in Manual mode channel 0 through out the programming sequence and outputs
valid conversion results. It is possible to change channel, range, GPIO by inserting extra frames in between two
programming blocks. It is also possible to bypass any programming block if the user does not intent to use that
feature.
(2)
It is possible to reprogram the device at any time during operation, regardless of what mode the device is in. During
programming the device continues its operation in whatever mode it is in and outputs valid data.
Figure 9. Device Power-Up Sequence
OPERATING IN MANUAL MODE
The details regarding entering and running in Manual channel sequencing mode are illustrated in Figure 10.
Table 1 lists the Mode Control Register settings for Manual mode in detail. Note that there are no Program
Registers for manual mode.
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CS
Frame: n-1
Device operation in Auto 1 or
Auto 2 mode
No
Change to Manual mode?
Yes
CS
Frame: n
Request
for Manual
mode
CS
Frame:
n+1
Entry into
Manual
Mode
CS
Frame:
n+2
Operation
in Manual
mode
* Sample: Samples and converts channel selected in ‘frame n-1’
* Mux : Selects channel incremented from previous frame as per auto sequence this channel will be
acquired in this frame and sampled at start of ‘frame n+1’
* Range: As programmed in ‘frame n-1’ . Applies to channel selected for acquisition in current frame
.
* SDI : Programming for ‘frame n +1’
DI15..12 = 0001 binary …. Selects manual mode
DI11=1 enables programming of ‘range and GPIO’
DI10..7 = binary address of channel
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
*SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n -1’
* GPIO :
O/P: latched on CS falling edge as per DI3..0 written in frame n-1’
I/P: Input status latched on falling edge of CSand transferred serially on SDO in the same
frame
* Sample: Samples and converts channel selected in ‘frame n’
* Mux : Selects channel programmed in ‘frame n’(Manual mode) this channel will be acquired in this
frame and sampled at start of ‘frame n+2’
* Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current frame
.*
SDI : Programming for ‘frame n+2’
DI15..12 = 0001 binary …. To continue in manual mode
DI11=1 enables programming of ‘range and GPIO’
DI10..7 = binary address of channel
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
*SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n’
* GPIO :
O/P: latched on CS falling edge as per DI3..0 written in frame ‘n’
I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same
frame
* Sample: Samples and converts channel selected in ‘frame n+1’
* Mux : Selects channel programmed in ‘frame n+1’ (Manual mode), this channel will be acquired in
this frame and sampled at start of ‘frame n+3’
* Range: As programmed in ‘frame n+1’ . Applies to channel selected for acquisition in current frame.*
SDI : Programming for ‘frame n+3’
DI15..12 = 0001 binary …. Selects manual mode
DI11=1 enables programming of ‘range and GPIO’
DI10..7 = binary address of channel
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
*SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n+1’
* GPIO :
O/P: latched on CS falling edge as per DI3..0 written in frame n+1’
I/P: Input status latched on falling edge of CSand transferred serially on SDO in the same
frame
CS
Continue operation in manual mode
Figure 10. Entering and Running in Manual Channel Sequencing Mode
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Table 1. Mode Control Register Settings for Manual Mode
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12
0001
0001
Selects Manual Mode
DI11
0
1
Enables programming of bits DI06-00.
0
Device retains values of DI06-00 from the previous frame.
DI10-07
0000
This four bit data represents the address of the next channel to be selected in the next frame. DI10: MSB and
DI07: LSB. e.g. 0000 represents channel- 0, 0001 represents channel-1 etc.
DI06
0
0
Selects 2.5V i/p range (Range 1)
1
Selects 5V i/p range (Range 2)
DI05
0
0
Device normal operation (no powerdown)
1
Device powers down on 16th SCLK falling edge
0
SDO outputs current channel address of the channel on DO15..12 followed by 12 bit conversion
result on DO11..00.
DI04
0
1
DI03-00
(1)
(2)
14
0000
GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below.
Lower data bits DO11-DO00 represent 12-bit conversion result of the current channel.
DOI5
DOI4
DOI3
DOI2
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured
as input. SDI bit and corresponding GPIO information is given below
DI03
DI02
DI01
DI00
GPIO3 (2)
GPIO2 (2)
GPIO1 (2)
GPIO0 (2)
GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
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OPERATING IN AUTO-1 MODE
The details regarding entering and running in Auto-1 channel sequencing mode are illustrated in the flowchart in
Figure 11. Table 2 lists the Mode Control Register settings for Auto-1 mode in detail.
CS
Frame: n-1
Device operation in Manual or
Auto-2 mode
No
Change to Auto -1 mode?
Yes
CS
Frame: n
Request
for Auto-1
mode
CS
Frame:
n+1
Entry into
Auto-1
Mode
CS
Frame:
n+2
Operation
in Auto-1
mode
* Sample: Samples and converts channel selected in ‘frame n -1’
* Mux : Selects channel incremented from previous frame as per Auto -2 sequence, or channel
programmed in previous frame in case of manual mode. This channel will be acquired in this frame
and sampled at start of ‘frame n +1’
* Range: As programmed in ‘frame n-1’ . Applies to channel selected for acquisition in current frame
.
* SDI : Programming for ‘frame n+1’
DI15..12 = 0010 binary …. Selects Auto-1 mode
DI11=1 enables programming of ‘range and GPIO’
DI10 = x, Device automatically resets channel to lowest number in Auto -1 sequence.
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
*SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n -1’
* GPIO :
O/P: latched on CS falling edge as per DI 3..0 written in frame n-1’
I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same
frame
* Sample: Samples and converts channel selected in ‘frame n’
* Mux : Selects lowest channel# in Auto-1 sequence; this channel will be acquired in this frame and
sampled at start of ‘frame n+2’
* Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current frame
.
* SDI : Programming for ‘frame n +2’
DI15..12 = 0010 binary …. To continue in Auto-1 mode
DI11=1 enables programming of ‘range and GPIO’
DI10 =0, not to reset channel sequence
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
*SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n’
* GPIO :
O/P: latched on CS falling edge as per DI 3..0 written in frame ‘n’
I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same
frame
* Sample: Samples and converts channel selected in ‘frame n+1’ (ie. Lowest channel# in Auto-1
sequence)
* Mux : Selects next higher channel in Auto -1 sequence, this channel will be acquired in this frame
and sampled at start of ‘frame n +3’
* Range: As programmed in ‘frame n+1’ . Applies to channel selected for acquisition in current frame.*
SDI : Programming for ‘frame n+3’
DI15..12 = 0010 binary …. To continue in Auto-1 mode
DI11=1 enables programming of ‘range and GPIO’
DI10 =0 not to reset channel sequence
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
*SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n+1’
* GPIO :
O/P: latched on CS falling edge as per DI3..0 written in frame n+1’
I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same
frame
CS
Continue operation in Auto -1 mode
Figure 11. Entering and Running in Auto-1 Channel Sequencing Mode
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Table 2. Mode Control Register Settings for Auto-1 Mode
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12
0001
0010
Selects Auto-1 Mode
DI11
0
1
Enables programming of bits DI10-00.
0
Device retains values of DI10-00 from previous frame.
1
The channel counter is reset to the lowest programmed channel in the Auto-1 Program Register
0
The channel counter increments every conversion (No reset)
DI10
0
DI09-07
000
xxx
Do not care
DI06
0
0
Selects 2.5V i/p range (Range 1)
1
Selects 5V i/p range (Range 2)
0
Device normal operation (no powerdown)
1
Device powers down on the 16th SCLK falling edge
0
SDO outputs current channel address of the channel on DO15..12 followed by 12-bit conversion
result on DO11..00.
DI05
0
DI04
0
1
DI03-00
(1)
(2)
16
0000
GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below.
Lower data bits DO11-DO00 represent 12-bit conversion result of the current channel.
DO15
DO14
DO13
DO12
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured
as input. SDI bit and corresponding GPIO information is given below
DI03
DI02
DI01
DI00
GPIO3 (2)
GPIO2 (2)
GPIO1 (2)
GPIO0 (2)
GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
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The Auto-1 Program Register is programmed (once on powerup or reset) to pre-select the channels for the
Auto-1 sequence. Auto-1 Program Register programming requires two CS frames for complete programming. In
the first CS frame the device enters the Auto-1 register programming sequence and in the second frame it
programs the Auto-1 Program Register. Refer to Table 2, Table 3, and Table 4 for complete details.
CS
Device in any operation mode
No
Program Auto 1 register?
Yes
SDI: DI15..12 = 1000
(Device enters Auto 1 programming sequence)
CS
Entry into Auto 1
register
programming
sequence
CS
SDI: DI15..0 as per tables 4,5
Auto 1 register
programming
End of Auto 1 register programming
NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to
change the range or write GPIO data into the device during programming.
Figure 12. Auto-1 Register Programming Flowchart
Table 3. Program Register Settings for Auto-1 Mode
BITS
RESET
STATE
DESCRIPTION
LOGIC STATE
FUNCTION
FRAME 1
DI15-12
NA
1000
DI11-00
NA
Do not care
Device enters Auto-1 program sequence. Device programming is done in the next frame.
All 1s
1 (individual bit)
FRAME 2
DI15-00
A particular channel is programmed to be selected in the channel scanning sequence. The
channel numbers are mapped one-to-one with respect to the SDI bits; e.g.
DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00
A particular channel is programmed to be skipped in the channel scanning sequence. The
channel numbers are mapped one-to-one with respect to the SDI bits; e.g.
DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00
0 (individual bit)
Table 4. Mapping of Channels to SDI Bits
Device (1)
8 Chan
(1)
SDI BITS
DI15
DI14
DI13
DI12
DI11
DI10
DI09
DI08
DI07
DI06
DI05
DI04
DI03
DI02
DI01
DI00
X
X
X
X
X
X
X
X
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
When operating in Auto-1 mode, the device only scans the channels programmed to be selected.
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OPERATING IN AUTO-2 MODE
The details regarding entering and running in Auto-2 channel sequencing mode are illustrated in Figure 13.
Table 5 lists the Mode Control Register settings for Auto-2 mode in detail.
CS
Frame: n-1
Device operation in Manual or
Auto -1 mode
No
Change to Auto- 2 mode ?
Yes
CS
Frame: n
Request
for Auto-2
mode
CS
Frame:
n+1
Entry into
Auto-2
Mode
CS
Frame:
n+2
Operation
in Auto-2
mode
* Sample: Samples and converts channel selected in ‘frame n-1’
* Mux : Selects channel incremented from previous frame as per Auto-1 sequence, or channel
programmed in previous frame in case of manual mode.
. This channel will be acquired in this frame
and sampled at start of ‘frame n +1’
* Range: As programmed in ‘frame n-1’. Applies to channel selected for acquisition in current frame
.
* SDI : Programming for ‘frame n+1’
DI15..12 = 0011 binary …. Selects Auto-2 mode
DI11=1 enables programming of ‘range and GPIO’
DI10 = x, Device automatically resets to channel 0.
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
*SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n -1’
* GPIO :
O/P: latched on CS falling edge as per DI 3..0 written in frame n -1’
I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same
frame
* Sample: Samples and converts channel selected in ‘frame n’
* Mux : Selects channel0 (Auto-2 sequence always starts with Ch -0); this channel will be acquired
in this frame and sampled at start of ‘frame n+2’
* Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current frame
.
* SDI : Programming for ‘frame n +2’
DI15..12 = 0011 binary …. To continue in Auto -2 mode
DI11=1 enables programming of ‘range and GPIO’
DI10 =0, not to reset channel sequence
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
*SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n’
* GPIO :
O/P: latched on CS falling edge as per DI 3..0 written in frame ‘n’
I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same
frame
* Sample: Samples and converts channel 0
* Mux : Selects next higher channel in Auto -2 sequence, this channel will be acquired in this frame
and sampled at start of ‘frame n+3’
* Range: As programmed in ‘frame n+1’. Applies to channel selected for acquisition in current frame.*
SDI : Programming for ‘frame n+3’
DI15..12 = 0011 binary …. To continue in Auto -2 mode
DI11=1 enables programming of ‘range and GPIO’
DI10 =0 not to reset channel sequence
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
*SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n+1’
* GPIO :
O/P: latched on CS falling edge as per DI 3..0 written in frame n+1’
I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same
frame
CS
Continue operation in Auto-2 mode
Figure 13. Entering and Running in Auto-2 Channel Sequencing Mode
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Table 5. Mode Control Register Settings for Auto-2 Mode
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12
0001
0011
Selects Auto-2 Mode
DI11
0
1
Enables programming of bits DI10-00.
0
Device retains values of DI10-00 from the previous frame.
1
Channel number is reset to Ch-00.
0
Channel counter increments every conversion.(No reset).
DI10
0
DI09-07
000
xxx
Do not care
DI06
0
0
Selects 2.5V i/p range (Range 1)
1
Selects 5V i/p range (Range 2)
0
Device normal operation (no powerdown)
1
Device powers down on the 16th SCLK falling edge
0
SDO outputs the current channel address of the channel on DO15..12 followed by the 12-bit
conversion result on DO11..00.
DI05
DI04
0
0
1
DI03-00
(1)
0000
GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below.
Lower data bits DO11-DO00 represent the 12-bit conversion result of the current channel.
DO15
DO14
DO13
DO12
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
GPIO data for the channels configured as output. Device ignores data for the channel which is configured as
input. SDI bit and corresponding GPIO information is given below
DI03
DI02
DI01
DI00
GPIO3 (1)
GPIO2 (1)
GPIO1 (1)
GPIO0 (1)
GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
The Auto-2 Program Register is programmed (once on powerup or reset) to pre-select the last channel (or
sequence depth) in the Auto-2 sequence. Unlike Auto-1 Program Register programming, Auto-2 Program
Register programming requires only 1 CS frame for complete programming. See Figure 14 and Table 6 for
complete details.
CS
Device in any operation mode
No
Program Auto 2 register?
Yes
CS
SDI: Di15..12 = 1001
DI9..6 = binary address of last channel in the sequence
refer tables 6
Auto 2 register
programming
End of Auto 2 register programming
NOTE: The device continues its operation in the selected mode during programming. SDO is valid, however it is not possible
to change the range or write GPIO data into the device during programming.
Figure 14. Auto-2 Register Programming Flowchart
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Table 6. Program Register Settings for Auto-2 Mode
BITS
RESET
STATE
DESCRIPTION
LOGIC
STATE
FUNCTION
DI15-12
NA
1001
DI11-10
NA
Do not care
Auto-2 program register is selected for programming
DI09-06
NA
aaaa
DI05-00
NA
Do not care
This 4-bit data represents the address of the last channel in the scanning sequence. During device
operation in Auto-2 mode, the channel counter starts at CH-00 and increments every frame until it
equals “aaaa”. The channel counter roles over to CH-00 in the next frame.
CONTINUED OPERATION IN A SELECTED MODE
Once a device is programmed to operate in one of the modes, the user may want to continue operating in the
same mode. Mode Control Register settings to continue operating in a selected mode are detailed in Table 7.
Table 7. Continued Operation in a Selected Mode
BITS
RESET
STATE
DESCRIPTION
LOGIC
STATE
FUNCTION
DI15-12
0001
0000
The device continues to operate in the selected mode. In Auto-1 and Auto-2 modes the channel
counter increments normally, whereas in the Manual mode it continues with the last selected
channel. The device ignores data on DI11-DI00 and continues operating as per the previous
settings. This feature is provided so that SDI can be held low when no changes are required in the
Mode Control Register settings.
DI11-00
All '0'
Device ignores these bits when DI15-12 is set to 0000 logic state
PROGRAMMING ALARM THRESHOLDS
There are two Alarm Program Registers per channel, one for setting the high alarm threshold and the other for
setting the low alarm threshold. For ease of programming, two alarm programming registers per channel,
corresponding to four consecutive channels, are assembled into one group (a total eight registers). There are
four such groups for 16 channel devices and 3/2/1 such groups for 12/8/4 channel devices respectively. The
grouping of the various channels for each device in the ADS7955-Q1 is listed in Table 8. The details regarding
programming the alarm thresholds are illustrated in the flowchart in Figure 15. Table 9 lists the details regarding
the Alarm Program Register settings.
Table 8. Grouping of Alarm Program Registers
GROUP NO.
REGISTERS
0
High and low alarm for channel 0, 1, 2, and 3
1
High and low alarm for channel 4, 5, 6, and 7
Each alarm group requires 9 CS frames for programming their respective alarm thresholds. In the first frame the
device enters the programming sequence and in each subsequent frame it programs one of the registers from
the group. The device offers a feature to program less than eight registers in one programming sequence. The
device exits the alarm threshold programming sequence in the next frame after it encounters the first ‘Exit Alarm
Program’ bit high.
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CS
Device in any operation mode
No
Program alarm thresholds?
Yes
SDI: DI15..12 = 11XX
(xx indicates group of four channels; refer table 8)
Device enters alarm register programming sequence
CS
Entry into alarm
register
programming
sequence
CS
SDI: DI15..0 as per table 8 (program alarm thresholds)
Alarm register
programming
sequence
No
Yes
DI12 = 1?
Yes
Program another group of four channels?
No
End of alarm programing
NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to
change the range or write GPIO data into the device during programming.
Figure 15. Alarm Program Register Programming Flowchart
Table 9. Alarm Program Register Settings
DESCRIPTION
BITS
RESET STATE
LOGIC
STATE
FUNCTION
FRAME 1
DI15-12
NA
1100
Device enters ‘alarm programming sequence’ for group 0
1101
Device enters ‘alarm programming sequence’ for group 1
1110
Device enters ‘alarm programming sequence’ for group 2
1111
Device enters ‘alarm programming sequence’ for group 3
Note: DI15-12 = 11bb is the alarm programming request for group bb. Here ‘bb’ represents the alarm programming group number in binary
format.
DI11-14
NA
Do not care
FRAME 2 AND ONWARDS
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Table 9. Alarm Program Register Settings (continued)
DESCRIPTION
BITS
RESET STATE
LOGIC
STATE
FUNCTION
DI15-14
NA
cc
Where “cc” represents the lower two bits of the channel number in binary format. The device
programs the alarm for the channel represented by the binary number “bbcc”. Note that “bb” is
programmed in the first frame.
DI13
NA
1
High alarm register selection
0
Low alarm register selection
0
Continue alarm programming sequence in next frame
1
Exit Alarm Programming in the next frame. Note: If the alarm programming sequence is not
terminated using this feature then the device will remain in the alarm programming sequence
state and all SDI data will be treated as alarm thresholds.
Do not care
DI12
NA
DI11-10
NA
xx
DI09-00
All ones for high
alarm register
and all zeros for
low alarm register
This 10-bit data represents the alarm threshold. The 10-bit alarm threshold is compared with the upper 10-bit
word of the 12-bit conversion result. The device sets off an alarm when the conversion result is higher (High
Alarm) or lower (Low Alarm) than this number. For 10-bit devices, all 10 bits of the conversion result are
compared with the set threshold. For 8-bit devices, all 8 bits of the conversion result are compared with DI09
to DI02 and DI00, 01 are 'do not care'.
PROGRAMMING GPIO REGISTERS
NOTE
GPIO 1 to 3 are available only in TSSOP packaged devices. The QFN device offers 'GPIO
0' only. As a result, all references related to 'GPIO 0' only are valid in the case of QFN
package devices.
The device has four General Purpose Input and Output (GPIO) pins. Each of the four pins can be independently
programmed as General Purpose Output (GPO) or General Purpose Input (GPI). It is also possible to use the
GPIOs for some pre-assigned functions (refer to Table 10 for details). GPO data can be written into the device
through the SDI line. The device refreshes the GPO data on every CS falling edge as per the SDI data written in
the previous frame. Similarly, the device latches GPI status on the CS falling edge and outputs it on SDO (if GPI
is read enabled by writing DI04 = 1 during the previous frame) in the same frame starting on the CS falling edge.
The details regarding programming the GPIO registers are illustrated in the flowchart in Figure 16. Table 10 lists
the details regarding GPIO Register programming settings.
22
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CS
Device in any operation mode
No
Program GPIO register?
Yes
SDI: DI15..12 = 0100
Refer table 9 for DI11..00 data
CS
GPIO register
programming
End of GPIO register programming
NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to
change the range or write GPIO data into the device during programming.
Figure 16. GPIO Program Register Programming Flowchart
Table 10. GPIO Program Register Settings
BITS
RESET
STATE
DESCRIPTION
LOGIC
STATE
FUNCTION
DI15-12
NA
0100
Device selects GPIO Program Registers for programming.
DI11-10
00
00
Do not program these bits to any logic state other than ‘00’
DI09
0
1
Device resets all registers in the next CS frame to the reset state shown in the corresponding tables (it
also resets itself).
0
Device normal operation
DI08
0
1
Device configures GPIO3 as the device power-down input.
0
GPIO3 remains general purpose I or O. Program 0 for QFN packaged devices.
DI07
0
1
Device configures GPIO2 as device range input.
0
GPIO2 remains general purpose I or O. Program 0 for QFN packaged devices.
000
GPIO1 and GPIO0 remain general purpose I or O. Valid setting for QFN packaged devices.
xx1
Device configures GPIO0 as ‘high or low’ alarm output. This is an active high output. GPIO1 remains
general purpose I or O. Valid setting for QFN packaged devices.
010
Device configures GPIO0 as high alarm output. This is an active high output. GPIO1 remains general
purpose I or O. Valid setting for QFN packaged devices.
100
Device configures GPIO1 as low alarm output. This is an active high output. GPIO0 remains general
purpose I or O. Setting not allowed for QFN packaged devices.
110
Device configures GPIO1 as low alarm output and GPIO0 as a high alarm output. These are active high
outputs. Setting not allowed for QFN packaged devices.
DI06-04
000
Note: The following settings are valid for GPIO which are not assigned a specific function through bits DI08..04
DI03
0
DI02
0
DI01
DI00
0
0
1
GPIO3 pin is configured as general purpose output. Program 1 for QFN packaged devices.
0
GPIO3 pin is configured as general purpose input. Setting not allowed for QFN packaged devices.
1
GPIO2 pin is configured as general purpose output. Program 1 for QFN packaged devices.
0
GPIO2 pin is configured as general purpose input. Setting not allowed for QFN packaged devices.
1
GPIO1 pin is configured as general purpose output. Program 1 for QFN packaged devices.
0
GPIO1 pin is configured as general purpose input. Setting not allowed for QFN packaged devices.
1
GPIO0 pin is configured as general purpose output. Valid setting for QFN packaged devices.
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Table 10. GPIO Program Register Settings (continued)
BITS
RESET
STATE
DESCRIPTION
LOGIC
STATE
0
24
FUNCTION
GPIO0 pin is configured as general purpose input. Valid setting for QFN packaged devices.
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APPLICATION INFORMATION
ANALOG INPUT
The ADS7955-Q1 device offers a 10-bit ADC with 8-channel multiplexers for analog input. The multiplexer output
is available on the MXO pin. AINP is the ADC input pin. The devices offers flexibility for a system designer as
both signals are accessible esternally.
Typically it is convenient to short MXO to the AINP pin so that signal input to each multiplexer channel can be
processed independently. In this condition it is recommended to limit source impedance to 50Ω or less. Higher
source impedance may affect the signal settling time after a multiplexer channel change. This condition can
affect linearity and total harmonic distortion.
MXO
AINP
GPIO 0, H Alarm
Ch0
Ch1
GPIO 1, L Alarm
Ch2
GPIO 2, Range
GPIO 3, PD
From sensors, INA etc.
There is a restriction on
source impedance.
RSOURCE £ 50 W
ADC
SDO
To
Host
SDI
SCLK
CS
Chn*
REF
10 mF
REF5025
o/p
GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers 'GPIO 0' only. As a result all
references related to 'GPIO 0' only are valid in case of QFN package devices.
Figure 17. Typical Application Diagram Showing MXO Shorted to AINP
Another option is to add a common ADC driver buffer between the MXO and AINP pins. This relaxes the
restriction on source impedance to a large extent. Refer to the typical characteristics section for the effect of
source impedance on device performance. The typical characteristics show that the device has respectable
performance with up to 1kΩ source impedance. This topology (including a common ADC driver) is useful when
all channel signals are within the acceptable range of the ADC. In this case the user can save on signal
conditioning circuit for each channel.
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High Input
impedance PGA
(or non inverting buffer
like THS4031)
PGA Gain
Control
GPIO
1, 2, 3
MXO
AINP
GPIO 0
H/L Alarm
Ch0
Ch1
Ch2
From sensors, INA etc.
Source impedance has very
little effect on performance.
Refer to Typical Characteristics
for details.
ADC
SDO
To
Host
SDI
SCLK
CS
Chn*
REF
10 mF
REF5025
o/p
GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers 'GPIO 0' only. As a result all
references related to 'GPIO 0' only are valid in case of QFN package devices.
Figure 18. Typical Application Diagram Showing Common Buffer/PGA for all Channels
When the converter samples an input, the voltage difference between AINP and AGND is captured on the
internal capacitor array. The (peak) input current through the analog inputs depends upon a number of factors:
sample rate, input voltage, and source impedance. The current into the ADS7955-Q1 charges the internal
capacitor array during the sample period. After this capacitance has been fully charged, there is no further input
current. When the converter goes into hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the Ch0 ..
Chn and AINP inputs should be within the limits specified. Outside of these ranges, converter linearity may not
meet specifications.
80 W
ohm
MXO
Ch0
200 Wohm
3 pF
AINP
5 pF
7 pF
Chn
20M W
ohm
3 pF
Ch0 assumed to be on
Chn assumed to be off
Figure 19. ADC and Mux Equivalent Circuit
26
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REFERENCE
The ADS7955-Q1 can operate with an external 2.5V ± 10mV reference. A clean, low noise, well-decoupled
reference voltage on the REF pin is required to ensure good performance of the converter. A low noise band-gap
reference like the REF5025 can be used to drive this pin. A 10-μF ceramic decoupling capacitor is required
between the REF and GND pins of the converter. The capacitor should be placed as close as possible to the
pins of the device.
POWER SAVING
The ADS7955-Q1 device offers a power-down feature to save power when not in use. There are two ways to
powerdown the device. It can be powered down by writing DI05 = 1 in the Mode Control register (refer to
Table 1, Table 2 and Table 5); in this case the device powers down on the 16th falling edge of SCLK in the next
data frame. Another way to powerdown the device is through GPIO. GPIO3 can act as a PD input (refer to
Table 10, for assigning this functionality to GPIO3). This is an asynchronous and active low input. The device
powers down instantaneously after GPIO3 (PD) = 0. The device will powerup again on the CS falling edge while
DI05 = 0 in the Mode Control register and GPIO3 (PD) = 1.
DIGITAL OUTPUT
As discussed previously in the Device Operation section, the digital output of the ADS7955-Q1 device is SPI
compatible. The following table lists the output codes corresponding to various analog input voltages.
Table 11. Ideal Input Voltages and Output Codes
DESCRIPTION
ANALOG VALUE
DIGITAL OUTPUT
Full scale range
Range 1 → Vref
Range 2 → 2×Vref
Least significant bit (LSB)
Vref/1024
2Vref/1024
Full scale
Vref – 1 LSB
2Vref – 1 LSB
11 1111 1111
3FF
Midscale
Vref/2
Vref
10 0000 0000
200
Midscale – 1 LSB
Vref/2 – 1 LSB
Vref – 1 LSB
01 1111 1111
1FF
Zero
0V
0V
00 0000 0000
000
STRAIGHT BINARY
BINARY CODE
HEX CODE
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
ADS7955QDBTRQ1
ACTIVE
TSSOP
DBT
30
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS7955Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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