ADS8401IBPFBR

ADS8401 SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 16-BIT, 1.25 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG-TODIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE FEATURES D 1.25-MHz Sample Rate D 16-Bit NMC Ensured Over Temperature D Zero Latency D Unipolar Single-Ended Input Range: 0 V to Vref APPLICATIONS D DWDM D Instrumentation D High-Speed, High-Resolution, Zero Latency Data Acquisition Systems D Onboard Reference D Onboard Reference Buffer D High-Speed Parallel Interface D Power Dissipation: 155 mW at 1.25 MHz Typ D Wide Digital Supply D 8-/16-Bit Bus Transfer D 48-Pin TQFP Package D Transducer Interface D Medical Instruments D Communication DESCRIPTION The ADS8401 is a 16-bit, 1.25 MHz A/D converter with an internal 4.096-V reference. The device includes a 16-bit capacitor-based SAR A/D converter with inherent sample and hold. The ADS8401 offers a full 16-bit interface and an 8-bit option where data is read using two 8-bit read cycles. The ADS8401 has a unipolar single-ended input. It is available in a 48-lead TQFP package and is characterized over the industrial –40°C to 85°C temperature range. SAR +IN –IN REFIN + _ Output Latches and 3-State Drivers BYTE 16-/8-Bit Parallel DATA Output Bus CDAC Comparator RESET Conversion and Control Logic CONVST BUSY CS RD REFOUT 4.096-V Internal Reference Clock Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2002–2003, Texas Instruments Incorporated ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES RESOLUTION (BIT) PACKAGE TYPE PACKAGE DESIGNATOR TEMPERATURE RANGE ORDERING INFORMATION TRANSPORT MEDIA QUANTITY Tape and reel 250 Tape and reel 1000 Tape and reel 250 Tape and reel 1000 MODEL ADS8401I ±6 –2 3 2~3 15 48 Pin Pin TQFP PFB –40°C to to 85°C ADS8401IPFBT ADS8401IPFBR ADS8401IBPFBT ADS8401IBPFBR ADS8401IB ±3 5 3.5 –1 2 1~2 16 48 Pin Pin TQFP PFB –40°C to to 85°C NOTE: For the most current specifications and package information, refer to our website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT +IN to AGND Voltage –IN to AGND +VA to AGND Voltage range range +VBD to BDGND +VA to +VBD Digital input voltage to BDGND Digital output voltage to BDGND Operating free-air temperature range, TA Storage temperature range, Tstg Junction temperature (TJ max) Power dissipation TQFP package θJA thermal impedance Vapor phase (60 sec) Lead temperature soldering temperature, Infrared (15 sec) +VA + 0.1 V 0.5 V –0.3 V to 7 V –0.3 V to 7 V –0.3 V to 2.5 V –0.3 V to +VBD + 0.3 V –0.3 V to +VBD + 0.3 V –40°C to 85°C –65°C to 150°C 150°C (TJMax – TA)/θJA 86°C/W 215°C 220°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Analog Input Full-scale input voltage (see Note 1) Absolute input voltage Input capacitance Input leakage current System Performance Resolution ADS8401I No missing codes Integral linearity (see Notes 2 and 3) Differential linearity Differentiallinearity Offset error (see Note 4) Gain error (see Notes 4 and 5) Noise DC Power supply rejection ratio Sampling Dynamics Conversion time Acquisition time Throughput rate Aperture delay Aperture jitter Step response Overvoltage recovery (1) Ideal input span, does not include gain or offset error. (2) LSB means least significant bit (3) This is endpoint INL, not best fit. (4) Measured relative to an ideal full-scale input (+IN – –IN) of 4.096 V (5) This specification does not include the internal reference voltage error and drift. 2 25 100 100 150 At FFFFh output code, +VA = 4.75 V to 5.25 V, Vref = 4.096 V, See Note 4 ADS8401IB ADS8401I ADS8401IB ADS8401I ADS8401IB ADS8401I ADS8401IB ADS8401I ADS8401IB 15 16 –6 –3.5 –2 –1 –1.5 –0.75 –0.15 –0.098 60 2 ±2.5 ±2 ±1 ±0.75 ±0.5 ±0.25 16 +IN – –IN +IN –IN 0 –0.2 –0.2 25 0.5 MAX Vref Vref + 0.2 0.2 UNIT V V pF nA Bits Bits 6 3.5 3 2 1.5 0.75 0.15 0.098 %FS µV RMS LSB LSB mV mV LSB 610 1.25 ns ns MHz ns ps ns ns 3 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 SPECIFICATIONS (CONTINUED) TA = –40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Dynamic Characteristics Total harmonic distortion (THD) (see Note 1) Signal-to-noise ratio (SNR) Signal-to-noise + distortion (SINAD) Spurious free dynamic range (SFDR) –3dB Small signal bandwidth External Voltage Reference Input Reference voltage at REFIN, Vref Reference resistance (see Note 2) Internal Reference Output Internal reference start-up time Vref range Source Current Line Regulation Drift Digital Input/Output Logic family VIH VIL VOH VOL IIH = 5 µA IIL = 5 µA IOH = 2 TTL loads IOL = 2 TTL loads +VBD–1 –0.3 +VBD – 0.6 0 Straight Binary CMOS +VBD + 0.3 0.8 +VBD 0.4 V from 95% (+VA), with 1 µF storage capacitor IOUT = 0 Static load +VA = 4.75 ~ 5.25 V IOUT = 0 0.6 36 4.065 4.096 120 4.13 10 ms V µA mV PPM/C 2.5 4.096 500 4.2 V kΩ VIN = 4 Vpp at 100 kHz VIN = 4 Vpp at 100 kHz VIN = 4 Vpp at 100 kHz VIN = 4 Vpp at 100 kHz –93 86 85 93 5 dB dB dB dB MHz MAX UNIT Logic level L il l Data format Power Supply Requirements Power su ly supply voltage +VBD (see Notes 3 and 4) +VA (see Note 4) fs = 1.25 MHz fs = 1.25 MHz 2.95 4.75 3.3 5 31 155 5.25 5.25 34 V V mA mW °C +VA Supply current (see Note 5) Power dissipation (see Note 5) Temperature Range Operating free-air –40 85 (1) Calculated on the first nine harmonics of the input frequency (2) Can vary ±20% (3) The difference between +VA and +VBD should not be less than 2.3 V, i.e., if +VA is 5.25 V, +VBD should be minimum of 2.95 V. (4) +VBD ≥ +VA – 2.3 V (5) This includes only VA+ current. +VBD current is typically 1 mA with 5 pF load capacitance on output pins. 4 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V (see Notes 1, 2, and 3) PARAMETER tCONV tACQ tpd1 tpd2 tw1 tsu1 tw2 tw3 tw4 th1 td1 tsu2 tw5 ten td2 td3 tw6 th2 tpd4 tsu3 th3 tdis td5 Conversion time Acquisition time CONVST low to conversion started (BUSY high) Propagation delay time, End of conversion to BUSY low Pulse duration, CONVST low Setup time, CS low to CONVST low Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal low Pulse duration, BUSY signal high Hold time, First data bus data transition (RD low, or CS low for read cycle, or BYTE input changes) after CONVST low Delay time, CS low to RD low Setup time, RD high to CS high Pulse duration, RD low time Enable time, RD low (or CS low for read cycle) to data valid Delay time, data hold from RD high Delay time, BYTE rising edge or falling edge to data valid RD high Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge Setup time, BYTE rising edge to RD falling edge Hold time, BYTE falling edge to RD falling edge Disable time, RD High (CS high for read cycle) to 3-stated data bus Delay time, BUSY low to MSB data valid 0 2 20 50 Max(td5) 0 0 20 0 20 20 40 0 0 50 20 Min(tACQ) 630 20 0 20 10 150 35 20 MIN TYP 600 MAX 610 UNIT ns ns ns ns ns ns ns ps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tsu4 Setup time, BYTE change before BUSY falling edge 2 (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. (3) All timings are measured with 20 pF equivalent loads on all data bits and BUSY pins. 5 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = 5 V, +VBD = 3 V (see Notes 1, 2, and 3) PARAMETER tCONV tACQ tpd1 tpd2 tw1 tsu1 tw2 tw3 tw4 th1 td1 tsu2 tw5 ten td2 td3 tw6 th2 tpd4 tsu3 th3 tdis td5 Conversion time Acquisition time CONVST low to conversion started (BUSY high) Propagation delay time, end of conversion to BUSY low Pulse duration, CONVST low Setup time, CS low to CONVST low Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal low Pulse duration, BUSY signal high Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS 16/16 input changes) after CONVST low Delay time, CS low to RD low Setup time, RD high to CS high Pulse duration, RD low Enable time, RD low (or CS low for read cycle) to data valid Delay time, data hold from RD high Delay time, BUS16/16 or BYTE rising edge or falling edge to data valid Pulse duration, RD high time Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge Setup time, BYTE rising edge to RD falling edge Hold time, BYTE falling edge to RD falling edge Disable time, RD High (CS high for read cycle) to 3-stated data bus Delay time, BUSY low to MSB data valid delay time 0 2 20 50 Max(td5) 0 0 30 0 30 30 40 0 0 50 30 Min(tACQ) 630 20 0 20 10 150 40 20 MIN TYP 600 MAX 610 UNIT ns ns ns ns ns ns ns ps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tsu4 Setup time, BYTE change before BUSY falling edge 2 (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. (3) All timings are measured with 10 pF equivalent loads on all data bits and BUSY pins. 6 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 PIN ASSIGNMENTS PFB PACKAGE (TOP VIEW) 36 35 34 33 32 31 30 29 28 27 26 25 +VBD RESET BYTE CONVST RD CS +VA AGND AGND +VA REFM REFM BUSY BDGND +VBD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 BDGND 37 38 39 40 41 42 43 44 45 46 47 48 12 3 45 678 24 23 22 21 20 19 18 17 16 15 14 13 9 10 11 12 +VBD DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 AGND AGND +VA REFIN REFOUT NC +VA AGND +IN –IN AGND +VA +VA NC – No connection AGND AGND 7 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 TERMINAL FUNCTIONS NAME AGND BDGND BUSY BYTE NO. 5, 8, 11, 12, 14, 15, 44, 45 25, 35 36 39 I/O – – O I Analog ground Digital ground for bus interface digital supply Status output. High when a conversion is in progress. Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[15:8]. Convert start Chip select 8-Bit Bus Data Bus Dt B DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 –IN +IN NC REFIN REFM REFOUT RESET RD +VA +VBD 16 17 18 19 20 21 22 23 26 27 28 29 30 31 32 33 7 6 3 1 47, 48 2 38 41 4, 9, 10, 13, 43, 46 24, 34, 37 O O O O O O O O O O O O O O O O I I – I I O I I – – D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) Inverting input channel Non inverting input channel No connection Reference input Reference ground Reference output. Add 1 µF capacitor between the REFOUT pin and REFM pin when internal reference is used. Current conversion is aborted and output latches are cleared (set to zeros) when this pin is asserted low. RESET works independantly of CS. Synchronization pulse for the parallel output. Analog power supplies, 5-V dc Digital power supply for bus BYTE = 0 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) All ones All ones All ones All ones All ones All ones All ones All ones BYTE = 1 D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) 16-Bit Bus BYTE = 0 DESCRIPTION CONVST CS 40 42 I I 8 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 TIMING DIAGRAMS tw1 CONVST tpd1 BUSY tsu1 CS CONVERT† t(CONV) SAMPLING† (When CS Toggle) t(ACQ) BYTE th1 tpd4 RD td1 tsu2 th2 t(CONV) tpd2 tw3 tw2 tw4 ten DB[15:8] Hi–Z D [15:8] DB[7:0] Hi–Z D [7:0] †Signal internal to device D [7:0] tdis Hi–Z Hi–Z Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling 9 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 tw1 CONVST tpd1 BUSY tsu1 CS CONVERT† t(CONV) SAMPLING† (When CS Toggle) tpd2 tw2 tw4 tw3 t(CONV) t(ACQ) BYTE th1 tpd4 RD = 0 ten DB[15:8] Hi–Z D [15:8] tdis D [7:0] Hi–Z th2 DB[7:0] †Signal internal to device Hi–Z D [7:0] Hi–Z Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND 10 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 tw1 CONVST tpd1 BUSY tpd2 tw2 tw4 tw3 CS = 0 CONVERT† t(CONV) t(CONV) SAMPLING† (When CS = 0) t(ACQ) BYTE th1 tpd4 RD ten DB[15:8] Hi–Z D [15:8] D [7:0] tdis Hi–Z th2 DB[7:0] †Signal internal to device Hi–Z D [7:0] Hi–Z Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling 11 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 tw1 CONVST tpd1 BUSY tw4 tpd2 tw2 tw3 CS = 0 CONVERT† t(CONV) t(CONV) t(ACQ) SAMPLING† (When CS = 0) BYTE th1 th1 td3 D [7:0] D [15:8] Next D [15:8] RD = 0 tdis td5 DB[15:8] Previous D [7:0] DB[7:0] D [7:0] Next D [7:0] †Signal internal to device Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto Read CS RD BYTE ten ten DB[15:0] Hi–Z Valid tdis Hi–Z Valid Valid td3 tdis Hi–Z Figure 5. Detailed Timing for Read Cycles 12 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 TYPICAL CHARACTERISTICS† HISTOGRAM (DC Code Spread) NEAR FULL SCALE 98304 CONVERSIONS 40000 35000 30000 25000 20000 15000 10000 5000 0 65255 65260 65264 +VA = 5 V, Code = 65260 86.4 86.2 SNR – Signal-To- Noise Ratio – dB 86 85.8 SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE fi = 100 kHz (+IN– –IN) = Full Scale 85.6 85.4 85.2 85 –10 5 20 35 50 65 TA – Free-Air Temperature – °C 80 Figure 6 Figure 7 SIGNAL-TO-NOISE PLUS DISTORTION vs FREE-AIR TEMPERATURE 85.4 SINAD – Signal-To-Noise Plus Distortion – dB SFDR – Spurious Free-Dynamic Range – dB fi = 100 kHz (+IN– –IN) = Full Scale 85.2 93.3 93.2 93.1 93 92.9 92.8 92.7 92.6 92.5 92.4 92.3 92.2 –40 SPURIOUS FREE-DYNAMIC RANGE vs FREE-AIR TEMPERATURE fi = 100 kHz (+IN– –IN) = Full Scale 85 84.8 84.6 84.4 84.2 –10 5 20 35 50 65 80 –20 0 20 40 60 80 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 8 Figure 9 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 13 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE –92.2 THD – Total Harmonic Distortion – dB –92.3 –92.4 –92.5 –92.6 –92.7 –92.8 –92.9 –93 –93.1 –93.2 –93.3 –40 –25 85.8 –10 5 20 35 50 65 80 0 fi = 100 kHz (+IN– –IN) = Full Scale SNR – Signal-To- Noise Ratio – dB 87.2 87 86.8 86.6 SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY TA = 25°C (+IN– –IN) = Full Scale 86.4 86.2 86 20 40 60 80 100 TA – Free-Air Temperature – °C fi – Input Frequency – kHz Figure 10 Figure 11 SIGNAL-TO-NOISE PLUS DISTORTION vs INPUT FREQUENCY 87 SINAD – Signal-To-Noise Plus Distortion – dB 86.8 86.6 86.4 86.2 86 85.8 85.6 85.4 13.85 85.2 85 0 20 40 60 80 100 fi – Input Frequency – kHz 13.8 0 20 ENOB – Bits 14.05 14 13.95 13.9 TA = 25°C (+IN– –IN) = Full Scale 14.2 14.15 14.1 ENOB vs INPUT FREQUENCY 40 60 80 fi – Input Frequency – kHz 100 Figure 12 Figure 13 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 14 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 SPURIOUS FREE-DYNAMIC RANGE vs INPUT FREQUENCY 106 SFDR – Spurious Free-Dynamic Range – dB THD – Total Harmonic Distortion – dB 104 102 TA = 25°C (+IN– –IN) = Full Scale –92 –94 –96 –98 TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 100 98 –100 –102 –104 –106 TA = 25°C (+IN– –IN) = Full Scale 96 94 92 0 20 40 60 80 100 fi– Input Frequency – kHz 0 20 40 60 80 fi – Input Frequency – kHz 100 Figure 14 SUPPLY CURRENT vs SAMPLE RATE 31.5 31 I CC – Supply Current – mA 30.5 EG – Gain Error – %FS 30 29.5 29 28.5 28 27.5 27 250 500 750 1000 1250 0.012 4.75 4.85 0.019 TA = 25°C Current of +VA only 0.022 Figure 15 GAIN ERROR vs SUPPLY VOLTAGE 0.017 0.014 TA = 25°C External Reference = 4.096 V (REFIN) Sample Rate – KSPS 4.95 5.05 5.15 +VA – Supply Voltage – V 5.25 Figure 16 Figure 17 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 15 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 OFFSET ERROR vs SUPPLY VOLTAGE 0.14 0.12 0.10 0.08 Vref – Internal Reference Voltage – V 4.104 INTERNAL REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE 4.100 EO – Offset Error – mV 4.096 0.06 0.04 0.02 0 4.75 TA = 25°C External Reference = 4.096 V (REFIN) 4.092 4.088 4.85 4.95 5.05 5.15 +VA – Supply Voltage – V 5.25 4.084 –40 –25 –10 5 20 35 50 65 80 TA – Free-Air Temperature – °C Figure 18 Figure 19 GAIN ERROR vs FREE-AIR TEMPERATURE 0.028 0.30 OFFSET ERROR vs FREE-AIR TEMPERATURE External Reference = 4.096 V (REFIN) 0.024 EG – Gain Error – %FS 0.25 0.019 EO – Offset Error – mV External Reference = 4.096 V (REFIN) 0.20 0.014 0.15 0.009 0.10 0.004 0.05 0 –40 –25 –10 5 20 35 50 65 TA – Free-Air Temperature – °C 80 0 –40 –25 –10 5 20 35 50 65 80 TA – Free-Air Temperature – °C Figure 20 Figure 21 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 16 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 SUPPLY CURRENT vs FREE-AIR TEMPERATURE 31.4 DNL – Differential Nonlinearity (Max) – LSB DIFFERENTIAL NONLINEARITY (MAX) vs FREE-AIR TEMPERATURE 1.24 External Reference = 4.096 V (REFIN) 1.20 I CC – Supply Current – mA 31.2 1.16 31.0 1.12 1.08 30.8 External Reference = 4.096 V (REFIN) Current of +VA Only 30.6 –40 –25 –10 5 20 35 50 65 TA – Free-Air Temperature – °C 80 1.04 1 –40 –25 –10 5 20 35 50 65 80 TA – Free-Air Temperature – °C Figure 22 Figure 23 DIFFERENTIAL NONLINEARITY (MIN) vs FREE-AIR TEMPERATURE –0.72 DNL – Differential Nonlinearity (MIN) – LSB INL – Integral Nonlinearity (MAX) – LSB 2 INTEGRAL NONLINEARITY (MAX) vs FREE-AIR TEMPERATURE 1.6 –0.76 1.2 –0.80 0.8 –0.84 External Reference = 4.096 V (REFIN) –0.88 –40 0.4 External Reference = 4.096 V (REFIN) 0 –40 –25 –10 5 20 35 50 65 TA – Free-Air Temperature – °C 80 –25 –10 5 20 35 50 65 80 TA – Free-Air Temperature – °C Figure 24 Figure 25 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 17 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 INTEGRAL NONLINEARITY (MIN) vs FREE-AIR TEMPERATURE –2 INL – Integral Nonlinearity (MIN) – LSB 5 4 –2.4 INL – Integral Nonlinearity – LSB 3 2 1 0 –1 INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE +VA = +VBD = 5 V, TA = 25°C Max –2.8 –3.2 Min –2 –3 –4 2.0 –3.6 External Reference = 4.096 V (REFIN) –4 –40 –25 –10 5 20 35 50 65 TA – Free-Air Temperature – °C 80 2.5 3.0 3.5 4.0 4.5 Vref – Reference Voltage – V Figure 26 Figure 27 DIFFERENTIAL NONLINEARITY vs REFERENCE VOLTAGE 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Min –0.5 –1.0 2.0 Max +VA = +VBD = 5 V, TA = 25°C DNL – Differential Nonlinearity – LSB 2.5 3.0 3.5 4.0 Vref – Reference Voltage – V 4.5 Figure 28 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 18 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 DNL 1.2 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 –1.2 DNL – LSB 0 16384 32768 Code 49152 65536 TA = 25°C, External Reference = 4.096 V (REFIN) Figure 29 INL 2.5 2 1.5 INL – LSB 1 0.5 0 –0.5 –1 –1.5 –2 –2.5 0 16384 32768 Code 49152 65536 TA = 25°C, External Reference = 4.096 V (REFIN) Figure 30 FFT SPECTRUM RESPONSE 0 Magnitude – dB of Full Scale –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 0 100 200 300 Frequency – kHz 400 500 600 32768 Points, fS = 1.25 MHz, Internal Reference = 4.096 V (REFIN), TA = 25°C, fi = 100 kHz, (+IN– –IN) = Full Scale Figure 31 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 19 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 APPLICATION INFORMATION MICROCONTROLLER INTERFACING ADS8401 to 8-Bit Microcontroller Interface Figure 32 shows a parallel interface between the ADS8401 and a typical microcontroller using the 8-bit data bus. The BUSY signal is used as a falling-edge interrupt to the microcontroller. Analog 5 V 0.1 µF AGND 10 µF 1 µF 0.1 µF Ext Ref Input Analog Input +VA REFIN REFM AGND +IN –IN Micro Controller GPIO GPIO P[7:0] RD GPIO INT CS BYTE DB[15:8] RD CONVST BUSY ADS8401 BDGND BDGND +VBD 0.1 µF Digital 3 V Figure 32. ADS8401 Application Circuitry (using external reference) Analog 5 V 0.1 µF 10 µF AGND 0.1 µF 1 µF REFOUT REFM +VA REFIN AGND AGND ADS8401 Figure 33. Use Internal Reference 20 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 PRINCIPLES OF OPERATION The ADS8401 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on charge redistribution, which inherently includes a sample/hold function. See Figure 32 for the application circuit for the ADS8401. The conversion clock is generated internally. The conversion time of 610 ns is capable of sustaining a 1.25-MHz throughput. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. REFERENCE The ADS8401 can operate with an external reference with a range from 2.5 V to 4.2 V. A 4.096-V internal reference is included. When internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with an 0.1 µF decoupling capacitor and 1 µF storage capacitor between pin 2 (REFOUT) and pins 47 and 48 (REFM) (see Figure 33). The internal reference of the converter is double buffered. If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected (floating) if external reference is used. ANALOG INPUT When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The voltage on the –IN input is limited between –0.2 V and 0.2 V, allowing the input to reject small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.2 V to Vref + 0.2 V. The input span (+IN – (–IN)) is limited to 0 V to Vref. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8401 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25 pF) to an 16-bit settling level within the acquisition time (150 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN and –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, the converter ’s linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output impedance of the sources driving +IN and –IN inputs are matched. If this is not observed, the two inputs could have different setting time. This may result in offset error, gain error and linearity error which varies with temperature and input voltage. DIGITAL INTERFACE Timing And Control See the timing diagrams in the specifications section for detailed information on timing signals and their requirements. The ADS8401 uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter. No external clock input is required. Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8401 switches from the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is important to the performance of the converter. The BUSY output is brought high after CONVST goes low. BUSY stays high throughout the conversion process and returns low when the conversion has ended. 21 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when BUSY is low. Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus with the conversion. Reading Data The ADS8401 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This is 100 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should be attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used for multiword read operations. BYTE is used whenever lower bits of the converter result are output on the higher byte of the bus. Refer to Table 1 for ideal output codes. Table 1. Ideal Input Voltages and Output Codes DESCRIPTION FULL SCALE RANGE Least significant bit (LSB) Full scale Midscale Midscale – 1 LSB Zero ANALOG VALUE Vref Vref/65536 Vref – 1 LSB Vref/2 Vref/2 – 1 LSB 0V DIGITAL OUTPUT STRAIGHT BINARY BINARY CODE 1111 1111 1111 1111 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 HEX CODE FFFF 8000 7FFF 0000 The output data is a full 16-bit word (D15–D0) on DB15–DB0 pins (MSB–LSB) if BYTE is low. The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15–DB8. In this case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on pins DB15–DB8, then bringing BYTE high. When BYTE is high, the low bits (D7–D0) appear on pins DB15–D8. These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity. DATA READ OUT BYTE High Low DB15–DB8 D7–D0 D15–D8 DB7–DB0 All one’s D7–D0 RESET RESET is an asynchronous active low input signal (that works independently of CS). Minimum RESET low time is 20 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In addition, all output latches are cleared (set to zero’s) after RESET. The converter goes back to normal operation mode no later than 20 ns after RESET input is brought high. The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling edge of CS, whichever is later. POWER-ON INITIALIZATION One RESET pulse followed by three conversion cycles must be given to the converter after powerup to ensure proper operation. The next pulse can be issued once both +VA and +VBD reach 95% of the minimum required value. 22 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8401 circuitry. As the ADS8401 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the ADS8401 draws very little current from an external reference, as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and a 1-µF storage capacitor are recommended from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the same ground plane under the device. The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8401 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 2 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply, removing the high frequency noise. Table 2. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE SUPPLY PINS Pin pairs that require shortest path to decoupling capacitors Pins that require no decoupling CONVERTER ANALOG SIDE (4,5), (8,9), (10,11), (13,15), (43,44), (45,46) 12, 14 CONVERTER DIGITAL SIDE (24,25), (34, 35) 37 23 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,50 36 25 0,27 0,17 0,08 M 37 24 48 13 0,13 NOM 1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,05 MIN 1,05 0,95 Seating Plane 0,75 0,45 Gage Plane 0,25 0°– 7° 12 1,20 MAX 0,08 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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