ADS8371IBPFBR

 SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005     
    


  
   

 
 FEATURES D 750-KSPS Sample Rate D High Linearity: D D D D D D D D D D APPLICATIONS − +0.9 LSB INL Typ, +1.5 LSB Max − −0.4/+0.6 LSB DNL Typ, +1 LSB Max Onboard Reference Buffer and Conversion Clock 0 V to 4.096 V Unipolar Inputs Low Noise: 88 dB SNR High Dynamic Range: 110 dB SFDR Very Low Offset and Offset Drift Low Power: 130 mW at 750 KSPS Wide Buffer Supply, 2.7 V to 5.25 V Flexible 8-/16-Bit Parallel Interface Direct Pin Compatible With ADS8381/ADS8383 48-Pin TQFP Package −IN + _ Medical Instruments Optical Networking Transducer Interface High Accuracy Data Acquisition Systems Magnetometers DESCRIPTION The ADS8371 is an 16-bit, 750 kHz A/D converter. The device includes a 16-bit capacitor-based SAR A/D converter with inherent sample and hold. The ADS8371 offers a full 16-bit interface or an 8-bit bus option using two read cycles. The ADS8371 is available in a 48-lead TQFP package and is characterized over the industrial −40°C to 85°C temperature range. SAR +IN D D D D D Output Latches and 3-State Drivers CDAC BYTE 16-/8-Bit Parallel DATA Output Bus Comparator REFIN Clock Conversion and Control Logic CONVST BUSY CS RD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  

!"#$%&'(!$" !) *+%%,"( ') $# -+./!*'(!$" 0'(,1 %$0+*() *$"#$%& ($ )-,*!#!*'(!$") -,% (2, (,%&) $# ,3') ")(%+&,"() )('"0'%0 4'%%'"(51 %$0+*(!$" -%$*,))!"6 0$,) "$( ",*,))'%!/5 !"*/+0, (,)(!"6 $# '// -'%'&,(,%)1 Copyright  2003 − 2005, Texas Instruments Incorporated 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION MODEL MAXIMUM INTEGRAL LINEARITY (LSB) ADS8371I ADS8371IB MAXIMUM DIFFERENTIAL LINEARITY (LSB) ±2.5 −1/1.5 ±1.5 ±1 NO MISSING CODES RESOLUTION (BIT) PACKAGE TYPE 16 48 Pin TQFP 16 48 Pin TQFP PACKAGE DESIGNATOR TEMPERATURE RANGE PFB −40 C to −40°C 85°C PFB −40 C to −40°C 85°C ORDERING INFORMATION TRANSPORT MEDIA QUANTITY ADS8371IPFBT Tape and reel 250 ADS8371IPFBR Tape and reel 1000 ADS8371IBPFBT Tape and reel 250 ADS8371IBPFBR Tape and reel 1000 NOTE: For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT Voltage Voltage range +IN to AGND −0.4 V to +VA + 0.1 V −IN to AGND −0.4 V to 0.5 V +VA to AGND −0.3 V to 7 V +VBD to BDGND +VA to +VBD −0.3 V to 7 V −0.3 V to 2.55 V Digital input voltage to BDGND −0.3 V to +VBD + 0.3 V Digital output voltage to BDGND −0.3 V to +VBD + 0.3 V Operating free-air temperature range, TA −40°C to 85°C Storage temperature range, Tstg −65°C to 150°C Junction temperature (TJ max) Power dissipation TQFP package θJA thermal impedance Vapor phase (60 sec) Lead temperature, soldering Infrared (15 sec) 150°C (TJMax − TA)/θJA 86°C/W 215°C 220°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 SPECIFICATIONS TA = −40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 750 kHz (unless otherwise noted) ADS8371IB ADS8371I TEST PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNIT Analog Input Full-scale input voltage (see Note 1) Absolute input voltage +IN − −IN 0 +IN −0.2 Vref Vref + 0.2 −IN −0.2 0.2 Input capacitance Input leakage current 0 −0.2 Vref Vref + 0.2 −0.2 0.2 V V 45 45 pF 1 1 nA 16 Bits System Performance Resolution 16 No missing codes 16 Integral linearity (see Notes 2 and 3) Differential linearity Offset error Gain error (see Note 4) −1.5 −0.8/0.9 −1 −0.75 1.5 −2.5 −0.4/0.6 1 −1 ±0.25 0.75 −1 0.075 −0.15 −0.075 Noise Power supply rejection ratio 16 At 3FFFFh output code Bits ±0.5 2.5 LSB 1.5 LSB 1 0.15 mV %FS 60 60 µV RMS 75 75 dB Sampling Dynamics Conversion time Acquisition time 1.13 0.2 1.13 µs 750 kHz µs 0.2 Throughput rate 750 Aperture delay 4 4 ns Aperture jitter 15 15 ps Step response 150 150 ns 150 150 ns Over voltage recovery (1) Ideal input span, does not include gain or offset error. (2) LSB means least significant bit (3) This is endpoint INL, not best fit. (4) Measured relative to an ideal full-scale input (+IN − −IN) of 4.096 V 3 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 SPECIFICATIONS (CONTINUED) TA = −40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 750 kHz (unless otherwise noted) ADS8371IB ADS8371I TEST PARAMETER CONDITIONS MIN TYP MAX MIN TYP UNIT MAX UNIT Dynamic Characteristics Total harmonic distortion (THD) (see Note 1) Signal to noise ratio (SNR) (see Note 1) 1 kHz −106 −100 10 kHz −99 −96 50 kHz −92 −90 100 kHz −90 −88 1 kHz 87.7 87 10 kHz 87.5 87 50 kHz 87.2 87 100 kHz 87 87 87.6 87 10 kHz 87 86 50 kHz 86 85 100 kHz 85 84 1 kHz 110 106 10 kHz 100 97 50 kHz 95 92 100 kHz 94 90 3 3 1 kHz Signal to noise + distortion (SINAD) (see Note 1) Spurious free dynamic range (SFDR) (see Note 1) −3dB Small signal bandwidth dB dB dB dB MHz Voltage Reference Input Reference voltage at REFIN, Vref Reference resistance (see Note 2) Reference current drain fs = 750 kHz (1) Calculated on the first nine harmonics of the input frequency (2) Can vary ±20% 4 2.5 4.096 4.2 500 2.5 4.096 4.2 500 1 V kΩ 1 mA 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 SPECIFICATIONS (CONTINUED) TA = −40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 750 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital Input/Output Logic family Logic level CMOS VIH VIL IIH = 5 µA IIL = 5 µA VOH VOL IOH = 2 TTL loads IOL = 2 TTL loads +VBD−1 +VBD + 0.3 0.8 −0.3 V +VBD − 0.6 0.4 Straight Binary Data format Power Supply Requirements Power supply voltage +VBD Buffer supply 2.7 +VA Analog Supply 4.75 Supply current, 750-kHz sample rate (1) Power dissipation, 750-kHz sample rate (1) 3.3 5.25 V 5 5.25 26 28 mA V 130 140 mW 85 °C Temperature Range Operating free-air −40 (1) This includes only +VA current. +VBD current is typical 1 mA with 5 pF load capacitance on all output pins. 5 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 TIMING CHARACTERISTICS All specifications typical at −40°C to 85°C, +VA = +VBD = 5 V (see Notes 1, 2, and 3) PARAMETER MIN TYP MAX UNIT 1.13 µs tCONV tACQ Conversion time tHOLD tpd1 Sampling capacitor hold time 25 ns CONVST low to conversion started (BUSY high) 45 ns tpd2 tpd3 Propagation delay time, End of conversion to BUSY low 20 ns Propagation delay time, from start of conversion (internal state) to rising edge of BUSY 20 ns tw1 tsu1 Pulse duration, CONVST low 40 400 ns Setup time, CS low to CONVST low 20 tw2 Pulse duration, CONVST high 20 Acquisition time CONVST falling edge jitter tw3 tw4 th1 Pulse duration, BUSY signal low ns ns 10 40 ps µs Min(tACQ) Pulse duration, BUSY signal high Hold time, First data bus data transition (CS low for read cycle, or RD or BYTE input changes) after CONVST low µs 0.2 1.13 µs 400 ns td1 tsu2 Delay time, CS low to RD low tw5 ten Pulse duration, RD low time td2 td3 Delay time, data hold from RD high Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid 10 tw6 tw7 Pulse duration, RD high 20 ns 20 ns th2 Hold time, last CS rising edge or changes of RD or BYTE to CONVST falling edge 125 ns tpd4 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge Max(td5) ns Setup time, RD high to CS high 0 ns 0 ns 50 Enable time, RD low (or CS low for read cycle) to data valid Pulse duration, CS high time ns 20 5 ns ns 20 ns tsu3 th3 Setup time, BYTE transition to RD falling edge 10 ns Hold time, BYTE transition to RD falling edge 10 ns tdis Disable time, RD High (CS high for read cycle) to 3-stated data bus 20 ns td5 Delay time, BUSY low to MSB data valid 30 ns tsu5 Setup time, BYTE transition to next BYTE transition 50 tsu(AB) Setup time, from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST used to abort) or to the next falling edge of CS (when CS is used to abort). 65 700 ns tf(CONVST) Falling time, (CONVST falling edge) 10 30 ns ns tsu6 Setup time, CS falling edge to CONVST falling edge when RD = 0 125 ns (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2 except for CONVST. (2) See timing diagrams. (3) All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins. 6 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 TIMING CHARACTERISTICS All specifications typical at −40°C to 85°C, +VA = 5 V, +VBD = 3 V (see Notes 1, 2, and 3) PARAMETER MIN TYP MAX UNIT 1.13 µs tCONV tACQ Conversion time tHOLD tpd1 Sampling capacitor hold time 25 ns CONVST low to conversion started (BUSY high) 50 ns tpd2 tpd3 Propagation delay time, end of conversion to BUSY low 25 ns Propagation delay time, from start of conversion (internal state) to rising edge of BUSY 25 ns tw1 tsu1 Pulse duration, CONVST low 40 400 ns Setup time, CS low to CONVST low 20 tw2 Pulse duration, CONVST high 20 Acquisition time µs 0.2 CONVST falling edge jitter ns ns 10 ps µs tw3 tw4 Pulse duration, BUSY signal low Min(tACQ) th1 Hold time, first data bus transition (CS low for read cycle, or RD or BYTE input changes) after CONVST low td1 tsu2 Delay time, CS low to RD low tw5 ten Pulse duration, RD low td2 td3 Delay time, data hold from RD high 10 Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid 10 tw6 tw7 Pulse duration, RD high time 20 ns 20 ns th2 tpd4 Hold time, last CS rising edge or changes of RD, or BYTE to CONVST falling edge 125 ns Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge Max(td5) ns tsu3 th3 Setup time, BYTE transition to RD falling edge 10 ns Hold time, BYTE transition to RD falling edge 10 ns tdis Disable time, RD High (CS high for read cycle) to 3-stated data bus 30 ns td5 Delay time, BUSY low to MSB data valid delay time 40 ns tsu5 Setup time, BYTE transition to next BYTE transition 50 tsu(AB) Setup time, from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST used to abort) or to the next falling edge of CS (when CS is used to abort). 70 700 ns tf(CONVST) Falling time, (CONVST falling edge) 10 30 ns Pulse duration, BUSY signal high Setup time, RD high to CS high 40 µs 400 ns 0 ns 0 ns 50 Enable time, RD low (or CS low for read cycle) to data valid Pulse duration, CS high time 1.13 ns 30 ns ns 30 ns ns tsu6 Setup time, CS falling edge to CONVST falling edge when RD = 0 125 ns (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2 except for CONVST. (2) See timing diagrams. (3) All timing are measured with 10 pF equivalent loads on all data bits and BUSY pins. 7 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 PIN ASSIGNMENTS BUSY NC NC DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 BDGND PFB PACKAGE (TOP VIEW) 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 41 20 42 19 43 18 44 17 45 16 46 15 47 14 48 3 4 5 6 7 8 13 9 10 11 12 REFIN NC NC +VA AGND +IN −IN AGND +VA +VA 1 2 NC − No connection. 8 AGND AGND +VBD BDGND BYTE CONVST RD CS +VA AGND AGND +VA REFM REFM +VBD DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 AGND AGND +VA 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 TERMINAL FUNCTIONS NAME AGND BDGND NO. I/O 5, 8, 11, 12, 14, 15, 44, 45 − Analog ground DESCRIPTION 25, 38 − Digital ground for buffer supply BUSY 36 O Status output. High when a conversion is in progress. BYTE 39 I Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[15:8]. CONVST 40 I Convert start. The falling edge of this input ends the acquisition period and starts the hold period. CS 42 I Chip select. The falling edge of this input starts the acquisition period. 8-Bit Bus Data Bus BYTE = 0 16-Bit Bus BYTE = 1 BYTE = 0 DB15 16 O D15 (MSB) D7 D15 (MSB) DB14 17 O D14 D6 D14 DB13 18 O D13 D5 D13 DB12 19 O D12 D4 D12 DB11 20 O D11 D3 D11 DB10 21 O D10 D2 D10 DB9 22 O D9 D1 D9 DB8 23 O D8 D0 (LSB) D8 DB7 26 O D7 All ones D7 DB6 27 O D6 All ones D6 DB5 28 O D5 All ones D5 DB4 29 O D4 All ones D4 DB3 30 O D3 All ones D3 DB2 31 O D2 All ones D2 DB1 32 O D1 All ones D1 DB0 33 O D0 (LSB) All ones D0 (LSB) −IN 7 I Inverting input channel +IN 6 I Non inverting input channel NC 2, 3, 34, 35 − No connection REFIN 1 I Reference input REFM 47, 48 I Reference ground RD 41 I Synchronization pulse for the parallel output. When CS is low, this serves as the output enable and puts the previous conversion result on the bus. +VA 4, 9, 10, 13, 43, 46 − Analog power supplies, 5-V dc 24, 37 − Digital power supply for the buffer +VBD 9 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 TIMING DIAGRAMS tw2 tw1 CONVST tpd1 tpd2 tw4 tw3 BUSY tsu1 tw7 CS tpd3 CONVERT† tHOLD tCONV tCONV SAMPLING† (When CS Toggle) tACQ BYTE tsu(AB) tsu(AB) tsu5 th1 tsu5 tsu5 tsu5 tsu2 tpd4 th2 td1 RD tdis ten DB[15:8] Hi−Z Hi−Z D[15:8] DB[7:0] D[7:0] Hi−Z Hi−Z D[7:0] †Signal internal to device Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling 10 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 tw1 tw2 CONVST tpd1 tw4 tpd2 tw3 BUSY tw7 tsu6 tsu6 CS tpd3 CONVERT† tCONV tCONV tHOLD SAMPLING† (When CS Toggle) tACQ tsu(AB) tsu(AB) tsu5 BYTE tsu5 th1 tsu5 tsu5 tdis tsu2 tpd4 th2 ten RD = 0 ten ten DB[15:8] Hi−Z Previous D [15:8] tdis Hi−Z D[15:8] DB[7:0] Previous Hi−Z D [7:0] Hi−Z Hi−Z Previous D [15:8] Hi−Z Previous D [7:0] D[7:0] D[7:0] †Signal internal to device Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND 11 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 tw1 tw2 CONVST tpd1 tpd2 tw4 tw3 BUSY CS = 0 tpd3 CONVERT† tCONV tCONV tHOLD t(ACQ) SAMPLING† (When CS = 0) tsu(AB) tsu(AB) tsu5 BYTE tsu5 th1 tpd4 th2 RD tdis ten DB[15:8] Hi−Z Hi−Z D[15:8] DB[7:0] Hi−Z D[7:0] Hi−Z D[7:0] †Signal internal to device Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling 12 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 tw2 tw1 CONVST tpd1 tw4 tpd2 tw3 BUSY CS = 0 CONVERT† tCONV tCONV tpd3 tpd3 tHOLD tHOLD t(ACQ) SAMPLING† (When CS = 0) tsu(AB) tsu(AB) BYTE tsu5 tsu5 th1 th1 tdis tsu5 tsu5 RD = 0 td5 DB[15:8] Previous D[7:0] D[7:0] Next D[15:8] D[15:8] DB[7:0] Next D[7:0] D[7:0] †Signal internal to device Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto Read CS RD tsu4 BYTE ten tdis tdis ten DB[15:0] td3 Hi−Z Valid Hi−Z Valid Valid Hi−Z Figure 5. Detailed Timing for Read Cycles 13 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS(1) HISTOGRAM (DC CODE SPREAD) HALF SCALE 4096 CONVERSIONS 2000 1800 1600 +VA = 5 V, +VBD = 5 V, TA = 255C, fs = 750 KSPS 1400 Count 1200 1000 800 600 400 200 32766 32765 32764 32763 32762 32761 32760 32759 32758 32757 0 code Figure 6 GAIN ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs FREE-AIR TEMPERATURE 0.1 0.1 +VA = 5 V, +VBD = 5 V, fs = 750 KSPS, Vref = 4.096 V E G − Gain Error − %FS 0.06 0.02 0.00 −0.02 −0.04 0.04 0.02 0 −0.02 −0.04 −0.06 −0.06 −0.08 −0.08 −15 10 35 60 TA − Free-Air Temperature − °C Figure 7 14 0.06 0.04 −0.1 −40 +VA = 5 V, +VBD = 5 V, fS = 750 KSPS, Vref = 2.5 V 0.08 E G − Gain Error − %FS 0.08 85 −0.1 −40 −15 10 35 60 TA − Free-Air Temperature − °C Figure 8 85 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 OFFSET ERROR vs FREE-AIR TEMPERATURE OFFSET ERROR vs FREE-AIR TEMPERATURE 1 1 +VA = 5 V, +VBD = 5 V, fS = 750 KSPS, Vref = 4.096 V 0.8 0.6 0.4 EO − Offset Error − mV EO − Offset Error − mV 0.6 0.2 0.0 −0.2 −0.4 0.4 0.2 0 −0.2 −0.4 −0.6 −0.6 −0.8 −0.8 −1 −40 −15 10 35 60 TA − Free-Air Temperature − °C +VA = 5 V, +VBD = 5 V, fS = 750 KSPS, Vref = 2.5 V 0.8 −1 −40 85 Figure 9 INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 1 0.6 MAX INL − Integral Nonlinearity − LSBs DNL − Differential Nonlinearity − LSBs 85 Figure 10 DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 0.4 +VA = 5 V, +VBD = 5 V, fS = 750 KSPS, Vref = 4.096 V 0.2 0 −0.2 MIN −0.4 −0.6 −40 −15 10 35 60 TA − Free-Air Temperature − °C MAX 0.5 +VA = 5 V, +VBD = 5 V, fS = 750 KSPS, Vref = 4.096 V 0 −0.5 MIN −1 −1.5 −15 10 35 60 TA − Free-Air Temperature − °C Figure 11 85 −40 −15 10 35 60 TA − Free-Air Temperature − °C 85 Figure 12 15 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 INTEGRAL NONLINEARITY vs SAMPLE RATE DIFFERENTIAL NONLINEARITY vs SAMPLE RATE 0.5 DNL − Differential Nonlinearity − LSBs 0.8 INL − Integral Nonlinearity − LSBs MAX 0.6 0.4 +VA = 5 V, +VBD = 5 V, TA = 255C, Vref = 4.096 V 0.2 0 −0.2 −0.4 −0.6 MIN −0.8 −1 125 250 375 500 Sample Rate − KSPS 625 0.2 0.1 0 −0.1 −0.2 MIN −0.3 −0.4 Figure 13 250 375 500 Sample Rate − KSPS 625 750 Figure 14 GAIN ERROR vs SUPPLY VOLTAGE OFFSET ERROR vs SUPPLY VOLTAGE 0.1 0.14 TA = 255C, fS = 750 KSPS, Vref = 4.096 V TA = 255C, fS = 750 KSPS, Vref = 4.096 V 0.08 0.06 0.135 0.04 EO − Offset Error − mV E G − Gain Error − %FS +VA = 5 V, +VBD = 5 V, TA = 255C, Vref = 4.096 V 0.3 −0.5 125 750 MAX 0.4 0.02 0.0 −0.02 −0.04 0.13 0.125 −0.06 −0.08 −0.1 4.75 5 VDD − Supply Voltage − V Figure 15 16 5.25 0.12 4.75 5 VDD − Supply Voltage − V Figure 16 5.25 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 SUPPLY CURRENT vs SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs SUPPLY VOLTAGE 0.6 25.6 I DD − Supply Current − mA 25.4 25.2 DNL − Differential Nonlinearity − LSBs TA = 255C, fS = 750 KSPS, Vref = 4.096 V 25 24.8 24.6 24.4 24.2 24 23.8 23.6 4.75 5 VDD − Supply Voltage − V MAX 0.4 0.2 0 −0.2 MIN −0.4 −0.6 4.75 5.25 Figure 17 0.8 DNL − Differential Nonlinearity − LSBs INL − Integral Nonlinearity − LSBs MAX 0.4 TA = 255C, fS = 750 KSPS, Vref = 4.096 V 0.2 0 −0.2 −0.4 −0.6 MIN −1 −1.2 4.75 5.25 DIFFERENTIAL NONLINEARITY vs REFERENCE VOLTAGE 0.8 −0.8 5 VDD − Supply Voltage − V Figure 18 INTEGRAL NONLINEARITY vs SUPPLY VOLTAGE 0.6 TA = 255C, fS = 750 KSPS, Vref = 4.096 V 5 VDD − Supply Voltage − V Figure 19 5.25 0.6 MAX 0.4 +VBD = 5 V, +VA = 5 V, fS = 750 KSPS, Vref = 4.096 V 0.2 0 −0.2 −0.4 −0.6 2.5 MIN 2.84 3.18 3.52 3.86 Vref − Reference Voltage − V 4.2 Figure 20 17 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 OFFSET ERROR vs REFERENCE VOLTAGE 0.8 0.5 0.6 0.4 MAX 0.4 0.3 +VBD = 5 V, +VA = 5 V, TA = 255C, fS = 750 KSPS 0.2 0 EO − Offset Error − mV INL − Integral Nonlinearity − LSBs INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE −0.2 −0.4 −0.6 MIN 0.2 0.1 0 −0.1 −0.2 −0.8 −0.3 −1 −0.4 −1.2 2.5 2.84 3.18 3.52 3.86 Vref − Reference Voltage − V +VBD = 5 V, +VA = 5 V, TA = 255C, fS = 750 KSPS −0.5 2.5 4.2 Figure 21 TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE −80 +VA = 5 V, +VBD = 5 V, fi = 99 kHz, fS = 750 KSPS, vI = 4 Vpp, Vref = 4.096 V 89 THD − Total Harmonic Distortion − dB SNR − Signal-to-Noise Ratio − dB 90 88 87 86 −15 10 35 TA − Temperature − 5C Figure 23 18 4.2 Figure 22 SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE 85 −40 2.84 3.18 3.52 3.86 Vref − Reference Voltage − V 60 85 −85 −90 −95 −100 −105 +VA = 5 V, +VBD = 5 V, fi = 99 kHz, fS = 750 KSPS, vI = 4 Vpp, Vref = 4.096 V −110 −115 −120 −40 −15 10 35 60 TA − Free-Air Temperature − °C Figure 24 85 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 90 110 +VA = 5 V, +VBD = 5 V, fi = 99 kHz, fS = 750 KSPS, VI = 4 Vpp, Vref = 4.096 V 105 100 SINAD − Signal-to-Noise and Distortion − dB SFDR − Spurious Free Dynamic Range − dB SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE 95 90 85 80 75 −15 10 35 60 88 87 86 85 84 83 82 81 80 −40 70 −40 +VA = 5 V, +VBD = 5 V, fi = 99 kHz, fS = 750 KSPS, VI = 4 Vpp, Vref = 4.096 V 89 85 TA − Free-Air Temperature − °C Figure 25 SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 14.6 14.4 90 +VA = 5 V, +VBD = 5 V, fi = 99 kHz, fS = 750 KSPS, VI = 4 Vpp, Vref = 4.096 V SNR − Signal-to-Noise Ratio − dB ENOB − Effective Number of Bits − Bits 14.8 85 Figure 26 EFFECTIVE NUMBER OF BITS vs FREE-AIR TEMPERATURE 15 −15 10 35 60 TA − Free-Air Temperature − °C 14.2 14 13.8 13.6 13.4 +VA = 5 V, +VBD = 5 V, TA = 255C, fS = 750 KSPS, VI = 4 Vpp, Vref = 4.096 V 89 88 87 86 13.2 13 −40 85 −15 10 35 60 TA − Free-Air Temperature − °C Figure 27 85 1 10 100 fi − Input Frequency − kHz Figure 28 19 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY 90 +VA = 5 V, +VBD = 5 V, fS = 750 KSPS, VI = 4 Vpp, Vref = 4.096 V −85 SINAD − Signal-to-Noise and Distortion − dB THD − Total Harmonic Distortion − dB −80 −90 −95 −100 −105 −110 +VA = 5 V, +VBD = 5 V, fS = 750 KSPS, VI = 4 Vpp, Vref = 4.096 V 89 88 87 86 85 84 83 82 81 80 1 10 fi − Input Frequency − kHz 100 1 Figure 29 SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY 120 15 +VA = 5 V, +VBD = 5 V, fS = 750 KSPS, VI = 4 Vpp, Vref = 4.096 V 14.8 14.6 14.4 SFDR − Spurious Free Dynamic Range − dB ENOB − Effective Number of Bits − Bits 100 Figure 30 EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 14.2 14 13.8 13.6 13.4 13.2 +VA = 5 V, +VBD = 5 V, fS = 750 KSPS, VI = 4 Vpp, Vref = 4.096 V 115 110 105 100 95 90 85 80 13 1 10 fi − Input Frequency − kHz Figure 31 20 10 fi − Input Frequency − kHz 100 1 10 fi − Input Frequency − kHz Figure 32 100 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 +VA SUPPLY CURRENT vs SAMPLE RATE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 26 25.8 +VA = 5.25 V, +VBD = 5.25 V, fS = 750 KSPS, Vref = 4.096 V +VA − Supply Current − mA 25.6 25.5 25.4 25.3 25.2 25 +VA = 5.25 V, +VBD = 5.25 V, TA = 255C, Vref = 4.096 V 24.5 24 23.5 23 22.5 22 25.1 −40 −15 10 35 60 85 21.5 125 250 TA − Free-Air Temperature − °C Figure 33 375 500 Sample Rate − KSPS 625 750 Figure 34 INTEGRAL NONLINEARITY 3 +VA = 5 V, +VBD = 5 V, TA = 255C, fS = 750 KSPS, Vref = 4.096 V 2 INL − LSBs I DD − Supply Current − mA 25.7 25.5 1 0 −1 −2 −3 0 16384 32768 Code 49152 65536 Figure 35 21 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 DIFFERENTIAL NONLINEARITY 3 +VA = 5 V, +VBD = 5 V, TA = 255C, fS = 750 KSPS, Vref = 4.096 V DNL − LSBs 2 1 0 −1 −2 −3 0 16384 32768 49152 65536 Code Figure 36 FFT 0 −20 +VA = 5 V, +VBD = 3 V, TA = 255C, fS = 750 KSPS, fi = 99 kHz, VI = 4 Vpp, 16384 Points,Vref = 4.096 V Amplitude − dB −40 −60 −80 −100 −120 −140 −160 −180 0 75000 150000 225000 fi − Input Frequency − Hz Figure 37 22 300000 375000 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 APPLICATION INFORMATION MICROCONTROLLER INTERFACING ADS8371 to 8-Bit Microcontroller Interface Figure 38 shows a parallel interface between the ADS8371 and a typical microcontroller using the 8-bit data bus. The BUSY signal is used as a falling-edge interrupt to the microcontroller. Analog 5 V REF 3040 0.1 µF OUT AGND 10 µF Ext Ref Input 100 Ω 0.1 µF Micro Controller −IN +IN +VA REFIN REFM AGND Analog Input Digital 3 V AD8371 GPIO GPIO GPIO RD AD[7:0] 1000 Ω CS BYTE CONVST RD DB[15:8] 0.1 µF BDGND BDGND +VBD Figure 38. ADS8371 Application Circuitry 23 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 PRINCIPLES OF OPERATION The ADS8371 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 38 for the application circuit for the ADS8371. The conversion clock is generated internally. The conversion time of 1.13 µs is capable of sustaining a 750-kHz throughput. The analog input is provided to two input pins: +IN and −IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. REFERENCE The ADS8371 can operate with an external reference with a range from 2.5 V to 4.2 V. The reference voltage on the input pin 1 (REFIN) of the converter is internally buffered. A clean, low noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF3040 can be used to drive this pin. A 0.1-uF decoupling capacitor is required between pin 1 and pin 48 of the converter. This capacitor should be placed as close as possible to the pins of the device. Designers should strive to minimize the routing length of the traces that connect the terminals of the capacitor to the pins of the converter. An RC network can also be used to filter the reference voltage. A 100-Ω series resistor and a 0.1-uF capacitor, which can also serve as the decoupling capacitor, can be used to filter the reference voltage. ANALOG INPUT When the converter enters the hold mode, the voltage difference between the +IN and −IN inputs is captured on the internal capacitor array. The voltage on the −IN input is limited between –0.2 V and 0.2 V, allowing the input to reject small signals which are common to both the +IN and −IN inputs. The +IN input has a range of –0.2 V to Vref + 0.2 V. The input span (+IN − (−IN)) is limited to 0 V to Vref. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8371 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (45 pF) to an 16-bit settling level within the acquisition time (200 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN and −IN inputs and the span (+IN − (−IN)) should be within the limits specified. Outside of these ranges, the converter’s linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output impedance of the sources driving the +IN and −IN inputs are matched. If this is not observed, the two inputs could have different setting times. This may result in offset error, gain error, and linearity error which changes with temperature and input voltage. The analog input to the converter needs to be driven with a low noise, high-speed op-amp like the THS4031. An RC filter is recommended at the input pins to low-pass filter the noise from the source. A series resistor of 15 Ω and a decoupling capacitor of 200 pF is recommended. The input to the converter is a unipolar input voltage in the range 0 V to Vref. The THS4031 can be used in the source follower configuration to drive the converter. 24 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 ADS8371 + _ Unipolar Input THS4031 _ + 15 Ω +IN 200 pF −IN 50 Ω Figure 39. Unipolar Input to Converter In systems where the input is bipolar, the THS4031 can be used in the inverting configuration with an additional DC bias applied to its + input so as to keep the input to the ADS8371 within its rated operating voltage range. This configuration is also recommended when the ADS8371 is used in signal processing applications where good SNR and THD performance is required. The DC bias can be derived from the REF3020 or the REF3040 reference voltage ICs. The input configuration shown below is capable of delivering better than 87-dB SNR and –90-db THD at an input frequency of 100 kHz. In case bandpass filters are used to filter the input, care should be taken to ensure that the signal swing at the input of the bandpass filter is small so as to keep the distortion introduced by the filter minimal. In such cases, the gain of the circuit shown in Figure 40 can be increased to keep the input to the ADS8371 large to keep the SNR of the system high. Note that the gain of the system from the + input to the output of the THS4031 in such a configuration is a function of the gain of the AC signal. A resistor divider can be used to scale the output of the REF3020 or REF3040 to reduce the voltage at the DC input to THS4031 to keep the voltage at the input of the converter within its rated operating range. ADS8371 + _ Vdc Vac 360 Ω THS4031 100 Ω _ + +IN 33 nF −IN 360 Ω Figure 40. Bipolar Input to Converter DIGITAL INTERFACE Timing And Control See the timing diagrams in the specifications section for detailed information on timing signals and their requirements. The ADS8371 uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter. No external clock input is required. Conversions are initiated by bringing the CONVST pin low for a minimum of 40 ns (after the 40 ns minimum requirement has been met, the CONVST pin can be brought high), while CS is low. The BUSY output is brought high immediately following CONVST going low. BUSY stays high throughout the conversion process and returns low when the conversion has ended. Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when BUSY is low. Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus with the conversion. 25 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 Digital Inputs The converter switches from sample to hold mode at the falling edge of the CONVST input pin. A clean and low jitter falling edge is important to the performance of the converter. A sharp falling transition on this pin can affect the voltage that is acquired by the converter. A falling transition time in the range of 10 ns to 30 ns is required to achieve the rated performance of the converter. A resistor of approximately 1000 Ω (10% tolerance) can be placed in series with the CONVST input pin to satisfy this requirement. The other digital inputs to the ADS8371 do not require any resistors in series with them. However, certain precautions are necessary to ensure that transitions on these inputs do not affect converter performance. It is recommended that all activity on the input pins happen during the first 400 ns of the conversion period. This allows the error correction circuits inside the device to correct for any errors that these activities cause on the converter output. For example, when the converter is operated with CS and RD tied to ground, the signal CONVST can be brought low to initiate a conversion and brought high after a duration not exceeding 400 ns. Figure 41 shows the recommended timing for the CONVST input with RD and CS tied low. tacq tconv 125 ns(1) 400 ns 730 ns(1) tw1 125 ns RD BUSY (1)Quiet Zone (No bus activity) Figure 42. Bus Activity Split to Avoid Quiet Zone If the RD pin is brought high to three-state the data buses, the three-stating operation should occur 125 ns before the end of the acquisition phase. Figure 43 shows the recommended timing for using the ADS8381 in this mode of operation. The same principle applies to other bus activities such as BYTE. tacq tconv 125 ns(1) 730 ns(1) 400 ns tw1 < 400 ns CONVST CS = 0 RD th2 > 125 ns BUSY (1)Quiet Zone (No bus activity) Figure 43. Read Timing if the Bus Needs to be Three-Stated 27 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 Reading Data The ADS8371 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when CS and RD are both low. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used for multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher byte of the bus. Refer to Table 1 for ideal output codes. Table 1. Ideal Input Voltages and Output Codes DESCRIPTION Full scale range Least significant bit (LSB) +Full scale Midscale Midscale – 1 LSB Zero ANALOG VALUE DIGITAL OUTPUT STRAIGHT BINARY (+Vref) (+Vref)/65536 BINARY CODE HEX CODE (+Vref) – 1 LSB (+Vref)/2 1111 1111 1111 1111 FFFF 1000 0000 0000 0000 8000 (+Vref)/2 – 1 LSB 0V 0111 1111 1111 1111 7FFF 0000 0000 0000 0000 0000 The output data is a full 16-bit word (D15−D0) on DB15–DB0 pins (MSB−LSB) if BYTE is low. The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15−DB8. In this case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on pins DB15−DB8, then bringing BYTE high. When BYTE is high, the low bits (D7−D0) appear on pins DB15−D8. These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity. Table 2. Conversion Data Readout DATA READ OUT BYTE DB15−DB8 PINS DB7−DB0 PINS High D7−D0 All one’s Low D15−D8 D7−D0 RESET The device can be reset through the use of the combination fo CS and CONVST. Since the BUSY signal is held at high during the conversion, either one of these conditions triggers an internal self-clear reset to the converter. D Issue a CONVST when CS is low and internal CONVERT state is high. The falling edge of CONVST starts a reset. D Issue a CS (select the device) while internal CONVERT state is high. The falling edge of CS causes a reset. Once the device is reset, all output latches are cleared (set to zeroes) and the BUSY signal is brought low. A new sampling period is started at the falling edge of the BUSY signal immediately after the instant of the internal reset. INITIALIZATION At first power on there are three read cycles required (RD must be toggled three times). If conversion cycle is attempted before these initialization read cycles, the first three conversion cycles will not produce valid results. This is used to load factory trimming data for a specific device to assure high accuracy of the converter. Because of this requirement, the RD pin cannot be tied permanently to BDGND. System designers can still achieve the AUTO READ function if the power-on requirement is satisfied. 28 
 www.ti.com SLAS390B − JUNE 2003 − REVISED FEBRUARY 2005 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8371 circuitry. As the ADS8371 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the ADS8371 draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor is recommended from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the same ground plane under the device. The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8371 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 3 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply, removing the high frequency noise. Table 3. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE SUPPLY PINS CONVERTER ANALOG SIDE CONVERTER DIGITAL SIDE Pin pairs that require shortest path to decoupling capacitors (4,5), (8,9), (10,11), (13,15), (43,44), (45,46) (24,25) Pins that require no decoupling 12, 14 37, 38 29 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) ADS8371IBPFBT ACTIVE TQFP PFB 48 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS8371I B Samples ADS8371IPFBT ACTIVE TQFP PFB 48 250 RoHS & Green Call TI Level-2-260C-1 YEAR -40 to 85 ADS8371I Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of