AM6442, AM6441, AM6422, AM6421, AM6412, AM6411
SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
AM64x Sitara™ Processors
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1 Features
Processor cores:
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1× Dual 64-bit Arm® Cortex®-A53 microprocessor
subsystem at up to 1.0 GHz
– Dual-core Cortex-A53 cluster with 256KB L2
shared cache with SECDED ECC
– Each A53 Core has 32KB L1 DCache with
SECDED ECC and 32KB L1 ICache with Parity
protection
Up to 2× Dual-core Arm® Cortex®-R5F MCU
subsystems at up to 800 MHz, integrated for realtime processing
– Dual-core Arm® Cortex®-R5F supports dualcore and single-core modes
– 32KB ICache, 32KB DCache and 64KB TCM
per each R5F core for a total of 256KB TCM
with SECDED ECC on all memories
1× Single-core Arm® Cortex®-M4F MCU at up to
400 MHz
– 256KB SRAM with SECDED ECC
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Memory subsystem:
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Industrial subsystem:
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2× gigabit Industrial Communication Subsystems
(PRU_ICSSG)
– Supports Profinet IRT, Profinet RT, EtherNet/IP,
EtherCAT, Time-Sensitive Networking (TSN),
and more
– Backward compatibility with 10/100Mb
PRU_ICSS
– Each PRU_ICSSG contains:
• 2× Ethernet ports
– MII (10/100)
– RGMII (10/100/1000)
• 6 PRU RISC cores per PRU_ICSSG each
core having:
– Instruction RAM with ECC
– Broadside RAM
– Multiplier with optional accumulator
(MAC)
– CRC16/32 hardware accelerator
– Byte swap for Big/Little Endian
conversion
– SUM32 hardware accelerator for UDP
checksum
– Task Manager for preemption support
• Three Data RAMs with ECC
• 8 banks of 30 × 32-bit register scratchpad
memory
• Interrupt controller and task manager
Two 64-bit Industrial Ethernet Peripherals
(IEPs) for time stamping and other time
synchronization functions
18× Sigma-Delta filters
– Short circuit logic
– Over-current logic
6× Multi-protocol position encoder interfaces
One Enhanced Capture Module (ECAP)
16550-compatible UART with a dedicated
192-MHz clock to support 12-Mbps
PROFIBUS
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Up to 2MB of On-chip RAM (OCSRAM) with
SECDED ECC:
– Can be divided into smaller banks in
increments of 256KB for as many as 8 separate
memory banks
– Each memory bank can be allocated to a single
core to facilitate software task partitioning
DDR Subsystem (DDRSS)
– Supports LPDDR4, DDR4 memory types
– 16-Bit data bus with inline ECC
– Supports speeds up to 1600 MT/s
1× General-Purpose Memory Controller (GPMC)
– 16-Bit parallel bus with 133 MHz clock or
– 32-Bit parallel bus with 100 MHz clock
– Error Location Module (ELM) support
System on Chip (SoC) Services:
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Device Management Security Controller (DMSC-L)
– Centralized SoC system controller
– Manages system services including initial boot,
security, and clock/reset/power management
– Communication with various processing units
over message manager
– Simplified interface for optimizing unused
peripherals
Data Movement Subsystem (DMSS)
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Block Copy DMA (BCDMA)
Packet DMA (PKTDMA)
Secure Proxy (SEC_PROXY)
Ring Accelerator (RINGACC)
Security:
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Secure boot supported
– Hardware-enforced Root-of-Trust (RoT)
– Support to switch RoT via backup key
– Support for takeover protection, IP protection,
and anti-roll back protection
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AM6442, AM6441, AM6422, AM6421, AM6412, AM6411
www.ti.com
SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
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Trusted Execution Environment (TEE) supported
– Arm TrustZone® based TEE
– Secure watchdog/timer/IPC
– Extensive firewall support for isolation
– Secure storage support
– Replay Protected Memory Block (RPMB)
support
Security co-processor (DMSC-L) for key and
security management, with dedicated device level
interconnect for security
Cryptographic acceleration supported
– Session-aware cryptographic engine with ability
to auto-switch key-material based on incoming
data stream
• Supports cryptographic cores
– AES – 128-/192-/256-Bit key sizes
– SHA2 – 224-/256-/384-/512-Bit key sizes
– DRBG with true random number generator
– PKA (Public Key Accelerator) to Assist in
RSA/ECC processing for secure boot
Debugging security
– Secure software controlled debug access
– Security aware debugging
High-speed interfaces:
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General connectivity:
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Control interfaces:
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1× Integrated Ethernet switch (CPSW3G)
supporting:
– Up to 2 Ethernet ports
• RMII (10/100)
• RGMII (10/100/1000)
– IEEE 1588 (2008 Annex D, Annex E, Annex F)
with 802.1AS PTP
– Clause 45 MDIO PHY management
– Energy efficient Ethernet (802.3az)
1× PCI-Express® Gen2 controller (PCIE)
– Supports Gen2 operation
– Supports Single Lane operation
1× USB 3.1 Dual-Role Device (DRD) Subsystem
(USBSS)
– Port configurable as USB host,
USB device, or
USB Dual-Role device
– USB device: High-speed (480 Mbps), and
Full-speed (12Mbps)
– USB host: SuperSpeed Gen 1 (5 Gbps),
High-speed (480 Mbps),
Full-speed (12 Mbps), and
Low-speed (1.5 Mbps)
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6× Inter-Integrated Circuit (I2C) ports
9× configurable Universal Asynchronous Receive/
Transmit (UART) modules
1× Flash Subsystem (FSS) that can be configured
as Octal SPI (OSPI) flash interfaces or one Quad
SPI (QSPI)
1× 12-Bit Analog-to-Digital Converters (ADC)
– Up to 4 MSPS
– 8× multiplexed analog inputs
7× Multichannel Serial Peripheral Interfaces
(MCSPI) controllers
6× Fast Serial Interface Receiver (FSI_RX) cores
2× Fast Serial Interface Transmitter (FSI_TX)
cores
3× General-Purpose I/O (GPIO) modules
9x Enhanced Pulse-Width Modulator (EPWM)
modules
3× Enhanced Capture (ECAP) modules
3× Enhanced Quadrature Encoder Pulse (EQEP)
modules
2× Modular Controller Area Network (MCAN)
modules with or without full CAN-FD support
Media and data storage:
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2× Multi-Media Card/Secure Digital (MMC/SD/
SDIO) interfaces
– One 4-bit for SD/SDIO;
– One 8-bit for eMMC
– Integrated analog switch for voltage switching
between 3.3V to 1.8V for high-speed cards
Power management:
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Simplified power sequence
Integrated SDIO LDO for handling automatic
voltage transition for SD interface
Integrated voltage supervisor for safety monitoring
of over-under voltage conditions
Integrated power supply glitch detector for
detecting fast supply transients
Copyright © 2023 Texas Instruments Incorporated
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Functional Safety:
• Functional Safety-Compliant targeted
– Developed for functional safety applications
– Documentation will be available to aid IEC
61508 functional safety system design
– Systematic capability up to SIL 3 targeted
– Hardware integrity up to SIL 2 targeted
– Safety-related certification
• IEC 61508 certification planned
• Functional Safety Features
– ECC or parity on calculation-critical memories
– ECC and parity on select internal bus
interconnect
– Built-In Self-Test (BIST) for CPU and on-chip
RAM
– Error Signaling Module (ESM) with error pin
– Runtime safety diagnostics, voltage,
temperature, and clock monitoring, windowed
watchdog timers, CRC engine for memory
integrity checks
– Dedicated MCU domain memory, interfaces,
and M4F core capable of being isolated from
the larger SoC with Freedom From Interference
(FFI) features
• Separate interconnect
• Firewalls and timeout gaskets
• Dedicated PLL
• Dedicated I/O supply
• Separate reset
Copyright © 2023 Texas Instruments Incorporated
SoC architecture:
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Supports primary boot from UART, I2C, OSPI/
QSPI Flash, SPI Flash, parallel NOR Flash,
parallel NAND Flash, SD, eMMC, USB, PCIe, and
Ethernet interfaces
16-nm FinFET technology
17.2 mm × 17.2 mm, 0.8-mm pitch, 441-pin BGA
package
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
2 Applications
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Programmable Logic Controller (PLC)
Motor Drives
Remote I/O
Industrial Robots
Condition-Monitoring Gateway
3 Description
AM64x is an extension of the Sitara™ Industrial-grade family of heterogeneous Arm® processors. AM64x is built
for industrial applications, such as motor drives and Programmable Logic Controllers (PLCs), which require a
unique combination of real-time processing and communications with applications processing. AM64x combines
two instances of the Sitara device's gigabit TSN-enabled PRU-ICSSG with up to two Arm® Cortex®-A53 cores,
up to four Cortex-R5F MCUs, and a Cortex-M4F MCU.
AM64x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled
Memory banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for
rapid data movement in and out of the SoC. This deterministic architecture allows for AM64x to handle the tight
control loops found in servo drives while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters,
and absolute encoder interfaces help enable a number of different architectures found in these systems.
The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Realtime (RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term
Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux
world with the real-time world by enabling isolation between Linux applications and real-time streams through
configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and
the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently.
The AM64x provides flexible industrial communications capability including full protocol stacks for EtherCAT
SubDevice, PROFINET device, EtherNet/IP adapter, and IO-Link Master. The PRU-ICSSG further provides
capability for gigabit and TSN based protocols. In addition, the PRU-ICSSG also enables additional interfaces in
the SoC including sigma delta decimation filters and absolute encoder interfaces.
Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals
which can all be isolated from the rest of the SoC. AM64x also supports secure boot.
Package Information
(1)
(2)
4
PART NUMBER
PACKAGE(1)
PACKAGE SIZE(2)
AM6442
ALV (FCBGA, 441)
17.2 mm × 17.2 mm
AM6441
ALV (FCBGA, 441)
17.2 mm × 17.2 mm
AM6422
ALV (FCBGA, 441)
17.2 mm × 17.2 mm
AM6421
ALV (FCBGA, 441)
17.2 mm × 17.2 mm
AM6412
ALV (FCBGA, 441)
17.2 mm × 17.2 mm
AM6411
ALV (FCBGA, 441)
17.2 mm × 17.2 mm
For more information, see Mechanical, Packaging, and Orderable Information.
The package size (length × width) is a nominal value and includes pins, where applicable.
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Product Folder Links: AM6442 AM6441 AM6422 AM6421 AM6412 AM6411
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
3.1 Functional Block Diagram
Figure 3-1 is functional block diagram for the device.
Note
To understand what device features are currently supported by TI Software Development Kits
(SDKs), search for the AM64x Software Build Sheet located in the Downloads tab option provided
at Processor-SDK-AM64x.
AM64x
Application cores
® ®
2x
Arm
Arm
®
®
Cortex -A53
-A53
Cortex
Real-time cores
®
Arm
®
Cortex -A53
®
®
Arm
®
Cortex -R5F
256KB L2 with ECC
Arm
®
Cortex -R5F
Isolated core
®
Arm
®
Cortex -R5F
128KB TCM
®
Arm
®
Cortex -R5F
128KB TCM
(A)
®
Arm
®
Cortex -M4F
256KB SRAM
System Memory
2 MB SRAM with ECC
2x MMCSD
DDR4/LPDDR4 with inline ECC
Security
SHA
Secure
Boot
System Services
PKA
DRBG
12x GP Timers
MD5
3DES
4x WWDT
AES
Industrial Connectivity
Sync
Manager
Isolated Connectivity
General Connectivity
(A)
(for use with Cortex-M4F)
PRU-ICSS(Gb)
2x GMAC
Encoder
with 9x ∑∆
PRU-ICSS(Gb)
2x GMAC
Encoder
with 9x ∑∆
GPMC / ELM
GPIO
8x FSI
5x MCSPI
9x EPWM
4x I2C
3x ECAP
7x UART
3x EQEP
OSPI or QSPI
2x CAN-FD
1x ADC
PCIe(C)
1x Single lane
Gen 2
3-port Gb
Ethernet(B)
1x USB 3.1 DRD(C)
GPIO
2x MCSPI
2x I2C
2x UART
intro_001
A.
B.
C.
Isolation of peripherals and M4F core is an optional feature.
One port is internally connected only; not connected to any pins.
USB SuperSpeed and PCIe share a common SerDes PHY. Therefore, USB will be limited to non-SuperSpeed modes when using the
SerDes PHY for PCIe.
Figure 3-1. Functional Block Diagram
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 4
3 Description.......................................................................4
3.1 Functional Block Diagram........................................... 5
4 Revision History.............................................................. 7
5 Device Comparison....................................................... 10
5.1 Related Products...................................................... 12
6 Terminal Configuration and Functions........................13
6.1 Pin Diagrams............................................................ 13
6.2 Pin Attributes.............................................................14
6.3 Signal Descriptions................................................... 59
6.4 Pin Connectivity Requirements.................................94
7 Specifications................................................................ 99
7.1 Absolute Maximum Ratings...................................... 99
7.2 ESD Ratings........................................................... 101
7.3 Power-On Hours (POH).......................................... 101
7.4 Recommended Operating Conditions.....................102
7.5 Operating Performance Points................................103
7.6 Power Consumption Summary............................... 103
7.7 Electrical Characteristics.........................................104
7.8 VPP Specifications for One-Time Programmable
(OTP) eFuses............................................................ 110
7.9 Thermal Resistance Characteristics........................111
6
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7.10 Timing and Switching Characteristics................... 112
8 Detailed Description....................................................232
8.1 Overview................................................................. 232
8.2 Processor Subsystems........................................... 233
8.3 Accelerators and Coprocessors..............................235
8.4 Other Subsystems.................................................. 235
9 Applications, Implementation, and Layout............... 243
9.1 Device Connection and Layout Fundamentals....... 243
9.2 Peripheral- and Interface-Specific Design
Information................................................................ 244
9.3 Clock Routing Guidelines........................................251
10 Device and Documentation Support........................252
10.1 Device Nomenclature............................................252
10.2 Tools and Software............................................... 255
10.3 Documentation Support........................................ 255
10.4 Support Resources............................................... 255
10.5 Trademarks........................................................... 255
10.6 Electrostatic Discharge Caution............................256
10.7 Glossary................................................................256
11 Mechanical, Packaging, and Orderable
Information.................................................................. 257
11.1 Packaging Information.......................................... 257
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
4 Revision History
Changes from September 22, 2022 to October 31, 2023 (from Revision E (SEPTEMBER 2022)
to Revision F (OCTOBER 2023))
Page
• (Features): Updated the Security features to clarify what is supported..............................................................1
• (Package Information): Updated the table to match the new content standard..................................................4
• (Functional Block Diagram): Updated URL for Software Build Sheet.................................................................5
• (Device Comparison): Updated URL for Software Build Sheet........................................................................ 10
• (Device Comparison): Corrected the name of the JTAG User ID register........................................................ 10
• (Device Comparison): Defined the R5F cores enabled in each device and changed the R5F TCM memory
size from "256KB" to "4 x 64KB" in the 2 x Dual Core devices, and "2 x 128KB" in the 2 x Single Core
devices..............................................................................................................................................................10
• (Device Comparison): Added Functional Safety Optional for AM6422.............................................................10
• (Device Comparison): Changed General-Purpose Memory Controller (GPMC) address range from 1GB to
128MB.............................................................................................................................................................. 10
• (GPMC0 Signal Descriptions): Moved the GPMC0_FCLK_MUX signal from System Signal Descriptions to
GPMC0 Signal Descriptions............................................................................................................................. 59
• (System Signal Descriptions): Moved the GPMC0_FCLK_MUX signal from System Signal Descriptions to
GPMC0 Signal Descriptions............................................................................................................................. 59
• (Pin Connectivity Requirements): Updated the second paragraph of the note following the Connectivity
Requirements table. The update clarifies the operation of configurable device IOs and includes precautions
that must be taken to prevent floating signals from damaging device input buffers......................................... 94
• (Specifications): Remove note that says specifications are preliminary .......................................................... 99
• (Power-On Hours): Updated the table to match the new content standard....................................................101
• (Recommended Operating Conditions): Added the Automotive temperature range...................................... 102
• (I2C OD FS Electrical Characteristics): Changed the IOL minimum value from 20 to 10 for both 1.8 V and 3.3
V modes..........................................................................................................................................................104
• (DDR Electrical Characteristics): Added references to the respective JEDEC standards..............................109
• (System Timing): Removed the Timing Conditions table from this section and added separate Timing
Conditions tables to each of the Reset Timing, Safety Signal Timing, and Clock Timing sections................. 118
• (Reset Timing): Added Timing Conditions table to define conditions specific to reset inputs and outputs..... 118
• (MCU_RESETSTATz, and RESETSTATz Switching Characteristics): Changed the minimum value of
parameter RST8 from "4040*S" to "966*S" and the minimum value of parameter RST9 from "301200" to
"4040*S"..........................................................................................................................................................118
• (MCU_RESETSTATz, and RESETSTATz Switching Characteristics): Changed the minimum value of
parameter RST13 from "0" to "960"................................................................................................................ 118
• (RESETSTATz Switching Characteristics): Changed the minimum value of parameter RST16 from "T" to
"900*T", the minimum value of parameter RST17 from "W" to "4040*S", and replaced the contents of table
note 2.............................................................................................................................................................. 118
• (PORz_OUT Switching Characteristics): Changed the minimum value of parameter RST26 from "0" to
"1840"..............................................................................................................................................................118
• (Safety Signal Timing): Added Timing Conditions table to define conditions specific to
MCU_SAFETY_ERRORn output....................................................................................................................123
• (MCU_ERRORn Switching Characteristics): Changed "RST22" to "SFTY3" in table note 5......................... 123
• (Clock Timing): Added Timing Conditions table to define conditions specific to clock inputs and outputs..... 124
• (Clock Timing Requirements): Updated the Timing Requirements figure with a single generic waveform and
updated the parameter numbers in the Timing Requirements table to reference the generic clock waveform....
........................................................................................................................................................................124
• (Clock Switching Characteristics): Updated the Switching Characteristics figure with a single generic
waveform and updated the parameter numbers in the Switching Characteristics table to reference the generic
clock waveform............................................................................................................................................... 124
• (MCU_OSC0 Crystal Implementation): Changing the crystal oscillator circuit diagram back to the original
version used in previous revisions of this document...................................................................................... 127
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
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(CPSW3G MDIO Timing): Included PCB Connectivity Requirements in the Timing Conditions table, changed
the minimum setup time value (parameter MDIO1) from "90" to "45", and changed the minimum and
maximum output delay time values (parameter MDIO7) from "-150" and "150" to "-10" and "10"
respectively.....................................................................................................................................................133
(GPMC0 IOSETs): Removed GPMC0_CLKLB since there is no pin with this name .....................................171
(MCSPI Switching Characteristics - Controller Mode): Replaced previous table notes 2 and 3 with new table
notes 2, 3, 4, and 5.........................................................................................................................................176
(MMC0 Timing Requirements – Legacy SDR Mode): Changed the minimum values for LSDR1 and LSDR3
from 9.69 to 1.56, and the minimum values for LSDR2 and LSDR4 from 27.97 to 5.44................................183
(MMC0 Switching Characteristics – Legacy SDR Mode): Changed the minimum values for LSDR8 and
LSDR9 from -16.1 to -2.3, and the maximum values for HSSDR8 and HSSDR9 from 16.1 to 2.9................183
(MMC0 Timing Requirements – High Speed SDR Mode): Changed the minimum values for HSSDR1 and
HSSDR3 from 2.99 to 2.55.............................................................................................................................184
(MMC0 Switching Characteristics – High Speed SDR Mode): Changed the minimum values for HSSDR8 and
HSSDR9 from -6.35 to -2.3, and the maximum values for HSSDR8 and HSSDR9 from 6.35 to 2.9.............184
(MMC0 Timing Requirements – High Speed DDR Mode): Changed the minimum values for HSDDR1 from
3.88 to 1.62, and the minimum values for HSDDR2 from 2.67 to 2.52.......................................................... 185
(MMC0 Switching Characteristics – High Speed DDR Mode): Changed the maximum value for HSDDR8 from
16.19 to 7.65...................................................................................................................................................185
(MMC1 DLL Delay Mapping for All Timing Modes): Changed the value of OTAPDLYENA from 0x0 to 0x1 for
Default Speed and High Speed modes. Also changed UHS-I DR50 to UHS-I DDR50 to correct a
typographical error in the mode name............................................................................................................187
(Timing Requirements for MMC1 – Default Speed Mode): Changed the minimum values for DS1 and DS3
from 2.55 to 2.15, and the minimum values for DS2 and DS2 from 19.67 to 1.67.........................................189
(Switching Characteristics for MMC1 – Default Speed Mode): Changed the minimum values for DS8 and DS9
from -14.1 to -1.8, and the maximum values for DS8 and DS9 from 14.1 to 1.8........................................... 189
(Timing Requirements for MMC1 – High Speed Mode): Changed the minimum values for HS1 and HS3 from
2.55 to 2.15, and the minimum values for HS2 and HS2 from 2.67 to 1.67................................................... 190
(Switching Characteristics for MMC1 – High Speed Mode): Changed the minimum values for HS8 and HS9
from -7.35 to -1.8, and the maximum values for HS8 and HS9 from 3.35 to 1.8........................................... 190
(Timing Requirements for MMC1 – UHS-I SDR12 Mode): Changed the minimum values for SDR121 and
SDR123 from 21.65 to 2.35............................................................................................................................191
(Switching Characteristics for MMC1 – UHS-I SDR12 Mode): Changed the minimum values for SDR128 and
SDR129 from -13.6 to 1.2, and the maximum values for SDR128 and SDR129 from 13.6 to 8....................191
(Timing Requirements for MMC1 – UHS-I SDR25 Mode): Changed the minimum values for SDR251 and
SDR253 from 2.15 to 1.95..............................................................................................................................192
(Switching Characteristics for MMC1 – UHS-I SDR25 Mode): Changed the minimum values for SDR258 and
SDR259 from -7.1 to 2.4, and the maximum values for SDR258 and SDR259 from 3.1 to 8........................192
(Timing Requirements for MMC1 – UHS-I DDR50 Mode): Removed Timing Requirements since the UHS-I
DDR50 mode requires a tuning algorithm to be used for optimal input timing............................................... 194
(Switching Characteristics for MMC1 – UHS-I DDR50 Mode): Changed the maximum value for DDR508 from
13.1 to 6.35.....................................................................................................................................................194
(Switching Characteristics for MMC1 – UHS-I SDR104 Mode): Changed the minimum values for SDR1046
and SDR1047 from 2.08 to 2.12, the minimum values for SDR1048 and SDR1049 from 1.12 to 1.08, and
maximum values for SDR1048 and SDR1049 from 3.16 to 3.2..................................................................... 195
(OSPI Switching Characteristics – PHY Data Training): Added maximum values to the OSPI0_CLK Cycle
Time parameter (O1) to define a minimum operating frequency of 133MHz. Also updated Note 1 and Note 4,
where "in ns" was added to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to
"reference clock" in Note 4 so it matches the clock name used in the TRM.................................................. 199
(OSPI0 Switching Characteristics – PHY SDR Mode): Updated Note 1 and Note 4, where "in ns" was added
to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 4 so it
matches the clock name used in the TRM..................................................................................................... 201
(OSPI0 Switching Characteristics – PHY DDR Mode): Updated Note 1 and Note 4, where "in ns" was added
to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 4 so it
matches the clock name used in the TRM..................................................................................................... 203
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
(OSPI0 Timing Requirements – Tap SDR Mode): Updated the constant values associated with the minimum
setup and minimum hold formulas in parameters O19 and O20. Note 2 was also updated to change "refclk" to
"reference clock" so it matches the clock name used in the TRM..................................................................205
(OSPI0 Switching Characteristics – Tap SDR Mode): Updated Note 1 and Note 4, where "in ns" was added to
the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 4 so it
matches the clock name used in the TRM..................................................................................................... 205
(OSPI0 Timing Requirements – Tap DDR Mode): Updated the constant values associated with the minimum
setup and minimum hold formulas in parameters O13 and O14. Note 2 was also updated to change "refclk" to
"reference clock" so it matches the clock name used in the TRM..................................................................207
(OSPI0 Switching Characteristics – Tap DDR Mode): Changed the "OSPI_RD_DATA_CAPTURE_REG" bit
field from "DELAY_FLD" to "DDR_READ_DELAY_FLD" in the note associated with parameter O6.............207
(OSPI0 Switching Characteristics – Tap DDR Mode): Updated the minimum data output delay and maximum
data output delay formulas in parameter O6. Also updated Note 1 and Note 5, where "in ns" was added to the
OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 5 so it
matches the clock name used in the TRM..................................................................................................... 207
(PCIe): Updated the "For more details about features and ..." paragraph......................................................208
(PRUSS PRU Switching Characteristics – Direct Output Mode): Changed the maximum skew value for the
GPO to GPO parameter (PRDO1) from 3ns to 2ns........................................................................................209
(PRU_ICSSG UART Switching Characteristics): Added the TRM UART baud rate settings reference to Note
1......................................................................................................................................................................218
(USB): Updated the "For more details about features and ..." paragraph...................................................... 229
(Power Supply Designs): Updated recommended PMIC from LP8733xx to TPS65220 or TPS65219.......... 243
(USB VBUS Design Guidelines): Changed the 3.5 kΩ resistor value to 3.48kΩ since 3.5kΩ is not a standard
value for 1% resistors..................................................................................................................................... 248
(Clock Routing Guidelines): Added new section............................................................................................ 251
(Device Naming Convention): Added the Automotive temperature range......................................................254
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
5 Device Comparison
Table 5-1 shows a comparison between devices, highlighting the differences.
Note
Availability of features listed in this table are a function of shared IO pins, where IO signals associated
with many of the features are multiplexed to a limited number of pins. The SysConfig tool should
be used to assign signal functions to pins. This will provide a better understanding of limitations
associated with pin multiplexing.
Note
To understand what device features are currently supported by TI Software Development Kits
(SDKs), search for the AM64x Software Build Sheet located in the Downloads tab option provided
at Processor-SDK-AM64x.
Table 5-1. Device Comparison
REFERENCE
NAME
FEATURES
AM6442
AM6441
AM6422
AM6421
AM6412
AM6411
CTRL_MMR_CFG0_JTAG_USER_ID[31:13](1)
Register bit values by device "Features" code (See Nomenclature Description table for more information on device features)
C:
–
–
–
–
0x19403
0x19203
D:
0x19464
0x19264
0x19424
0x19224
–
–
E:
0x19465
0x19265
–
0x19225
–
–
F:
0x19466
0x19266
–
0x19226
–
–
Dual Core
Single Core
Dual Core
Single Core
Dual Core
PROCESSORS AND ACCELERATORS
Speed Grades (See Table 7-1)
S
Arm Cortex-A53 Microprocessor Subsystem
Arm A53
2 × Dual Core
R5FSS0_CORE0
R5FSS0_CORE1
R5FSS1_CORE0
R5FSS1_CORE1
S, K
2 × Single Core
R5FSS0_CORE0
R5FSS1_CORE0
Arm Cortex-R5F
Arm R5F
Arm Cortex-M4F
Arm M4F
Device Management Security Controller
DMSC-L
Yes
Crypto Accelerators
Security
Yes
Single Core
Single Core
R5FSS0_CORE0
Single Core
Functional Safety Optional(4)
Single Core
PROGRAM AND DATA STORAGE
On-Chip Shared Memory (RAM) in MAIN Domain OCSRAM
2MB
R5F Tightly Coupled Memory (TCM)
TCM
4 x 64KB
2 x 128KB
On-Chip Shared Memory (RAM) in M4F Domain
MCU_MSRAM
DDR4/LPDDR4 DDR Subsystem
DDRSS
Up to 2GB (16-bit data) with inline ECC
General-Purpose Memory Controller
GPMC
Up to 128MB with ECC
1 x 128KB
256KB
PERIPHERALS
Modular Controller Area Network Interface
MCAN
Full CAN-FD Support(2)
MCAN
General-Purpose I/O
GPIO
Inter-Integrated Circuit Interface
I2C
Analog-to-Digital Converter
ADC
Multichannel Serial Peripheral Interface
MCSPI
Multi-Media Card/ Secure Digital Interface
Fast Serial Interface
Flash Subsystem
10
(FSS)(3)
Optional
No
Optional
No
No
Up to 198
6
1
No
7
MMCSD0
eMMC (8-bits)
MMCSD1
SD/SDIO (4-bits)
FSI_TX
2
FSI_RX
6
OSPI0/QSPI0
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2
Optional
Yes
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Table 5-1. Device Comparison (continued)
REFERENCE
NAME
FEATURES
AM6442
AM6441
AM6422
AM6421
PCI Express Port with Integrated SerDes PHY
PCIE0
Programmable Real-Time Unit Subsystem(5)
PRU_ICSSG
PRU_ICSSG Industrial Communication
Support(6)
PRU_ICSSG
Gigabit Ethernet Interface
CPSW3G
General-Purpose Timers
TIMER
16 (4 in MCU Channel)
Enhanced Pulse-Width Modulator Module
EPWM
9
Enhanced Capture Module
ECAP
3
Enhanced Quadrature Encoder Pulse Module
EQEP
3
Universal Asynchronous Receiver and
Transmitter
UART
9
Universal Serial Bus (USB3.1 Gen1) SuperSpeed
Dual-Role-Device (DRD) Ports with SS SerDes
USB0
PHY and USB 2.0 PHY
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Single
AM6412
AM6411
No
No
Lane(7)
2
Optional
Optional
Yes
Optional
Yes
Yes(7)
For more details about the CTRL_MMR_CFG0_JTAG_USER_ID register and DEVICE_ID bit field, see the device TRM.
Full CAN-FD Support is available when selecting an orderable part number that includes a feature code of E or F. Refer to
Nomenclature Description table for the definition of feature codes.
One flash interface, configured as OSPI0 or QSPI0.
Functional Safety is available when selecting an orderable part number that includes a feature code of F. Refer to Nomenclature
Description table for the definition of feature codes.
Orderable part numbers with a feature code of C support using PRU_ICSSG for use cases other than industrial communication. Refer
to Nomenclature Description table for the definition of feature codes.
PRU_ICSSG industrial communication includes Ethernet networking (MII/RGMII, MDIO), Sigma-Delta (SD) decimation, and three
channel peripheral interface (EnDat 2.2 and BiSS). PRU_ICSSG industrial communication support is available when selecting an
orderable part number that includes a feature code of D, E, or F. Refer to Nomenclature Description table for the definition of feature
codes.
USB SuperSpeed and PCIe share a common SerDes PHY. Therefore, USB will be limited to non-SuperSpeed modes when using the
SerDes PHY for PCIe.
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5.1 Related Products
Sitara™ processors Broad family of scalable processors based on Arm® Cortex®-A cores with flexible
accelerators, peripherals, connectivity and unified software support – perfect for sensors to servers. Sitara
processors have the reliability needed for use in industrial applications.
AM64x Sitara™ processors AM6x processors enable gigabit industrial Ethernet networks, robust operation
with extensive ECC on memories, and enhanced security features. Additional features such as an integrated
lockstep MCU subsystem and diagnostic libraries help enable functional safety systems.
Sitara™ processors - Applications Sitara™ processors provide scalable solutions for a wide range of
applications from HMIs and gateways to more complex equipment such as drives and substation automation
equipment. Sitara processors also offer multi-protocol support for industrial communication protocols such as
EtherCAT®, Ethernet/IP, and Profinet.
Sitara™ processors - Reference designs TI provides many reference designs containing ‘building block’
solutions to enable customers to rapidly develop their own unique products and solutions.
Companion Products for AM64x Review products that are frequently purchased or used in conjunction with
this product to complete your design.
12
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
6 Terminal Configuration and Functions
6.1 Pin Diagrams
Note
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt
is made to use "ball" only when referring to the physical package.
Figure 6-1 shows the ball locations for the 441-ball flip chip ball grid array (FCBGA) package to quickly locate
signal names and ball grid numbering. This figure is used in conjunction with Table 6-1 through Table 6-80 (Pin
Attributes table and all Signal Descriptions tables, including the Connectivity Requirements table).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PRG1_PRU0
_GPO6
PRG1_PRU0
_GPO11
PRG1_PRU0
_GPO14
PRG1_PRU1
_GPO11
PRG1_PRU1
_GPO14
PRG1_PRU1
_GPO2
PRG1_PRU1
_GPO5
PRG1_PRU1
_GPO17
VSS
SERDES0
_TX0_N
SERDES0
_TX0_P
VSS
USB0_DP
USB0_DM
VSS
VSS
PRG0_PRU0
_GPO4
PRG0_PRU0
_GPO12
PRG0_PRU1
_GPO16
PRG0_PRU0
_GPO10
PRG1
_MDIO0
_MDIO
Y
PRG0_PRU0
_GPO0
PRG0_PRU1
_GPO0
PRG0_PRU0
_GPO11
PRG0_PRU1
_GPO12
PRG0_PRU1
_GPO9
PRG1
_MDIO0
_MDC
PRG1_PRU0
_GPO0
PRG1_PRU0
_GPO4
PRG1_PRU0
_GPO15
PRG1_PRU1
_GPO16
PRG1_PRU1
_GPO15
PRG1_PRU1
_GPO3
PRG1_PRU1
_GPO18
VSS
SERDES0
_RX0_N
SERDES0
_RX0_P
VSS
GPMC0
_WAIT1
VSS
GPMC0
_AD15
GPMC0
_AD14
W
PRG0_PRU0
_GPO19
PRG0_PRU1
_GPO1
PRG0_PRU1
_GPO4
PRG0_PRU1
_GPO11
PRG0_PRU1
_GPO7
PRG0_PRU0
_GPO9
PRG1_PRU0
_GPO19
PRG1_PRU0
_GPO2
PRG1_PRU0
_GPO13
VSS
PRG1_PRU1
_GPO0
PRG1_PRU1
_GPO4
PRG1_PRU0
_GPO8
PRG1_PRU1
_GPO10
RSVD4
SERDES0
_REFCLK0N
SERDES0
_REFCLK0P
VSS
GPMC0
_WAIT0
GPMC0
_AD11
GPMC0
_AD12
V
PRG0_PRU0
_GPO18
PRG0_PRU0
_GPO3
PRG0_PRU1
_GPO2
PRG0_PRU0
_GPO14
PRG0_PRU1
_GPO17
PRG0_PRU1
_GPO10
PRG1_PRU0
_GPO18
PRG1_PRU0
_GPO3
PRG1_PRU0
_GPO16
PRG1_PRU1
_GPO12
PRG1_PRU1
_GPO1
PRG1_PRU1
_GPO19
PRG1_PRU0
_GPO5
PRG1_PRU1
_GPO9
PRG1_PRU1
_GPO7
RSVD5
VSS
GPMC0
_AD13
GPMC0_AD8
GPMC0_AD6
GPMC0_AD7
U
PRG0_PRU0
_GPO17
PRG0_PRU0
_GPO2
VSS
PRG0_PRU0
_GPO16
PRG0_PRU1
_GPO15
PRG0_PRU1
_GPO14
PRG1_PRU0
_GPO17
PRG1_PRU0
_GPO1
PRG1_PRU0
_GPO12
PRG1_PRU1
_GPO13
PRG1_PRU1
_GPO6
PRG1_PRU1
_GPO8
PRG1_PRU0
_GPO7
PRG1_PRU0
_GPO10
PRG1_PRU0
_GPO9
USB0_ID
USB0
_RCALIB
GPMC0_AD4
GPMC0_AD5
GPMC0_AD3
GPMC0_AD1
T
PRG0_PRU0
_GPO7
PRG0_PRU0
_GPO8
PRG0_PRU0
_GPO6
PRG0_PRU1
_GPO3
PRG0_PRU0
_GPO15
PRG0_PRU1
_GPO13
CAP_VDDS1
VSS
VDDSHV2
VSS
VSS
VDDA_0P85
_USB0
SERDES0
_REXT
USB0_VBUS
VSS
VSS
GPMC0_AD9
GPMC0_AD2
GPMC0
_BE1n
R
PRG0_PRU1
_GPO8
PRG0_PRU1
_GPO19
PRG0_PRU0
_GPO5
PRG0_PRU0
_GPO1
PRG0_PRU1
_GPO6
PRG0_PRU0
_GPO13
VSS
VDDSHV2
VSS
VDDSHV2
CAP_VDDS2
VSS
VDDA_3P3
_USB0
VDDA_1P8
_SERDES0
VDDA_1P8
_USB0
GPMC0
_AD10
GPMC0_CLK
GPMC0_OEn
_REn
GPMC0
_CSn0
GPMC0
_CSn1
GPMC0
_CSn3
P
VSS
PRG0
_MDIO0
_MDIO
PRG0
_MDIO0
_MDC
PRG0_PRU1
_GPO5
PRG0_PRU1
_GPO18
VSS
VDDSHV1
VSS
VDD_CORE
VSS
VDDA_0P85
_SERDES0
_C
VDDA_0P85
_SERDES0
VDDA_0P85
_SERDES0
VDDSHV3
VDDSHV3
GPMC0
_ADVn_ALE
GPMC0
_BE0n_CLE
VSS
GPMC0
_CSn2
OSPI0_D5
OSPI0_D4
N
DDR0_DQS1
DDR0_DQ15
DDR0_DQ13
DDR0_DQ12
DDR0_DQ8
VDDSHV1
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDDA_PLL0
VSS
CAP_VDDS3
VSS
GPMC0_WPn
GPMC0_DIR
OSPI0_D6
OSPI0_DQS
OSPI0_CLK
OSPI0
_LBCLKO
M
DDR0_DQS1
_n
DDR0_DM1
DDR0_DQ11
DDR0_DQ14
DDR0_A12
VSS
VDDSHV1
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDDR_CORE
VDDSHV4
VDDSHV4
CAP_VDDS4
OSPI0_D7
OSPI0_D1
OSPI0_D0
OSPI0_D2
OSPI0_D3
L
VSS
DDR0_DQ10
VSS
DDR0_DQ9
DDR0_A7
VDDS_DDR
VSS
VDD_CORE
VSS
VDDR_CORE
VDDA
_TEMP1
VDD_CORE
CAP_VDDS5
VDDSHV5
VDDSHV5
VSS
OSPI0
_CSn3
OSPI0
_CSn1
OSPI0
_CSn0
MMC1_CLK
MMC1_DAT1
K
RSVD7
RSVD6
DDR0_A10
DDR0_A13
DDR0_PAR
VSS
VDDS_DDR
VSS
VDD_CORE
VMON_VSYS
VDD_CORE
VDDA_MCU
VDD_MMC0
VDDS_MMC0
CAP
_VDDSHV
_MMC1
VMON_1P8
_MCU
OSPI0
_CSn2
MMC1_DAT3
MMC1_DAT2
MMC0_DAT0
MMC1_DAT0
J
DDR0_A11
DDR0_A6
DDR0_A8
DDR0_A9
DDR0_CAS
_n
VDDS_DDR
VSS
VDDS_DDR
_C
VSS
VDD_CORE
VDDA_PLL2
VDD_CORE
VDDA_ADC
VSS
ADC0_REFP
ADC0_REFN
MMC0_DAT3
MMC0_DAT2
MMC1_CMD
MMC0_DAT1
MMC0_CMD
H
DDR0
_ALERT_n
DDR0_ACT
_n
DDR0_BG1
DDR0_WE_n
DDR0_CAL0
VSS
VDDS_DDR
VSS
VDDA_PLL1
CAP_VDDS
_MCU
VSS
CAP_VDDS0
VDDS_OSC
VDD_DLL
_MMC0
VDDA_3P3
_SDIO
RSVD0
MMC0_DAT4
MMC0_DAT6
MMC0_DAT5
VSS
VSS
G
VSS
DDR0_BG0
VSS
DDR0_BA0
DDR0_BA1
VDDS_DDR
VSS
VDDSHV
_MCU
VSS
VDDSHV
_MCU
VDDA
_TEMP0
VDDSHV0
RSVD2
VDDSHV0
VPP
VSS
MMC0_DAT7
MMC0_CLK
MMC0_DS
ADC0_AIN0
ADC0_AIN4
F
DDR0_CK0
DDR0_A5
DDR0_CKE1
DDR0_CKE0
DDR0_ODT1
DDR0_RAS
_n
VDDS_DDR
VSS
VDDSHV
_MCU
VSS
VDDSHV0
RSVD8
VMON_3P3
_MCU
VMON_3P3
_SOC
VSS
RESETSTA
Tz
RSVD3
MMC0
_CALPAD
ADC0_AIN6
ADC0_AIN1
ADC0_AIN5
E
DDR0_CK0
_n
DDR0_A2
DDR0_CS0
_n
DDR0_CS1
_n
DDR0_ODT0
MCU_SPI0
_CLK
MCU_SPI0
_D0
MCU_UART0
_RTSn
MCU_I2C0
_SCL
EMU1
VSS
VMON_1P8
_SOC
VSS
UART1_TXD
UART1_RXD
UART1
_RTSn
PORz_OUT
RESET
_REQz
USB0
_DRVVBUS
ADC0_AIN7
ADC0_AIN2
D
VSS
DDR0_A0
DDR0_A4
DDR0_A3
DDR0
_RESET0_n
MCU_SPI0
_CS0
MCU_SPI1
_CLK
MCU_UART0
_CTSn
MCU_UART1
_TXD
EMU0
TRSTn
SPI0_CS0
SPI0_CLK
SPI1_CS1
UART0_RXD
UART1
_CTSn
MCAN1_RX
ADC0_AIN3
RSVD1
C
DDR0_DQS0
DDR0_DQ6
VSS
DDR0_DQ5
DDR0_A1
MCU_SPI0
_CS1
MCU_SPI1
_D0
MCU_SPI1
_D1
MCU_UART1
_RXD
VSS
TDI
TMS
SPI0_CS1
SPI1_CLK
VSS
UART0_TXD
MCAN1_TX
I2C1_SCL
EXTINTn
MMC1_SDWP
MCU_OSC0
_XI
B
DDR0_DQS0
_n
DDR0_DM0
DDR0_DQ4
DDR0_DQ7
DDR0_DQ2
MCU_SPI0
_D1
MCU_SPI1
_CS1
MCU_UART1
_CTSn
MCU_UART1
_RTSn
MCU_I2C1
_SDA
TCK
MCU
_RESETz
MCU_RESETS
TATz
SPI1_CS0
SPI1_D0
UART0
_CTSn
MCAN0_RX
I2C0_SDA
I2C1_SDA
MCU_OSC0
_XO
MCU_PORz
A
VSS
DDR0_DQ1
DDR0_DQ0
DDR0_DQ3
VSS
VSS
MCU_SPI1
_CS0
MCU_UART0
_TXD
MCU_UART0
_RXD
MCU_I2C0
_SDA
MCU_I2C1
_SCL
TDO
SPI0_D0
SPI0_D1
SPI1_D1
UART0
_RTSn
MCAN0_TX
I2C0_SCL
EXT
_REFCLK1
MCU
_SAFETY
_ERRORn
VSS
AA
ECAP0_IN
MMC1_SDCD
_APWM_OUT
GPMC0_AD0 GPMC0_WEn
Not to scale
Figure 6-1. ALV FCBGA-N441 Pin Diagram (Bottom View)
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6.2 Pin Attributes
The following list describes the contents of each column in Table 6-1, Pin Attributes:
1. BALL NUMBER: Ball numbers assigned to each terminal of the Ball Grid Array package.
2. BALL NAME: Ball name assigned to each terminal of the Ball Grid Array package (this name is typically
taken from the primary MUXMODE 0 signal function).
3. SIGNAL NAME: Signal name(s) of all dedicated and pin multiplexed signal functions associated with a ball.
Note
Many device pins support multiple signal functions. Some signal functions are selected via a
single layer of multiplexers associated with pins. Other signal functions are selected via two or
more layers of multiplexers, where one layer is associated with the pins and other layers are
associated with peripheral logic functions.
Table 6-1, Pin Attributes only defines signal multiplexing at the pins. For more information,
related to signal multiplexing at the pins, see the Pad Configuration Registers section in the
Device Configuration chapter of the device TRM. For information associated with peripheral signal
multiplexing, see the respective peripheral chapter in the device TRM.
4. MUX MODE: The MUXMODE value associated with each pin multiplexed signal function:
a. MUXMODE 0 is the primary pin multiplexed signal function. However, the primary pin multiplexed signal
function is not necessarily the default pin multiplexed signal function.
Note
The value found in the MUX MODE AFTER RESET column defines the default pin
multiplexed signal function selected when MCU_PORz is deasserted.
b. MUXMODE values 1 through 15 are possible for pin multiplexed signal functions. However, not all
MUXMODE values have been implemented. The only valid MUXMODE values are those defined as pin
multiplexed signal functions within the Pin Attributes table. Only valid values of MUXMODE should be
used.
c. Bootstrap defines SOC configuration pins, where the logic state applied to each pin is latched on the
rising edge of PORz_OUT. These input signal functions are fixed to their respective pins and are not
programmable via MUXMODE.
d. An empty box means Not Applicable.
Note
The following configurations of MUXMODE must be avoided for proper device operation.
• Configuring multiple pins operating as inputs to the same pin multiplexed signal function is not
supported as it can yield unexpected results.
• Configuring a pin to an undefined pin multiplexing mode will cause the pin behavior to be
undefined.
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5. TYPE: Signal type and direction:
• I = Input
• O = Output
• OD = Output, with open-drain output function
• IO = Input, Output, or simultaneously Input and Output
• IOD = Input, Output, or simultaneously Input and Output, with open-drain output function
• IOZ = Input, Output, or simultaneously Input and Output, with three-state output function
• OZ = Output with three-state output function
• A = Analog
• PWR = Power
• GND = Ground
• CAP = LDO Capacitor.
6. DSIS: The deselected input state (DSIS) indicates the state driven to the subsystem input (logic "0", logic
"1", or "pad" level) when the pin multiplexed signal function is not selected by MUXMODE.
• 0: Logic 0 driven to the subsystem input.
• 1: Logic 1 driven to the subsystem input.
• pad: Logic state of the pad is driven to the subsystem input.
• An empty box means Not Applicable.
7. BALL STATE DURING RESET RX/TX/PULL: State of the terminal while MCU_PORz is asserted, where RX
defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state of
internal pull resistors:
• RX (Input buffer)
– Off: The input buffer is disabled.
– On: The input buffer is enabled.
• TX (Output buffer)
– Off: The output buffer is disabled.
– Low: The output buffer is enabled and drives VOL.
• PULL (Internal pull resistors)
– Off: Internal pull resistors are turned off.
– Up: Internal pull-up resistor is turned on.
– Down: Internal pull-down resistor is turned on.
– NA: Not Applicable.
• An empty box means Not Applicable.
8. BALL STATE AFTER RESET RX/TX/PULL: State of the terminal after MCU_PORz is deasserted, where
RX defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state
of internal pull resistors:
• RX (Input buffer)
– Off: The input buffer is disabled.
– On: The input buffer is enabled.
• TX (Output buffer)
– Off: The output buffer is disabled.
– SS: The subsystem selected with MUXMODE determines the output buffer state.
• PULL (Internal pull resistors)
– Off: Internal pull resistors are turned off.
– Up: Internal pull-up resistor is turned on.
– Down: Internal pull-down resistor is turned on.
– NA: Not Applicable.
• An empty box means Not Applicable.
9. MUX MODE AFTER RESET: The value found in this column defines the default pin multiplexed signal
function after MCU_PORz is deasserted.
An empty box means Not Applicable.
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10. I/O OPERATING VOLTAGE: This column describes I/O operating voltage options of the respective power
supply, when applicable.
An empty box means Not Applicable.
For more information, see valid operating voltage range(s) defined for each power supply in Section 7.4,
Recommended Operating Conditions.
11. POWER: The power supply of the associated I/O, when applicable.
An empty box means Not Applicable.
12. HYS: Indicates if the input buffer associated with this I/O has hysteresis:
• Yes: With hysteresis
• No: Without hysteresis
• An empty box means Not Applicable.
For more information, see the hysteresis values in Section 7.7, Electrical Characteristics.
13. BUFFER TYPE: This column defines the buffer type associated with a terminal. This information can be
used to determine which Electrical Characteristics table is applicable.
An empty box means Not Applicable.
For electrical characteristics, refer to the appropriate buffer type table in Section 7.7, Electrical
Characteristics.
14. PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and
pulldown resistors can be enabled or disabled via software.
• PU: Internal pull-up
• PD: Internal pull-down
• PU/PD: Internal pull-up and pull-down
• An empty box means No internal pull.
15. PADCONFIG Register:Name of the IO pad configuration register associated with Ball.
16. PADCONFIG Address:Physical address of the IO pad configuration register associated with Ball.
16
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
J16
ADC0_REFN
ADC0_REFN
A
1.8 V
VDDA_ADC0
J15
ADC0_REFP
ADC0_REFP
A
1.8 V
VDDA_ADC0
G20
ADC0_AIN0
ADC0_AIN0
A
1.8 V
VDDA_ADC0
Yes
ADC12B
F20
ADC0_AIN1
ADC0_AIN1
A
1.8 V
VDDA_ADC0
Yes
ADC12B
E21
ADC0_AIN2
ADC0_AIN2
A
1.8 V
VDDA_ADC0
Yes
ADC12B
D20
ADC0_AIN3
ADC0_AIN3
A
1.8 V
VDDA_ADC0
Yes
ADC12B
G21
ADC0_AIN4
ADC0_AIN4
A
1.8 V
VDDA_ADC0
Yes
ADC12B
F21
ADC0_AIN5
ADC0_AIN5
A
1.8 V
VDDA_ADC0
Yes
ADC12B
F19
ADC0_AIN6
ADC0_AIN6
A
1.8 V
VDDA_ADC0
Yes
ADC12B
E20
ADC0_AIN7
ADC0_AIN7
A
1.8 V
VDDA_ADC0
Yes
ADC12B
H12
CAP_VDDS0
CAP_VDDS0
CAP
ADC12B
ADC12B
T7
CAP_VDDS1
CAP_VDDS1
CAP
R11
CAP_VDDS2
CAP_VDDS2
CAP
N14
CAP_VDDS3
CAP_VDDS3
CAP
M16
CAP_VDDS4
CAP_VDDS4
CAP
L13
CAP_VDDS5
CAP_VDDS5
CAP
K15
CAP_VDDSHV_MMC1
CAP_VDDSHV_MMC1
CAP
H10
CAP_VDDS_MCU
CAP_VDDS_MCU
CAP
H2
DDR0_ACT_n
DDR0_ACT_n
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
H1
DDR0_ALERT_n
DDR0_ALERT_n
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
J5
DDR0_CAS_n
DDR0_CAS_n
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
K5
DDR0_PAR
DDR0_PAR
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
F6
DDR0_RAS_n
DDR0_RAS_n
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
H4
DDR0_WE_n
DDR0_WE_n
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
D2
DDR0_A0
DDR0_A0
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
DDR
C5
DDR0_A1
DDR0_A1
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
E2
DDR0_A2
DDR0_A2
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
D4
DDR0_A3
DDR0_A3
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
D3
DDR0_A4
DDR0_A4
O
PULL
UP/DOWN
TYPE [14]
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
18
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
F2
DDR0_A5
DDR0_A5
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
J2
DDR0_A6
DDR0_A6
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
L5
DDR0_A7
DDR0_A7
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
J3
DDR0_A8
DDR0_A8
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
J4
DDR0_A9
DDR0_A9
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
K3
DDR0_A10
DDR0_A10
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
J1
DDR0_A11
DDR0_A11
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
DDR
M5
DDR0_A12
DDR0_A12
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
K4
DDR0_A13
DDR0_A13
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
G4
DDR0_BA0
DDR0_BA0
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
DDR
G5
DDR0_BA1
DDR0_BA1
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
G2
DDR0_BG0
DDR0_BG0
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
H3
DDR0_BG1
DDR0_BG1
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
DDR
H5
DDR0_CAL0
DDR0_CAL0
A
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
F1
DDR0_CK0
DDR0_CK0
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
E1
DDR0_CK0_n
DDR0_CK0_n
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
F4
DDR0_CKE0
DDR0_CKE0
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
F3
DDR0_CKE1
DDR0_CKE1
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
E3
DDR0_CS0_n
DDR0_CS0_n
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
E4
DDR0_CS1_n
DDR0_CS1_n
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
B2
DDR0_DM0
DDR0_DM0
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
M2
DDR0_DM1
DDR0_DM1
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
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UP/DOWN
TYPE [14]
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
A3
DDR0_DQ0
DDR0_DQ0
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
A2
DDR0_DQ1
DDR0_DQ1
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
B5
DDR0_DQ2
DDR0_DQ2
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
A4
DDR0_DQ3
DDR0_DQ3
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
B3
DDR0_DQ4
DDR0_DQ4
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
C4
DDR0_DQ5
DDR0_DQ5
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
C2
DDR0_DQ6
DDR0_DQ6
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
DDR
B4
DDR0_DQ7
DDR0_DQ7
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
N5
DDR0_DQ8
DDR0_DQ8
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
L4
DDR0_DQ9
DDR0_DQ9
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
DDR
L2
DDR0_DQ10
DDR0_DQ10
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
M3
DDR0_DQ11
DDR0_DQ11
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
N4
DDR0_DQ12
DDR0_DQ12
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
DDR
N3
DDR0_DQ13
DDR0_DQ13
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
M4
DDR0_DQ14
DDR0_DQ14
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
N2
DDR0_DQ15
DDR0_DQ15
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
C1
DDR0_DQS0
DDR0_DQS0
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
B1
DDR0_DQS0_n
DDR0_DQS0_n
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
N1
DDR0_DQS1
DDR0_DQS1
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
M1
DDR0_DQS1_n
DDR0_DQS1_n
IO
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
E5
DDR0_ODT0
DDR0_ODT0
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
F5
DDR0_ODT1
DDR0_ODT1
O
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
DDR
PULL
UP/DOWN
TYPE [14]
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
D5
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
DDR0_RESET0_n
DDR0_RESET0_n
TYPE
[5]
DSIS
[6]
0
IO
SYNC0_OUT
1
O
CPTS0_RFT_CLK
2
I
0
CP_GEMAC_CPTS0_RFT_CLK
5
I
0
SPI4_CS3
6
IO
1
GPIO1_68
7
IO
pad
PADCONFIG:
MCU_PADCONFIG31
0x0408407C
EMU0
0
IO
1
EMU1
EMU1
0
IO
1
PADCONFIG:
MCU_PADCONFIG32
0x04084080
MCU_OBSCLK0
15
O
EXTINTn
EXTINTn
0
I
1
PADCONFIG:
PADCONFIG158
0x000F4278
GPIO1_70
7
IOD
pad
0
PADCONFIG:
PADCONFIG156
0x000F4270
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
1.1 V/1.2 V
VDDS_DDR,
VDDS_DDR_C
O
ECAP0_IN_APWM_OUT
ECAP0_IN_APWM_OUT
D18
SIGNAL NAME [3]
MUX
MODE
[4]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DDR
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
On / Off / Up
On / Off / Up
0
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
On / Off / Up
On / Off / Up
0
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / NA
Off / Off / NA
7
1.8 V/3.3 V
VDDSHV0
Yes
I2C OD FS
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
EMU0
D10
E10
C19
A19
P16
EXT_REFCLK1
0
I
EXT_REFCLK1
SYNC1_OUT
1
O
PADCONFIG:
PADCONFIG157
0x000F4274
SPI2_CS3
2
IO
CLKOUT0
5
O
GPIO1_69
7
IO
GPMC0_ADVn_ALE
0
O
20
pad
FSI_RX5_CLK
1
I
0
GPMC0_ADVn_ALE
UART5_RXD
2
I
1
PADCONFIG:
PADCONFIG33
0x000F4084
EHRPWM_TZn_IN3
3
I
0
TRC_DATA15
6
O
GPIO0_32
7
IO
pad
PRG0_PWM3_TZ_IN
9
I
0
GPMC0_CLK
0
O
0
FSI_RX4_CLK
1
I
0
UART4_RTSn
2
O
EHRPWM3_SYNCO
3
O
GPMC0_FCLK_MUX
4
O
TRC_DATA14
6
O
GPIO0_31
7
IO
PRG0_PWM3_TZ_OUT
9
O
GPMC0_CLK
R17
1
PADCONFIG:
PADCONFIG31
0x000F407C
pad
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
N17
R18
T21
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
T20
TYPE
[5]
O
DSIS
[6]
GPMC0_DIR
0
GPMC0_DIR
EQEP0_B
3
I
0
PADCONFIG:
PADCONFIG41
0x000F40A4
GPIO0_40
7
IO
pad
EHRPWM6_B
8
IO
0
PRG1_PWM2_B0
9
IO
1
GPMC0_OEn_REn
0
O
FSI_RX5_D0
1
I
GPMC0_OEn_REn
UART5_TXD
2
O
PADCONFIG:
PADCONFIG34
0x000F4088
EHRPWM4_A
3
IO
TRC_DATA16
6
O
GPIO0_33
7
IO
pad
PRG0_PWM3_A1
9
IO
0
GPMC0_WEn
0
O
0
FSI_RX5_D1
1
I
UART5_RTSn
2
O
PADCONFIG:
PADCONFIG35
0x000F408C
EHRPWM4_B
3
IO
TRC_DATA17
6
O
GPIO0_34
7
IO
pad
PRG0_PWM3_B1
9
IO
1
GPMC0_WPn
0
O
FSI_TX1_CLK
1
O
EQEP0_A
3
I
GPMC0_A22
4
OZ
TRC_DATA22
6
O
GPIO0_39
7
IO
pad
EHRPWM6_A
8
IO
0
PRG1_PWM2_A0
9
IO
0
GPMC0_AD0
0
IO
0
FSI_RX2_CLK
1
I
0
GPMC0_AD0
UART2_RXD
2
I
1
PADCONFIG:
PADCONFIG15
0x000F403C
EHRPWM0_SYNCI
3
I
0
TRC_CLK
6
O
7
IO
Bootstrap
I
PADCONFIG:
PADCONFIG40
0x000F40A0
GPIO0_15
BOOTMODE00
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
0
GPMC0_WEn
GPMC0_WPn
N16
SIGNAL NAME [3]
MUX
MODE
[4]
0
0
0
pad
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
GPMC0_AD1
U21
PADCONFIG:
PADCONFIG16
0x000F4040
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
GPMC0_AD1
0
IO
0
FSI_RX2_D0
1
I
0
UART2_TXD
2
O
EHRPWM0_SYNCO
3
O
TRC_CTL
6
O
GPIO0_16
7
IO
PRG0_PWM2_TZ_OUT
9
O
SIGNAL NAME [3]
BOOTMODE01
GPMC0_AD2
T18
PADCONFIG:
PADCONFIG17
0x000F4044
GPMC0_AD3
U20
PADCONFIG:
PADCONFIG18
0x000F4048
Bootstrap
I
0
IO
0
FSI_RX2_D1
1
I
0
UART2_RTSn
2
O
EHRPWM_TZn_IN0
3
I
TRC_DATA0
6
O
GPIO0_17
7
IO
pad
PRG0_PWM2_TZ_IN
9
I
0
Bootstrap
I
GPMC0_AD3
0
IO
0
FSI_RX3_CLK
1
I
0
UART3_RXD
2
I
1
EHRPWM0_A
3
IO
0
TRC_DATA1
6
O
GPIO0_18
7
IO
pad
PRG0_PWM2_A0
9
IO
0
Bootstrap
I
GPMC0_AD4
0
IO
0
FSI_RX3_D0
1
I
0
UART3_TXD
2
O
EHRPWM0_B
3
IO
TRC_DATA2
6
O
GPIO0_82
7
IO
pad
PRG0_PWM2_B0
9
IO
1
Bootstrap
I
BOOTMODE03
GPMC0_AD4
U18
PADCONFIG:
PADCONFIG19
0x000F404C
BOOTMODE04
22
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
pad
GPMC0_AD2
BOOTMODE02
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
0
0
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
GPMC0_AD5
0
IO
0
FSI_RX3_D1
1
I
0
UART3_RTSn
2
O
EHRPWM1_A
3
IO
TRC_DATA3
6
O
GPIO0_83
7
IO
pad
PRG0_PWM2_A1
9
IO
0
Bootstrap
I
GPMC0_AD6
0
IO
0
FSI_RX4_D0
1
I
0
UART4_RXD
2
I
1
EHRPWM1_B
3
IO
0
TRC_DATA4
6
O
GPIO0_21
7
IO
pad
PRG0_PWM2_B1
9
IO
1
Bootstrap
I
GPMC0_AD7
0
IO
0
FSI_RX4_D1
1
I
0
UART4_TXD
2
O
GPMC0_AD7
EHRPWM_TZn_IN1
3
I
0
PADCONFIG:
PADCONFIG22
0x000F4058
EHRPWM8_A
4
IO
0
TRC_DATA5
6
O
GPIO0_22
7
IO
pad
PRG1_PWM2_A2
9
IO
0
Bootstrap
I
GPMC0_AD8
0
IO
0
FSI_RX0_CLK
1
I
0
UART2_CTSn
2
I
1
EHRPWM2_A
3
IO
0
TRC_DATA6
6
O
GPIO0_23
7
IO
pad
PRG0_PWM2_A2
9
IO
0
Bootstrap
I
GPMC0_AD5
U19
PADCONFIG:
PADCONFIG20
0x000F4050
SIGNAL NAME [3]
BOOTMODE05
GPMC0_AD6
V20
PADCONFIG:
PADCONFIG21
0x000F4054
BOOTMODE06
V21
BOOTMODE07
GPMC0_AD8
V19
PADCONFIG:
PADCONFIG23
0x000F405C
BOOTMODE08
0
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
GPMC0_AD9
0
IO
0
FSI_RX0_D0
1
I
0
UART3_CTSn
2
I
1
EHRPWM2_B
3
IO
0
TRC_DATA7
6
O
GPIO0_24
7
IO
pad
PRG0_PWM2_B2
9
IO
1
BOOTMODE09
Bootstrap
I
GPMC0_AD10
0
IO
0
FSI_RX0_D1
1
I
0
UART4_CTSn
2
I
1
GPMC0_AD10
EHRPWM_TZn_IN2
3
I
0
PADCONFIG:
PADCONFIG25
0x000F4064
EHRPWM8_B
4
IO
0
TRC_DATA8
6
O
GPIO0_25
7
IO
pad
PRG1_PWM2_B2
9
IO
1
BOOTMODE10
Bootstrap
I
GPMC0_AD11
0
IO
0
FSI_RX1_CLK
1
I
0
UART5_CTSn
2
I
1
EQEP1_A
3
I
0
TRC_DATA9
6
O
GPIO0_26
7
IO
pad
EHRPWM7_A
8
IO
0
BOOTMODE11
Bootstrap
I
GPMC0_AD12
0
IO
0
FSI_RX1_D0
1
I
0
UART6_CTSn
2
I
1
EQEP1_B
3
I
0
TRC_DATA10
6
O
GPIO0_27
7
IO
pad
EHRPWM7_B
8
IO
0
Bootstrap
I
GPMC0_AD9
T17
R16
PADCONFIG:
PADCONFIG24
0x000F4060
GPMC0_AD11
W20
PADCONFIG:
PADCONFIG26
0x000F4068
GPMC0_AD12
W21
PADCONFIG:
PADCONFIG27
0x000F406C
SIGNAL NAME [3]
BOOTMODE12
24
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
V18
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
GPMC0_AD13
0
IO
0
FSI_RX1_D1
1
I
0
GPMC0_AD13
EHRPWM3_A
3
IO
0
PADCONFIG:
PADCONFIG28
0x000F4070
TRC_DATA11
6
O
GPIO0_28
7
IO
pad
0
SIGNAL NAME [3]
PRG0_PWM3_A0
9
IO
BOOTMODE13
Bootstrap
I
GPMC0_AD14
0
IO
FSI_TX0_D0
1
O
UART6_RXD
2
I
1
EHRPWM3_B
3
IO
0
TRC_DATA12
6
O
GPIO0_29
7
IO
pad
PRG0_PWM3_B0
9
IO
1
BOOTMODE14
Bootstrap
I
GPMC0_AD15
0
IO
FSI_TX0_D1
1
O
GPMC0_AD15
UART6_TXD
2
O
PADCONFIG:
PADCONFIG30
0x000F4078
EHRPWM3_SYNCI
3
I
TRC_DATA13
6
O
GPMC0_AD14
Y21
Y20
PADCONFIG:
PADCONFIG29
0x000F4074
GPIO0_30
GPMC0_BE0n_CLE
P17
PADCONFIG:
PADCONFIG36
0x000F4090
GPMC0_BE1n
T19
PADCONFIG:
PADCONFIG37
0x000F4094
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
0
0
0
7
IO
Bootstrap
I
GPMC0_BE0n_CLE
0
O
FSI_TX1_D0
1
O
UART6_RTSn
2
O
EHRPWM_TZn_IN4
3
I
0
EHRPWM7_A
5
IO
0
TRC_DATA18
6
O
GPIO0_35
7
IO
pad
PRG1_PWM2_A1
9
IO
0
GPMC0_BE1n
0
O
FSI_TX0_CLK
1
O
EHRPWM5_A
3
IO
TRC_DATA19
6
O
GPIO0_36
7
IO
pad
PRG0_PWM3_A2
9
IO
0
BOOTMODE15
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
pad
0
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
R19
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
P19
R21
W19
26
TYPE
[5]
DSIS
[6]
GPMC0_CSn0
0
O
GPMC0_CSn0
EQEP0_S
3
IO
PADCONFIG:
PADCONFIG42
0x000F40A8
TRC_DATA23
6
O
GPIO0_41
7
IO
pad
EHRPWM6_SYNCI
8
I
0
GPMC0_CSn1
0
O
EQEP0_I
3
IO
EHRPWM_TZn_IN2
5
I
0
GPIO0_42
7
IO
pad
EHRPWM6_SYNCO
8
O
PRG1_PWM2_TZ_OUT
9
O
GPMC0_CSn2
0
O
I2C2_SCL
1
IOD
1
GPMC0_CSn2
TIMER_IO8
2
IO
0
PADCONFIG:
PADCONFIG44
0x000F40B0
EQEP1_S
3
IO
0
EHRPWM_TZn_IN4
5
I
0
GPIO0_43
7
IO
pad
PRG1_PWM2_TZ_IN
9
I
0
GPMC0_CSn3
0
O
GPMC0_CSn1
R20
SIGNAL NAME [3]
MUX
MODE
[4]
PADCONFIG:
PADCONFIG43
0x000F40AC
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
0
0
I2C2_SDA
1
IOD
1
GPMC0_CSn3
TIMER_IO9
2
IO
0
PADCONFIG:
PADCONFIG45
0x000F40B4
EQEP1_I
3
IO
0
GPMC0_A20
4
OZ
EHRPWM_TZn_IN5
5
I
0
GPIO0_44
7
IO
pad
GPMC0_WAIT0
0
I
1
GPMC0_WAIT0
EHRPWM5_B
3
IO
0
PADCONFIG:
PADCONFIG38
0x000F4098
TRC_DATA20
6
O
GPIO0_37
7
IO
pad
PRG0_PWM3_B2
9
IO
1
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
A18
B18
C18
B19
DSIS
[6]
1
0
I
FSI_TX1_D1
1
O
EHRPWM_TZn_IN5
3
I
GPMC0_A21
4
OZ
EHRPWM7_B
5
IO
TRC_DATA21
6
O
GPIO0_38
7
IO
pad
PRG1_PWM2_B1
9
IO
1
I2C0_SCL
I2C0_SCL
0
IOD
1
PADCONFIG:
PADCONFIG152
0x000F4260
GPIO1_64
7
IOD
pad
I2C0_SDA
I2C0_SDA
0
IOD
1
PADCONFIG:
PADCONFIG153
0x000F4264
GPIO1_65
7
IOD
pad
PADCONFIG:
PADCONFIG39
0x000F409C
0
I2C1_SCL
0
IOD
1
CPTS0_HW1TSPUSH
1
I
0
PADCONFIG:
PADCONFIG154
0x000F4268
TIMER_IO0
2
IO
0
SPI2_CS1
3
IO
1
GPIO1_66
7
IO
pad
I2C1_SDA
0
IOD
1
I2C1_SDA
CPTS0_HW2TSPUSH
1
I
0
PADCONFIG:
PADCONFIG155
0x000F426C
TIMER_IO1
2
IO
0
SPI2_CS2
3
IO
1
GPIO1_67
7
IO
pad
MCAN0_RX
0
I
1
UART4_TXD
1
O
TIMER_IO3
2
IO
SYNC3_OUT
3
O
SPI4_CS2
6
IO
1
GPIO1_61
7
IO
pad
EQEP2_S
8
IO
0
UART0_RIn
9
I
1
PADCONFIG:
PADCONFIG149
0x000F4254
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
Off / Off / NA
On / SS / NA
7
1.8 V/3.3 V
VDDSHV0
Yes
I2C OD FS
Off / Off / NA
On / SS / NA
7
1.8 V/3.3 V
VDDSHV0
Yes
I2C OD FS
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
0
I2C1_SCL
MCAN0_RX
B17
TYPE
[5]
GPMC0_WAIT1
GPMC0_WAIT1
Y18
SIGNAL NAME [3]
MUX
MODE
[4]
0
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
MCAN0_TX
0
O
UART4_RXD
1
I
1
TIMER_IO2
2
IO
0
SYNC2_OUT
3
O
SPI4_CS1
6
IO
1
GPIO1_60
7
IO
pad
EQEP2_I
8
IO
0
UART0_DTRn
9
O
MCAN1_RX
0
I
1
I2C3_SDA
1
IOD
1
ECAP2_IN_APWM_OUT
2
IO
0
OBSCLK0
3
O
MCAN1_RX
TIMER_IO5
4
IO
PADCONFIG:
PADCONFIG151
0x000F425C
UART5_TXD
5
O
EHRPWM_SOCB
6
O
GPIO1_63
7
IO
pad
EQEP2_B
8
I
0
UART0_DSRn
9
I
1
OBSCLK0
15
O
MCAN1_TX
0
O
I2C3_SCL
1
IOD
1
ECAP1_IN_APWM_OUT
2
IO
0
SYSCLKOUT0
3
O
TIMER_IO4
4
IO
0
UART5_RXD
5
I
1
EHRPWM_SOCA
6
O
GPIO1_62
7
IO
pad
EQEP2_A
8
I
0
UART0_DCDn
9
I
1
MCU_I2C0_SCL
MCU_I2C0_SCL
0
IOD
1
PADCONFIG:
MCU_PADCONFIG18
0x04084048
MCU_GPIO0_18
7
IOD
pad
MCU_I2C0_SDA
MCU_I2C0_SDA
0
IOD
1
PADCONFIG:
MCU_PADCONFIG19
0x0408404C
MCU_GPIO0_19
7
IOD
pad
MCAN0_TX
A17
D17
PADCONFIG:
PADCONFIG148
0x000F4250
MCAN1_TX
C17
E9
A10
28
PADCONFIG:
PADCONFIG150
0x000F4258
SIGNAL NAME [3]
DSIS
[6]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / NA
On / SS / NA
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
I2C OD FS
Off / Off / NA
On / SS / NA
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
I2C OD FS
0
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
A11
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
MCU_I2C1_SCL
MCU_I2C1_SCL
0
IOD
1
PADCONFIG:
MCU_PADCONFIG20
0x04084050
MCU_GPIO0_20
7
IO
pad
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
MCU_I2C1_SDA
MCU_I2C1_SDA
0
IOD
1
B10
PADCONFIG:
MCU_PADCONFIG21
0x04084054
MCU_GPIO0_21
7
IO
pad
C21
MCU_OSC0_XI
MCU_OSC0_XI
I
1.8 V
VDDS_OSC
Yes
HFOSC
B20
MCU_OSC0_XO
MCU_OSC0_XO
O
1.8 V
VDDS_OSC
Yes
HFOSC
0
1.8 V
VDDS_OSC
Yes
FS RESET
MCU_PORz
B21
B13
PADCONFIG:
MCU_PADCONFIG23
0x0408405C
MCU_PORz
0
I
MCU_RESETSTATz
MCU_RESETSTATz
0
O
PADCONFIG:
MCU_PADCONFIG24
0x04084060
MCU_GPIO0_22
7
IO
MCU_RESETz
0
PADCONFIG:
MCU_PADCONFIG25
0x04084064
MCU_SAFETY_ERRORn
MCU_SPI0_CLK
PADCONFIG:
MCU_PADCONFIG2
0x04084008
Off / Low / Off
Off / SS / Off
0
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
I
On / Off / Up
On / Off / Up
0
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
0
IO
Off / Off / Down
On / SS / Down
0
1.8 V
VDDS_OSC
Yes
LVCMOS
PU/PD
MCU_SPI0_CLK
0
IO
0
MCU_GPIO0_11
7
IO
pad
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
MCU_SPI1_CLK
MCU_SPI1_CLK
0
IO
0
PADCONFIG:
MCU_PADCONFIG7
0x0408401C
MCU_GPIO0_7
7
IO
pad
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
MCU_SPI0_CS0
MCU_SPI0_CS0
0
IO
1
PADCONFIG:
MCU_PADCONFIG0
0x04084000
MCU_GPIO0_13
7
IO
pad
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
MCU_SPI0_CS1
0
IO
1
MCU_OBSCLK0
1
O
MCU_SYSCLKOUT0
2
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
MCU_GPIO0_12
7
IO
pad
MCU_RESETz
B12
PADCONFIG:
MCU_PADCONFIG22
0x04084058
MCU_SAFETY_ERRORn
A20
E6
D7
D6
MCU_SPI0_CS1
C6
PADCONFIG:
MCU_PADCONFIG1
0x04084004
pad
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
E7
B6
A7
B7
C7
C8
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
A9
A8
30
DSIS
[6]
MCU_SPI0_D0
0
IO
0
PADCONFIG:
MCU_PADCONFIG3
0x0408400C
MCU_GPIO0_10
7
IO
pad
MCU_SPI0_D1
MCU_SPI0_D1
0
IO
0
PADCONFIG:
MCU_PADCONFIG4
0x04084010
MCU_GPIO0_4
7
IO
pad
MCU_SPI1_CS0
MCU_SPI1_CS0
0
IO
1
PADCONFIG:
MCU_PADCONFIG5
0x04084014
MCU_GPIO0_5
7
IO
pad
MCU_SPI1_CS1
MCU_SPI1_CS1
0
IO
1
PADCONFIG:
MCU_PADCONFIG6
0x04084018
MCU_EXT_REFCLK0
1
I
0
MCU_GPIO0_6
7
IO
pad
MCU_SPI1_D0
MCU_SPI1_D0
0
IO
0
PADCONFIG:
MCU_PADCONFIG8
0x04084020
MCU_GPIO0_8
7
IO
pad
MCU_SPI1_D1
MCU_SPI1_D1
0
IO
0
PADCONFIG:
MCU_PADCONFIG9
0x04084024
MCU_GPIO0_9
7
IO
pad
MCU_UART0_CTSn
0
I
1
MCU_TIMER_IO0
1
IO
0
MCU_SPI0_CS2
2
IO
1
MCU_GPIO0_1
7
IO
pad
MCU_UART0_RTSn
0
O
MCU_TIMER_IO1
1
IO
0
MCU_SPI1_CS2
2
IO
1
PADCONFIG:
MCU_PADCONFIG12
0x04084030
MCU_UART0_RTSn
E8
TYPE
[5]
MCU_SPI0_D0
MCU_UART0_CTSn
D8
SIGNAL NAME [3]
MUX
MODE
[4]
PADCONFIG:
MCU_PADCONFIG13
0x04084034
MCU_GPIO0_0
7
IO
pad
MCU_UART0_RXD
MCU_UART0_RXD
0
I
1
PADCONFIG:
MCU_PADCONFIG10
0x04084028
MCU_GPIO0_3
7
IO
pad
MCU_UART0_TXD
MCU_UART0_TXD
0
O
PADCONFIG:
MCU_PADCONFIG11
0x0408402C
MCU_GPIO0_2
7
IO
pad
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MCU_UART1_CTSn
B8
PADCONFIG:
MCU_PADCONFIG16
0x04084040
MCU_UART1_RTSn
B9
C9
PADCONFIG:
MCU_PADCONFIG17
0x04084044
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
MCU_UART1_CTSn
0
I
1
MCU_TIMER_IO2
1
IO
0
MCU_SPI0_CS3
2
IO
1
MCU_GPIO0_16
7
IO
pad
MCU_UART1_RTSn
0
O
MCU_TIMER_IO3
1
IO
0
MCU_SPI1_CS3
2
IO
1
MCU_GPIO0_17
7
IO
pad
MCU_UART1_RXD
MCU_UART1_RXD
0
I
1
PADCONFIG:
MCU_PADCONFIG14
0x04084038
MCU_GPIO0_14
7
IO
pad
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
1.8 V
VDDS_MMC0,
VDD_MMC0,
VDD_DLL_MMC0
eMMCPHY
MCU_UART1_TXD
MCU_UART1_TXD
0
O
D9
PADCONFIG:
MCU_PADCONFIG15
0x0408403C
MCU_GPIO0_15
7
IO
F18
MMC0_CALPAD
MMC0_CALPAD
A
G18
MMC0_CLK
MMC0_CLK
IO
On / Low / Off
On / SS / Off
1.8 V
VDDS_MMC0,
VDD_MMC0,
VDD_DLL_MMC0
eMMCPHY
PU/PD
J21
MMC0_CMD
MMC0_CMD
IO
On / Off / Up
On / SS / Up
1.8 V
VDDS_MMC0,
VDD_MMC0,
VDD_DLL_MMC0
eMMCPHY
PU/PD
G19
MMC0_DS
MMC0_DS
IO
On / Off / Down
On / Off / Down
1.8 V
VDDS_MMC0,
VDD_MMC0,
VDD_DLL_MMC0
eMMCPHY
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV5
Yes
SDIO
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV5
Yes
SDIO
PU/PD
L20
J19
pad
MMC1_CLK
0
MMC1_CLK
UART2_CTSn
1
IO
I
1
PADCONFIG:
PADCONFIG163
0x000F428C
TIMER_IO4
2
IO
0
UART4_RXD
3
I
1
GPIO1_75
7
IO
pad
MMC1_CMD
0
IO
1
MMC1_CMD
UART2_RTSn
1
O
PADCONFIG:
PADCONFIG165
0x000F4294
TIMER_IO5
2
IO
UART4_TXD
3
O
GPIO1_76
7
IO
0
pad
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
D19
C20
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
MMC1_SDCD
0
I
0
MMC1_SDCD
UART3_CTSn
1
I
1
PADCONFIG:
PADCONFIG166
0x000F4298
TIMER_IO6
2
IO
0
UART5_RXD
3
I
1
GPIO1_77
7
IO
pad
MMC1_SDWP
0
I
0
MMC1_SDWP
UART3_RTSn
1
O
PADCONFIG:
PADCONFIG167
0x000F429C
TIMER_IO7
2
IO
UART5_TXD
3
O
GPIO1_78
7
IO
0
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
pad
K20
MMC0_DAT0
MMC0_DAT0
IO
On / Off / Up
On / SS / Up
1.8 V
VDDS_MMC0,
VDD_MMC0,
VDD_DLL_MMC0
eMMCPHY
PU/PD
J20
MMC0_DAT1
MMC0_DAT1
IO
On / Off / Up
On / SS / Up
1.8 V
VDDS_MMC0,
VDD_MMC0,
VDD_DLL_MMC0
eMMCPHY
PU/PD
J18
MMC0_DAT2
MMC0_DAT2
IO
On / Off / Up
On / SS / Up
1.8 V
VDDS_MMC0,
VDD_MMC0,
VDD_DLL_MMC0
eMMCPHY
PU/PD
J17
MMC0_DAT3
MMC0_DAT3
IO
On / Off / Up
On / SS / Up
1.8 V
VDDS_MMC0,
VDD_MMC0,
VDD_DLL_MMC0
eMMCPHY
PU/PD
H17
MMC0_DAT4
MMC0_DAT4
IO
On / Off / Up
On / SS / Up
1.8 V
VDDS_MMC0,
VDD_MMC0,
VDD_DLL_MMC0
eMMCPHY
PU/PD
H19
MMC0_DAT5
MMC0_DAT5
IO
On / Off / Up
On / SS / Up
1.8 V
VDDS_MMC0,
VDD_MMC0,
VDD_DLL_MMC0
eMMCPHY
PU/PD
H18
MMC0_DAT6
MMC0_DAT6
IO
On / Off / Up
On / SS / Up
1.8 V
VDDS_MMC0,
VDD_MMC0,
VDD_DLL_MMC0
eMMCPHY
PU/PD
G17
MMC0_DAT7
MMC0_DAT7
IO
On / Off / Up
On / SS / Up
1.8 V
VDDS_MMC0,
VDD_MMC0,
VDD_DLL_MMC0
eMMCPHY
PU/PD
Off / Off / Off
Off / Off / Off
1.8 V/3.3 V
VDDSHV5
SDIO
PU/PD
K21
32
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MMC1_DAT0
0
IO
1
MMC1_DAT0
CP_GEMAC_CPTS0_HW2TSPUSH
1
I
0
PADCONFIG:
PADCONFIG162
0x000F4288
TIMER_IO3
2
IO
0
UART3_TXD
3
O
GPIO1_74
7
IO
7
Yes
pad
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
L21
K19
K18
N20
N19
N21
L19
L18
K17
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
MMC1_DAT1
0
IO
1
MMC1_DAT1
CP_GEMAC_CPTS0_HW1TSPUSH
1
I
0
PADCONFIG:
PADCONFIG161
0x000F4284
TIMER_IO2
2
IO
0
UART3_RXD
3
I
1
GPIO1_73
7
IO
pad
MMC1_DAT2
0
IO
1
MMC1_DAT2
CP_GEMAC_CPTS0_TS_SYNC
1
O
PADCONFIG:
PADCONFIG160
0x000F4280
TIMER_IO1
2
IO
UART2_TXD
3
O
GPIO1_72
7
IO
pad
MMC1_DAT3
0
IO
1
MMC1_DAT3
CP_GEMAC_CPTS0_TS_COMP
1
O
PADCONFIG:
PADCONFIG159
0x000F427C
TIMER_IO0
2
IO
0
UART2_RXD
3
I
1
pad
0
GPIO1_71
7
IO
OSPI0_CLK
OSPI0_CLK
0
O
PADCONFIG:
PADCONFIG0
0x000F4000
GPIO0_0
7
IO
pad
OSPI0_DQS
OSPI0_DQS
0
I
0
PADCONFIG:
PADCONFIG2
0x000F4008
GPIO0_2
7
IO
pad
OSPI0_LBCLKO
OSPI0_LBCLKO
0
IO
0
PADCONFIG:
PADCONFIG1
0x000F4004
GPIO0_1
7
IO
pad
OSPI0_CSn0
OSPI0_CSn0
0
O
PADCONFIG:
PADCONFIG11
0x000F402C
GPIO0_11
7
IO
OSPI0_CSn1
OSPI0_CSn1
0
O
PADCONFIG:
PADCONFIG12
0x000F4030
GPIO0_12
7
IO
OSPI0_CSn2
OSPI0_CSn2
0
O
PADCONFIG:
PADCONFIG13
0x000F4034
OSPI0_RESET_OUT1
2
O
GPIO0_13
7
IO
pad
pad
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV5
Yes
SDIO
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV5
Yes
SDIO
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV5
Yes
SDIO
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
pad
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
OSPI0_CSn3
L17
M19
M18
M20
M21
P21
P20
N18
M17
PADCONFIG:
PADCONFIG14
0x000F4038
MUX
MODE
[4]
TYPE
[5]
OSPI0_CSn3
0
O
OSPI0_RESET_OUT0
1
O
OSPI0_ECC_FAIL
2
I
1
SIGNAL NAME [3]
DSIS
[6]
GPIO0_14
7
IO
pad
OSPI0_D0
OSPI0_D0
0
IO
0
PADCONFIG:
PADCONFIG3
0x000F400C
GPIO0_3
7
IO
pad
OSPI0_D1
OSPI0_D1
0
IO
0
PADCONFIG:
PADCONFIG4
0x000F4010
GPIO0_4
7
IO
pad
OSPI0_D2
OSPI0_D2
0
IO
0
PADCONFIG:
PADCONFIG5
0x000F4014
GPIO0_5
7
IO
pad
OSPI0_D3
OSPI0_D3
0
IO
0
PADCONFIG:
PADCONFIG6
0x000F4018
GPIO0_6
7
IO
pad
OSPI0_D4
OSPI0_D4
0
IO
0
PADCONFIG:
PADCONFIG7
0x000F401C
GPIO0_7
7
IO
pad
OSPI0_D5
OSPI0_D5
0
IO
0
PADCONFIG:
PADCONFIG8
0x000F4020
GPIO0_8
7
IO
pad
OSPI0_D6
OSPI0_D6
0
IO
0
PADCONFIG:
PADCONFIG9
0x000F4024
GPIO0_9
7
IO
pad
OSPI0_D7
OSPI0_D7
0
IO
0
PADCONFIG:
PADCONFIG10
0x000F4028
GPIO0_10
7
IO
pad
PADCONFIG:
PADCONFIG171
0x000F42AC
PORz_OUT
0
O
PRG0_MDIO0_MDC
PRG0_MDIO0_MDC
0
O
PADCONFIG:
PADCONFIG129
0x000F4204
GPIO1_41
7
IO
GPMC0_A13
9
OZ
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
LVCMOS
PU/PD
Off / Low / Off
Off / SS / Off
0
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
PORz_OUT
E17
P3
34
pad
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
P2
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
U2
PRG0_MDIO0_MDIO
0
IO
0
GPIO1_40
7
IO
pad
GPMC0_A12
9
OZ
PRG0_PRU0_GPO0
0
IO
0
PRG0_PRU0_GPI0
1
I
0
PRG0_RGMII1_RD0
2
I
0
PRG0_PWM3_A0
3
IO
0
GPIO1_0
7
IO
pad
UART2_CTSn
10
I
1
PRG0_PRU0_GPO1
0
IO
0
PRG0_PRU0_GPI1
1
I
0
PRG0_RGMII1_RD1
2
I
0
PRG0_PWM3_B0
3
IO
1
GPIO1_1
7
IO
pad
UART2_TXD
10
O
PRG0_PRU0_GPO2
0
IO
0
PRG0_PRU0_GPI2
1
I
0
PRG0_PRU0_GPO2
PRG0_RGMII1_RD2
2
I
0
PADCONFIG:
PADCONFIG90
0x000F4168
PRG0_PWM2_A0
3
IO
0
GPIO1_2
7
IO
pad
GPMC0_A0
9
OZ
UART2_RTSn
10
O
PRG0_PRU0_GPO3
0
IO
0
PRG0_PRU0_GPI3
1
I
0
PRG0_RGMII1_RD3
2
I
0
PRG0_PWM3_A2
3
IO
0
GPIO1_3
7
IO
pad
UART3_CTSn
10
I
1
PRG0_PRU0_GPO4
0
IO
0
PRG0_PRU0_GPI4
1
I
0
PRG0_PRU0_GPO4
PRG0_RGMII1_RX_CTL
2
I
0
PADCONFIG:
PADCONFIG92
0x000F4170
PRG0_PWM2_B0
3
IO
1
GPIO1_4
7
IO
pad
GPMC0_A1
9
OZ
UART3_TXD
10
O
PADCONFIG:
PADCONFIG88
0x000F4160
PADCONFIG:
PADCONFIG89
0x000F4164
PRG0_PRU0_GPO3
V2
AA2
DSIS
[6]
PADCONFIG:
PADCONFIG128
0x000F4200
PRG0_PRU0_GPO1
R4
TYPE
[5]
PRG0_MDIO0_MDIO
PRG0_PRU0_GPO0
Y1
SIGNAL NAME [3]
MUX
MODE
[4]
PADCONFIG:
PADCONFIG91
0x000F416C
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
R3
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
T1
W6
36
DSIS
[6]
PRG0_PRU0_GPO5
0
IO
0
PRG0_PRU0_GPI5
1
I
0
PADCONFIG:
PADCONFIG93
0x000F4174
PRG0_PWM3_B2
3
IO
1
GPIO1_5
7
IO
pad
UART3_RTSn
10
O
PRG0_PRU0_GPO6
0
IO
0
PRG0_PRU0_GPI6
1
I
0
PRG0_RGMII1_RXC
2
I
0
PRG0_PWM3_A1
3
IO
0
GPIO1_6
7
IO
pad
UART4_CTSn
10
I
1
PRG0_PRU0_GPO7
0
IO
0
PRG0_PRU0_GPI7
1
I
0
PRG0_IEP0_EDC_LATCH_IN1
2
I
0
PRG0_PRU0_GPO7
PRG0_PWM3_B1
3
IO
1
PADCONFIG:
PADCONFIG95
0x000F417C
CPTS0_HW2TSPUSH
4
I
0
CP_GEMAC_CPTS0_HW2TSPUSH
5
I
0
TIMER_IO6
6
IO
0
GPIO1_7
7
IO
pad
UART4_TXD
10
O
PRG0_PRU0_GPO8
0
IO
0
PRG0_PRU0_GPI8
1
I
0
PRG0_PWM2_A1
3
IO
0
GPIO1_8
7
IO
pad
GPMC0_A2
9
OZ
UART4_RTSn
10
O
PRG0_PRU0_GPO9
0
IO
0
PRG0_PRU0_GPI9
1
I
0
PRG0_UART0_CTSn
2
I
1
PRG0_PRU0_GPO9
PRG0_PWM3_TZ_IN
3
I
0
PADCONFIG:
PADCONFIG97
0x000F4184
RGMII1_RX_CTL
4
I
0
RMII1_RX_ER
5
I
0
PRG0_IEP0_EDIO_DATA_IN_OUT28
6
IO
0
GPIO1_9
7
IO
pad
UART2_RXD
10
I
1
PADCONFIG:
PADCONFIG94
0x000F4178
PRG0_PRU0_GPO8
T2
TYPE
[5]
PRG0_PRU0_GPO5
PRG0_PRU0_GPO6
T3
SIGNAL NAME [3]
MUX
MODE
[4]
PADCONFIG:
PADCONFIG96
0x000F4180
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
AA5
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
PRG0_PRU0_GPO10
0
IO
0
PRG0_PRU0_GPI10
1
I
0
PRG0_UART0_RTSn
2
O
PRG0_PRU0_GPO10
PRG0_PWM2_B1
3
IO
1
PADCONFIG:
PADCONFIG98
0x000F4188
RGMII1_RXC
4
I
0
RMII_REF_CLK
5
I
0
PRG0_IEP0_EDIO_DATA_IN_OUT29
6
IO
0
GPIO1_10
7
IO
pad
UART3_RXD
10
I
1
PRG0_PRU0_GPO11
0
IO
0
PRG0_PRU0_GPI11
1
I
0
PRG0_RGMII1_TD0
2
O
PRG0_PWM3_TZ_OUT
3
O
GPIO1_11
7
IO
pad
UART4_RXD
10
I
1
PRG0_PRU0_GPO12
0
IO
0
PRG0_PRU0_GPI12
1
I
0
PRG0_RGMII1_TD1
2
O
PRG0_PWM0_A0
3
IO
0
GPIO1_12
7
IO
pad
GPMC0_A14
9
OZ
PRG0_PRU0_GPO13
0
IO
0
PRG0_PRU0_GPI13
1
I
0
PRG0_PRU0_GPO13
PRG0_RGMII1_TD2
2
O
PADCONFIG:
PADCONFIG101
0x000F4194
PRG0_PWM0_B0
3
IO
1
SPI3_D0
6
IO
0
GPIO1_13
7
IO
pad
GPMC0_A15
9
OZ
PRG0_PRU0_GPO14
0
IO
0
PRG0_PRU0_GPI14
1
I
0
PRG0_PRU0_GPO14
PRG0_RGMII1_TD3
2
O
PADCONFIG:
PADCONFIG102
0x000F4198
PRG0_PWM0_A1
3
IO
0
SPI3_D1
6
IO
0
GPIO1_14
7
IO
pad
GPMC0_A3
9
OZ
PRG0_PRU0_GPO11
Y3
PADCONFIG:
PADCONFIG99
0x000F418C
PRG0_PRU0_GPO12
AA3
R6
V4
PADCONFIG:
PADCONFIG100
0x000F4190
SIGNAL NAME [3]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
T5
U4
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
PRG0_PRU0_GPO15
0
IO
0
PRG0_PRU0_GPI15
1
I
0
PRG0_PRU0_GPO15
PRG0_RGMII1_TX_CTL
2
O
PADCONFIG:
PADCONFIG103
0x000F419C
PRG0_PWM0_B1
3
IO
1
SPI3_CS1
6
IO
1
GPIO1_15
7
IO
pad
GPMC0_A16
9
OZ
PRG0_PRU0_GPO16
0
IO
0
PRG0_PRU0_GPI16
1
I
0
PRG0_PRU0_GPO16
PRG0_RGMII1_TXC
2
IO
0
PADCONFIG:
PADCONFIG104
0x000F41A0
PRG0_PWM0_A2
3
IO
0
SPI3_CLK
6
IO
0
GPIO1_16
7
IO
pad
GPMC0_A4
9
OZ
PRG0_PRU0_GPO17
0
IO
0
PRG0_PRU0_GPI17
1
I
0
PRG0_IEP0_EDC_SYNC_OUT1
2
O
PRG0_PWM0_B2
3
IO
CPTS0_TS_SYNC
4
O
CP_GEMAC_CPTS0_TS_SYNC
5
O
SPI3_CS0
6
IO
1
GPIO1_17
7
IO
pad
TIMER_IO11
8
IO
0
GPMC0_A17
9
OZ
PRG0_PRU0_GPO18
0
IO
0
PRG0_PRU0_GPI18
1
I
0
PRG0_IEP0_EDC_LATCH_IN0
2
I
0
PRG0_PWM0_TZ_IN
3
I
0
PRG0_PRU0_GPO18
CPTS0_HW1TSPUSH
4
I
0
PADCONFIG:
PADCONFIG106
0x000F41A8
CP_GEMAC_CPTS0_HW1TSPUSH
5
I
0
EHRPWM8_A
6
IO
0
GPIO1_18
7
IO
pad
UART4_CTSn
8
I
1
GPMC0_A5
9
OZ
UART2_RXD
10
I
PRG0_PRU0_GPO17
U1
V1
38
PADCONFIG:
PADCONFIG105
0x000F41A4
SIGNAL NAME [3]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
1
1
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
W1
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
V3
T4
DSIS
[6]
PRG0_PRU0_GPO19
0
IO
0
PRG0_PRU0_GPI19
1
I
0
PRG0_IEP0_EDC_SYNC_OUT0
2
O
SIGNAL NAME [3]
PRG0_PWM0_TZ_OUT
3
O
CPTS0_TS_COMP
4
O
PADCONFIG:
PADCONFIG107
0x000F41AC
CP_GEMAC_CPTS0_TS_COMP
5
O
EHRPWM8_B
6
IO
0
GPIO1_19
7
IO
pad
UART4_RTSn
8
O
GPMC0_A6
9
OZ
UART3_RXD
10
I
1
PRG0_PRU1_GPO0
0
IO
0
PRG0_PRU1_GPI0
1
I
0
PRG0_RGMII2_RD0
2
I
0
GPIO1_20
7
IO
pad
EQEP0_A
8
I
0
UART5_CTSn
10
I
1
PRG0_PRU1_GPO1
0
IO
0
PRG0_PRU1_GPI1
1
I
0
PRG0_RGMII2_RD1
2
I
0
GPIO1_21
7
IO
pad
0
PADCONFIG:
PADCONFIG108
0x000F41B0
PRG0_PRU1_GPO1
W2
TYPE
[5]
PRG0_PRU0_GPO19
PRG0_PRU1_GPO0
Y2
MUX
MODE
[4]
PADCONFIG:
PADCONFIG109
0x000F41B4
EQEP0_B
8
I
UART5_TXD
10
O
PRG0_PRU1_GPO2
0
IO
0
PRG0_PRU1_GPI2
1
I
0
PRG0_PRU1_GPO2
PRG0_RGMII2_RD2
2
I
0
PADCONFIG:
PADCONFIG110
0x000F41B8
PRG0_PWM2_A2
3
IO
0
GPIO1_22
7
IO
pad
EQEP0_S
8
IO
0
UART5_RTSn
10
O
PRG0_PRU1_GPO3
0
IO
0
PRG0_PRU1_GPI3
1
I
0
PRG0_PRU1_GPO3
PRG0_RGMII2_RD3
2
I
0
PADCONFIG:
PADCONFIG111
0x000F41BC
GPIO1_23
7
IO
pad
EQEP1_A
8
I
0
GPMC0_A18
9
OZ
UART6_CTSn
10
I
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
1
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
W3
P4
R5
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
PRG0_PRU1_GPO4
0
IO
0
PRG0_PRU1_GPI4
1
I
0
PRG0_PRU1_GPO4
PRG0_RGMII2_RX_CTL
2
I
0
PADCONFIG:
PADCONFIG112
0x000F41C0
PRG0_PWM2_B2
3
IO
1
GPIO1_24
7
IO
pad
0
40
8
I
UART6_TXD
10
O
PRG0_PRU1_GPO5
0
IO
PRG0_PRU1_GPI5
1
I
0
PADCONFIG:
PADCONFIG113
0x000F41C4
GPIO1_25
7
IO
pad
EQEP1_S
8
IO
0
UART6_RTSn
10
O
PRG0_PRU1_GPO6
0
IO
0
PRG0_PRU1_GPI6
1
I
0
PRG0_PRU1_GPO6
PRG0_RGMII2_RXC
2
I
0
PADCONFIG:
PADCONFIG114
0x000F41C8
GPIO1_26
7
IO
pad
EQEP2_A
8
I
0
GPMC0_A19
9
OZ
UART4_CTSn
10
I
1
PRG0_PRU1_GPO7
0
IO
0
PRG0_PRU1_GPI7
1
I
0
PRG0_IEP1_EDC_LATCH_IN1
2
I
0
RGMII1_RD0
4
I
0
RMII1_RXD0
5
I
0
GPIO1_27
7
IO
pad
EQEP2_B
8
I
0
UART4_TXD
10
O
PRG0_PRU1_GPO8
0
IO
0
PRG0_PRU1_GPI8
1
I
0
PRG0_PWM2_TZ_OUT
3
O
GPIO1_28
7
IO
pad
EQEP2_S
8
IO
0
UART4_RTSn
10
O
PADCONFIG:
PADCONFIG115
0x000F41CC
PRG0_PRU1_GPO8
R1
EQEP1_B
PRG0_PRU1_GPO5
PRG0_PRU1_GPO7
W5
SIGNAL NAME [3]
PADCONFIG:
PADCONFIG116
0x000F41D0
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
0
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
Y5
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
PRG0_PRU1_GPO9
0
IO
0
PRG0_PRU1_GPI9
1
I
0
PRG0_UART0_RXD
2
I
1
PRG0_PRU1_GPO9
RGMII1_RD1
4
I
0
PADCONFIG:
PADCONFIG117
0x000F41D4
RMII1_RXD1
5
I
0
PRG0_IEP0_EDIO_DATA_IN_OUT30
6
IO
0
GPIO1_29
7
IO
pad
EQEP0_I
8
IO
0
UART5_RXD
10
I
1
PRG0_PRU1_GPO10
0
IO
0
PRG0_PRU1_GPI10
1
I
0
PRG0_UART0_TXD
2
O
PRG0_PWM2_TZ_IN
3
I
0
RGMII1_RD2
4
I
0
RMII1_TXD0
5
O
PRG0_IEP0_EDIO_DATA_IN_OUT31
6
IO
0
GPIO1_30
7
IO
pad
EQEP1_I
8
IO
0
UART6_RXD
10
I
1
PRG0_PRU1_GPO11
0
IO
0
PRG0_PRU1_GPI11
1
I
0
PRG0_RGMII2_TD0
2
O
GPIO1_31
7
IO
pad
EQEP2_I
8
IO
0
UART4_RXD
10
I
1
PRG0_PRU1_GPO12
0
IO
0
PRG0_PRU1_GPI12
1
I
0
PRG0_RGMII2_TD1
2
O
PRG0_PWM1_A0
3
IO
0
GPIO1_32
7
IO
pad
EQEP2_B
8
I
0
GPMC0_A7
9
OZ
UART4_TXD
10
O
PRG0_PRU1_GPO10
V6
PADCONFIG:
PADCONFIG118
0x000F41D8
PRG0_PRU1_GPO11
W4
PADCONFIG:
PADCONFIG119
0x000F41DC
PRG0_PRU1_GPO12
Y4
PADCONFIG:
PADCONFIG120
0x000F41E0
SIGNAL NAME [3]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
PRG0_PRU1_GPO13
0
IO
0
PRG0_PRU1_GPI13
1
I
0
PRG0_RGMII2_TD2
2
O
PRG0_PWM1_B0
3
IO
1
GPIO1_33
7
IO
pad
EQEP0_I
8
IO
0
GPMC0_A8
9
OZ
UART5_RXD
10
I
1
PRG0_PRU1_GPO14
0
IO
0
PRG0_PRU1_GPI14
1
I
0
PRG0_RGMII2_TD3
2
O
PRG0_PWM1_A1
3
IO
0
GPIO1_34
7
IO
pad
EQEP1_I
8
IO
0
GPMC0_A9
9
OZ
UART6_RXD
10
I
1
PRG0_PRU1_GPO15
0
IO
0
PRG0_PRU1_GPI15
1
I
0
PRG0_PRU1_GPO15
PRG0_RGMII2_TX_CTL
2
O
PADCONFIG:
PADCONFIG123
0x000F41EC
PRG0_PWM1_B1
3
IO
1
GPIO1_35
7
IO
pad
GPMC0_A10
9
OZ
PRG0_ECAP0_IN_APWM_OUT
10
IO
0
PRG0_PRU1_GPO16
0
IO
0
PRG0_PRU1_GPI16
1
I
0
PRG0_PRU1_GPO16
PRG0_RGMII2_TXC
2
IO
0
PADCONFIG:
PADCONFIG124
0x000F41F0
PRG0_PWM1_A2
3
IO
0
GPIO1_36
7
IO
pad
GPMC0_A11
9
OZ
PRG0_ECAP0_SYNC_OUT
10
O
PRG0_PRU1_GPO13
T6
PADCONFIG:
PADCONFIG121
0x000F41E4
PRG0_PRU1_GPO14
U6
U5
AA4
42
PADCONFIG:
PADCONFIG122
0x000F41E8
SIGNAL NAME [3]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
V5
P5
R2
Y6
AA6
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
PRG0_PRU1_GPO17
0
IO
0
PRG0_PRU1_GPI17
1
I
0
PRG0_IEP1_EDC_SYNC_OUT1
2
O
PRG0_PRU1_GPO17
PRG0_PWM1_B2
3
IO
1
PADCONFIG:
PADCONFIG125
0x000F41F4
RGMII1_RD3
4
I
0
RMII1_TXD1
5
O
GPIO1_37
7
IO
PRG0_ECAP0_SYNC_OUT
8
O
PRG0_ECAP0_SYNC_IN
10
I
0
PRG0_PRU1_GPO18
0
IO
0
PRG0_PRU1_GPI18
1
I
0
PRG0_IEP1_EDC_LATCH_IN0
2
I
0
PRG0_PRU1_GPO18
PRG0_PWM1_TZ_IN
3
I
0
PADCONFIG:
PADCONFIG126
0x000F41F8
MDIO0_MDIO
4
IO
0
RMII1_TX_EN
5
O
EHRPWM7_A
6
IO
0
GPIO1_38
7
IO
pad
PRG0_ECAP0_SYNC_IN
8
I
0
PRG0_PRU1_GPO19
0
IO
0
PRG0_PRU1_GPI19
1
I
0
PRG0_IEP1_EDC_SYNC_OUT0
2
O
PRG0_PRU1_GPO19
PRG0_PWM1_TZ_OUT
3
O
PADCONFIG:
PADCONFIG127
0x000F41FC
MDIO0_MDC
4
O
RMII1_CRS_DV
5
I
EHRPWM7_B
6
IO
0
GPIO1_39
7
IO
pad
0
SIGNAL NAME [3]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
pad
0
PRG0_ECAP0_IN_APWM_OUT
8
IO
PRG1_MDIO0_MDC
PRG1_MDIO0_MDC
0
O
PADCONFIG:
PADCONFIG87
0x000F415C
MDIO0_MDC
4
O
GPIO0_86
7
IO
pad
PRG1_MDIO0_MDIO
PRG1_MDIO0_MDIO
0
IO
0
PADCONFIG:
PADCONFIG86
0x000F4158
MDIO0_MDIO
4
IO
0
GPIO0_85
7
IO
pad
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
PRG1_PRU0_GPO0
Y7
PADCONFIG:
PADCONFIG46
0x000F40B8
PRG1_PRU0_GPO1
U8
PADCONFIG:
PADCONFIG47
0x000F40BC
PRG1_PRU0_GPO2
W8
PADCONFIG:
PADCONFIG48
0x000F40C0
PRG1_PRU0_GPO3
V8
PADCONFIG:
PADCONFIG49
0x000F40C4
PRG1_PRU0_GPO4
Y8
PADCONFIG:
PADCONFIG50
0x000F40C8
PRG1_PRU0_GPO5
V13
44
PADCONFIG:
PADCONFIG51
0x000F40CC
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
PRG1_PRU0_GPO0
0
IO
0
PRG1_PRU0_GPI0
1
I
0
PRG1_RGMII1_RD0
2
I
0
PRG1_PWM3_A0
3
IO
0
GPIO0_45
7
IO
pad
GPMC0_AD16
8
IO
0
PRG1_PRU0_GPO1
0
IO
0
PRG1_PRU0_GPI1
1
I
0
PRG1_RGMII1_RD1
2
I
0
PRG1_PWM3_B0
3
IO
1
GPIO0_46
7
IO
pad
GPMC0_AD17
8
IO
0
PRG1_PRU0_GPO2
0
IO
0
PRG1_PRU0_GPI2
1
I
0
PRG1_RGMII1_RD2
2
I
0
PRG1_PWM2_A0
3
IO
0
GPIO0_47
7
IO
pad
GPMC0_AD18
8
IO
0
PRG1_PRU0_GPO3
0
IO
0
PRG1_PRU0_GPI3
1
I
0
PRG1_RGMII1_RD3
2
I
0
PRG1_PWM3_A2
3
IO
0
GPIO0_48
7
IO
pad
GPMC0_AD19
8
IO
0
PRG1_PRU0_GPO4
0
IO
0
PRG1_PRU0_GPI4
1
I
0
PRG1_RGMII1_RX_CTL
2
I
0
PRG1_PWM2_B0
3
IO
1
GPIO0_49
7
IO
pad
GPMC0_AD20
8
IO
0
PRG1_PRU0_GPO5
0
IO
0
PRG1_PRU0_GPI5
1
I
0
PRG1_PWM3_B2
3
IO
1
RGMII1_RX_CTL
4
I
0
GPIO0_50
7
IO
pad
GPMC0_AD21
8
IO
0
SIGNAL NAME [3]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
PRG1_PRU0_GPO6
0
IO
0
PRG1_PRU0_GPI6
1
I
0
PRG1_RGMII1_RXC
2
I
0
PRG1_PWM3_A1
3
IO
0
GPIO0_51
7
IO
pad
GPMC0_AD22
8
IO
0
PRG1_PRU0_GPO7
0
IO
0
PRG1_PRU0_GPI7
1
I
0
PRG1_IEP0_EDC_LATCH_IN1
2
I
0
PRG1_PRU0_GPO7
PRG1_PWM3_B1
3
IO
1
PADCONFIG:
PADCONFIG53
0x000F40D4
CPTS0_HW2TSPUSH
4
I
0
CLKOUT0
5
O
TIMER_IO10
6
IO
0
GPIO0_52
7
IO
pad
GPMC0_AD23
8
IO
0
PRG1_PRU0_GPO8
0
IO
0
PRG1_PRU0_GPI8
1
I
0
PRG1_PWM2_A1
3
IO
0
RGMII1_RXC
4
I
0
GPIO0_53
7
IO
pad
GPMC0_AD24
8
IO
0
PRG1_PRU0_GPO9
0
IO
0
PRG1_PRU0_GPI9
1
I
0
PRG1_UART0_CTSn
2
I
1
PRG1_PRU0_GPO9
PRG1_PWM3_TZ_IN
3
I
0
PADCONFIG:
PADCONFIG55
0x000F40DC
RGMII1_TX_CTL
4
O
RMII1_RX_ER
5
I
PRG1_IEP0_EDIO_DATA_IN_OUT28
6
IO
0
GPIO0_54
7
IO
pad
GPMC0_AD25
8
IO
0
PRG1_PRU0_GPO6
AA7
U13
PADCONFIG:
PADCONFIG52
0x000F40D0
PRG1_PRU0_GPO8
W13
U15
PADCONFIG:
PADCONFIG54
0x000F40D8
SIGNAL NAME [3]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
0
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www.ti.com
SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
U14
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
PRG1_PRU0_GPO10
0
IO
0
PRG1_PRU0_GPI10
1
I
0
PRG1_UART0_RTSn
2
O
PRG1_PRU0_GPO10
PRG1_PWM2_B1
3
IO
1
PADCONFIG:
PADCONFIG56
0x000F40E0
RGMII1_TXC
4
IO
0
RMII_REF_CLK
5
I
0
PRG1_IEP0_EDIO_DATA_IN_OUT29
6
IO
0
GPIO0_55
7
IO
pad
GPMC0_AD26
8
IO
0
PRG1_PRU0_GPO11
0
IO
0
PRG1_PRU0_GPI11
1
I
0
PRG1_RGMII1_TD0
2
O
PRG1_PWM3_TZ_OUT
3
O
GPIO0_56
7
IO
pad
GPMC0_AD27
8
IO
0
PRG1_PRU0_GPO12
0
IO
0
PRG1_PRU0_GPI12
1
I
0
PRG1_RGMII1_TD1
2
O
PRG1_PWM0_A0
3
IO
0
GPIO0_57
7
IO
pad
GPMC0_AD28
8
IO
0
PRG1_PRU0_GPO13
0
IO
0
PRG1_PRU0_GPI13
1
I
0
PRG1_RGMII1_TD2
2
O
PRG1_PWM0_B0
3
IO
1
GPIO0_58
7
IO
pad
GPMC0_AD29
8
IO
0
PRG1_PRU0_GPO14
0
IO
0
PRG1_PRU0_GPI14
1
I
0
PRG1_RGMII1_TD3
2
O
PRG1_PWM0_A1
3
IO
0
GPIO0_59
7
IO
pad
GPMC0_AD30
8
IO
0
PRG1_PRU0_GPO11
AA8
PADCONFIG:
PADCONFIG57
0x000F40E4
PRG1_PRU0_GPO12
U9
PADCONFIG:
PADCONFIG58
0x000F40E8
PRG1_PRU0_GPO13
W9
PADCONFIG:
PADCONFIG59
0x000F40EC
PRG1_PRU0_GPO14
AA9
46
PADCONFIG:
PADCONFIG60
0x000F40F0
SIGNAL NAME [3]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
PRG1_PRU0_GPO15
Y9
PADCONFIG:
PADCONFIG61
0x000F40F4
PRG1_PRU0_GPO16
V9
PADCONFIG:
PADCONFIG62
0x000F40F8
PRG1_PRU0_GPO17
U7
PADCONFIG:
PADCONFIG63
0x000F40FC
PRG1_PRU0_GPO18
V7
PADCONFIG:
PADCONFIG64
0x000F4100
PRG1_PRU0_GPO19
W7
PADCONFIG:
PADCONFIG65
0x000F4104
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
PRG1_PRU0_GPO15
0
IO
0
PRG1_PRU0_GPI15
1
I
0
PRG1_RGMII1_TX_CTL
2
O
PRG1_PWM0_B1
3
IO
1
GPIO0_60
7
IO
pad
GPMC0_AD31
8
IO
0
PRG1_PRU0_GPO16
0
IO
0
PRG1_PRU0_GPI16
1
I
0
PRG1_RGMII1_TXC
2
IO
0
PRG1_PWM0_A2
3
IO
0
GPIO0_61
7
IO
pad
GPMC0_BE2n
8
O
PRG1_PRU0_GPO17
0
IO
0
PRG1_PRU0_GPI17
1
I
0
PRG1_IEP0_EDC_SYNC_OUT1
2
O
PRG1_PWM0_B2
3
IO
CPTS0_TS_SYNC
4
O
TIMER_IO7
6
IO
0
GPIO0_62
7
IO
pad
GPMC0_A0
8
OZ
PRG1_PRU0_GPO18
0
IO
0
PRG1_PRU0_GPI18
1
I
0
PRG1_IEP0_EDC_LATCH_IN0
2
I
0
PRG1_PWM0_TZ_IN
3
I
0
CPTS0_HW1TSPUSH
4
I
0
TIMER_IO8
6
IO
0
GPIO0_63
7
IO
pad
GPMC0_A1
8
OZ
PRG1_PRU0_GPO19
0
IO
0
PRG1_PRU0_GPI19
1
I
0
PRG1_IEP0_EDC_SYNC_OUT0
2
O
PRG1_PWM0_TZ_OUT
3
O
CPTS0_TS_COMP
4
O
TIMER_IO9
6
IO
0
GPIO0_64
7
IO
pad
GPMC0_A2
8
OZ
SIGNAL NAME [3]
1
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
W11
V11
AA12
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
PRG1_PRU1_GPO0
0
IO
0
PRG1_PRU1_GPI0
1
I
0
PRG1_PRU1_GPO0
PRG1_RGMII2_RD0
2
I
0
PADCONFIG:
PADCONFIG66
0x000F4108
RGMII2_RD0
4
I
0
RMII2_RXD0
5
I
0
GPIO0_65
7
IO
pad
GPMC0_A3
8
OZ
PRG1_PRU1_GPO1
0
IO
0
PRG1_PRU1_GPI1
1
I
0
PRG1_PRU1_GPO1
PRG1_RGMII2_RD1
2
I
0
PADCONFIG:
PADCONFIG67
0x000F410C
RGMII2_RD1
4
I
0
RMII2_RXD1
5
I
0
GPIO0_66
7
IO
pad
GPMC0_A4
8
OZ
PRG1_PRU1_GPO2
0
IO
0
PRG1_PRU1_GPI2
1
I
0
PRG1_PRU1_GPO2
PRG1_RGMII2_RD2
2
I
0
PADCONFIG:
PADCONFIG68
0x000F4110
PRG1_PWM2_A2
3
IO
0
RGMII2_RD2
4
I
0
GPIO0_67
7
IO
pad
GPMC0_A5
8
OZ
PRG1_PRU1_GPO3
0
IO
0
PRG1_PRU1_GPI3
1
I
0
PRG1_RGMII2_RD3
2
I
0
RGMII2_RD3
4
I
0
GPIO0_68
7
IO
pad
GPMC0_A6
8
OZ
PRG1_PRU1_GPO4
0
IO
0
PRG1_PRU1_GPI4
1
I
0
PRG1_RGMII2_RX_CTL
2
I
0
PRG1_PWM2_B2
3
IO
1
RGMII2_RX_CTL
4
I
0
RMII2_RX_ER
5
I
0
GPIO0_69
7
IO
pad
GPMC0_A7
8
OZ
PRG1_PRU1_GPO3
Y12
PADCONFIG:
PADCONFIG69
0x000F4114
PRG1_PRU1_GPO4
W12
48
PADCONFIG:
PADCONFIG70
0x000F4118
SIGNAL NAME [3]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
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www.ti.com
SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
AA13
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
0
IO
0
PRG1_PRU1_GPI5
1
I
0
PADCONFIG:
PADCONFIG71
0x000F411C
RGMII1_RD0
4
I
0
GPIO0_70
7
IO
pad
GPMC0_A8
8
OZ
PRG1_PRU1_GPO6
0
IO
0
PRG1_PRU1_GPI6
1
I
0
PRG1_RGMII2_RXC
2
I
0
RGMII2_RXC
4
I
0
GPIO0_71
7
IO
pad
GPMC0_A9
8
OZ
PRG1_PRU1_GPO7
0
IO
0
PRG1_PRU1_GPI7
1
I
0
PRG1_IEP1_EDC_LATCH_IN1
2
I
0
RGMII1_TD0
4
O
RMII1_RXD0
5
I
SPI3_CS3
6
IO
1
GPIO0_72
7
IO
pad
GPMC0_A10
8
OZ
PRG1_PRU1_GPO8
0
IO
0
PRG1_PRU1_GPI8
1
I
0
PRG1_PWM2_TZ_OUT
3
O
RGMII1_RD1
4
I
0
GPIO0_73
7
IO
pad
GPMC0_A11
8
OZ
PRG1_PRU1_GPO9
0
IO
0
PRG1_PRU1_GPI9
1
I
0
PRG1_UART0_RXD
2
I
1
RGMII1_TD1
4
O
RMII1_RXD1
5
I
PRG1_IEP0_EDIO_DATA_IN_OUT30
6
IO
0
GPIO0_74
7
IO
pad
GPMC0_A12
8
OZ
PADCONFIG:
PADCONFIG72
0x000F4120
PADCONFIG:
PADCONFIG73
0x000F4124
PRG1_PRU1_GPO8
U12
PADCONFIG:
PADCONFIG74
0x000F4128
PRG1_PRU1_GPO9
V14
DSIS
[6]
PRG1_PRU1_GPO5
PRG1_PRU1_GPO7
V15
TYPE
[5]
PRG1_PRU1_GPO5
PRG1_PRU1_GPO6
U11
SIGNAL NAME [3]
MUX
MODE
[4]
PADCONFIG:
PADCONFIG75
0x000F412C
0
0
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
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AM6442, AM6441, AM6422, AM6421, AM6412, AM6411
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
W14
AA10
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
PRG1_PRU1_GPO10
0
IO
0
PRG1_PRU1_GPI10
1
I
0
PRG1_UART0_TXD
2
O
PRG1_PRU1_GPO10
PRG1_PWM2_TZ_IN
3
I
PADCONFIG:
PADCONFIG76
0x000F4130
RGMII1_TD2
4
O
RMII1_TXD0
5
O
PRG1_IEP0_EDIO_DATA_IN_OUT31
6
IO
0
GPIO0_75
7
IO
pad
GPMC0_A13
8
OZ
PRG1_PRU1_GPO11
0
IO
0
PRG1_PRU1_GPI11
1
I
0
PRG1_PRU1_GPO11
PRG1_RGMII2_TD0
2
O
PADCONFIG:
PADCONFIG77
0x000F4134
RGMII2_TD0
4
O
RMII2_TXD0
5
O
GPIO0_76
7
IO
GPMC0_A14
8
OZ
PRG1_PRU1_GPO12
0
IO
0
PRG1_PRU1_GPI12
1
I
0
PRG1_RGMII2_TD1
2
O
PRG1_PWM1_A0
3
IO
RGMII2_TD1
4
O
RMII2_TXD1
5
O
GPIO0_77
7
IO
GPMC0_A15
8
OZ
PRG1_PRU1_GPO13
0
IO
0
PRG1_PRU1_GPI13
1
I
0
PRG1_RGMII2_TD2
2
O
PRG1_PWM1_B0
3
IO
RGMII2_TD2
4
O
RMII2_CRS_DV
5
I
0
GPIO0_78
7
IO
pad
GPMC0_A16
8
OZ
PRG1_PRU1_GPO12
V10
PADCONFIG:
PADCONFIG78
0x000F4138
PRG1_PRU1_GPO13
U10
50
PADCONFIG:
PADCONFIG79
0x000F413C
SIGNAL NAME [3]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
0
pad
0
pad
1
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
AA11
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
PRG1_PRU1_GPO14
0
IO
0
PRG1_PRU1_GPI14
1
I
0
PRG1_PRU1_GPO14
PRG1_RGMII2_TD3
2
O
PADCONFIG:
PADCONFIG80
0x000F4140
PRG1_PWM1_A1
3
IO
RGMII2_TD3
4
O
GPIO0_79
7
IO
GPMC0_A17
8
OZ
PRG1_PRU1_GPO15
0
IO
0
PRG1_PRU1_GPI15
1
I
0
PRG1_RGMII2_TX_CTL
2
O
PRG1_PWM1_B1
3
IO
RGMII2_TX_CTL
4
O
RMII2_TX_EN
5
O
GPIO0_80
7
IO
GPMC0_A18
8
OZ
PRG1_PRU1_GPO16
0
IO
0
PRG1_PRU1_GPI16
1
I
0
PRG1_PRU1_GPO16
PRG1_RGMII2_TXC
2
IO
0
PADCONFIG:
PADCONFIG82
0x000F4148
PRG1_PWM1_A2
3
IO
0
RGMII2_TXC
4
IO
0
GPIO0_81
7
IO
pad
GPMC0_A19
8
OZ
PRG1_PRU1_GPO17
0
IO
0
PRG1_PRU1_GPI17
1
I
0
PRG1_IEP1_EDC_SYNC_OUT1
2
O
PRG1_PRU1_GPO17
PRG1_PWM1_B2
3
IO
PADCONFIG:
PADCONFIG83
0x000F414C
RGMII1_TD3
4
O
RMII1_TXD1
5
O
GPIO0_19
7
IO
GPMC0_BE3n
8
O
PRG1_ECAP0_SYNC_OUT
9
O
PRG1_PRU1_GPO15
Y11
Y10
AA14
PADCONFIG:
PADCONFIG81
0x000F4144
SIGNAL NAME [3]
0
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
pad
1
pad
1
pad
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AM6442, AM6441, AM6422, AM6421, AM6412, AM6411
www.ti.com
SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
Y13
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
O
Off / Low / Off
Off / SS / Off
0
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
I
On / Off / Up
On / Off / Up
0
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
TYPE
[5]
DSIS
[6]
PRG1_PRU1_GPO18
0
IO
0
PRG1_PRU1_GPI18
1
I
0
PRG1_IEP1_EDC_LATCH_IN0
2
I
0
PRG1_PRU1_GPO18
PRG1_PWM1_TZ_IN
3
I
0
PADCONFIG:
PADCONFIG84
0x000F4150
RGMII1_RD2
4
I
0
RMII1_TX_EN
5
O
GPIO0_20
7
IO
pad
UART5_CTSn
8
I
1
PRG1_ECAP0_SYNC_IN
9
I
0
PRG1_PRU1_GPO19
0
IO
0
PRG1_PRU1_GPI19
1
I
0
PRG1_IEP1_EDC_SYNC_OUT0
2
O
PRG1_PWM1_TZ_OUT
3
O
RGMII1_RD3
4
I
0
RMII1_CRS_DV
5
I
0
SPI3_CS2
6
IO
1
GPIO0_84
7
IO
pad
UART5_RTSn
8
O
PRG1_ECAP0_IN_APWM_OUT
9
IO
RESETSTATz
0
0
PRG1_PRU1_GPO19
V12
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
MUX
MODE
[4]
PADCONFIG:
PADCONFIG85
0x000F4154
SIGNAL NAME [3]
0
RESETSTATz
F16
PADCONFIG:
PADCONFIG169
0x000F42A4
RESET_REQz
52
E18
PADCONFIG:
PADCONFIG168
0x000F42A0
RESET_REQz
H16
RSVD0
RSVD0
N/A
D21
RSVD1
RSVD1
N/A
G13
RSVD2
RSVD2
N/A
F17
RSVD3
RSVD3
N/A
W15
RSVD4
RSVD4
N/A
V16
RSVD5
RSVD5
N/A
K2
RSVD6
RSVD6
N/A
K1
RSVD7
RSVD7
N/A
F12
RSVD8
RSVD8
N/A
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
T13
W16
W17
Y15
Y16
AA16
AA17
D13
C14
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SERDES0_REXT
SERDES0_REFCLK0N
SERDES0_REFCLK0P
SERDES0_RX0_N
SERDES0_RX0_P
SERDES0_TX0_N
SIGNAL NAME [3]
MUX
MODE
[4]
SERDES0_REXT
TYPE
[5]
DSIS
[6]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
1.8 V
VDDA_1P8_SERDES0
,
VDDA_0P85_SERDES
0,
VDDA_0P85_SERDES
0_C
SERDES
1.8 V
VDDA_1P8_SERDES0
,
VDDA_0P85_SERDES
0,
VDDA_0P85_SERDES
0_C
SERDES
1.8 V
VDDA_1P8_SERDES0
,
VDDA_0P85_SERDES
0,
VDDA_0P85_SERDES
0_C
SERDES
1.8 V
VDDA_1P8_SERDES0
,
VDDA_0P85_SERDES
0,
VDDA_0P85_SERDES
0_C
SERDES
1.8 V
VDDA_1P8_SERDES0
,
VDDA_0P85_SERDES
0,
VDDA_0P85_SERDES
0_C
SERDES
1.8 V
VDDA_1P8_SERDES0
,
VDDA_0P85_SERDES
0,
VDDA_0P85_SERDES
0_C
SERDES
1.8 V
VDDA_1P8_SERDES0
,
VDDA_0P85_SERDES
0,
VDDA_0P85_SERDES
0_C
SERDES
A
SERDES0_REFCLK0N
IO
SERDES0_REFCLK0P
IO
SERDES0_RX0_N
I
SERDES0_RX0_P
I
SERDES0_TX0_N
O
SERDES0_TX0_P
SERDES0_TX0_P
O
SPI0_CLK
SPI0_CLK
0
IO
0
PADCONFIG:
PADCONFIG132
0x000F4210
GPIO1_44
7
IO
pad
SPI1_CLK
SPI1_CLK
0
IO
0
PADCONFIG:
PADCONFIG137
0x000F4224
EHRPWM6_SYNCI
3
I
0
GPIO1_49
7
IO
pad
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
D12
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
A13
A14
B14
B15
A15
54
DSIS
[6]
SPI0_CS0
0
IO
1
PADCONFIG:
PADCONFIG130
0x000F4208
GPIO1_42
7
IO
pad
SPI0_CS1
0
IO
1
CPTS0_TS_COMP
1
O
I2C2_SCL
2
IOD
1
TIMER_IO10
3
IO
0
PRG0_IEP0_EDIO_OUTVALID
4
O
UART6_RXD
5
I
ADC_EXT_TRIGGER0
6
I
0
GPIO1_43
7
IO
pad
SPI0_D0
SPI0_D0
0
IO
0
PADCONFIG:
PADCONFIG133
0x000F4214
GPIO1_45
7
IO
pad
SPI0_D1
SPI0_D1
0
IO
0
PADCONFIG:
PADCONFIG134
0x000F4218
GPIO1_46
7
IO
pad
SPI1_CS0
SPI1_CS0
0
IO
1
PADCONFIG:
PADCONFIG135
0x000F421C
EHRPWM6_A
3
IO
0
GPIO1_47
7
IO
pad
SPI1_CS1
0
IO
1
CPTS0_TS_SYNC
1
O
I2C2_SDA
2
IOD
PRG1_IEP0_EDIO_OUTVALID
4
O
UART6_TXD
5
O
ADC_EXT_TRIGGER1
6
I
0
GPIO1_48
7
IO
pad
PADCONFIG:
PADCONFIG131
0x000F420C
SPI1_CS1
D14
TYPE
[5]
SPI0_CS0
SPI0_CS1
C13
SIGNAL NAME [3]
MUX
MODE
[4]
PADCONFIG:
PADCONFIG136
0x000F4220
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
1
1
TIMER_IO11
8
IO
0
SPI1_D0
SPI1_D0
0
IO
0
PADCONFIG:
PADCONFIG138
0x000F4228
EHRPWM6_SYNCO
3
O
GPIO1_50
7
IO
pad
SPI1_D1
SPI1_D1
0
IO
0
PADCONFIG:
PADCONFIG139
0x000F422C
EHRPWM6_B
3
IO
0
GPIO1_51
7
IO
pad
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
I
On / Off / Up
On / Off / Up
0
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
0
I
On / Off / Up
On / Off / Up
0
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
TDO
0
OZ
Off / Off / Up
Off / SS / Up
0
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
TMS
0
I
On / Off / Up
On / Off / Up
0
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
TRSTn
0
I
On / Off / Down
On / Off / Down
0
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
UART0_CTSn
0
I
1
SPI0_CS2
1
IO
1
ADC_EXT_TRIGGER0
2
I
0
UART0_CTSn
UART2_RXD
3
I
1
PADCONFIG:
PADCONFIG142
0x000F4238
TIMER_IO6
4
IO
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
SPI4_CLK
6
IO
0
GPIO1_54
7
IO
pad
EQEP0_S
8
IO
0
CP_GEMAC_CPTS0_TS_SYNC
9
O
UART0_RTSn
0
O
SPI0_CS3
1
IO
UART0_RTSn
UART2_TXD
3
O
PADCONFIG:
PADCONFIG143
0x000F423C
TIMER_IO7
4
IO
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
SPI4_D0
6
IO
0
GPIO1_55
7
IO
pad
EQEP0_I
8
IO
0
UART0_RXD
0
I
1
SPI2_D0
2
IO
0
GPIO1_52
7
IO
pad
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
EQEP0_A
8
I
0
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
MUX
MODE
[4]
TYPE
[5]
TCK
0
TDI
SIGNAL NAME [3]
DSIS
[6]
TCK
B11
PADCONFIG:
MCU_PADCONFIG26
0x04084068
TDI
C11
PADCONFIG:
MCU_PADCONFIG28
0x04084070
TDO
A12
PADCONFIG:
MCU_PADCONFIG29
0x04084074
TMS
C12
PADCONFIG:
MCU_PADCONFIG30
0x04084078
TRSTn
D11
B16
A16
PADCONFIG:
MCU_PADCONFIG27
0x0408406C
UART0_RXD
D15
PADCONFIG:
PADCONFIG140
0x000F4230
1
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
D16
E16
E15
E14
56
TYPE
[5]
DSIS
[6]
UART0_TXD
0
O
SPI2_D1
2
IO
0
GPIO1_53
7
IO
pad
EQEP0_B
8
I
0
UART1_CTSn
0
I
1
SPI1_CS2
1
IO
1
ADC_EXT_TRIGGER1
2
I
0
UART1_CTSn
PCIE0_CLKREQn
3
IO
0
PADCONFIG:
PADCONFIG146
0x000F4248
UART3_RXD
4
I
1
CP_GEMAC_CPTS0_TS_SYNC
5
O
SPI4_D1
6
IO
0
GPIO1_58
7
IO
pad
EQEP1_S
8
IO
0
UART1_RTSn
0
O
UART0_TXD
C16
SIGNAL NAME [3]
MUX
MODE
[4]
PADCONFIG:
PADCONFIG141
0x000F4234
SPI1_CS3
1
IO
UART1_RTSn
UART3_TXD
4
O
PADCONFIG:
PADCONFIG147
0x000F424C
CP_GEMAC_CPTS0_HW2TSPUSH
5
I
0
SPI4_CS0
6
IO
1
GPIO1_59
7
IO
pad
EQEP1_I
8
IO
0
UART1_RXD
0
I
1
UART1_RXD
SPI2_CS0
2
IO
1
PADCONFIG:
PADCONFIG144
0x000F4240
CP_GEMAC_CPTS0_TS_COMP
5
O
GPIO1_56
7
IO
pad
EQEP1_A
8
I
0
UART1_TXD
0
O
UART1_TXD
SPI2_CLK
2
IO
PADCONFIG:
PADCONFIG145
0x000F4244
CP_GEMAC_CPTS0_HW1TSPUSH
5
I
0
GPIO1_57
7
IO
pad
EQEP1_B
8
I
0
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
1
0
AA20
USB0_DM
USB0_DM
IO
1.8 V/3.3 V
VDDA_3P3_USB0,
VDDA_1P8_USB0,
VDDA_0P85_USB0
USB2PHY
AA19
USB0_DP
USB0_DP
IO
1.8 V/3.3 V
VDDA_3P3_USB0,
VDDA_1P8_USB0,
VDDA_0P85_USB0
USB2PHY
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
DSIS
[6]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
Off / Off / Down
Off / Off / Down
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
USB0_DRVVBUS
USB0_DRVVBUS
0
O
E19
PADCONFIG:
PADCONFIG170
0x000F42A8
GPIO1_79
7
IO
U16
USB0_ID
USB0_ID
A
1.8 V/3.3 V
VDDA_3P3_USB0,
VDDA_1P8_USB0,
VDDA_0P85_USB0
USB2PHY
U17
USB0_RCALIB
USB0_RCALIB
A
1.8 V/3.3 V
VDDA_3P3_USB0,
VDDA_1P8_USB0,
VDDA_0P85_USB0
USB2PHY
T14
USB0_VBUS
USB0_VBUS
A
1.8 V/3.3 V
VDDA_3P3_USB0,
VDDA_1P8_USB0,
VDDA_0P85_USB0
USB2PHY
P12, P13
VDDA_0P85_SERDES0
VDDA_0P85_SERDES0
PWR
P11
VDDA_0P85_SERDES0_C
VDDA_0P85_SERDES0_C
PWR
T12
VDDA_0P85_USB0
VDDA_0P85_USB0
PWR
R14
VDDA_1P8_SERDES0
VDDA_1P8_SERDES0
PWR
R15
VDDA_1P8_USB0
VDDA_1P8_USB0
PWR
H15
VDDA_3P3_SDIO
VDDA_3P3_SDIO
PWR
R13
VDDA_3P3_USB0
VDDA_3P3_USB0
PWR
J13
VDDA_ADC
VDDA_ADC
PWR
K12
VDDA_MCU
VDDA_MCU
PWR
N12
VDDA_PLL0
VDDA_PLL0
PWR
H9
VDDA_PLL1
VDDA_PLL1
PWR
J11
VDDA_PLL2
VDDA_PLL2
PWR
G11
VDDA_TEMP0
VDDA_TEMP0
PWR
L11
VDDA_TEMP1
VDDA_TEMP1
PWR
L10, M13
VDDR_CORE
VDDR_CORE
PWR
F11, G12,
G14
VDDSHV0
VDDSHV0
PWR
M7, N6, P7
VDDSHV1
VDDSHV1
PWR
R10, R8, T9
VDDSHV2
VDDSHV2
PWR
P14, P15
VDDSHV3
VDDSHV3
PWR
M14, M15
VDDSHV4
VDDSHV4
PWR
L14, L15
VDDSHV5
VDDSHV5
PWR
F9, G10, G8
VDDSHV_MCU
VDDSHV_MCU
PWR
F7, G6, H7,
J6, K7, L6
VDDS_DDR
VDDS_DDR
PWR
J8
VDDS_DDR_C
VDDS_DDR_C
PWR
K14
VDDS_MMC0
VDDS_MMC0
PWR
H13
VDDS_OSC
VDDS_OSC
PWR
pad
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
NUMBER [1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
J10, J12,
K11, K9, L12,
VDD_CORE
L8, M11, M9,
N10, N8, P9
SIGNAL NAME [3]
MUX
MODE
[4]
TYPE
[5]
VDD_CORE
PWR
H14
VDD_DLL_MMC0
VDD_DLL_MMC0
PWR
K13
VDD_MMC0
VDD_MMC0
PWR
K16
VMON_1P8_MCU
VMON_1P8_MCU
A
E12
VMON_1P8_SOC
VMON_1P8_SOC
A
F13
VMON_3P3_MCU
VMON_3P3_MCU
A
F14
VMON_3P3_SOC
VMON_3P3_SOC
A
K10
VMON_VSYS
VMON_VSYS
G15
VPP
VPP
PWR
A1, A21, A5,
A6, AA1,
AA15, AA18,
AA21, C10,
C15, C3, D1,
E11, E13,
F10, F15, F8,
G1, G16, G3,
G7, G9, H11,
H20, H21,
H6, H8, J14,
J7, J9, K6,
K8, L1, L16,
VSS
L3, L7, L9,
M10, M12,
M6, M8, N11,
N13, N15,
N7, N9, P1,
P10, P18, P6,
P8, R12, R7,
R9, T10, T11,
T15, T16, T8,
U3, V17,
W10, W18,
Y14, Y17,
Y19
VSS
GND
58
DSIS
[6]
BALL
STATE
DURING
RESET
RX/TX/PULL [7]
BALL
STATE
AFTER
RESET
RX/TX/PULL [8]
MUX
MODE
AFTER
RESET
[9]
I/O
OPERATING
VOLTAGE [10]
POWER [11]
HYS
[12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
A
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6.3 Signal Descriptions
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing
options.
The following list describes the column headers:
1. SIGNAL NAME: The name of the signal passing through the pin.
Note
Signal names and descriptions provided in each Signal Descriptions table, represent the pin
multiplexed signal function which is implemented at the pin and selected via PADCONFIG
registers. Device subsystems may provide secondary multiplexing of signal functions, which are
not described in these tables. For more information on secondary multiplexed signal functions,
see the respective peripheral chapter of the device TRM.
2. PIN TYPE: Signal direction and type:
• I = Input
• O = Output
• OD = Output, with open-drain output function
• IO = Input, Output, or simultaneously Input and Output
• IOD = Input, Output, or simultaneously Input and Output with open-drain output function
• IOZ = Input, Output, or simultaneously Input and Output with three-state output function
• OZ = Output with three-state output function
• A = Analog
• PWR = Power
• GND = Ground
• CAP = LDO Capacitor
3. DESCRIPTION: Description of the signal
4. BALL: Ball number(s) associated with signal
For more information on the IO cell configurations, see the Pad Configuration Registers section in Device
Configuration chapter of the device TRM.
6.3.1 ADC
Note
The ADC can be configured to operate as eight general-purpose digital inputs. For more information,
see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.
6.3.1.1 MAIN Domain
Table 6-2. ADC0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
(4)
A
ADC0 Negative Reference
J16
ADC0_REFP (4)
A
ADC0 Positive Reference
J15
(1) (2) (3)
A
ADC Analog Input 0 / GPIO1_80 (Input Only)
G20
ADC0_AIN1 (1) (2) (3)
A
ADC Analog Input 1 / GPIO1_81 (Input Only)
F20
(1) (2) (3)
A
ADC Analog Input 2 / GPIO1_82 (Input Only)
E21
ADC0_AIN3 (1) (2) (3)
A
ADC Analog Input 3 / GPIO1_83 (Input Only)
D20
ADC0_AIN4 (1) (2) (3)
A
ADC Analog Input 4 / GPIO1_84 (Input Only)
G21
ADC0_AIN5 (1) (2) (3)
A
ADC Analog Input 5 / GPIO1_85 (Input Only)
F21
(1) (2) (3)
A
ADC Analog Input 6 / GPIO1_86 (Input Only)
F19
ADC0_REFN
ADC0_AIN0
ADC0_AIN2
ADC0_AIN6
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Table 6-2. ADC0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
ADC0_AIN7 (1) (2) (3)
A
ADC Analog Input 7 / GPIO1_87 (Input Only)
ADC_EXT_TRIGGER0
I
ADC Trigger Input
B16, C13
ADC_EXT_TRIGGER1
I
ADC Trigger Input
D14, D16
(1)
(2)
(3)
(4)
E20
The General Purpose Input signal associated with this ADC0_AIN input has a debounce function when ADC0 is configured to operate
in GPI mode. For more information on configuring ADC0 to operate in GPI mode, see the TRM Analog-to-Digital Converter (ADC)
section in the Peripherals chapter. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter.
The ADC0_AIN[7:0] inputs only have hysterisis when ADC0 is configured to operate in GPI mode.
Any unused ADC0_AIN inputs must be pulled to VSS through a resistor or connected directly to VSS when VDDA_ADC is connected
to a power source.
The ADC0_REFP and ADC0_REFN reference inputs are analog inputs which must be treated like high transient power supply rails,
where ADC0_REFN is expected to be connected directly to the PCB ground plane along with all other VSS pins, and ADC0_REFP is
connected to a power source capable of providing at least 4mA of current. ADC0_REFP may be connected to the same power source
as VDDA_ADC0 if the voltage tolerance of the supply provides an acceptable accuracy for the ADC reference. A high frequency
decoupling capacitor must be connected directly between ADC0_REFP and ADC0_REFN. The high frequency decoupling capacitor
should be placed in the ball array on the back side of the PCB and connected directly to the ADC0_REFP and ADC0_REFN pins with
vias. ADC0_REFP may be connected to VSS if ADC0 is not used and VDDA_ADC0 has been connected to VSS. The high frequency
decoupling capacitor described above will not be required if ADC0 is not used and ADC0_REFP is connected to VSS. See the Pin
Connectivity Requirements section for more information on ADC0 connectivity.
6.3.2 CPSW3G
6.3.2.1 MAIN Domain
Table 6-3. CPSW3G0 RGMII1 Signal Descriptions
SIGNAL NAME [1]
RGMII1_RXC
RGMII1_RX_CTL
PIN TYPE [2]
DESCRIPTION [3]
I
RGMII Receive Clock
ALV PIN [4]
AA5, W13
I
RGMII Receive Control
V13, W6
RGMII1_TXC
IO
RGMII Transmit Clock
U14
RGMII1_TX_CTL
O
RGMII Transmit Control
U15
RGMII1_RD0
I
RGMII Receive Data 0
AA13, W5
RGMII1_RD1
I
RGMII Receive Data 1
U12, Y5
RGMII1_RD2
I
RGMII Receive Data 2
V6, Y13
RGMII1_RD3
I
RGMII Receive Data 3
V12, V5
RGMII1_TD0
O
RGMII Transmit Data 0
V15
RGMII1_TD1
O
RGMII Transmit Data 1
V14
RGMII1_TD2
O
RGMII Transmit Data 2
W14
RGMII1_TD3
O
RGMII Transmit Data 3
AA14
Table 6-4. CPSW3G0 RGMII2 Signal Descriptions
SIGNAL NAME [1]
RGMII2_RXC
RGMII2_RX_CTL
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
I
RGMII Receive Clock
U11
I
RGMII Receive Control
W12
RGMII2_TXC
IO
RGMII Transmit Clock
Y10
RGMII2_TX_CTL
O
RGMII Transmit Control
Y11
RGMII2_RD0
I
RGMII Receive Data 0
W11
RGMII2_RD1
I
RGMII Receive Data 1
V11
RGMII2_RD2
I
RGMII Receive Data 2
AA12
RGMII2_RD3
I
RGMII Receive Data 3
Y12
RGMII2_TD0
O
RGMII Transmit Data 0
AA10
RGMII2_TD1
O
RGMII Transmit Data 1
V10
RGMII2_TD2
O
RGMII Transmit Data 2
U10
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Table 6-4. CPSW3G0 RGMII2 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
RGMII2_TD3
O
DESCRIPTION [3]
ALV PIN [4]
RGMII Transmit Data 3
AA11
Table 6-5. CPSW3G0 RMII1 and RMII2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
RMII1_CRS_DV
DESCRIPTION [3]
ALV PIN [4]
I
RMII Carrier Sense / Data Valid
R2, V12
RMII1_RX_ER
I
RMII Receive Data Error
U15, W6
RMII1_TX_EN
O
RMII Transmit Enable
P5, Y13
RMII2_CRS_DV
I
RMII Carrier Sense / Data Valid
U10
RMII2_RX_ER
I
RMII Receive Data Error
W12
RMII2_TX_EN
O
RMII Transmit Enable
Y11
RMII1_RXD0
I
RMII Receive Data 0
V15, W5
RMII1_RXD1
I
RMII Receive Data 1
V14, Y5
RMII1_TXD0
O
RMII Transmit Data 0
V6, W14
RMII1_TXD1
O
RMII Transmit Data 1
AA14, V5
RMII2_RXD0
I
RMII Receive Data 0
W11
RMII2_RXD1
I
RMII Receive Data 1
V11
RMII2_TXD0
O
RMII Transmit Data 0
AA10
RMII2_TXD1
O
RMII Transmit Data 1
V10
I
RMII Reference Clock
AA5, U14
RMII_REF_CLK
(1)
(1)
RMII_REF_CLK is common to both RMII1 and RMII2.
6.3.3 CPTS
6.3.3.1 MAIN Domain
Table 6-6. CP GEMAC CPTS0 Signal Descriptions
SIGNAL NAME [1]
CP_GEMAC_CPTS0_RFT_CLK
CP_GEMAC_CPTS0_TS_COMP
CP_GEMAC_CPTS0_TS_SYNC
CP_GEMAC_CPTS0_HW1TSPUSH
CP_GEMAC_CPTS0_HW2TSPUSH
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
I
CPTS Reference Clock Input to CPSW3G0 CPTS
D18
O
CPTS Time Stamp Counter Compare Output from
CPSW3G0 CPTS
E15, K18, W1
O
CPTS Time Stamp Counter Bit Output from CPSW3G0
CPTS
B16, D16, K19,
U1
I
CPTS Hardware Time Stamp Push Input to CPSW3G0
CPTS
E14, L21, V1
I
CPTS Hardware Time Stamp Push Input to CPSW3G0
CPTS
E16, K21, T1
Table 6-7. CPTS0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
CPTS0_RFT_CLK
I
CPTS Reference Clock Input
CPTS0_TS_COMP
O
CPTS Time Stamp Counter Compare Output
C13, W1, W7
CPTS0_TS_SYNC
O
CPTS Time Stamp Counter Bit Output
D14, U1, U7
I
CPTS Hardware Time Stamp Push Input to Time Sync
Router
C18, V1, V7
I
CPTS Hardware Time Stamp Push Input to Time Sync
Router
B19, T1, U13
O
CPTS Time Stamp Generator Bit 0 Output from Time
Sync Router
D18
O
CPTS Time Stamp Generator Bit 1 Output from Time
Sync Router
A19
CPTS0_HW1TSPUSH
CPTS0_HW2TSPUSH
SYNC0_OUT
SYNC1_OUT
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Table 6-7. CPTS0 Signal Descriptions (continued)
SIGNAL NAME [1]
SYNC2_OUT
SYNC3_OUT
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
O
CPTS Time Stamp Generator Bit 2 Output from Time
Sync Router
A17
O
CPTS Time Stamp Generator Bit 3 Output from Time
Sync Router
B17
6.3.4 DDRSS
6.3.4.1 MAIN Domain
Table 6-8. DDRSS0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
DDR0_ACT_n
O
DDRSS Activation Command
H2
DDR0_ALERT_n
IO
DDRSS Alert
H1
DDR0_CAS_n
O
DDRSS Column Address Strobe
J5
DDR0_PAR
O
DDRSS Command and Address Parity
K5
DDR0_RAS_n
O
DDRSS Row Address Strobe
F6
DDR0_WE_n
O
DDRSS Write Enable
H4
DDR0_A0
O
DDRSS Address Bus
D2
DDR0_A1
O
DDRSS Address Bus
C5
DDR0_A2
O
DDRSS Address Bus
E2
DDR0_A3
O
DDRSS Address Bus
D4
DDR0_A4
O
DDRSS Address Bus
D3
DDR0_A5
O
DDRSS Address Bus
F2
DDR0_A6
O
DDRSS Address Bus
J2
DDR0_A7
O
DDRSS Address Bus
L5
DDR0_A8
O
DDRSS Address Bus
J3
DDR0_A9
O
DDRSS Address Bus
J4
DDR0_A10
O
DDRSS Address Bus
K3
DDR0_A11
O
DDRSS Address Bus
J1
DDR0_A12
O
DDRSS Address Bus
M5
DDR0_A13
O
DDRSS Address Bus
K4
DDR0_BA0
O
DDRSS Bank Address
G4
DDR0_BA1
O
DDRSS Bank Address
G5
DDR0_BG0
O
DDRSS Bank Group
G2
DDR0_BG1
O
DDRSS Bank Group
H3
DDR0_CAL0
(1)
A
IO Pad Calibration Resistor
H5
DDR0_CK0
O
DDRSS Clock
F1
DDR0_CK0_n
O
DDRSS Negative Clock
E1
DDR0_CKE0
O
DDRSS Clock Enable
F4
DDR0_CKE1
O
DDRSS Clock Enable
F3
DDR0_CS0_n
O
DDRSS Chip Select 0
E3
DDR0_CS1_n
O
DDRSS Chip Select 1
E4
DDR0_DM0
IO
DDRSS Data Mask
B2
DDR0_DM1
IO
DDRSS Data Mask
M2
DDR0_DQ0
IO
DDRSS Data
A3
DDR0_DQ1
IO
DDRSS Data
A2
DDR0_DQ2
IO
DDRSS Data
B5
DDR0_DQ3
IO
DDRSS Data
A4
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Table 6-8. DDRSS0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
DDR0_DQ4
IO
DDRSS Data
B3
DDR0_DQ5
IO
DDRSS Data
C4
DDR0_DQ6
IO
DDRSS Data
C2
DDR0_DQ7
IO
DDRSS Data
B4
DDR0_DQ8
IO
DDRSS Data
N5
DDR0_DQ9
IO
DDRSS Data
L4
DDR0_DQ10
IO
DDRSS Data
L2
DDR0_DQ11
IO
DDRSS Data
M3
DDR0_DQ12
IO
DDRSS Data
N4
DDR0_DQ13
IO
DDRSS Data
N3
DDR0_DQ14
IO
DDRSS Data
M4
DDR0_DQ15
IO
DDRSS Data
N2
DDR0_DQS0
IO
DDRSS Data Strobe 0
C1
DDR0_DQS0_n
IO
DDRSS Complimentary Data Strobe 0
B1
DDR0_DQS1
IO
DDRSS Data Strobe 1
N1
DDR0_DQS1_n
IO
DDRSS Complimentary Data Strobe 1
M1
DDR0_ODT0
O
DDRSS On-Die Termination for Chip Select 0
E5
DDR0_ODT1
O
DDRSS On-Die Termination for Chip Select 1
F5
DDR0_RESET0_n
O
DDRSS Reset
D5
(1)
An external 240 Ω ±1% resistor must be connected between this pin and VSS. The maximum power dissipation for the resistor is
5.2mW. No external voltage should be applied to this pin.
6.3.5 ECAP
6.3.5.1 MAIN Domain
Table 6-9. ECAP0 Signal Descriptions
SIGNAL NAME [1]
ECAP0_IN_APWM_OUT
PIN TYPE [2]
IO
DESCRIPTION [3]
ALV PIN [4]
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Output
D18
Table 6-10. ECAP1 Signal Descriptions
SIGNAL NAME [1]
ECAP1_IN_APWM_OUT
PIN TYPE [2]
IO
DESCRIPTION [3]
ALV PIN [4]
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Output
C17
Table 6-11. ECAP2 Signal Descriptions
SIGNAL NAME [1]
ECAP2_IN_APWM_OUT
PIN TYPE [2]
IO
DESCRIPTION [3]
ALV PIN [4]
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Output
D17
6.3.6 Emulation and Debug
6.3.6.1 MAIN Domain
Table 6-12. Trace Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
TRC_CLK
O
Trace Clock
T20
TRC_CTL
O
Trace Control
U21
TRC_DATA0
O
Trace Data 0
T18
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Table 6-12. Trace Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
TRC_DATA1
O
Trace Data 1
U20
TRC_DATA2
O
Trace Data 2
U18
TRC_DATA3
O
Trace Data 3
U19
TRC_DATA4
O
Trace Data 4
V20
TRC_DATA5
O
Trace Data 5
V21
TRC_DATA6
O
Trace Data 6
V19
TRC_DATA7
O
Trace Data 7
T17
TRC_DATA8
O
Trace Data 8
R16
TRC_DATA9
O
Trace Data 9
W20
TRC_DATA10
O
Trace Data 10
W21
TRC_DATA11
O
Trace Data 11
V18
TRC_DATA12
O
Trace Data 12
Y21
TRC_DATA13
O
Trace Data 13
Y20
TRC_DATA14
O
Trace Data 14
R17
TRC_DATA15
O
Trace Data 15
P16
TRC_DATA16
O
Trace Data 16
R18
TRC_DATA17
O
Trace Data 17
T21
TRC_DATA18
O
Trace Data 18
P17
TRC_DATA19
O
Trace Data 19
T19
TRC_DATA20
O
Trace Data 20
W19
TRC_DATA21
O
Trace Data 21
Y18
TRC_DATA22
O
Trace Data 22
N16
TRC_DATA23
O
Trace Data 23
R19
6.3.6.2 MCU Domain
Table 6-13. JTAG Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
EMU0
IO
Emulation Control 0
D10
EMU1
IO
Emulation Control 1
E10
TCK
I
JTAG Test Clock Input
B11
TDI
I
JTAG Test Data Input
C11
TDO
OZ
JTAG Test Data Output
A12
TMS
I
JTAG Test Mode Select Input
C12
TRSTn
I
JTAG Reset
D11
6.3.7 EPWM
6.3.7.1 MAIN Domain
Table 6-14. EPWM Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
EHRPWM_SOCA
O
EHRPWM Start of Conversion A
C17
EHRPWM_SOCB
O
EHRPWM Start of Conversion B
D17
EHRPWM_TZn_IN0
I
EHRPWM Trip Zone Input 0 (active low)
T18
EHRPWM_TZn_IN1
I
EHRPWM Trip Zone Input 1 (active low)
V21
EHRPWM_TZn_IN2
I
EHRPWM Trip Zone Input 2 (active low)
R16, R20
EHRPWM_TZn_IN3
I
EHRPWM Trip Zone Input 3 (active low)
P16
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Table 6-14. EPWM Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
EHRPWM_TZn_IN4
I
EHRPWM Trip Zone Input 4 (active low)
P17, P19
EHRPWM_TZn_IN5
I
EHRPWM Trip Zone Input 5 (active low)
R21, Y18
Table 6-15. EPWM0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
EHRPWM0_A
IO
EHRPWM Output A
U20
EHRPWM0_B
IO
EHRPWM Output B
U18
EHRPWM0_SYNCI
I
Sync Input to EHRPWM module from an external pin
T20
EHRPWM0_SYNCO
O
Sync Output to EHRPWM module to an external pin
U21
Table 6-16. EPWM1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
EHRPWM1_A
IO
EHRPWM Output A
U19
EHRPWM1_B
IO
EHRPWM Output B
V20
Table 6-17. EPWM2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
EHRPWM2_A
IO
EHRPWM Output A
V19
EHRPWM2_B
IO
EHRPWM Output B
T17
Table 6-18. EPWM3 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
EHRPWM3_A
IO
EHRPWM Output A
V18
EHRPWM3_B
IO
EHRPWM Output B
Y21
EHRPWM3_SYNCI
I
Sync Input to EHRPWM module from an external pin
Y20
EHRPWM3_SYNCO
O
Sync Output to EHRPWM module to an external pin
R17
Table 6-19. EPWM4 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
EHRPWM4_A
IO
EHRPWM Output A
R18
EHRPWM4_B
IO
EHRPWM Output B
T21
Table 6-20. EPWM5 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
EHRPWM5_A
IO
EHRPWM Output A
T19
EHRPWM5_B
IO
EHRPWM Output B
W19
Table 6-21. EPWM6 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
EHRPWM6_A
IO
EHRPWM Output A
EHRPWM6_B
IO
ALV PIN [4]
B14, N16
EHRPWM Output B
A15, N17
EHRPWM6_SYNCI
I
Sync Input to EHRPWM module from an external pin
C14, R19
EHRPWM6_SYNCO
O
Sync Output to EHRPWM module to an external pin
B15, R20
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Table 6-22. EPWM7 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
EHRPWM7_A
IO
EHRPWM Output A
P17, P5, W20
EHRPWM7_B
IO
EHRPWM Output B
R2, W21, Y18
Table 6-23. EPWM8 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
EHRPWM8_A
IO
EHRPWM Output A
V1, V21
EHRPWM8_B
IO
EHRPWM Output B
R16, W1
6.3.8 EQEP
6.3.8.1 MAIN Domain
Table 6-24. EQEP0 Signal Descriptions
SIGNAL NAME [1]
EQEP0_A (1)
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
I
EQEP Quadrature Input A
EQEP0_B (1)
I
EQEP Quadrature Input B
EQEP0_I (1)
IO
EQEP Index
A16, R20, T6, Y5
EQEP0_S (1)
IO
EQEP Strobe
B16, R19, V3
(1)
D15, N16, Y2
C16, N17, W2
This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
Table 6-25. EQEP1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
EQEP1_A (1)
I
EQEP Quadrature Input A
E15, T4, W20
EQEP1_B (1)
I
EQEP Quadrature Input B
E14, W21, W3
EQEP Index
E16, R21, U6,
V6
EQEP Strobe
D16, P19, P4
EQEP1_I (1)
IO
EQEP1_S (1)
(1)
IO
This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
Table 6-26. EQEP2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
(1)
I
EQEP Quadrature Input A
C17, R5
EQEP2_B (1)
I
EQEP Quadrature Input B
D17, W5, Y4
EQEP2_I (1)
IO
EQEP Index
A17, W4
EQEP2_S (1)
IO
EQEP Strobe
B17, R1
EQEP2_A
(1)
This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
6.3.9 FSI
6.3.9.1 MAIN Domain
Table 6-27. FSI0 RX Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
FSI_RX0_CLK
I
FSI Clock
FSI_RX0_D0
I
FSI Data
T17
FSI_RX0_D1
I
FSI Data
R16
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Table 6-28. FSI0 TX Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
FSI_TX0_CLK
O
FSI Clock
T19
FSI_TX0_D0
O
FSI Data
Y21
FSI_TX0_D1
O
FSI Data
Y20
Table 6-29. FSI1 RX Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
FSI_RX1_CLK
I
FSI Clock
W20
FSI_RX1_D0
I
FSI Data
W21
FSI_RX1_D1
I
FSI Data
V18
Table 6-30. FSI1 TX Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
FSI_TX1_CLK
O
FSI Clock
N16
FSI_TX1_D0
O
FSI Data
P17
FSI_TX1_D1
O
FSI Data
Y18
Table 6-31. FSI2 RX Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
FSI_RX2_CLK
I
FSI Clock
T20
FSI_RX2_D0
I
FSI Data
U21
FSI_RX2_D1
I
FSI Data
T18
Table 6-32. FSI3 RX Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
FSI_RX3_CLK
I
FSI Clock
U20
FSI_RX3_D0
I
FSI Data
U18
FSI_RX3_D1
I
FSI Data
U19
Table 6-33. FSI4 RX Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
FSI_RX4_CLK
I
FSI Clock
R17
FSI_RX4_D0
I
FSI Data
V20
FSI_RX4_D1
I
FSI Data
V21
Table 6-34. FSI5 RX Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
FSI_RX5_CLK
I
FSI Clock
P16
FSI_RX5_D0
I
FSI Data
R18
FSI_RX5_D1
I
FSI Data
T21
6.3.10 GPIO
6.3.10.1 MAIN Domain
Table 6-35. GPIO0 Signal Descriptions
SIGNAL NAME [1]
GPIO0_0
PIN TYPE [2]
IO
Copyright © 2023 Texas Instruments Incorporated
DESCRIPTION [3]
ALV PIN [4]
General Purpose Input/Output
N20
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Table 6-35. GPIO0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
GPIO0_1
IO
General Purpose Input/Output
GPIO0_2
IO
General Purpose Input/Output
N19
GPIO0_3
IO
General Purpose Input/Output
M19
GPIO0_4
IO
General Purpose Input/Output
M18
GPIO0_5
IO
General Purpose Input/Output
M20
GPIO0_6
IO
General Purpose Input/Output
M21
GPIO0_7
IO
General Purpose Input/Output
P21
GPIO0_8
IO
General Purpose Input/Output
P20
GPIO0_9
IO
General Purpose Input/Output
N18
GPIO0_10
IO
General Purpose Input/Output
M17
GPIO0_11
IO
General Purpose Input/Output
L19
GPIO0_12
IO
General Purpose Input/Output
L18
GPIO0_13
IO
General Purpose Input/Output
K17
GPIO0_14
IO
General Purpose Input/Output
L17
GPIO0_15
IO
General Purpose Input/Output
T20
GPIO0_16
IO
General Purpose Input/Output
U21
GPIO0_17
IO
General Purpose Input/Output
T18
GPIO0_18
IO
General Purpose Input/Output
U20
GPIO0_19
IO
General Purpose Input/Output
AA14
GPIO0_20
IO
General Purpose Input/Output
Y13
GPIO0_21
IO
General Purpose Input/Output
V20
GPIO0_22
IO
General Purpose Input/Output
V21
GPIO0_23
IO
General Purpose Input/Output
V19
GPIO0_24
IO
General Purpose Input/Output
T17
GPIO0_25
IO
General Purpose Input/Output
R16
GPIO0_26
IO
General Purpose Input/Output
W20
GPIO0_27
IO
General Purpose Input/Output
W21
GPIO0_28
IO
General Purpose Input/Output
V18
GPIO0_29
IO
General Purpose Input/Output
Y21
GPIO0_30
IO
General Purpose Input/Output
Y20
GPIO0_31
IO
General Purpose Input/Output
R17
GPIO0_32
IO
General Purpose Input/Output
P16
GPIO0_33
IO
General Purpose Input/Output
R18
GPIO0_34
IO
General Purpose Input/Output
T21
GPIO0_35
IO
General Purpose Input/Output
P17
GPIO0_36
IO
General Purpose Input/Output
T19
GPIO0_37
IO
General Purpose Input/Output
W19
GPIO0_38
IO
General Purpose Input/Output
Y18
GPIO0_39
IO
General Purpose Input/Output
N16
GPIO0_40
IO
General Purpose Input/Output
N17
GPIO0_41
IO
General Purpose Input/Output
R19
GPIO0_42
IO
General Purpose Input/Output
R20
(1)
IO
General Purpose Input/Output
P19
GPIO0_44 (1)
IO
General Purpose Input/Output
R21
GPIO0_45
IO
General Purpose Input/Output
Y7
GPIO0_43
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Table 6-35. GPIO0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
GPIO0_46
IO
General Purpose Input/Output
U8
GPIO0_47
IO
General Purpose Input/Output
W8
GPIO0_48
IO
General Purpose Input/Output
V8
GPIO0_49
IO
General Purpose Input/Output
Y8
GPIO0_50
IO
General Purpose Input/Output
V13
GPIO0_51
IO
General Purpose Input/Output
AA7
GPIO0_52
IO
General Purpose Input/Output
U13
GPIO0_53
IO
General Purpose Input/Output
W13
GPIO0_54
IO
General Purpose Input/Output
U15
GPIO0_55
IO
General Purpose Input/Output
U14
GPIO0_56
IO
General Purpose Input/Output
AA8
GPIO0_57
IO
General Purpose Input/Output
U9
GPIO0_58
IO
General Purpose Input/Output
W9
GPIO0_59
IO
General Purpose Input/Output
AA9
GPIO0_60
IO
General Purpose Input/Output
Y9
GPIO0_61
IO
General Purpose Input/Output
V9
GPIO0_62
IO
General Purpose Input/Output
U7
GPIO0_63
IO
General Purpose Input/Output
V7
GPIO0_64
IO
General Purpose Input/Output
W7
GPIO0_65
IO
General Purpose Input/Output
W11
GPIO0_66
IO
General Purpose Input/Output
V11
GPIO0_67
IO
General Purpose Input/Output
AA12
GPIO0_68
IO
General Purpose Input/Output
Y12
GPIO0_69
IO
General Purpose Input/Output
W12
GPIO0_70
IO
General Purpose Input/Output
AA13
GPIO0_71
IO
General Purpose Input/Output
U11
GPIO0_72
IO
General Purpose Input/Output
V15
GPIO0_73
IO
General Purpose Input/Output
U12
GPIO0_74
IO
General Purpose Input/Output
V14
GPIO0_75
IO
General Purpose Input/Output
W14
GPIO0_76
IO
General Purpose Input/Output
AA10
GPIO0_77
IO
General Purpose Input/Output
V10
GPIO0_78
IO
General Purpose Input/Output
U10
GPIO0_79
IO
General Purpose Input/Output
AA11
GPIO0_80
IO
General Purpose Input/Output
Y11
GPIO0_81
IO
General Purpose Input/Output
Y10
GPIO0_82
IO
General Purpose Input/Output
U18
GPIO0_83
IO
General Purpose Input/Output
U19
GPIO0_84
IO
General Purpose Input/Output
V12
GPIO0_85
IO
General Purpose Input/Output
AA6
GPIO0_86
IO
General Purpose Input/Output
Y6
(1)
This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
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Table 6-36. GPIO1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
GPIO1_0
IO
General Purpose Input/Output
Y1
GPIO1_1
IO
General Purpose Input/Output
R4
GPIO1_2
IO
General Purpose Input/Output
U2
GPIO1_3
IO
General Purpose Input/Output
V2
GPIO1_4
IO
General Purpose Input/Output
AA2
GPIO1_5
IO
General Purpose Input/Output
R3
GPIO1_6
IO
General Purpose Input/Output
T3
GPIO1_7
IO
General Purpose Input/Output
T1
GPIO1_8
IO
General Purpose Input/Output
T2
GPIO1_9
IO
General Purpose Input/Output
W6
GPIO1_10
IO
General Purpose Input/Output
AA5
GPIO1_11
IO
General Purpose Input/Output
Y3
GPIO1_12
IO
General Purpose Input/Output
AA3
GPIO1_13
IO
General Purpose Input/Output
R6
GPIO1_14
IO
General Purpose Input/Output
V4
GPIO1_15
IO
General Purpose Input/Output
T5
GPIO1_16
IO
General Purpose Input/Output
U4
GPIO1_17
IO
General Purpose Input/Output
U1
GPIO1_18
IO
General Purpose Input/Output
V1
GPIO1_19
IO
General Purpose Input/Output
W1
GPIO1_20
IO
General Purpose Input/Output
Y2
GPIO1_21
IO
General Purpose Input/Output
W2
GPIO1_22
IO
General Purpose Input/Output
V3
GPIO1_23
IO
General Purpose Input/Output
T4
GPIO1_24
IO
General Purpose Input/Output
W3
GPIO1_25
IO
General Purpose Input/Output
P4
GPIO1_26
IO
General Purpose Input/Output
R5
GPIO1_27
IO
General Purpose Input/Output
W5
GPIO1_28
IO
General Purpose Input/Output
R1
GPIO1_29
IO
General Purpose Input/Output
Y5
GPIO1_30
IO
General Purpose Input/Output
V6
GPIO1_31
IO
General Purpose Input/Output
W4
GPIO1_32
IO
General Purpose Input/Output
Y4
GPIO1_33
IO
General Purpose Input/Output
T6
GPIO1_34
IO
General Purpose Input/Output
U6
GPIO1_35
IO
General Purpose Input/Output
U5
GPIO1_36
IO
General Purpose Input/Output
AA4
GPIO1_37
IO
General Purpose Input/Output
V5
GPIO1_38
IO
General Purpose Input/Output
P5
GPIO1_39
IO
General Purpose Input/Output
R2
GPIO1_40
IO
General Purpose Input/Output
P2
GPIO1_41
IO
General Purpose Input/Output
P3
GPIO1_42
IO
General Purpose Input/Output
D12
GPIO1_43
IO
General Purpose Input/Output
C13
GPIO1_44
IO
General Purpose Input/Output
D13
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Table 6-36. GPIO1 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
GPIO1_45
IO
General Purpose Input/Output
A13
GPIO1_46
IO
General Purpose Input/Output
A14
GPIO1_47
IO
General Purpose Input/Output
B14
GPIO1_48
IO
General Purpose Input/Output
D14
GPIO1_49
IO
General Purpose Input/Output
C14
GPIO1_50
IO
General Purpose Input/Output
B15
GPIO1_51
IO
General Purpose Input/Output
A15
GPIO1_52
IO
General Purpose Input/Output
D15
GPIO1_53
IO
General Purpose Input/Output
C16
GPIO1_54
IO
General Purpose Input/Output
B16
GPIO1_55
IO
General Purpose Input/Output
A16
GPIO1_56
IO
General Purpose Input/Output
E15
GPIO1_57
IO
General Purpose Input/Output
E14
GPIO1_58
IO
General Purpose Input/Output
D16
GPIO1_59
IO
General Purpose Input/Output
E16
GPIO1_60
IO
General Purpose Input/Output
A17
GPIO1_61
IO
General Purpose Input/Output
B17
GPIO1_62
IO
General Purpose Input/Output
C17
GPIO1_63
IO
General Purpose Input/Output
D17
GPIO1_64
IOD
General Purpose Input/Output
A18
GPIO1_65
IOD
General Purpose Input/Output
B18
GPIO1_66
IO
General Purpose Input/Output
C18
GPIO1_67
IO
General Purpose Input/Output
B19
IO
General Purpose Input/Output
D18
IO
General Purpose Input/Output
A19
GPIO1_68
(1)
GPIO1_69
GPIO1_70
(1)
IOD
General Purpose Input/Output
C19
GPIO1_71 (1)
IO
General Purpose Input/Output
K18
(1)
IO
General Purpose Input/Output
K19
GPIO1_73 (1)
IO
General Purpose Input/Output
L21
GPIO1_74 (1)
IO
General Purpose Input/Output
K21
GPIO1_75 (1)
IO
General Purpose Input/Output
L20
GPIO1_76 (1)
IO
General Purpose Input/Output
J19
(1)
IO
General Purpose Input/Output
D19
GPIO1_78 (1)
IO
General Purpose Input/Output
C20
GPIO1_79
IO
General Purpose Input/Output
E19
GPIO1_72
GPIO1_77
(1)
This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
6.3.10.2 MCU Domain
Table 6-37. MCU_GPIO0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
MCU_GPIO0_0 (1)
IO
General Purpose Input/Output
E8
MCU_GPIO0_1 (1)
IO
General Purpose Input/Output
D8
MCU_GPIO0_2
IO
General Purpose Input/Output
A8
MCU_GPIO0_3
IO
General Purpose Input/Output
A9
MCU_GPIO0_4
IO
General Purpose Input/Output
B6
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Table 6-37. MCU_GPIO0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
MCU_GPIO0_5 (1)
IO
General Purpose Input/Output
(1)
MCU_GPIO0_6
ALV PIN [4]
A7
IO
General Purpose Input/Output
B7
MCU_GPIO0_7
IO
General Purpose Input/Output
D7
MCU_GPIO0_8
IO
General Purpose Input/Output
C7
MCU_GPIO0_9
IO
General Purpose Input/Output
C8
MCU_GPIO0_10
IO
General Purpose Input/Output
E7
MCU_GPIO0_11
IO
General Purpose Input/Output
E6
(1)
IO
General Purpose Input/Output
C6
MCU_GPIO0_13 (1)
IO
General Purpose Input/Output
D6
MCU_GPIO0_14
IO
General Purpose Input/Output
C9
MCU_GPIO0_15
IO
General Purpose Input/Output
D9
(1)
IO
General Purpose Input/Output
B8
MCU_GPIO0_17 (1)
IO
General Purpose Input/Output
B9
MCU_GPIO0_18
IOD
General Purpose Input/Output
E9
MCU_GPIO0_19
IOD
General Purpose Input/Output
A10
MCU_GPIO0_20 (1)
IO
General Purpose Input/Output
A11
MCU_GPIO0_21 (1)
IO
General Purpose Input/Output
B10
MCU_GPIO0_22
IO
General Purpose Input/Output
B13
MCU_GPIO0_12
MCU_GPIO0_16
(1)
This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
6.3.11 GPMC
6.3.11.1 MAIN Domain
Table 6-38. GPMC0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
O
GPMC Address Valid (active low) or Address Latch
Enable
GPMC0_CLK (1)
O
GPMC clock
R17
GPMC0_DIR
O
GPMC Data Bus Signal Direction Control
N17
O
GPMC functional clock output selected through a mux
logic
R17
R18
GPMC0_ADVn_ALE
GPMC0_FCLK_MUX
P16
O
GPMC Output Enable (active low) or Read Enable
(active low)
GPMC0_WEn
O
GPMC Write Enable (active low)
T21
GPMC0_WPn
O
GPMC Flash Write Protect (active low)
N16
GPMC0_OEn_REn
GPMC0_A0
GPMC0_A1
GPMC0_A2
GPMC0_A3
GPMC0_A4
GPMC0_A5
GPMC0_A6
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GPMC Address 0 Output. Only used to effectively
address 8-bit data non-multiplexed memories
U2, U7
OZ
GPMC address 1 Output in A/D non-multiplexed mode
and Address 17 in A/D multiplexed mode
AA2, V7
OZ
GPMC address 2 Output in A/D non-multiplexed mode
and Address 18 in A/D multiplexed mode
T2, W7
OZ
GPMC address 3 Output in A/D non-multiplexed mode
and Address 19 in A/D multiplexed mode
V4, W11
OZ
GPMC address 4 Output in A/D non-multiplexed mode
and Address 20 in A/D multiplexed mode
U4, V11
OZ
GPMC address 5 Output in A/D non-multiplexed mode
and Address 21 in A/D multiplexed mode
AA12, V1
OZ
GPMC address 6 Output in A/D non-multiplexed mode
and Address 22 in A/D multiplexed mode
W1, Y12
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Table 6-38. GPMC0 Signal Descriptions (continued)
SIGNAL NAME [1]
GPMC0_A7
GPMC0_A8
GPMC0_A9
GPMC0_A10
GPMC0_A11
GPMC0_A12
GPMC0_A13
GPMC0_A14
GPMC0_A15
GPMC0_A16
GPMC0_A17
GPMC0_A18
GPMC0_A19
GPMC0_A20
GPMC0_A21
GPMC0_A22
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
OZ
GPMC address 7 Output in A/D non-multiplexed mode
and Address 23 in A/D multiplexed mode
W12, Y4
OZ
GPMC address 8 Output in A/D non-multiplexed mode
and Address 24 in A/D multiplexed mode
AA13, T6
OZ
GPMC address 9 Output in A/D non-multiplexed mode
and Address 25 in A/D multiplexed mode
U11, U6
OZ
GPMC address 10 Output in A/D non-multiplexed
mode and Address 26 in A/D multiplexed mode
U5, V15
OZ
GPMC address 11 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
AA4, U12
OZ
GPMC address 12 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
P2, V14
OZ
GPMC address 13 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
P3, W14
OZ
GPMC address 14 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
AA10, AA3
OZ
GPMC address 15 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
R6, V10
OZ
GPMC address 16 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
T5, U10
OZ
GPMC address 17 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
AA11, U1
OZ
GPMC address 18 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
T4, Y11
OZ
GPMC address 19 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
R5, Y10
OZ
GPMC address 20 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
R21
OZ
GPMC address 21 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
Y18
OZ
GPMC address 22 Output in A/D non-multiplexed
mode and unused in A/D multiplexed mode
N16
IO
GPMC Data 0 Input/Output in A/D non-multiplexed
mode and additionally Address 1 Output in A/D
multiplexed mode
T20
IO
GPMC Data 1 Input/Output in A/D non-multiplexed
mode and additionally Address 2 Output in A/D
multiplexed mode
U21
IO
GPMC Data 2 Input/Output in A/D non-multiplexed
mode and additionally Address 3 Output in A/D
multiplexed mode
T18
IO
GPMC Data 3 Input/Output in A/D non-multiplexed
mode and additionally Address 4 Output in A/D
multiplexed mode
U20
IO
GPMC Data 4 Input/Output in A/D non-multiplexed
mode and additionally Address 5 Output in A/D
multiplexed mode
U18
IO
GPMC Data 5 Input/Output in A/D non-multiplexed
mode and additionally Address 6 Output in A/D
multiplexed mode
U19
IO
GPMC Data 6 Input/Output in A/D non-multiplexed
mode and additionally Address 7 Output in A/D
multiplexed mode
V20
GPMC0_AD0
GPMC0_AD1
GPMC0_AD2
GPMC0_AD3
GPMC0_AD4
GPMC0_AD5
GPMC0_AD6
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Table 6-38. GPMC0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
V21
IO
GPMC Data 8 Input/Output in A/D non-multiplexed
mode and additionally Address 9 Output in A/D
multiplexed mode
V19
IO
GPMC Data 9 Input/Output in A/D non-multiplexed
mode and additionally Address 10 Output in A/D
multiplexed mode
T17
IO
GPMC Data 10 Input/Output in A/D non-multiplexed
mode and additionally Address 11 Output in A/D
multiplexed mode
R16
IO
GPMC Data 11 Input/Output in A/D non-multiplexed
mode and additionally Address 12 Output in A/D
multiplexed mode
W20
IO
GPMC Data 12 Input/Output in A/D non-multiplexed
mode and additionally Address 13 Output in A/D
multiplexed mode
W21
IO
GPMC Data 13 Input/Output in A/D non-multiplexed
mode and additionally Address 14 Output in A/D
multiplexed mode
V18
IO
GPMC Data 14 Input/Output in A/D non-multiplexed
mode and additionally Address 15 Output in A/D
multiplexed mode
Y21
IO
GPMC Data 15 Input/Output in A/D non-multiplexed
mode and additionally Address 16 Output in A/D
multiplexed mode
Y20
IO
GPMC Data 16 Input/Output in A/D non-multiplexed
mode and additionally Address 17 Output in A/D
multiplexed mode
Y7
IO
GPMC Data 17 Input/Output in A/D non-multiplexed
mode and additionally Address 18 Output in A/D
multiplexed mode
U8
IO
GPMC Data 18 Input/Output in A/D non-multiplexed
mode and additionally Address 19 Output in A/D
multiplexed mode
W8
IO
GPMC Data 19 Input/Output in A/D non-multiplexed
mode and additionally Address 20 Output in A/D
multiplexed mode
V8
IO
GPMC Data 20 Input/Output in A/D non-multiplexed
mode and additionally Address 21 Output in A/D
multiplexed mode
Y8
IO
GPMC Data 21 Input/Output in A/D non-multiplexed
mode and additionally Address 22 Output in A/D
multiplexed mode
V13
IO
GPMC Data 22 Input/Output in A/D non-multiplexed
mode and additionally Address 23 Output in A/D
multiplexed mode
AA7
IO
GPMC Data 23 Input/Output in A/D non-multiplexed
mode and additionally Address 24 Output in A/D
multiplexed mode
U13
IO
GPMC Data 24 Input/Output in A/D non-multiplexed
mode and additionally Address 25 Output in A/D
multiplexed mode
W13
IO
GPMC Data 25 Input/Output in A/D non-multiplexed
mode and additionally Address 26 Output in A/D
multiplexed mode
U15
GPMC0_AD8
GPMC0_AD9
GPMC0_AD10
GPMC0_AD11
GPMC0_AD12
GPMC0_AD13
GPMC0_AD14
GPMC0_AD15
GPMC0_AD16
GPMC0_AD17
GPMC0_AD18
GPMC0_AD19
GPMC0_AD20
GPMC0_AD21
GPMC0_AD22
GPMC0_AD23
GPMC0_AD24
GPMC0_AD25
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ALV PIN [4]
IO
GPMC0_AD7
74
DESCRIPTION [3]
GPMC Data 7 Input/Output in A/D non-multiplexed
mode and additionally Address 8 Output in A/D
multiplexed mode
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Table 6-38. GPMC0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
IO
GPMC Data 26 Input/Output in A/D non-multiplexed
mode and additionally Address 27 Output in A/D
multiplexed mode
U14
IO
GPMC Data 27 Input/Output in A/D non-multiplexed
mode and additionally Address 28 Output in A/D
multiplexed mode
AA8
IO
GPMC Data 28 Input/Output in A/D non-multiplexed
mode and additionally Address 29 Output in A/D
multiplexed mode
U9
IO
GPMC Data 29 Input/Output in A/D non-multiplexed
mode and additionally Address 30 Output in A/D
multiplexed mode
W9
IO
GPMC Data 30 Input/Output in A/D non-multiplexed
mode and additionally Address 31 Output in A/D
multiplexed mode
AA9
IO
GPMC Data 31 Input/Output in A/D non-multiplexed
mode and additionally Address 0 Output in A/D
multiplexed mode
Y9
O
GPMC Lower-Byte Enable (active low) or Command
Latch Enable
P17
GPMC0_BE1n
O
GPMC Upper-Byte Enable (active low)
T19
GPMC0_BE2n
O
GPMC Upper-Byte Enable (active low)
V9
GPMC0_BE3n
O
GPMC Upper-Byte Enable (active low)
AA14
GPMC0_CSn0
O
GPMC Chip Select 0 (active low)
R19
GPMC0_CSn1
O
GPMC Chip Select 1 (active low)
R20
GPMC0_CSn2
O
GPMC Chip Select 2 (active low)
P19
GPMC0_CSn3
O
GPMC Chip Select 3 (active low)
R21
GPMC0_WAIT0
I
GPMC External Indication of Wait
W19
GPMC0_WAIT1
I
GPMC External Indication of Wait
Y18
GPMC0_AD26
GPMC0_AD27
GPMC0_AD28
GPMC0_AD29
GPMC0_AD30
GPMC0_AD31
GPMC0_BE0n_CLE
(1)
The RXACTIVE bit of the CTRLMMR_PADCONFIG32 register must be set to 0x1 and the TX_DIS bit of the
CTRLMMR_PADCONFIG32 register must be reset to 0x0 when GPMC0 is operating in synchronous mode.
6.3.12 I2C
6.3.12.1 MAIN Domain
Table 6-39. I2C0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
I2C0_SCL
IOD
I2C Clock
A18
I2C0_SDA
IOD
I2C Data
B18
Table 6-40. I2C1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
I2C1_SCL
IOD
I2C Clock
C18
I2C1_SDA
IOD
I2C Data
B19
Table 6-41. I2C2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
I2C2_SCL
IOD
I2C Clock
C13, P19
I2C2_SDA
IOD
I2C Data
D14, R21
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Table 6-42. I2C3 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
I2C3_SCL
IOD
I2C Clock
C17
I2C3_SDA
IOD
I2C Data
D17
6.3.12.2 MCU Domain
Table 6-43. MCU_I2C0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
MCU_I2C0_SCL
IOD
I2C Clock
E9
MCU_I2C0_SDA
IOD
I2C Data
A10
Table 6-44. MCU_I2C1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
MCU_I2C1_SCL
IOD
I2C Clock
A11
MCU_I2C1_SDA
IOD
I2C Data
B10
6.3.13 MCAN
6.3.13.1 MAIN Domain
Table 6-45. MCAN0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
MCAN0_RX
I
MCAN Receive Data
B17
MCAN0_TX
O
MCAN Transmit Data
A17
Table 6-46. MCAN1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
MCAN1_RX
I
MCAN Receive Data
D17
MCAN1_TX
O
MCAN Transmit Data
C17
6.3.14 MCSPI
6.3.14.1 MAIN Domain
Table 6-47. MCSPI0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
SPI0_CLK
IO
SPI Clock
D13
SPI0_CS0
IO
SPI Chip Select 0
D12
SPI0_CS1
IO
SPI Chip Select 1
C13
SPI0_CS2
IO
SPI Chip Select 2
B16
SPI0_CS3
IO
SPI Chip Select 3
A16
SPI0_D0
IO
SPI Data 0
A13
SPI0_D1
IO
SPI Data 1
A14
Table 6-48. MCSPI1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
SPI1_CLK
IO
SPI Clock
SPI1_CS0
IO
SPI Chip Select 0
B14
SPI1_CS1
IO
SPI Chip Select 1
D14
SPI1_CS2
IO
SPI Chip Select 2
D16
SPI1_CS3
IO
SPI Chip Select 3
E16
76
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Table 6-48. MCSPI1 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
SPI1_D0
IO
SPI Data 0
B15
SPI1_D1
IO
SPI Data 1
A15
Table 6-49. MCSPI2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
SPI2_CLK
IO
SPI Clock
E14
SPI2_CS0
IO
SPI Chip Select 0
E15
SPI2_CS1
IO
SPI Chip Select 1
C18
SPI2_CS2
IO
SPI Chip Select 2
B19
SPI2_CS3
IO
SPI Chip Select 3
A19
SPI2_D0
IO
SPI Data 0
D15
SPI2_D1
IO
SPI Data 1
C16
Table 6-50. MCSPI3 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
SPI3_CLK
IO
SPI Clock
U4
SPI3_CS0
IO
SPI Chip Select 0
U1
SPI3_CS1
IO
SPI Chip Select 1
T5
SPI3_CS2
IO
SPI Chip Select 2
V12
SPI3_CS3
IO
SPI Chip Select 3
V15
SPI3_D0
IO
SPI Data 0
R6
SPI3_D1
IO
SPI Data 1
V4
Table 6-51. MCSPI4 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
SPI4_CLK
IO
SPI Clock
B16
SPI4_CS0
IO
SPI Chip Select 0
E16
SPI4_CS1
IO
SPI Chip Select 1
A17
SPI4_CS2
IO
SPI Chip Select 0
B17
SPI4_CS3
IO
SPI Chip Select 2
D18
SPI4_D0
IO
SPI Data 0
A16
SPI4_D1
IO
SPI Data 1
D16
6.3.14.2 MCU Domain
Table 6-52. MCU_MCSPI0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
MCU_SPI0_CLK
IO
SPI Clock
E6
MCU_SPI0_CS0
IO
SPI Chip Select 0
D6
MCU_SPI0_CS1
IO
SPI Chip Select 1
C6
MCU_SPI0_CS2
IO
SPI Chip Select 2
D8
MCU_SPI0_CS3
IO
SPI Chip Select 3
B8
MCU_SPI0_D0
IO
SPI Data 0
E7
MCU_SPI0_D1
IO
SPI Data 1
B6
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Table 6-53. MCU_MCSPI1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
MCU_SPI1_CLK
IO
SPI Clock
D7
MCU_SPI1_CS0
IO
SPI Chip Select 0
A7
MCU_SPI1_CS1
IO
SPI Chip Select 1
B7
MCU_SPI1_CS2
IO
SPI Chip Select 2
E8
MCU_SPI1_CS3
IO
SPI Chip Select 3
B9
MCU_SPI1_D0
IO
SPI Data 0
C7
MCU_SPI1_D1
IO
SPI Data 1
C8
6.3.15 MDIO
6.3.15.1 MAIN Domain
Table 6-54. MDIO0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
MDIO0_MDC
O
MDIO Clock
R2, Y6
MDIO0_MDIO
IO
MDIO Data
AA6, P5
6.3.16 MMC
6.3.16.1 MAIN Domain
Table 6-55. MMC0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
MMC0_CALPAD (1)
A
MMC/SD/SDIO Calibration Resistor
F18
MMC0_CLK
IO
MMC/SD/SDIO Clock
G18
MMC0_CMD
IO
MMC/SD/SDIO Command
J21
MMC0_DS
IO
MMC Data Strobe
G19
MMC0_DAT0
IO
MMC/SD/SDIO Data
K20
MMC0_DAT1
IO
MMC/SD/SDIO Data
J20
MMC0_DAT2
IO
MMC/SD/SDIO Data
J18
MMC0_DAT3
IO
MMC/SD/SDIO Data
J17
MMC0_DAT4
IO
MMC/SD/SDIO Data
H17
MMC0_DAT5
IO
MMC/SD/SDIO Data
H19
MMC0_DAT6
IO
MMC/SD/SDIO Data
H18
MMC0_DAT7
IO
MMC/SD/SDIO Data
G17
(1)
An external 10 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
Table 6-56. MMC1 Signal Descriptions
SIGNAL NAME [1]
MMC1_CLK
(1)
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
IO
MMC/SD/SDIO Clock
L20
MMC1_CMD
IO
MMC/SD/SDIO Command
J19
MMC1_SDCD
I
SD Card Detect
D19
MMC1_SDWP
I
SD Write Protect
C20
MMC1_DAT0
IO
MMC/SD/SDIO Data
K21
MMC1_DAT1
IO
MMC/SD/SDIO Data
L21
MMC1_DAT2
IO
MMC/SD/SDIO Data
K19
MMC1_DAT3
IO
MMC/SD/SDIO Data
K18
(1)
78
For MMC1_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG164 register must remain in its default state
of 0x1 because of retiming purposes.
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6.3.17 OSPI
6.3.17.1 MAIN Domain
Table 6-57. OSPI0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
OSPI0_CLK
O
OSPI Clock
N20
OSPI0_DQS
I
OSPI Data Strobe (DQS) or Loopback Clock Input
N19
OSPI0_ECC_FAIL
I
OSPI ECC Status
L17
OSPI0_LBCLKO
IO
OSPI Loopback Clock Output
N21
OSPI0_CSn0
O
OSPI Chip Select 0 (active low)
L19
OSPI0_CSn1
O
OSPI Chip Select 1 (active low)
L18
OSPI0_CSn2
O
OSPI Chip Select 2 (active low)
K17
OSPI0_CSn3
O
OSPI Chip Select 3 (active low)
L17
OSPI0_D0
IO
OSPI Data 0
M19
OSPI0_D1
IO
OSPI Data 1
M18
OSPI0_D2
IO
OSPI Data 2
M20
OSPI0_D3
IO
OSPI Data 3
M21
OSPI0_D4
IO
OSPI Data 4
P21
OSPI0_D5
IO
OSPI Data 5
P20
OSPI0_D6
IO
OSPI Data 6
N18
OSPI0_D7
IO
OSPI Data 7
M17
OSPI0_RESET_OUT0
O
OSPI Reset
L17
OSPI0_RESET_OUT1
O
OSPI Reset
K17
6.3.18 Power Supply
Table 6-58. Power Supply Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
CAP_VDDS0 (1)
CAP
External capacitor connection for IO group 0
(1)
CAP
External capacitor connection for IO group 1
T7
CAP_VDDS2 (1)
CAP
External capacitor connection for IO group 2
R11
CAP_VDDS3 (1)
CAP
External capacitor connection for IO group 3
N14
CAP_VDDS4 (1)
CAP
External capacitor connection for IO group 4
M16
CAP_VDDS5 (1)
CAP
External capacitor connection for IO group 5
L13
CAP_VDDSHV_MMC1 (2)
CAP
External capacitor connection for MMC1
K15
CAP_VDDS_MCU (1)
CAP
External capacitor connection for IO MCU
VDDA_0P85_SERDES0
PWR
SERDES0 0.85 V analog supply
VDDA_0P85_SERDES0_C
PWR
SERDES0 clock 0.85 V analog supply
P11
VDDA_0P85_USB0
PWR
USB0 0.85 V analog supply
T12
VDDA_1P8_SERDES0
PWR
SERDES0 1.8 V analog supply
R14
VDDA_1P8_USB0
PWR
USB0 1.8 V analog supply
R15
VDDA_3P3_SDIO
PWR
SDIO 3.3 V analog supply
H15
VDDA_3P3_USB0
PWR
USB0 3.3 V analog supply
R13
VDDA_ADC
PWR
ADC0 analog supply
J13
VDDA_MCU
PWR
POR and MCU PLL analog supply
K12
VDDA_PLL0
PWR
Main, PER1, and R5F PLL analog supply
N12
VDDA_PLL1
PWR
ARM and DDR PLL analog supply
H9
VDDA_PLL2
PWR
PER0 PLL analog supply
J11
VDDA_TEMP0
PWR
TEMP0 analog supply
G11
CAP_VDDS1
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H12
H10
P12, P13
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Table 6-58. Power Supply Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
VDDA_TEMP1
PWR
TEMP1 analog supply
VDDR_CORE
PWR
RAM supply
VDDSHV0
PWR
IO supply for IO group 0
VDDSHV1
PWR
IO supply for IO group 1
M7, N6, P7
VDDSHV2
PWR
IO supply for IO group 2
R10, R8, T9
VDDSHV3
PWR
IO supply for IO group 3
P14, P15
VDDSHV4
PWR
IO supply for IO group 4
M14, M15
VDDSHV5
PWR
IO supply for IO group 5
VDDSHV_MCU
PWR
IO supply for IO MCU
F9, G10, G8
DDR PHY IO supply
F7, G6, H7, J6,
K7, L6
VDDS_DDR
PWR
L11
L10, M13
F11, G12, G14
L14, L15
VDDS_DDR_C
PWR
DDR clock IO supply
J8
VDDS_MMC0
PWR
MMC0 PHY IO supply
K14
VDDS_OSC
PWR
MCU_OSC0 supply
VDD_CORE
H13
J10, J12, K11,
K9, L12, L8,
M11, M9, N10,
N8, P9
Core supply
PWR
VDD_DLL_MMC0
PWR
MMC0 PLL analog supply
H14
VDD_MMC0
PWR
MMC0 PHY core supply
K13
VPP
PWR
eFuse ROM programming supply
VSS
Ground
GND
(1)
(2)
G15
A1, A21, A5, A6,
AA1, AA15,
AA18, AA21,
C10, C15, C3,
D1, E11, E13,
F10, F15, F8,
G1, G16, G3,
G7, G9, H11,
H20, H21, H6,
H8, J14, J7, J9,
K6, K8, L1, L16,
L3, L7, L9, M10,
M12, M6, M8,
N11, N13, N15,
N7, N9, P1, P10,
P18, P6, P8,
R12, R7, R9,
T10, T11, T15,
T16, T8, U3,
V17, W10, W18,
Y14, Y17, Y19
This pin must always be connected via a 1-μF capacitor to VSS.
This pin must always be connected via a 3.3-μF ±20% capacitor to VSS when the SDIO_LDO is being used to source VDDSHV5.
Otherwise, this pin may be connected directly to VSS when the VDDA_3P3_SDIO pin is also connected directly to VSS.
6.3.19 PRU_ICSSG
Note
The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU
GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in
the device TRM.
80
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6.3.19.1 MAIN Domain
Table 6-59. PRU_ICSSG0 Signal Descriptions
SIGNAL NAME [1]
PRG0_ECAP0_IN_APWM_OUT
PIN TYPE [2]
IO
DESCRIPTION [3]
ALV PIN [4]
PRU-ICSSG Enhanced Capture (ECAP) Input or
Auxiliary PWM (APWM) Output
R2, U5
P5, V5
PRG0_ECAP0_SYNC_IN
I
PRU-ICSSG ECAP Sync Input
PRG0_ECAP0_SYNC_OUT
O
PRU-ICSSG ECAP Sync Output
PRG0_IEP0_EDIO_OUTVALID
O
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid
I
PRU_ICSSG Industrial Ethernet Distributed Clock
Latch Input
V1
I
PRU_ICSSG Industrial Ethernet Distributed Clock
Latch Input
T1
O
PRU_ICSSG Industrial Ethernet Distributed Clock
Sync Output
W1
O
PRU_ICSSG Industrial Ethernet Distributed Clock
Sync Output
U1
IO
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
W6
IO
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
AA5
IO
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
Y5
IO
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
V6
I
PRU_ICSSG Industrial Ethernet Distributed Clock
Latch Input
P5
I
PRU_ICSSG Industrial Ethernet Distributed Clock
Latch Input
W5
O
PRU_ICSSG Industrial Ethernet Distributed Clock
Sync Output
R2
O
PRU_ICSSG Industrial Ethernet Distributed Clock
Sync Output
V5
PRG0_MDIO0_MDC
O
PRU-ICSSG MDIO Clock
P3
PRG0_MDIO0_MDIO
IO
PRU-ICSSG MDIO Data
P2
PRG0_IEP0_EDC_LATCH_IN0
PRG0_IEP0_EDC_LATCH_IN1
PRG0_IEP0_EDC_SYNC_OUT0
PRG0_IEP0_EDC_SYNC_OUT1
PRG0_IEP0_EDIO_DATA_IN_OUT28
PRG0_IEP0_EDIO_DATA_IN_OUT29
PRG0_IEP0_EDIO_DATA_IN_OUT30
PRG0_IEP0_EDIO_DATA_IN_OUT31
PRG0_IEP1_EDC_LATCH_IN0
PRG0_IEP1_EDC_LATCH_IN1
PRG0_IEP1_EDC_SYNC_OUT0
PRG0_IEP1_EDC_SYNC_OUT1
AA4, V5
C13
PRG0_PRU0_GPI0
I
PRU-ICSSG PRU Data Input
Y1
PRG0_PRU0_GPI1
I
PRU-ICSSG PRU Data Input
R4
PRG0_PRU0_GPI2
I
PRU-ICSSG PRU Data Input
U2
PRG0_PRU0_GPI3
I
PRU-ICSSG PRU Data Input
V2
PRG0_PRU0_GPI4
I
PRU-ICSSG PRU Data Input
AA2
PRG0_PRU0_GPI5
I
PRU-ICSSG PRU Data Input
R3
PRG0_PRU0_GPI6
I
PRU-ICSSG PRU Data Input
T3
PRG0_PRU0_GPI7
I
PRU-ICSSG PRU Data Input
T1
PRG0_PRU0_GPI8
I
PRU-ICSSG PRU Data Input
T2
PRG0_PRU0_GPI9
I
PRU-ICSSG PRU Data Input
W6
PRG0_PRU0_GPI10
I
PRU-ICSSG PRU Data Input
AA5
PRG0_PRU0_GPI11
I
PRU-ICSSG PRU Data Input
Y3
PRG0_PRU0_GPI12
I
PRU-ICSSG PRU Data Input
AA3
PRG0_PRU0_GPI13
I
PRU-ICSSG PRU Data Input
R6
PRG0_PRU0_GPI14
I
PRU-ICSSG PRU Data Input
V4
PRG0_PRU0_GPI15
I
PRU-ICSSG PRU Data Input
T5
PRG0_PRU0_GPI16
I
PRU-ICSSG PRU Data Input
U4
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Table 6-59. PRU_ICSSG0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
PRG0_PRU0_GPI17
I
PRU-ICSSG PRU Data Input
U1
PRG0_PRU0_GPI18
I
PRU-ICSSG PRU Data Input
V1
PRG0_PRU0_GPI19
I
PRU-ICSSG PRU Data Input
W1
PRG0_PRU0_GPO0
IO
PRU-ICSSG PRU Data Output
Y1
PRG0_PRU0_GPO1
IO
PRU-ICSSG PRU Data Output
R4
PRG0_PRU0_GPO2
IO
PRU-ICSSG PRU Data Output
U2
PRG0_PRU0_GPO3
IO
PRU-ICSSG PRU Data Output
V2
PRG0_PRU0_GPO4
IO
PRU-ICSSG PRU Data Output
AA2
PRG0_PRU0_GPO5
IO
PRU-ICSSG PRU Data Output
R3
PRG0_PRU0_GPO6
IO
PRU-ICSSG PRU Data Output
T3
PRG0_PRU0_GPO7
IO
PRU-ICSSG PRU Data Output
T1
PRG0_PRU0_GPO8
IO
PRU-ICSSG PRU Data Output
T2
PRG0_PRU0_GPO9
IO
PRU-ICSSG PRU Data Output
W6
PRG0_PRU0_GPO10
IO
PRU-ICSSG PRU Data Output
AA5
PRG0_PRU0_GPO11
IO
PRU-ICSSG PRU Data Output
Y3
PRG0_PRU0_GPO12
IO
PRU-ICSSG PRU Data Output
AA3
PRG0_PRU0_GPO13
IO
PRU-ICSSG PRU Data Output
R6
PRG0_PRU0_GPO14
IO
PRU-ICSSG PRU Data Output
V4
PRG0_PRU0_GPO15
IO
PRU-ICSSG PRU Data Output
T5
PRG0_PRU0_GPO16
IO
PRU-ICSSG PRU Data Output
U4
PRG0_PRU0_GPO17
IO
PRU-ICSSG PRU Data Output
U1
PRG0_PRU0_GPO18
IO
PRU-ICSSG PRU Data Output
V1
PRG0_PRU0_GPO19
IO
PRU-ICSSG PRU Data Output
W1
PRG0_PRU1_GPI0
I
PRU-ICSSG PRU Data Input
Y2
PRG0_PRU1_GPI1
I
PRU-ICSSG PRU Data Input
W2
PRG0_PRU1_GPI2
I
PRU-ICSSG PRU Data Input
V3
PRG0_PRU1_GPI3
I
PRU-ICSSG PRU Data Input
T4
PRG0_PRU1_GPI4
I
PRU-ICSSG PRU Data Input
W3
PRG0_PRU1_GPI5
I
PRU-ICSSG PRU Data Input
P4
PRG0_PRU1_GPI6
I
PRU-ICSSG PRU Data Input
R5
PRG0_PRU1_GPI7
I
PRU-ICSSG PRU Data Input
W5
PRG0_PRU1_GPI8
I
PRU-ICSSG PRU Data Input
R1
PRG0_PRU1_GPI9
I
PRU-ICSSG PRU Data Input
Y5
PRG0_PRU1_GPI10
I
PRU-ICSSG PRU Data Input
V6
PRG0_PRU1_GPI11
I
PRU-ICSSG PRU Data Input
W4
PRG0_PRU1_GPI12
I
PRU-ICSSG PRU Data Input
Y4
PRG0_PRU1_GPI13
I
PRU-ICSSG PRU Data Input
T6
PRG0_PRU1_GPI14
I
PRU-ICSSG PRU Data Input
U6
PRG0_PRU1_GPI15
I
PRU-ICSSG PRU Data Input
U5
PRG0_PRU1_GPI16
I
PRU-ICSSG PRU Data Input
AA4
PRG0_PRU1_GPI17
I
PRU-ICSSG PRU Data Input
V5
PRG0_PRU1_GPI18
I
PRU-ICSSG PRU Data Input
P5
PRG0_PRU1_GPI19
I
PRU-ICSSG PRU Data Input
R2
PRG0_PRU1_GPO0
IO
PRU-ICSSG PRU Data Output
Y2
PRG0_PRU1_GPO1
IO
PRU-ICSSG PRU Data Output
W2
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-59. PRU_ICSSG0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
PRG0_PRU1_GPO2
IO
PRU-ICSSG PRU Data Output
PRG0_PRU1_GPO3
IO
PRU-ICSSG PRU Data Output
T4
PRG0_PRU1_GPO4
IO
PRU-ICSSG PRU Data Output
W3
PRG0_PRU1_GPO5
IO
PRU-ICSSG PRU Data Output
P4
PRG0_PRU1_GPO6
IO
PRU-ICSSG PRU Data Output
R5
PRG0_PRU1_GPO7
IO
PRU-ICSSG PRU Data Output
W5
PRG0_PRU1_GPO8
IO
PRU-ICSSG PRU Data Output
R1
PRG0_PRU1_GPO9
IO
PRU-ICSSG PRU Data Output
Y5
PRG0_PRU1_GPO10
IO
PRU-ICSSG PRU Data Output
V6
PRG0_PRU1_GPO11
IO
PRU-ICSSG PRU Data Output
W4
PRG0_PRU1_GPO12
IO
PRU-ICSSG PRU Data Output
Y4
PRG0_PRU1_GPO13
IO
PRU-ICSSG PRU Data Output
T6
PRG0_PRU1_GPO14
IO
PRU-ICSSG PRU Data Output
U6
PRG0_PRU1_GPO15
IO
PRU-ICSSG PRU Data Output
U5
PRG0_PRU1_GPO16
IO
PRU-ICSSG PRU Data Output
AA4
PRG0_PRU1_GPO17
IO
PRU-ICSSG PRU Data Output
V5
PRG0_PRU1_GPO18
IO
PRU-ICSSG PRU Data Output
P5
PRG0_PRU1_GPO19
IO
PRU-ICSSG PRU Data Output
R2
PRG0_PWM0_TZ_IN
I
PRU_ICSSG PWM Trip Zone Input
V1
PRG0_PWM0_TZ_OUT
O
PRU_ICSSG PWM Trip Zone Output
W1
PRG0_PWM1_TZ_IN
I
PRU_ICSSG PWM Trip Zone Input
P5
PRG0_PWM1_TZ_OUT
O
PRU_ICSSG PWM Trip Zone Output
PRG0_PWM2_TZ_IN
I
PRU_ICSSG PWM Trip Zone Input
PRG0_PWM2_TZ_OUT
O
PRU_ICSSG PWM Trip Zone Output
R1, U21
PRG0_PWM3_TZ_IN
I
PRU_ICSSG PWM Trip Zone Input
P16, W6
PRG0_PWM3_TZ_OUT
O
PRU_ICSSG PWM Trip Zone Output
R17, Y3
PRG0_PWM0_A0
IO
PRU_ICSSG PWM Output A
PRG0_PWM0_A1
IO
PRU_ICSSG PWM Output A
V4
PRG0_PWM0_A2
IO
PRU_ICSSG PWM Output A
U4
PRG0_PWM0_B0
IO
PRU_ICSSG PWM Output B
R6
PRG0_PWM0_B1
IO
PRU_ICSSG PWM Output B
T5
PRG0_PWM0_B2
IO
PRU_ICSSG PWM Output B
U1
PRG0_PWM1_A0
IO
PRU_ICSSG PWM Output A
Y4
PRG0_PWM1_A1
IO
PRU_ICSSG PWM Output A
U6
PRG0_PWM1_A2
IO
PRU_ICSSG PWM Output A
AA4
PRG0_PWM1_B0
IO
PRU_ICSSG PWM Output B
T6
PRG0_PWM1_B1
IO
PRU_ICSSG PWM Output B
U5
PRG0_PWM1_B2
IO
PRU_ICSSG PWM Output B
V5
PRG0_PWM2_A0
IO
PRU_ICSSG PWM Output A
U2, U20
PRG0_PWM2_A1
IO
PRU_ICSSG PWM Output A
T2, U19
PRG0_PWM2_A2
IO
PRU_ICSSG PWM Output A
V19, V3
PRG0_PWM2_B0
IO
PRU_ICSSG PWM Output B
AA2, U18
PRG0_PWM2_B1
IO
PRU_ICSSG PWM Output B
AA5, V20
PRG0_PWM2_B2
IO
PRU_ICSSG PWM Output B
T17, W3
PRG0_PWM3_A0
IO
PRU_ICSSG PWM Output A
V18, Y1
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R2
T18, V6
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-59. PRU_ICSSG0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
PRG0_PWM3_A1
IO
PRU_ICSSG PWM Output A
R18, T3
PRG0_PWM3_A2
IO
PRU_ICSSG PWM Output A
T19, V2
PRG0_PWM3_B0
IO
PRU_ICSSG PWM Output B
R4, Y21
PRG0_PWM3_B1
IO
PRU_ICSSG PWM Output B
T1, T21
PRG0_PWM3_B2
IO
PRU_ICSSG PWM Output B
R3, W19
PRG0_RGMII1_RXC
I
PRU_ICSSG RGMII Receive Clock
PRG0_RGMII1_RX_CTL
I
PRU_ICSSG RGMII Receive Control
AA2
T3
PRG0_RGMII1_TXC
IO
PRU_ICSSG RGMII Transmit Clock
U4
PRG0_RGMII1_TX_CTL
O
PRU_ICSSG RGMII Transmit Control
T5
PRG0_RGMII2_RXC
I
PRU_ICSSG RGMII Receive Clock
R5
PRG0_RGMII2_RX_CTL
I
PRU_ICSSG RGMII Receive Control
W3
PRG0_RGMII2_TXC
IO
PRU_ICSSG RGMII Transmit Clock
AA4
PRG0_RGMII2_TX_CTL
O
PRU_ICSSG RGMII Transmit Control
PRG0_RGMII1_RD0
I
PRU_ICSSG RGMII Receive Data
Y1
PRG0_RGMII1_RD1
I
PRU_ICSSG RGMII Receive Data
R4
PRG0_RGMII1_RD2
I
PRU_ICSSG RGMII Receive Data
U2
PRG0_RGMII1_RD3
I
PRU_ICSSG RGMII Receive Data
V2
PRG0_RGMII1_TD0
O
PRU_ICSSG RGMII Transmit Data
Y3
PRG0_RGMII1_TD1
O
PRU_ICSSG RGMII Transmit Data
AA3
PRG0_RGMII1_TD2
O
PRU_ICSSG RGMII Transmit Data
R6
PRG0_RGMII1_TD3
O
PRU_ICSSG RGMII Transmit Data
V4
PRG0_RGMII2_RD0
I
PRU_ICSSG RGMII Receive Data
Y2
PRG0_RGMII2_RD1
I
PRU_ICSSG RGMII Receive Data
W2
PRG0_RGMII2_RD2
I
PRU_ICSSG RGMII Receive Data
V3
PRG0_RGMII2_RD3
I
PRU_ICSSG RGMII Receive Data
T4
PRG0_RGMII2_TD0
O
PRU_ICSSG RGMII Transmit Data
W4
PRG0_RGMII2_TD1
O
PRU_ICSSG RGMII Transmit Data
Y4
PRG0_RGMII2_TD2
O
PRU_ICSSG RGMII Transmit Data
T6
PRG0_RGMII2_TD3
O
PRU_ICSSG RGMII Transmit Data
U6
PRG0_UART0_CTSn
I
PRU-ICSSG UART Clear to Send (active low)
W6
PRG0_UART0_RTSn
O
PRU-ICSSG UART Request to Send (active low)
AA5
PRG0_UART0_RXD
I
PRU-ICSSG UART Receive Data
Y5
PRG0_UART0_TXD
O
PRU-ICSSG UART Transmit Data
V6
U5
Table 6-60. PRU_ICSSG1 Signal Descriptions
SIGNAL NAME [1]
PRG1_ECAP0_IN_APWM_OUT
PIN TYPE [2]
IO
DESCRIPTION [3]
PRU-ICSSG Enhanced Capture (ECAP) Input or
Auxiliary PWM (APWM) Output
ALV PIN [4]
V12
PRG1_ECAP0_SYNC_IN
I
PRU-ICSSG ECAP Sync Input
PRG1_ECAP0_SYNC_OUT
O
PRU-ICSSG ECAP Sync Output
PRG1_IEP0_EDIO_OUTVALID
O
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid
I
PRU_ICSSG Industrial Ethernet Distributed Clock
Latch Input
V7
I
PRU_ICSSG Industrial Ethernet Distributed Clock
Latch Input
U13
PRG1_IEP0_EDC_LATCH_IN0
PRG1_IEP0_EDC_LATCH_IN1
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AA14
D14
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
Table 6-60. PRU_ICSSG1 Signal Descriptions (continued)
SIGNAL NAME [1]
PRG1_IEP0_EDC_SYNC_OUT0
PRG1_IEP0_EDC_SYNC_OUT1
PRG1_IEP0_EDIO_DATA_IN_OUT28
PRG1_IEP0_EDIO_DATA_IN_OUT29
PRG1_IEP0_EDIO_DATA_IN_OUT30
PRG1_IEP0_EDIO_DATA_IN_OUT31
PRG1_IEP1_EDC_LATCH_IN0
PRG1_IEP1_EDC_LATCH_IN1
PRG1_IEP1_EDC_SYNC_OUT0
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
O
PRU_ICSSG Industrial Ethernet Distributed Clock
Sync Output
W7
O
PRU_ICSSG Industrial Ethernet Distributed Clock
Sync Output
U7
IO
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
U15
IO
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
U14
IO
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
V14
IO
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
W14
I
PRU_ICSSG Industrial Ethernet Distributed Clock
Latch Input
Y13
I
PRU_ICSSG Industrial Ethernet Distributed Clock
Latch Input
V15
O
PRU_ICSSG Industrial Ethernet Distributed Clock
Sync Output
V12
AA14
O
PRU_ICSSG Industrial Ethernet Distributed Clock
Sync Output
PRG1_MDIO0_MDC
O
PRU-ICSSG MDIO Clock
Y6
PRG1_MDIO0_MDIO
IO
PRU-ICSSG MDIO Data
AA6
PRG1_IEP1_EDC_SYNC_OUT1
PRG1_PRU0_GPI0
I
PRU-ICSSG PRU Data Input
PRG1_PRU0_GPI1
I
PRU-ICSSG PRU Data Input
U8
PRG1_PRU0_GPI2
I
PRU-ICSSG PRU Data Input
W8
PRG1_PRU0_GPI3
I
PRU-ICSSG PRU Data Input
V8
PRG1_PRU0_GPI4
I
PRU-ICSSG PRU Data Input
Y8
PRG1_PRU0_GPI5
I
PRU-ICSSG PRU Data Input
V13
PRG1_PRU0_GPI6
I
PRU-ICSSG PRU Data Input
AA7
PRG1_PRU0_GPI7
I
PRU-ICSSG PRU Data Input
U13
PRG1_PRU0_GPI8
I
PRU-ICSSG PRU Data Input
W13
PRG1_PRU0_GPI9
I
PRU-ICSSG PRU Data Input
U15
PRG1_PRU0_GPI10
I
PRU-ICSSG PRU Data Input
U14
PRG1_PRU0_GPI11
I
PRU-ICSSG PRU Data Input
AA8
PRG1_PRU0_GPI12
I
PRU-ICSSG PRU Data Input
U9
PRG1_PRU0_GPI13
I
PRU-ICSSG PRU Data Input
W9
PRG1_PRU0_GPI14
I
PRU-ICSSG PRU Data Input
AA9
PRG1_PRU0_GPI15
I
PRU-ICSSG PRU Data Input
Y9
PRG1_PRU0_GPI16
I
PRU-ICSSG PRU Data Input
V9
PRG1_PRU0_GPI17
I
PRU-ICSSG PRU Data Input
U7
PRG1_PRU0_GPI18
I
PRU-ICSSG PRU Data Input
V7
PRG1_PRU0_GPI19
I
PRU-ICSSG PRU Data Input
W7
PRG1_PRU0_GPO0
IO
PRU-ICSSG PRU Data Output
Y7
PRG1_PRU0_GPO1
IO
PRU-ICSSG PRU Data Output
U8
PRG1_PRU0_GPO2
IO
PRU-ICSSG PRU Data Output
W8
PRG1_PRU0_GPO3
IO
PRU-ICSSG PRU Data Output
V8
PRG1_PRU0_GPO4
IO
PRU-ICSSG PRU Data Output
Y8
PRG1_PRU0_GPO5
IO
PRU-ICSSG PRU Data Output
V13
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Table 6-60. PRU_ICSSG1 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
PRG1_PRU0_GPO6
IO
PRU-ICSSG PRU Data Output
AA7
PRG1_PRU0_GPO7
IO
PRU-ICSSG PRU Data Output
U13
PRG1_PRU0_GPO8
IO
PRU-ICSSG PRU Data Output
W13
PRG1_PRU0_GPO9
IO
PRU-ICSSG PRU Data Output
U15
PRG1_PRU0_GPO10
IO
PRU-ICSSG PRU Data Output
U14
PRG1_PRU0_GPO11
IO
PRU-ICSSG PRU Data Output
AA8
PRG1_PRU0_GPO12
IO
PRU-ICSSG PRU Data Output
U9
PRG1_PRU0_GPO13
IO
PRU-ICSSG PRU Data Output
W9
PRG1_PRU0_GPO14
IO
PRU-ICSSG PRU Data Output
AA9
PRG1_PRU0_GPO15
IO
PRU-ICSSG PRU Data Output
Y9
PRG1_PRU0_GPO16
IO
PRU-ICSSG PRU Data Output
V9
PRG1_PRU0_GPO17
IO
PRU-ICSSG PRU Data Output
U7
PRG1_PRU0_GPO18
IO
PRU-ICSSG PRU Data Output
V7
PRG1_PRU0_GPO19
IO
PRU-ICSSG PRU Data Output
W7
PRG1_PRU1_GPI0
I
PRU-ICSSG PRU Data Input
W11
PRG1_PRU1_GPI1
I
PRU-ICSSG PRU Data Input
V11
PRG1_PRU1_GPI2
I
PRU-ICSSG PRU Data Input
AA12
PRG1_PRU1_GPI3
I
PRU-ICSSG PRU Data Input
Y12
PRG1_PRU1_GPI4
I
PRU-ICSSG PRU Data Input
W12
PRG1_PRU1_GPI5
I
PRU-ICSSG PRU Data Input
AA13
PRG1_PRU1_GPI6
I
PRU-ICSSG PRU Data Input
U11
PRG1_PRU1_GPI7
I
PRU-ICSSG PRU Data Input
V15
PRG1_PRU1_GPI8
I
PRU-ICSSG PRU Data Input
U12
PRG1_PRU1_GPI9
I
PRU-ICSSG PRU Data Input
V14
PRG1_PRU1_GPI10
I
PRU-ICSSG PRU Data Input
W14
PRG1_PRU1_GPI11
I
PRU-ICSSG PRU Data Input
AA10
PRG1_PRU1_GPI12
I
PRU-ICSSG PRU Data Input
V10
PRG1_PRU1_GPI13
I
PRU-ICSSG PRU Data Input
U10
PRG1_PRU1_GPI14
I
PRU-ICSSG PRU Data Input
AA11
PRG1_PRU1_GPI15
I
PRU-ICSSG PRU Data Input
Y11
PRG1_PRU1_GPI16
I
PRU-ICSSG PRU Data Input
Y10
PRG1_PRU1_GPI17
I
PRU-ICSSG PRU Data Input
AA14
PRG1_PRU1_GPI18
I
PRU-ICSSG PRU Data Input
Y13
PRG1_PRU1_GPI19
I
PRU-ICSSG PRU Data Input
V12
PRG1_PRU1_GPO0
IO
PRU-ICSSG PRU Data Output
W11
PRG1_PRU1_GPO1
IO
PRU-ICSSG PRU Data Output
V11
PRG1_PRU1_GPO2
IO
PRU-ICSSG PRU Data Output
AA12
PRG1_PRU1_GPO3
IO
PRU-ICSSG PRU Data Output
Y12
PRG1_PRU1_GPO4
IO
PRU-ICSSG PRU Data Output
W12
PRG1_PRU1_GPO5
IO
PRU-ICSSG PRU Data Output
AA13
PRG1_PRU1_GPO6
IO
PRU-ICSSG PRU Data Output
U11
PRG1_PRU1_GPO7
IO
PRU-ICSSG PRU Data Output
V15
PRG1_PRU1_GPO8
IO
PRU-ICSSG PRU Data Output
U12
PRG1_PRU1_GPO9
IO
PRU-ICSSG PRU Data Output
V14
PRG1_PRU1_GPO10
IO
PRU-ICSSG PRU Data Output
W14
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Table 6-60. PRU_ICSSG1 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
PRG1_PRU1_GPO11
IO
PRU-ICSSG PRU Data Output
AA10
PRG1_PRU1_GPO12
IO
PRU-ICSSG PRU Data Output
V10
PRG1_PRU1_GPO13
IO
PRU-ICSSG PRU Data Output
U10
PRG1_PRU1_GPO14
IO
PRU-ICSSG PRU Data Output
AA11
PRG1_PRU1_GPO15
IO
PRU-ICSSG PRU Data Output
Y11
PRG1_PRU1_GPO16
IO
PRU-ICSSG PRU Data Output
Y10
PRG1_PRU1_GPO17
IO
PRU-ICSSG PRU Data Output
AA14
PRG1_PRU1_GPO18
IO
PRU-ICSSG PRU Data Output
Y13
PRG1_PRU1_GPO19
IO
PRU-ICSSG PRU Data Output
V12
PRG1_PWM0_TZ_IN
I
PRU_ICSSG PWM Trip Zone Input
V7
PRG1_PWM0_TZ_OUT
O
PRU_ICSSG PWM Trip Zone Output
W7
PRG1_PWM1_TZ_IN
I
PRU_ICSSG PWM Trip Zone Input
Y13
PRG1_PWM1_TZ_OUT
O
PRU_ICSSG PWM Trip Zone Output
V12
PRG1_PWM2_TZ_IN
I
PRU_ICSSG PWM Trip Zone Input
P19, W14
PRG1_PWM2_TZ_OUT
O
PRU_ICSSG PWM Trip Zone Output
R20, U12
PRG1_PWM3_TZ_IN
I
PRU_ICSSG PWM Trip Zone Input
U15
PRG1_PWM3_TZ_OUT
O
PRU_ICSSG PWM Trip Zone Output
AA8
PRG1_PWM0_A0
IO
PRU_ICSSG PWM Output A
U9
PRG1_PWM0_A1
IO
PRU_ICSSG PWM Output A
AA9
PRG1_PWM0_A2
IO
PRU_ICSSG PWM Output A
V9
PRG1_PWM0_B0
IO
PRU_ICSSG PWM Output B
W9
PRG1_PWM0_B1
IO
PRU_ICSSG PWM Output B
Y9
PRG1_PWM0_B2
IO
PRU_ICSSG PWM Output B
U7
PRG1_PWM1_A0
IO
PRU_ICSSG PWM Output A
V10
PRG1_PWM1_A1
IO
PRU_ICSSG PWM Output A
AA11
PRG1_PWM1_A2
IO
PRU_ICSSG PWM Output A
Y10
PRG1_PWM1_B0
IO
PRU_ICSSG PWM Output B
U10
PRG1_PWM1_B1
IO
PRU_ICSSG PWM Output B
Y11
PRG1_PWM1_B2
IO
PRU_ICSSG PWM Output B
AA14
PRG1_PWM2_A0
IO
PRU_ICSSG PWM Output A
N16, W8
PRG1_PWM2_A1
IO
PRU_ICSSG PWM Output A
P17, W13
PRG1_PWM2_A2
IO
PRU_ICSSG PWM Output A
AA12, V21
PRG1_PWM2_B0
IO
PRU_ICSSG PWM Output B
N17, Y8
PRG1_PWM2_B1
IO
PRU_ICSSG PWM Output B
U14, Y18
PRG1_PWM2_B2
IO
PRU_ICSSG PWM Output B
R16, W12
PRG1_PWM3_A0
IO
PRU_ICSSG PWM Output A
Y7
PRG1_PWM3_A1
IO
PRU_ICSSG PWM Output A
AA7
PRG1_PWM3_A2
IO
PRU_ICSSG PWM Output A
V8
PRG1_PWM3_B0
IO
PRU_ICSSG PWM Output B
U8
PRG1_PWM3_B1
IO
PRU_ICSSG PWM Output B
U13
PRG1_PWM3_B2
IO
PRG1_RGMII1_RXC
PRG1_RGMII1_RX_CTL
PRU_ICSSG PWM Output B
V13
I
PRU_ICSSG RGMII Receive Clock
AA7
I
PRU_ICSSG RGMII Receive Control
Y8
PRG1_RGMII1_TXC
IO
PRU_ICSSG RGMII Transmit Clock
V9
PRG1_RGMII1_TX_CTL
O
PRU_ICSSG RGMII Transmit Control
Y9
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Table 6-60. PRU_ICSSG1 Signal Descriptions (continued)
SIGNAL NAME [1]
PRG1_RGMII2_RXC
PRG1_RGMII2_RX_CTL
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
I
PRU_ICSSG RGMII Receive Clock
U11
I
PRU_ICSSG RGMII Receive Control
W12
PRG1_RGMII2_TXC
IO
PRU_ICSSG RGMII Transmit Clock
Y10
PRG1_RGMII2_TX_CTL
O
PRU_ICSSG RGMII Transmit Control
Y11
PRG1_RGMII1_RD0
I
PRU_ICSSG RGMII Receive Data
Y7
PRG1_RGMII1_RD1
I
PRU_ICSSG RGMII Receive Data
U8
PRG1_RGMII1_RD2
I
PRU_ICSSG RGMII Receive Data
W8
PRG1_RGMII1_RD3
I
PRU_ICSSG RGMII Receive Data
V8
PRG1_RGMII1_TD0
O
PRU_ICSSG RGMII Transmit Data
AA8
PRG1_RGMII1_TD1
O
PRU_ICSSG RGMII Transmit Data
U9
PRG1_RGMII1_TD2
O
PRU_ICSSG RGMII Transmit Data
W9
PRG1_RGMII1_TD3
O
PRU_ICSSG RGMII Transmit Data
AA9
PRG1_RGMII2_RD0
I
PRU_ICSSG RGMII Receive Data
W11
PRG1_RGMII2_RD1
I
PRU_ICSSG RGMII Receive Data
V11
PRG1_RGMII2_RD2
I
PRU_ICSSG RGMII Receive Data
AA12
PRG1_RGMII2_RD3
I
PRU_ICSSG RGMII Receive Data
Y12
PRG1_RGMII2_TD0
O
PRU_ICSSG RGMII Transmit Data
AA10
PRG1_RGMII2_TD1
O
PRU_ICSSG RGMII Transmit Data
V10
PRG1_RGMII2_TD2
O
PRU_ICSSG RGMII Transmit Data
U10
PRG1_RGMII2_TD3
O
PRU_ICSSG RGMII Transmit Data
AA11
PRG1_UART0_CTSn
I
PRU-ICSSG UART Clear to Send (active low)
U15
PRG1_UART0_RTSn
O
PRU-ICSSG UART Request to Send (active low)
U14
PRG1_UART0_RXD
I
PRU-ICSSG UART Receive Data
V14
PRG1_UART0_TXD
O
PRU-ICSSG UART Transmit Data
W14
6.3.20 Reserved
Table 6-61. Reserved Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
RSVD0
N/A
Reserved, must be left unconnected
H16
RSVD1
N/A
Reserved, must be left unconnected
D21
RSVD2
N/A
Reserved, must be left unconnected
G13
RSVD3
N/A
Reserved, must be left unconnected
F17
RSVD4
N/A
Reserved, must be left unconnected
W15
RSVD5
N/A
Reserved, must be left unconnected
V16
RSVD6
N/A
Reserved, must be left unconnected
K2
RSVD7
N/A
Reserved, must be left unconnected
K1
RSVD8
N/A
Reserved, must be left unconnected
F12
6.3.21 SERDES
6.3.21.1 MAIN Domain
Table 6-62. SERDES0 Signal Descriptions
SIGNAL NAME [1] ((2))
PCIE0_CLKREQn
SERDES0_REXT
(1)
SERDES0_REFCLK0N
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PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
IO
PCIE Clock Request Signal
D16
A
External SerDes PHY Calibration Resistor
T13
IO
SerDes PHY Reference Clock Input/Output (negative)
W16
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Table 6-62. SERDES0 Signal Descriptions (continued)
SIGNAL NAME [1] ((2))
PIN TYPE [2]
SERDES0_REFCLK0P
IO
DESCRIPTION [3]
ALV PIN [4]
SerDes PHY Reference Clock Input/Output (positive)
W17
SERDES0_RX0_N
I
SerDes PHY Differential Receive Data (negative)
Y15
SERDES0_RX0_P
I
SerDes PHY Differential Receive Data (positive)
Y16
SERDES0_TX0_N
O
SerDes PHY Differential Transmit Data (negative)
AA16
SERDES0_TX0_P
O
SerDes PHY Differential Transmit Data (positive)
AA17
(1)
(2)
An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
The functionality of these pins is controlled by SERDES0_LN0_CTRL_LANE_FUNC_SEL.
6.3.22 System and Miscellaneous
6.3.22.1 Boot Mode Configuration
6.3.22.1.1 MAIN Domain
Table 6-63. Sysboot Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
BOOTMODE00
I
Bootmode pin 0
T20
BOOTMODE01
I
Bootmode pin 1
U21
BOOTMODE02
I
Bootmode pin 2
T18
BOOTMODE03
I
Bootmode pin 3
U20
BOOTMODE04
I
Bootmode pin 4
U18
BOOTMODE05
I
Bootmode pin 5
U19
BOOTMODE06
I
Bootmode pin 6
V20
BOOTMODE07
I
Bootmode pin 7
V21
BOOTMODE08
I
Bootmode pin 8
V19
BOOTMODE09
I
Bootmode pin 9
T17
BOOTMODE10
I
Bootmode pin 10
R16
BOOTMODE11
I
Bootmode pin 11
W20
BOOTMODE12
I
Bootmode pin 12
W21
BOOTMODE13
I
Bootmode pin 13
V18
BOOTMODE14
I
Bootmode pin 14
Y21
BOOTMODE15
I
Bootmode pin 15
Y20
6.3.22.2 Clock
6.3.22.2.1 MCU Domain
Table 6-64. MCU Clock Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
MCU_OSC0_XI
I
High frequency oscillator input
C21
MCU_OSC0_XO
O
High frequency oscillator output
B20
6.3.22.3 System
6.3.22.3.1 MAIN Domain
Table 6-65. System Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
O
RMII Clock Output (50 MHz). This pin is used for clock
source to the external PHY and must be routed back to
the RMII_REF_CLK pin for proper device operation.
A19, U13
I
External Interrupt
CLKOUT0
EXTINTn
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Table 6-65. System Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
I
External clock input to Main Domain, routed to Timer
clock muxes as one of the selectable input clock
sources for Timer/WDT modules, or as reference clock
to MAIN_PLL2 (PER1 PLL)
A19
O
Observation clock output for test and debug purposes
only
D17
PORz_OUT
O
Main Domain POR status output
E17
RESETSTATz
O
Main Domain warm reset status output
F16
RESET_REQz
I
Main Domain external warm reset request input
E18
O
SYSCLK0 output from Main PLL controller (divided by
6) for test and debug purposes only
C17
EXT_REFCLK1
OBSCLK0
SYSCLKOUT0
6.3.22.3.2 MCU Domain
Table 6-66. MCU System Signal Descriptions
SIGNAL NAME [1]
MCU_EXT_REFCLK0
PIN TYPE [2]
DESCRIPTION [3]
I
External system clock input
ALV PIN [4]
B7
O
Observation clock output for test and debug purposes
only
MCU_PORz
I
MCU Domain cold reset
B21
MCU_RESETSTATz
O
MCU Domain warm reset status output
B13
MCU_RESETz
I
MCU Domain warm reset
B12
IO
Error signal output from MCU Domain ESM
A20
O
MCU Domain system clock output for test and debug
purposes only
C6
MCU_OBSCLK0
MCU_SAFETY_ERRORn
MCU_SYSCLKOUT0
C6, E10
6.3.22.4 VMON
Table 6-67. VMON Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
VMON_1P8_MCU
A
Voltage monitor input for 1.8 V MCU power supply
K16
VMON_1P8_SOC
A
Voltage monitor input for 1.8 V SoC power supply
E12
VMON_3P3_MCU
A
Voltage monitor input for 3.3 V MCU power supply
F13
VMON_3P3_SOC
A
Voltage monitor input for 3.3 V SoC power supply
F14
A
Voltage monitor input, fixed 0.45 V (+/-3%) threshold.
Use with external precision voltage divider to monitor a
higher voltage rail such as the PMIC input supply.
K10
VMON_VSYS
6.3.23 TIMER
6.3.23.1 MAIN Domain
Table 6-68. TIMER Signal Descriptions
SIGNAL NAME [1]
TIMER_IO0
TIMER_IO1
TIMER_IO2
TIMER_IO3
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PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
IO
Timer Inputs and Outputs (not tied to single timer
instance)
C18, K18
IO
Timer Inputs and Outputs (not tied to single timer
instance)
B19, K19
IO
Timer Inputs and Outputs (not tied to single timer
instance)
A17, L21
IO
Timer Inputs and Outputs (not tied to single timer
instance)
B17, K21
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Table 6-68. TIMER Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
TIMER_IO4
TIMER_IO5
TIMER_IO6
TIMER_IO7
TIMER_IO8
TIMER_IO9
TIMER_IO10
TIMER_IO11
DESCRIPTION [3]
ALV PIN [4]
IO
Timer Inputs and Outputs (not tied to single timer
instance)
C17, L20
IO
Timer Inputs and Outputs (not tied to single timer
instance)
D17, J19
IO
Timer Inputs and Outputs (not tied to single timer
instance)
B16, D19, T1
IO
Timer Inputs and Outputs (not tied to single timer
instance)
A16, C20, U7
IO
Timer Inputs and Outputs (not tied to single timer
instance)
P19, V7
IO
Timer Inputs and Outputs (not tied to single timer
instance)
R21, W7
IO
Timer Inputs and Outputs (not tied to single timer
instance)
C13, U13
IO
Timer Inputs and Outputs (not tied to single timer
instance)
D14, U1
6.3.23.2 MCU Domain
Table 6-69. MCU_TIMER Signal Descriptions
SIGNAL NAME [1]
MCU_TIMER_IO0
MCU_TIMER_IO1
MCU_TIMER_IO2
MCU_TIMER_IO3
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
IO
Timer Inputs and Outputs (not tied to single timer
instance)
D8
IO
Timer Inputs and Outputs (not tied to single timer
instance)
E8
IO
Timer Inputs and Outputs (not tied to single timer
instance)
B8
IO
Timer Inputs and Outputs (not tied to single timer
instance)
B9
6.3.24 UART
6.3.24.1 MAIN Domain
Table 6-70. UART0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
UART0_CTSn
I
UART Clear to Send (active low)
B16
UART0_DCDn
I
UART Data Carrier Detect (active low)
C17
UART0_DSRn
I
UART Data Set Ready (active low)
D17
UART0_DTRn
O
UART Data Terminal Ready (active low)
A17
UART0_RIn
I
UART Ring Indicator
B17
UART0_RTSn
O
UART Request to Send (active low)
A16
UART0_RXD
I
UART Receive Data
D15
UART0_TXD
O
UART Transmit Data
C16
Table 6-71. UART1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
UART1_CTSn
I
UART Clear to Send (active low)
D16
UART1_RTSn
O
UART Request to Send (active low)
E16
UART1_RXD
I
UART Receive Data
E15
UART1_TXD
O
UART Transmit Data
E14
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Table 6-72. UART2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
UART2_CTSn
I
UART Clear to Send (active low)
UART2_RTSn
O
UART Request to Send (active low)
UART2_RXD
I
UART2_TXD
O
ALV PIN [4]
L20, V19, Y1
J19, T18, U2
UART Receive Data
B16, K18, T20,
V1, W6
UART Transmit Data
A16, K19, R4,
U21
Table 6-73. UART3 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
UART3_CTSn
I
UART Clear to Send (active low)
UART3_RTSn
O
UART Request to Send (active low)
UART3_RXD
I
UART3_TXD
O
ALV PIN [4]
D19, T17, V2
C20, R3, U19
UART Receive Data
AA5, D16, L21,
U20, W1
UART Transmit Data
AA2, E16, K21,
U18
Table 6-74. UART4 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
UART4_CTSn
I
UART Clear to Send (active low)
R16, R5, T3, V1
UART4_RTSn
O
UART Request to Send (active low)
R1, R17, T2, W1
UART4_RXD
I
UART4_TXD
O
UART Receive Data
A17, L20, V20,
W4, Y3
UART Transmit Data
B17, J19, T1,
V21, W5, Y4
Table 6-75. UART5 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
UART5_CTSn
I
UART Clear to Send (active low)
UART5_RTSn
O
UART Request to Send (active low)
UART5_RXD
I
UART5_TXD
O
ALV PIN [4]
W20, Y13, Y2
T21, V12, V3
UART Receive Data
C17, D19, P16,
T6, Y5
UART Transmit Data
C20, D17, R18,
W2
Table 6-76. UART6 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
UART6_CTSn
I
UART Clear to Send (active low)
UART6_RTSn
O
UART Request to Send (active low)
UART6_RXD
I
UART6_TXD
O
ALV PIN [4]
T4, W21
P17, P4
UART Receive Data
C13, U6, V6,
Y21
UART Transmit Data
D14, W3, Y20
6.3.24.2 MCU Domain
Table 6-77. MCU_UART0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
MCU_UART0_CTSn
I
UART Clear to Send (active low)
D8
MCU_UART0_RTSn
O
UART Request to Send (active low)
E8
MCU_UART0_RXD
I
UART Receive Data
A9
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Table 6-77. MCU_UART0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
MCU_UART0_TXD
O
DESCRIPTION [3]
ALV PIN [4]
UART Transmit Data
A8
Table 6-78. MCU_UART1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
MCU_UART1_CTSn
I
UART Clear to Send (active low)
B8
MCU_UART1_RTSn
O
UART Request to Send (active low)
B9
MCU_UART1_RXD
I
UART Receive Data
C9
MCU_UART1_TXD
O
UART Transmit Data
D9
6.3.25 USB
6.3.25.1 MAIN Domain
Table 6-79. USB0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
USB0_DM
IO
USB 2.0 Differential Data (negative)
AA20
USB0_DP
IO
USB 2.0 Differential Data (positive)
AA19
USB0_DRVVBUS
O
USB VBUS control output (active high)
E19
USB0_ID
A
USB 2.0 Dual-Role Device Role Select
U16
USB0_RCALIB (1)
A
Pin to connect to calibration resistor
U17
USB0_VBUS (2)
A
USB Level-shifted VBUS Input
T14
(1)
(2)
An external 499 Ω ±1% resistor must be connected between this pin and VSS. The maximum power dissipation for the resistor is
7.2mW. No external voltage should be applied to this pin.
An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 9.2.3, USB
VBUS Design Guidelines.
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6.4 Pin Connectivity Requirements
This section describes connectivity requirements for package balls that have specific connectivity requirements
and unused package balls.
Note
All power balls must be supplied with the voltages specified in the Recommended Operating
Conditions section, unless otherwise specified.
Note
For additional clarification, "leave unconnected" or "no connect" (NC) means no signal traces can be
connected to these device ball numbers.
Table 6-80. Connectivity Requirements
BALL NUMBER
BALL NAME
CONNECTION REQUIREMENTS
A20
D11
MCU_SAFETY_ERRORn
TRSTn
Each of these balls must be connected to VSS through separate
external pull resistors to ensure the inputs associated with these
balls are held to a valid logic low level if a PCB signal trace
is connected and not actively driven by an attached device. The
internal pull-down can be used to hold a valid logic low level if no
PCB signal trace is connected to the ball.
D10
E10
B12
E18
B11
C11
C12
EMU0
EMU1
MCU_RESETz
RESET_REQz
TCK
TDI
TMS
Each of these balls must be connected to the corresponding power
supply(1) through separate external pull resistors to ensure the inputs
associated with these balls are held to a valid logic high level if a
PCB signal trace is connected and not actively driven by an attached
device. The internal pull-up can be used to hold a valid logic high
level if no PCB signal trace is connected to the ball.
A18
B18
E9
A10
I2C0_SCL
I2C0_SDA
MCU_I2C0_SCL
MCU_I2C0_SDA
Each of these balls must be connected to the corresponding power
supply(1) through separate external pull resistors to ensure the inputs
associated with these balls are held to a valid logic high level.
T20
U21
T18
U20
U18
U19
V20
V21
V19
T17
R16
W20
W21
V18
Y21
Y20
GPMC0_AD0
GPMC0_AD1
GPMC0_AD2
GPMC0_AD3
GPMC0_AD4
GPMC0_AD5
GPMC0_AD6
GPMC0_AD7
GPMC0_AD8
GPMC0_AD9
GPMC0_AD10
GPMC0_AD11
GPMC0_AD12
GPMC0_AD13
GPMC0_AD14
GPMC0_AD15
Each of these balls must be connected to the corresponding power
supply(1) or VSS through separate external pull resistors to ensure
the inputs associated with these balls are held to a valid logic high or
low level as appropriate to select the desired device boot mode.
J13
G20
F20
E21,
D20
G21
F21
F19
E20
J15
J16
VDDA_ADC
ADC0_AIN0
ADC0_AIN1
ADC0_AIN2
ADC0_AIN3
ADC0_AIN4
ADC0_AIN5
ADC0_AIN6
ADC0_AIN7
ADC0_REFP
ADC0_REFN
If the entire ADC0 is not used, each of these balls must be
connected directly to VSS.
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Table 6-80. Connectivity Requirements (continued)
BALL NUMBER
BALL NAME
CONNECTION REQUIREMENTS
G20
F20
E21,
D20
G21
F21
F19
E20
ADC0_AIN0
ADC0_AIN1
ADC0_AIN2
ADC0_AIN3
ADC0_AIN4
ADC0_AIN5
ADC0_AIN6
ADC0_AIN7
Any unused ADC0_AIN[7:0] ball must be pulled to VSS through a
resistor or connected directly to VSS when VDDA_ADC is connected
to a power source.
F7
G6
H7
J6,
K7
L6
J8
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR_C
If DDRSS0 is not used, each of these balls must be connected
directly to VSS.
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Table 6-80. Connectivity Requirements (continued)
BALL NUMBER
BALL NAME
CONNECTION REQUIREMENTS
H2
H1
J5
K5
F6
H4
D2
C5
E2
D4
D3
F2
J2
L5
J3
J4
K3
J1
M5
K4
G4
G5
G2
H3
H5
F1
E1
F4
F3
E3
E4
B2
M2
A3
A2
B5
A4
B3
C4
C2
B4
N5
L4
L2
M3
N4
N3
M4
N2
C1
B1
N1
M1
E5
F5
D5
DDR0_ACT_n
DDR0_ALERT_n
DDR0_CAS_n
DDR0_PAR
DDR0_RAS_n
DDR0_WE_n
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
DDR0_CAL0
DDR0_CK0
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n
DDR0_CS1_n
DDR0_DM0
DDR0_DM1
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQS0
DDR0_DQS0_n
DDR0_DQS1
DDR0_DQS1_n
DDR0_ODT0
DDR0_ODT1
DDR0_RESET0_n
K13
H14
VDD_MMC0
VDD_DLL_MMC0
If MMC0 is not used, each of these balls must be connected to the
same power source as VDD_CORE.
K14
VDDS_MMC0
If MMC0 is not used, each of these balls must be connected to
any 1.8-V power source that does not violate device power supply
sequencing requirements.
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If DDRSS0 is not used, leave unconnected.
Note: The DDR0 pins in this list can only be left unconnected
when VDDS_DDR and VDDS_DDR_C are connected to VSS. The
DDR0 pins must be connected as defined in the AM64x\AM243x
DDR Board Design and Layout Guidelines, when VDDS_DDR and
VDDS_DDR_C are connected to a power source.
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Table 6-80. Connectivity Requirements (continued)
BALL NUMBER
BALL NAME
CONNECTION REQUIREMENTS
F18
G18
J21
G19
K20
J20
J18
J17
H17
H19
H18
G17
MMC0_CALPAD
MMC0_CLK
MMC0_CMD
MMC0_DS
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3
MMC0_DAT4
MMC0_DAT5
MMC0_DAT6
MMC0_DAT7
If MMC0 is not used, each of these balls must be left unconnected.
H15
K15
VDDA_3P3_SDIO
CAP_VDDSHV_MMC1
If SDIO_LDO is not used to power VDDSHV5, each of these balls
must be connected directly to VSS.
P12
P13
P11
R14
VDDA_0P85_SERDES0
VDDA_0P85_SERDES0
VDDA_0P85_SERDES0_C
VDDA_1P8_SERDES0
T13
W16
W17
Y15
Y16
AA16
AA17
SERDES0_REXT
SERDES0_REFCLK0N
SERDES0_REFCLK0P
SERDES0_RX0_N
SERDES0_RX0_P
SERDES0_TX0_N
SERDES0_TX0_P
T12
R15
R13
VDDA_0P85_USB0
VDDA_1P8_USB0
VDDA_3P3_USB0
AA20
AA19
U16
U17
T14
USB0_DM
USB0_DP
USB0_ID
USB0_RCALIB
USB0_VBUS
K10
VMON_VSYS
If VMON_VSYS is not used, this ball must be connected directly to
VSS.
K16
E12
F13
F14
VMON_1P8_MCU
VMON_1P8_SOC
VMON_3P3_MCU
VMON_3P3_SOC
If VMON_1P8_MCU, VMON_1P8_SOC, VMON_3P3_MCU, and
VMON_3P3_SOC are not used to monitor the MCU and SOC power
rails, these balls must still be connected to their respective 1.8-V and
3.3-V power rails.
If SERDES0 is not used and the device boundary scan function
is required, each of these balls must be connected to valid power
sources.
If SERDES0 is not used and the device boundary scan function
is not required, each of these balls can alternatively be connected
directly to VSS.
If SERDES0 is not used, leave unconnected.
Note: The SERDES0_REXT pin can only be left unconnected
when VDDA_0P85_SERDES0, VDDA_0P85_SERDES0_C, and
VDDA_1P8_SERDES0 are connected to VSS. The
SERDES0_REXT pin must be connected to VSS through
the appropriate external resistor when VDDA_0P85_SERDES0,
VDDA_0P85_SERDES0_C, and VDDA_1P8_SERDES0 are
connected to power sources.
If USB0 is not used, each of these balls must be connected directly
to VSS.
If USB0 is not used, leave unconnected.
(1)
Note: The USB0_RCALIB pin can only be left unconnected when
VDDA_0P85_USB0, VDDA_1P8_USB0, and VDDA_3P3_USB0
are connected to VSS. The USB0_RCALIB pin must be
connected to VSS through the appropriate external resistor when
VDDA_0P85_USB0, VDDA_1P8_USB0, and VDDA_3P3_USB0 are
connected to power sources.
To determine which power supply is associated with any IO, see the POWER column of the Pin Attributes table.
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Note
Internal pull resistors are weak and may not source enough current to maintain a valid logic level
for some operating conditions. This can be the case when connected to components with leakage
to the opposite logic level, or when external noise sources couple to signal traces attached to balls
which are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors are
recommended to hold a valid logic level on balls with external connections.
Many of the device IOs are turned off by default and external pull resistors may be required to hold
inputs of any attached device in a valid logic state until software initializes the respective IOs. The
state of configurable device IOs are defined in the BALL STATE DURING RESET RX/TX/PULL and
BALL STATE AFTER RESET RX/TX/PULL columns of the Pin Attributes table. Any IO with its input
buffer (RX) turned off is allowed to float without damaging the device. However, any IO with its input
buffer (RX) turned on shall never be allowed to float to any potential between VILSS and VIHSS. The
input buffer can enter a high-current state which could damage the IO cell if allowed to float between
these levels.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
(1)(2)
PARAMETER
MIN
MAX
UNIT
VDD_CORE
Core supply
-0.3
1.05
V
VDDR_CORE
RAM supply
-0.3
1.05
V
VDD_MMC0
MMC0 PHY core supply
-0.3
1.05
V
VDD_DLL_MMC0
MMC0 PLL analog supply
-0.3
1.05
V
VDDA_0P85_SERDES0
SERDES0 0.85-V analog supply
-0.3
1.05
V
VDDA_0P85_SERDES0_C
SERDES0 clock 0.85-V analog supply
-0.3
1.05
V
VDDA_0P85_USB0
USB0 0.85-V analog supply
-0.3
1.05
V
VDDS_DDR
DDR PHY IO supply
-0.3
1.57
V
VDDS_DDR_C
DDR clock IO supply
-0.3
1.57
V
VDDS_MMC0
MMC0 PHY IO supply
-0.3
1.98
V
VDDS_OSC
MCU_OSC0 supply
-0.3
1.98
V
VDDA_MCU
POR and MCU PLL analog supply
-0.3
1.98
V
VDDA_ADC0
ADC0 analog supply
-0.3
1.98
V
VDDA_PLL0
Main, PER1, and R5F PLL analog supply
-0.3
1.98
V
VDDA_PLL1
ARM and DDR PLL analog supply
-0.3
1.98
V
VDDA_PLL2
PER0 PLL analog supply
-0.3
1.98
V
VDDA_1P8_SERDES0
SERDES0 1.8-V analog supply
-0.3
1.98
V
VDDA_1P8_USB0
USB0 1.8-V analog supply
-0.3
1.98
V
VDDA_TEMP0
TEMP0 analog supply
-0.3
1.98
V
VDDA_TEMP1
TEMP1 analog supply
-0.3
1.98
V
VPP
eFuse ROM programming supply
-0.3
1.98
V
VDDSHV_MCU
IO supply for IO MCU
-0.3
3.63
V
VDDSHV0
IO supply for IO group 0
-0.3
3.63
V
VDDSHV1
IO supply for IO group 1
-0.3
3.63
V
VDDSHV2
IO supply for IO group 2
-0.3
3.63
V
VDDSHV3
IO supply for IO group 3
-0.3
3.63
V
VDDSHV4
IO supply for IO group 4
-0.3
3.63
V
VDDSHV5
IO supply for IO group 5
-0.3
3.63
V
VDDA_3P3_USB0
USB0 3.3-V analog supply
-0.3
3.63
V
VDDA_3P3_SDIO
SDIO 3.3-V analog supply
Steady-state max voltage at all fail-safe IO pins
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-0.3
3.63
V
MCU_PORz
-0.3
3.63
V
MCU_I2C0_SCL, MCU_I2C0_SDA,
I2C0_SCL, I2C0_SDA, and EXTINTn
When operating at 1.8V
-0.3
1.98(3)
V
MCU_I2C0_SCL, MCU_I2C0_SDA,
I2C0_SCL, I2C0_SDA, and EXTINTn
When operating at 3.3V
-0.3
3.63(3)
VMON_1P8_MCU, and
VMON_1P8_SOC
-0.3
1.98
V
VMON_3P3_MCU, and
VMON_3P3_SOC
-0.3
3.63
V
VMON_VSYS(4)
-0.3
1.98
V
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over operating junction temperature range (unless otherwise noted)
(1)(2)
PARAMETER
Steady-state max voltage at all other IO pins(5)
MIN
MAX
USB0_VBUS(6)
-0.3
3.6
USB0_ID(7)
-0.3
3.6
-0.3
IO supply
voltage + 0.3
V
0.2 × VDD(8)
V
All other IO pins
20% of IO supply voltage for up to 20%
of the signal period (see Figure 7-1, IO
Transient Voltage Ranges)
Transient overshoot and undershoot at IO pin
I-Test
Latch-up performance(9)
Over-Voltage (OV) Test
TSTG
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
-100
+100
1.5 x
Storage temperature
-55
UNIT
V
mA
VDD(8)
V
+150
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Section 7.4, Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be
fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltage values are with respect to VSS, unless otherwise noted.
The absolute maximum ratings for these fail-safe pins depends on their IO supply operating voltage. Therefore, this value is also
defined by the maximum VIH value found in the I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics section, where
the electrical characteristics table has separate parameter values for 1.8-V mode and 3.3-V mode.
The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see Section 9.2.4, System Power
Supply Monitor Design Guidelines.
This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be
–0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used
to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range,
including power supply ramp-up and ramp-down sequences.
An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.2.3, USB
Design Guidelines.
The USB0_ID pin is connected to analog circuits in the USB0 PHY. The analog circuits source a known current while measuring
voltage, to determine the resistance value (RID), if connected to VSS through a resistor. This pin should be connected to VSS for USB
host operation, or left unconnected for USB device operation, and should never be connected to any external voltage source.
VDD is the voltage on the corresponding power-supply pin(s) for the IO.
For current pulse injection (I-Test):
•
Pins stressed per JEDEC JESD78 (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times
maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.
For over-voltage performance (Over-Voltage (OV) Test):
•
Supplies stressed per JEDEC JESD78 (Class II) and passed specified voltage injection.
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power
supply voltage. This allows external voltage sources to be connected to these IO terminals when the
respective IO power supplies are turned off. The MCU_I2C0_SCL, MCU_I2C0_SDA, I2C0_SCL, I2C0_SDA,
EXTINTn, VMON_1P8_MCU, VMON_1P8_SOC, VMON_3P3_MCU, VMON_3P3_SOC, VMON_VSYS, and
MCU_PORz are the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to
them should be limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in Section
7.1.
Overshoot = 20% of nominal
IO supply voltage
Tovershoot
Tperiod
Tundershoot
Undershoot = 20% of nominal
IO supply voltage
A.
Tovershoot + Tundershoot < 20% of Tperiod
Figure 7-1. IO Transient Voltage Ranges
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7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
(ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±1000
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Power-On Hours (POH)
POWER ON HOURS (POH)(1) (2) (3)
JUNCTION TEMPERATURE RANGE (TJ)
Extended Industrial
(1)
(2)
(3)
LIFETIME (POH)
–40°C to 105°C
100000
This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard
terms and conditions for TI semiconductor products.
Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted
temperatures.
POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH.
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7.4 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
SUPPLY NAME
MIN(1)
NOM
0.75-V operation
0.715
0.75
0.79
V
0.85-V operation
0.81
0.85
0.895
V
DESCRIPTION
MAX(1)
UNIT
VDD_CORE
Core supply
VDDR_CORE
RAM supply
0.81
0.85
0.895
V
VDD_MMC0(2)
MMC0 PHY core supply
0.81
0.85
0.895
V
VDD_DLL_MMC0(2)
MMC0 PLL analog supply
0.81
0.85
0.895
V
VDDA_0P85_SERDES0
SERDES0 0.85 V analog supply
0.81
0.85
0.895
V
VDDA_0P85_SERDES0_C SERDES0 clock 0.85 V analog supply
0.81
0.85
0.895
V
VDDA_0P85_USB0
USB0 0.85 V analog supply
0.81
0.85
0.895
V
VDDS_DDR(3)
DDR PHY IO supply
DDR clock IO supply
1.1-V operation
1.06
1.1
1.17
V
VDDS_DDR_C(3)
1.2-V operation
1.14
1.2
1.26
V
VDDS_MMC0
MMC0 PHY IO supply
1.71
1.8
1.89
V
VDDS_OSC
MCU_OSC0 supply
1.71
1.8
1.89
V
VDDA_MCU
POR and MCU PLL analog supply
1.71
1.8
1.89
V
VDDA_ADC0
ADC0 analog supply
1.71
1.8
1.89
V
VDDA_PLL0
Main, PER and R5F PLL analog supply
1.71
1.8
1.89
V
VDDA_PLL1
ARM and DDR PLL analog supply
1.71
1.8
1.89
V
VDDA_PLL2
PER0 PLL analog supply
1.71
1.8
1.89
V
VDDA_1P8_SERDES0
SERDES0 1.8 V analog supply
1.71
1.8
1.89
V
VDDA_1P8_USB0
USB0 1.8 V analog supply
1.71
1.8
1.89
V
VDDA_TEMP0
TEMP0 analog supply
1.71
1.8
1.89
V
VDDA_TEMP1
TEMP1 analog supply
1.71
1.8
1.89
V
VPP
eFuse ROM programming supply
1.71
1.8
1.89
V
VMON_1P8_MCU
Voltage monitor for 1.8 V MCU power supply
1.71
1.8
1.89
V
VMON_1P8_SOC
Voltage monitor for 1.8 V SoC power supply
1.71
1.8
1.89
V
VDDA_3P3_USB0
USB0 3.3 V analog supply
3.135
3.3
3.465
V
VDDA_3P3_SDIO
SDIO 3.3 V analog supply
3.135
3.3
3.465
V
VMON_3P3_MCU
Voltage monitor for 3.3 V MCU power supply
3.135
3.3
3.465
V
VMON_3P3_SOC
Voltage monitor for 3.3 V SoC power supply
3.135
3.3
3.465
V
VMON_VSYS
Voltage monitor pin
0
see(4)
1
V
0
see(5)
3.465
V
USB0_VBUS
USB Level-shifted VBUS Input
USB0_ID
USB0 analog I/O for RID detection
VDDSHV_MCU
Dual-voltage IO supply
VDDSHV0
Dual-voltage IO supply
VDDSHV1
Dual-voltage IO supply
VDDSHV2
Dual-voltage IO supply
VDDSHV3
Dual-voltage IO supply
VDDSHV4
Dual-voltage IO supply
102
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V
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.135
3.3
3.465
V
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.135
3.3
3.465
V
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.135
3.3
3.465
V
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.135
3.3
3.465
V
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.135
3.3
3.465
V
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.135
3.3
3.465
V
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over operating junction temperature range (unless otherwise noted)
SUPPLY NAME
VDDSHV5
Dual-voltage IO supply
TJ
(1)
(2)
(3)
(4)
(5)
(6)
MIN(1)
NOM
MAX(1)
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.135
3.3
3.465
V
DESCRIPTION
Operating junction temperature range
Automotive
–40
125
Extended Industrial
–40
105
UNIT
°C
The voltage at the device ball must never drop below the MIN voltage or rise above the MAX voltage for any amount of time during
normal device operation.
VDD_MMC0 and VDD_DLL_MMC0 must be connected to the same power source as VDD_CORE when MMC0 is not used. In this
case, VDD_MMC0 and VDD_DLL_MMC0 may be operated at a nominal voltage of 0.75 or 0.85.
VDDS_DDR and VDDS_DDR_C shall be sourced from the same power source.
The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see Section 9.2.4, System Power
Supply Monitor Design Guidelines.
An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.2.3, USB
Design Guidelines.
The USB0_ID pin is connected to analog circuits in the USB0 PHY. The analog circuits source a known current while measuring
voltage, to determine the resistance value (RID), if connected to VSS through a resistor. This pin should be connected to VSS for USB
host operation, or left unconnected for USB device operation, and should never be connected to any external voltage source.
7.5 Operating Performance Points
This section describes the operating conditions of the device. This section also contains the description of each
Operating Performance Point (OPP) for processor clocks and device core clocks.
Table 7-1 describes the maximum supported frequency per speed grade for the device.
Table 7-1. Speed Grade Maximum Frequency
MAXIMUM FREQUENCY (MHz)
(1)
DEVICE
SPEED
GRADE
A53SS
R5FSS
M4FSS
CBASS0
ICSSG
DMSC-L
DDR4(1)
LPDDR4(1)
AM64x
S
1000
800
400
250
333
250
800 (DDR-1600)
800 (LPDDR-1600)
AM64x
K
800
400
400
250
250
250
800 (DDR-1600)
800 (LPDDR-1600)
Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.
Refer to AM64x\AM243x DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR
frequency.
7.6 Power Consumption Summary
For information on the device power consumption, see the AM64x/AM243x Power Estimation Tool application
note.
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7.7 Electrical Characteristics
Note
The interfaces or signals described in Section 7.7.1 through Section 7.7.10 correspond to the
interfaces or signals available in multiplexing mode 0 (Primary Function).
All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical
characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC
electrical characteristics are specified for the different multiplexing modes (Functions).
7.7.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.8 V MODE
VIL
Input Low Voltage
VILSS
Input Low Voltage Steady State
VIH
Input High Voltage
(1)
0.7 × VDD
IIN
Input Leakage Current.
VOL
Output Low Voltage
VI = 1.8 V
or
VI = 0 V
±10
VOL(MAX)
Input Low Voltage
VILSS
Input Low Voltage Steady State
10
mA
V/s
(1)
Input High Voltage
0.7 × VDD
VIHSS
Input High Voltage Steady State
0.7 × VDD
Input Hysteresis Voltage
IIN
Input Leakage Current.
VOL
Output Low Voltage
IOL (3)
Low Level Output Current
SRI (5)
Input Slew Rate
(2)
(3)
(4)
(5)
(6)
104
V
18f(4)
or
1.8E+6
VIH
(1)
(1)
µA
(6)
VIL
VHYS
V
0.2 × VDD
Input Slew Rate
3.3 V MODE
V
1.98(2)
V
0.1 × VDD
SRI (5)
0.3 × VDD
mV
0.7 × VDD
Input Hysteresis Voltage
Low Level Output Current
V
(1)
(1)
Input High Voltage Steady State
VHYS
IOL
(1)
(1)
VIHSS
(3)
0.3 × VDD
0.3 × VDD
(1)
V
0.25 × VDD
(1)
V
3.63(2)
V
(1)
V
(1)
mV
0.05 × VDD
VI = 3.3 V
or
VI = 0 V
±10
0.4
VOL(MAX)
10
33f(4)
or
3.3E+6
µA
V
mA
8E+7
V/s
VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
This value also defines the Absolute Maximum Ratings value the IO.
The IOL parameter defines the minimum Low Level Output Current for which the device is able to maintain the specified VOL value.
The value defined by this parameter should be considered the maximum current available to a system implementation which needs to
maintain the specified VOL value for attached components.
f = toggle frequency of the input signal in Hz.
This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
I2C Hs-mode is not supported when operating the IO in 3.3 V mode.
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7.7.2 Fail-Safe Reset (FS RESET) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIL
Input Low Voltage
0.3 ×
VDDS_OSC
VILSS
Input Low Voltage Steady State
0.3 ×
VDDS_OSC
VIH
Input High Voltage
0.7 ×
VDDS_OSC
V
VIHSS
Input High Voltage Steady State
0.7 ×
VDDS_OSC
V
VHYS
Input Hysteresis Voltage
IIN
Input Leakage Current.
SRI (2)
Input Slew Rate
(1)
(2)
200
V
V
mV
VI = 1.8 V
or
VI = 0 V
±10
µA
18f(1)
or
1.8E+6
V/s
f = toggle frequency of the input signal in Hz.
This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
7.7.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.35 ×
VDDS_OSC
VIL
Input Low Voltage
VIH
Input High Voltage
VHYS
Input Hysteresis Voltage
IIN
Input Leakage Current.
V
0.65 ×
VDDS_OSC
V
49
VI = 1.8 V
or
VI = 0.0 V
mV
±10
µA
MAX
UNIT
7.7.4 eMMCPHY Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIL
Input Low Voltage
VILSS
Input Low Voltage Steady State
TEST CONDITIONS
VIH
Input High Voltage
VIHSS
Input High Voltage Steady State
IIN
Input Leakage Current.
RPU
Pull-up Resistor
RPD
Pull-down Resistor
VOL
Output Low Voltage
IOL = 2 mA
VOH
Output High Voltage
IOH = -2 mA
SRI
Input Slew Rate
MIN
TYP
0.35 ×
VDDS_MMC0
V
0.20
V
0.65 ×
VDDS_MMC0
V
1.4
V
VI = 1.8 V or 0 V
15
20
15
20
±10
µA
25
kΩ
25
kΩ
0.30
VDDS_MMC0
- 0.30
V
5E+8
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V
V/s
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7.7.5 SDIO Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.8 V MODE
VIL
Input Low Voltage
0.58
V
VILSS
Input Low Voltage Steady State
0.58
V
VIH
Input High Voltage
VIHSS
Input High Voltage Steady State
VHYS
Input Hysteresis Voltage
1.27
V
1.7
V
150
mV
VI = 1.8 V
or
VI = 0 V
IIN
Input Leakage Current.
RPU
Pull-up Resistor
40
RPD
Pull-down Resistor
40
VOL
Output Low Voltage
VOH
Output High Voltage
IOL (1)
Low Level Output Current
VOL(MAX)
4
mA
IOH (1)
High Level Output Current
VOH(MIN)
4
mA
SRI (3)
±10
µA
50
60
kΩ
50
60
kΩ
0.45
VDDSHV5 0.45
V
V
18f(2)
Input Slew Rate
or
1.8E+6
V/s
3.3 V MODE
VIL
Input Low Voltage
0.25 ×
VDDSHV5
V
VILSS
Input Low Voltage Steady State
0.15 ×
VDDSHV5
V
VIH
Input High Voltage
0.625 ×
VDDSHV5
V
VIHSS
Input High Voltage Steady State
0.625 ×
VDDSHV5
V
VHYS
Input Hysteresis Voltage
IIN
Input Leakage Current.
RPU
Pull-up Resistor
40
RPD
Pull-down Resistor
40
VOL
Output Low Voltage
VOH
Output High Voltage
IOL (1)
Low Level Output Current
VOL(MAX)
6
mA
IOH (1)
High Level Output Current
VOH(MIN)
10
mA
SRI (3)
(1)
(2)
(3)
106
150
mV
VI = 3.3 V
or
VI = 0 V
±10
µA
50
60
kΩ
50
60
kΩ
0.125 ×
VDDSHV5
0.75 ×
VDDSHV5
V
V
33f(2)
Input Slew Rate
or
3.3E+6
V/s
The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is
able to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current
available to a system implementation which needs to maintain the specified VOL and VOH values for attached components.
f = toggle frequency of the input signal in Hz.
This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
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7.7.6 LVCMOS Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.8-V MODE
VIL
Input Low Voltage
VILSS
Input Low Voltage Steady State
V
0.3 × VDD(1)
V
VDD(1)
V
V
VIH
Input High Voltage
0.65 ×
VIHSS
Input High Voltage Steady State
0.85 × VDD(1)
VHYS
Input Hysteresis Voltage
150
mV
VI = 1.8 V
or
VI = 0.0 V
IIN
Input Leakage Current.
RPU
Pull-up Resistor
15
RPD
Pull-down Resistor
15
VOL
Output Low Voltage
VDD(1)
VOH
Output High Voltage
IOL (2)
Low Level Output Current
VOL(MAX)
IOH (2)
High Level Output Current
VOH(MIN)
SRI (4)
0.35 × VDD(1)
Input Slew Rate
±10
µA
22
30
kΩ
22
30
kΩ
0.45
V
- 0.45
V
3
mA
3
mA
18f(3)
or
1.8E+6
V/s
3.3-V MODE
VIL
Input Low Voltage
0.8
V
VILSS
Input Low Voltage Steady State
VIH
Input High Voltage
0.6
V
VIHSS
Input High Voltage Steady State
2.0
V
VHYS
Input Hysteresis Voltage
150
mV
IIN
Input Leakage Current.
RPU
Pull-up Resistor
15
RPD
Pull-down Resistor
15
VOL
Output Low Voltage
VOH
Output High Voltage
2.0
V
VI = 3.3 V
or
VI = 0.0 V
±10
µA
22
30
kΩ
22
30
kΩ
0.4
V
2.4
V
(2)
Low Level Output Current
VOL(MAX)
5
mA
IOH (2)
High Level Output Current
VOH(MIN)
9
mA
IOL
SRI (4)
(1)
(2)
(3)
(4)
33f(3)
Input Slew Rate
or
3.3E+6
V/s
VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is
able to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current
available to a system implementation which needs to maintain the specified VOL and VOH values for attached components.
f = toggle frequency of the input signal in Hz.
This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
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7.7.7 ADC12B Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
VADC0_VREFP (1)
Positive Reference Voltage,
ADC0_VREFP
VADC0_VREFN (1)
Negative Reference Voltage,
ADC0_VREFN
TEST CONDITIONS
MIN
TYP
1.71
MAX
UNIT
1.89
V
VSS
V
VADC_AIN[7:0]
Analog Input Voltage,
ADC_AIN[7:0], Full-scale
VSS
VDDA_ADC0
DNL
Differential Non-Linearity
> -1
+1
LSB
INL
Integral Non-Linearity
-2
+2
LSB
V
LSBGAIN-ERROR
Gain Error
±10
LSB
LSBOFFSET-ERROR
Offset Error
±5
LSB
SNR
Signal-to-Noise Ratio
Input Signal:
200 kHz sine wave at
-0.5 dB Full Scale
70
dB
THD
Total Harmonic Distortion
Input Signal:
200 kHz sine wave at
-0.5 dB Full Scale
-75
dB
ZADC_AIN[0:7]
Analog Input Impedance,
ADC0_AIN[7:0]
IIN
CSMPL
(2)
Ω
Input Leakage
±10
μA
Sampling Capacitance
5.5
pF
ADC0 SMPL_CLK Frequency
60
MHz
13
ADC0
SMPL_CLK
Cycles
Sampling Dynamics
FSMPL_CLK
tC
Conversion Time
tACQ
Acquisition Time
TR
Sampling Rate
ADC0
257 SMPL_CLK
Cycles
2
ADC0 SMPL_CLK
= 60 MHz
4
MSPS
General Purpose Input Mode (3)
VIL
VILSS
108
V
Input Low Voltage Steady State
0.35 ×
VDDA_ADC0
V
0.65 ×
VDDA_ADC0
V
VIHSS
Input High Voltage Steady State
0.65 ×
VDDA_ADC0
V
VHYS
Input Hysteresis Voltage
II
(2)
0.35 ×
VDDA_ADC0
Input High Voltage
VIH
(1)
Input Low Voltage
Input Leakage Current
200
mV
ADC0_AIN[7:0] =
VDDA_ADC0
or
ADC0_AIN[7:0] = VSS
10
μA
The ADC0_REFP and ADC0_REFN reference inputs are analog inputs which must be treated like high transient power supply rails.
ADC0_REFN is expected to be connected directly to the PCB ground plane along with all other VSS pins, and ADC0_REFP is
connected to a power source capable of providing at least 4 mA of current. ADC0_REFP can be connected to the same power source
as VDDA_ADC0 if the voltage tolerance of the supply provides an acceptable accuracy for the ADC reference. A high frequency
decoupling capacitor must be connected directly to the ADC0_REFP and ADC0_REFN pins with vias and be placed in the ball array
on the back side of the PCB.
The ADC0_AIN pins are connected to an internal sampling capacitor for a user configurable acquisition time and acquisition frequency.
The input impedance of the ADC0_AIN pins is a function of the sampling capacitance along with user configurable acquisition time and
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acquisition frequency. The designer must understand the time required for the source impedance of each ADC0_AIN pin to charge the
internal sampling capacitor. The acquisition time must be set long enough for the internal sampling capacitor to settle to greater than
14 bits of accuracy.
ADC0 can be configured to operate in General Purpose Input mode, where all ADC0_AIN[7:0] inputs are globally enabled to operate
as digital inputs via the ADC0_CTRL register (gpi_mode_en = 1).
7.7.8 USB2PHY Electrical Characteristics
Note
USB0 interface is compliant with Universal Serial Bus Revision 2.0 Specification dated April 27, 2000
including ECNs and Errata as applicable.
7.7.9 SerDes PHY Electrical Characteristics
Note
The PCIe interface is compliant with the electrical parameters specified in PCI Express® Base
Specification Revision 4.0, February 19, 2014.
Note
USB0 instance is compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative
Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0 , July
26, 2013.
7.7.10 DDR Electrical Characteristics
Note
The DDR interface is compatible with DDR4 devices that are JESD79-4B standard-compliant, and
LPDDR4 devices that are JESD209-4B standard-compliant
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7.8 VPP Specifications for One-Time Programmable (OTP) eFuses
This section specifies the operating conditions required for programming the OTP eFuses..
7.8.1 Recommended Operating Conditions for OTP eFuse Programming
over operating junction temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
VDD_CORE
Supply voltage range for the core domain during OTP
operation; OPP NOM (BOOT)
VPP
Supply voltage range for the eFuse ROM domain during
normal operation without hardware support to program eFuse
ROM
MIN
NOM
See Recommended Operating
Conditions
I(VPP)
VPP current
SR(VPP)
VPP Slew Rate
TJ
Operating junction temperature range while programming
eFuse ROM.
(1)
(2)
UNIT
V
NC(1)
V
0
V
Supply voltage range for the eFuse ROM domain during
normal operation with hardware support to program eFuse
ROM
Supply voltage range for the eFuse ROM domain during OTP
programming(2)
MAX
1.71
1.8
0
25
1.89
V
400
mA
6E+4
V/s
85
°C
NC stands for No Connect.
Supply voltage range includes DC errors and peak-to-peak noise.
7.8.2 Hardware Requirements
The following hardware requirements must be met when programming keys in the OTP eFuses:
• The VPP power supply must be disabled when not programming OTP registers.
• The VPP power supply must be ramped up after the proper device power-up sequence (for more details, see
Section 7.10.2, Power Supply Sequencing).
7.8.3 Programming Sequence
Programming sequence for OTP eFuses:
• Power on the board per the power-up sequencing. No voltage should be applied on the VPP terminal during
power up and normal operation.
• Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP
software package).
• Apply the voltage on the VPP terminal according to the specification in Section 7.8.1.
• Run the software that programs the OTP registers.
• After validating the content of the OTP registers, remove the voltage from the VPP terminal.
7.8.4 Impact to Your Hardware Warranty
You accept that e-Fusing the TI Devices with security keys permanently alters them. You acknowledge that
the e-Fuse can fail, for example, due to incorrect or aborted program sequence or if you omit a sequence
step. Further the TI Device may fail to secure boot if the error code correction check fails for the Production
Keys or if the image is not signed and optionally encrypted with the current active Production Keys. These
types of situations will render the TI Device inoperable and TI will be unable to confirm whether the TI Devices
conformed to their specifications prior to the attempted e-Fuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY
(WARRANTY OR OTHERWISE) FOR ANY TI DEVICES THAT HAVE BEEN e-FUSED WITH SECURITY KEYS.
110
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7.9 Thermal Resistance Characteristics
For operation and reliability concerns, the maximum junction temperature of the device must be equal to or less
than the TJ value identified in Recommended Operating Conditions.
7.9.1 Thermal Resistance Characteristics
Table 7-2. Thermal Resistance Characteristics
TI recommends performing system level thermal simulations with worst case device power consumption.
°C/W(2)
AIR FLOW
(m/s)(3)
Junction-to-case
0.98
N/A
RΘJB
Junction-to-board
3.87
N/A
RΘJA
Junction-to-free air
12.8
0
9.2
1
8.2
2
T6
7.6
3
T7
0.53
0
0.55
1
0.57
2
T10
0.58
3
T11
3.74
0
T12
3.5
1
3.4
2
3.3
3
NO.
PARAMETER(1)
T1
RΘJC
T2
T3
DESCRIPTION
ALV Package
T4
T5
RΘJA
T8
Junction-to-moving air
ΨJT
T9
T13
Junction-to-package top
ΨJB
Junction-to-board
T14
(1)
(2)
(3)
These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and is subject to change based on environment as well as application. For more information, see the
EIA/JEDEC standards.
• JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Packages
°C/W = degrees Celsius per watt.
m/s = meters per second.
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7.10 Timing and Switching Characteristics
Note
The Timing Requirements and Switching Characteristics values may change following the silicon
characterization result.
Note
The default SLEWRATE settings in each pad configuration register must be used to ensure timings,
unless specific instructions are given otherwise.
7.10.1 Timing Parameters and Information
The timing parameter symbols used in Timing and Switching Characteristics sections are created in accordance
with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies have been
abbreviated in Table 7-3:
Table 7-3. Timing Parameters Subscripts
112
SYMBOL
PARAMETER
c
Cycle time (period)
d
Delay time
dis
Disable time
en
Enable time
h
Hold time
su
Setup time
START
Start bit
t
Transition time
v
Valid time
w
Pulse duration (width)
X
Unknown, changing, or don't care level
F
Fall time
H
High
L
Low
R
Rise time
V
Valid
IV
Invalid
AE
Active Edge
FE
First Edge
LE
Last Edge
Z
High impedance
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7.10.2 Power Supply Requirements
This section describes the power supply requirements to ensure proper device operation.
Note
All power balls must be supplied with the voltages specified in the Recommended Operating
Conditions section, unless otherwise specified in Signal Descriptions and Pin Connectivity
Requirements.
7.10.2.1 Power Supply Slew Rate Requirement
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the
maximum slew rate of supplies to be less than 18 mV/µs. For instance, as shown in Figure 7-2, TI recommends
having the supply ramp slew for a 1.8-V supply of more than 100 µs.
Figure 7-2 describes the Power Supply Slew Rate Requirement in the device.
Supply value
t
slew rate < 18 mV/μs
slew > (supply value) / (18 mV/μs)
or
supply value × 55.6 μs/V
SPRT740_ELCH_06
Figure 7-2. Power Supply Slew and Slew Rate
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7.10.2.2 Power Supply Sequencing
This section describes power sequence requirements using power sequence diagrams and associated notes.
Each power sequence diagram demonstrates the sequential order expected for each device power rail. This
is done by assigning each device power rail to one or more waveform. A dual-voltage power rail may be
associated with more than one waveform and the associated note will describe which waveform is applicable.
Each waveform defines a transition region for the associated power rails and shows its sequential relationship
to the transition regions of other power rails. The notes associated with the power sequence diagram provides
further detail of these requirements. See the Power-up Sequence section for details on power-up requirements,
and the Power-down Sequence section for details on power-down requirements.
Two types of power supply transition regions are used to simplify the power supply sequencing diagrams. The
legends shown in Figure 7-3 and Figure 7-4 along with their descriptions are provided to clarify what each
transition regions represents.
Figure 7-3 defines a transition region with multiple power rails which may be sourced from multiple power
supplies or a single power supply. Transitions shown within the transition region represent a use case where
multiple power supplies are used to source power rails associated with this waveform, and these power
supplies are allowed to ramp at different times within the region since they do not have any specific sequence
requirement relative to each other.
Figure 7-3. Multiple Power Supply Transition Legend
Figure 7-4 defines a transition region with one or more power rails which must be sourced from a single common
power supply. No transitions are shown within the region to represent a single ramp within the transition region.
Figure 7-4. Single Common Power Supply Transition Legend
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7.10.2.2.1 Power-Up Sequencing
Figure 7-5 describes the device power-up sequencing.
VSYS, VMON_VSYS
(3)
(3)
(3)
(3)
Note 1
VSYS
Note 2
VMON_VSYS
(3)
VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,
(3)
VDDSHV4 , VDDA_3P3_SDIO, VDDA_3P3_USB0,
(4)
VMON_3P3_SOC , VMON_3P3_MCU
(5)
(5)
(5)
(5)
(4)
(5)
VDDS_OSC, VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,
(5)
VDDSHV4 , VDDA_MCU, VDDA_ADC0, VDDA_PLL0, VDDA_PLL1,
(6)
VDDA_PLL2, VDDA_1P8_SERDES0, VDDA_1P8_USB0, VMON_1P8_MCU ,
(6)
VMON_1P8_SOC , VDDA_TEMP0, VDDA_TEMP1, VDDS_MMC0
VDDSHV5
(12)
(7)
VDDS_DDR , VDDS_DDR_C
VDD_CORE
VDD_CORE
(9)(10)
(7)
(8)(10)
(10)
, VDDR_CORE , VDDA_0P85_SERDES0_C,
VDDA_0P85_SERDES0, VDDA_0P85_USB0,
VDD_DLL_MMC0, VDD_MMC0
VPP
(11)
Hi-Z
MCU_PORz
MCU_OSC0_XI, MCU_OSC0_XO
AM64x_ELCH_01
Figure 7-5. Power-Up Sequencing
1. VSYS represents the name of a supply which sources power to the entire system. This supply is expected to
be a pre-regulated supply that sources power management devices which source all other supplies.
2. VMON_VSYS input is used to monitor VSYS via an external resistor divider circuit. For more information,
see Section 9.2.4, System Power Supply Monitor Design Guidelines.
3. VDDSHV_MCU and VDDSHVx [x=0-5] are dual voltage IO supplies which can be operated at 1.8V or
3.3V depending on the application requirements. When any of the VDDSHV_MCU or VDDSHVx [x=0-5] IO
supplies are operating at 3.3V, they shall be ramped up with other 3.3V supplies during the 3.3V ramp period
defined by this waveform.
4. The VMON_3P3_MCU and VMON_3P3_SOC inputs are used to monitor supply voltage and shall be
connected to the respective 3.3V supply source.
5. VDDSHV_MCU and VDDSHVx [x=0-5] are dual voltage IO supplies which can be operated at 1.8V or
3.3V depending on the application requirements. When any of the VDDSHV_MCU or VDDSHVx [x=0-5] IO
supplies are operating at 1.8V, they shall be ramped up with other 1.8V supplies during the 1.8V ramp period
defined by this waveform.
6. The VMON_1P8_MCU and VMON_1P8_SOC inputs are used to monitor supply voltage and shall be
connected to the respective 1.8V supply source.
7. VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp
together.
8. VDD_CORE can be operated at 0.75V or 0.85V. When VDD_CORE is operating at 0.75V, it shall be ramped
up prior to all 0.85V supplies as shown in this waveform.
9. VDD_CORE can be operated at 0.75V or 0.85V. When VDD_CORE is operating at 0.85V, it shall be ramped
up with other 0.85V supplies during the 0.85V ramp period defined by this waveform.
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10. The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE +
0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after
VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements
beyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered by
the same source so they ramp together when VDD_CORE is operating at 0.85V.
11. VPP is the 1.8V eFuse programming supply, which shall be left floating (HiZ) or grounded during power-up/
down sequences and during normal device operation. This supply shall only be sourced while programming
eFuse.
12. VDDSHV5 was designed to support power-up, power-down, or dynamic voltage change without any
dependency on other power rails. This capability is required to support UHS-I SD Cards.
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7.10.2.2.2 Power-Down Sequencing
Figure 7-6 describes the device power-down sequencing.
VSYS
VSYS, VMON_VSYS
(1)
(1)
(1)
(1)
VMON_VSYS
(1)
VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,
(1)
VDDSHV4 , VDDA_3P3_SDIO, VDDA_3P3_USB0,
VMON_3P3_SOC, VMON_3P3_MCU
(2)
(2)
(2)
(2)
(2)
VDDS_OSC, VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,
(2)
VDDSHV4 , VDDA_MCU, VDDA_ADC0, VDDA_PLL0, VDDA_PLL1,
VDDA_PLL2, VDDA_1P8_SERDES0, VDDA_1P8_USB0, VMON_1P8_MCU,
VMON_1P8_SOC, VDDA_TEMP0, VDDA_TEMP1, VDDS_MMC0
VDDSHV5
(6)
VDDS_DDR, VDDS_DDR_C
VDD_CORE
VDD_CORE
(4)(5)
(3)(5)
(5)
, VDDR_CORE , VDDA_0P85_SERDES0_C,
VDDA_0P85_SERDES0, VDDA_0P85_USB0,
VDD_DLL_MMC0, VDD_MMC0
VPP
Hi-Z
MCU_PORz
MCU_OSC0_XI, MCU_OSC0_XO
AM64x_ELCH_02
Figure 7-6. Power-Down Sequencing
1.
2.
3.
4.
5.
VDDSHV_MCU and VDDSHVx [x=0-5] when operating at 3.3V.
VDDSHV_MCU and VDDSHVx [x=0-5] when operating at 1.8V.
VDD_CORE when operating at 0.75V.
VDD_CORE when operating at 0.85V.
The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE +
0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after
VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements
beyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered by
the same source so they ramp together when VDD_CORE is operating at 0.85V.
6. VDDSHV5 was designed to support power-up, power-down, or dynamic voltage change without any
dependency on other power rails. This capability is required to support UHS-I SD Cards.
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7.10.3 System Timing
For more details about features and additional description information on the subsystem multiplexing signals,
see the corresponding subsections within Signal Descriptions and Detailed Description sections.
7.10.3.1 Reset Timing
Tables and figures provided in this section define timing conditions, timing requirements, and switching
characteristics for reset related signals.
Table 7-4. Reset Timing Conditions
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
VDD(1) = 1.8V
0.0018
V/ns
VDD(1) = 3.3V
0.0033
V/ns
OUTPUT CONDITIONS
CL
(1)
Output load capacitance
30 pF
VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
Table 7-5. MCU_PORz Timing Requirements
see Figure 7-7
NO.
PARAMETER
RST1
th(SUPPLIES_VALID - MCU_PORz)
RST2
RST3
MIN
Hold time, MCU_PORz active (low) at Power-up
after supplies valid (using external crystal circuit)
tw(MCU_PORzL)
MAX
UNIT
9500000
ns
Hold time, MCU_PORz active (low) at Power-up
after supplies valid and external clock stable (using
external LVCMOS clock source)
1200
ns
Pulse Width, MCU_PORz low after Power-up
(without removal of Power or system reference
clock MCU_OSC0_XI/XO)
1200
ns
Figure 7-7. MCU_PORz Timing Requirements
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Table 7-6. MCU_RESETSTATz, and RESETSTATz Switching Characteristics
see Figure 7-8
NO.
PARAMETER
RST4
td(MCU_PORzL-MCU_RESETSTATzL)
Delay time, MCU_PORz active (low) to
MCU_RESETSTATz active (low)
RST5
td(MCU_PORzH-MCU_RESETSTATzH)
Delay time, MCU_PORz inactive (high) to
MCU_RESETSTATz inactive (high)
RST6
td(MCU_PORzL-RESETSTATzL)
Delay time, MCU_PORz active (low) to
RESETSTATz active (low)
RST7
td(MCU_PORzH-RESETSTATzH)
Delay time, MCU_PORz inactive (high) to
RESETSTATz inactive (high)
RST8
tw(MCU_RESETSTATzL)
Pulse Width, MCU_RESETSTATz low
(SW_MCU_WARMRST)
RST9
tw(RESETSTATzL)
Pulse Width, RESETSTATz low
(SW_MCU_WARMRST, SW_MAIN_PORz, or
SW_MAIN_WARMRST)
(1)
MIN
MAX
UNIT
0
ns
6120*S(1)
ns
0
ns
9195*S(1)
ns
966*S(1)
ns
4040*S
ns
S = MCU_OSC0_XI/XO clock period in ns.
Figure 7-8. MCU_RESETSTATz, and RESETSTATz Switching Characteristics
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Table 7-7. MCU_RESETz Timing Requirements
see Figure 7-9
NO.
PARAMETER
RST10 tw(MCU_RESETzL) (1)
(1)
MIN
Pulse Width, MCU_RESETz active (low)
MAX
1200
UNIT
ns
This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 7-8. MCU_RESETSTATz, and RESETSTATz Switching Characteristics
see Figure 7-9
NO.
PARAMETER
RST11 td(MCU_RESETzL-MCU_RESETSTATzL)
Delay time, MCU_RESETz active (low) to
MCU_RESETSTATz active (low)
RST12 td(MCU_RESETzH-MCU_RESETSTATzH)
Delay time, MCU_RESETz inactive (high) to
MCU_RESETSTATz inactive (high)
RST13 td(MCU_RESETzL-RESETSTATzL)
Delay time, MCU_RESETz active (low) to
RESETSTATz active (low)
RST14 td(MCU_RESETzH-RESETSTATzH)
Delay time, MCU_RESETz inactive (high) to
RESETSTATz inactive (high)
(1)
MIN
MAX
UNIT
0
ns
966*S(1)
ns
960
ns
4040*S(1)
ns
S = MCU_OSC0_XI/XO clock period in ns.
Figure 7-9. MCU_RESETz, MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching
Characteristics
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Table 7-9. RESET_REQz Timing Requirements
see Figure 7-10
NO.
PARAMETER
RST15 tw(RESET_REQzL) (1)
(1)
MIN
Pulse Width, RESET_REQz active (low)
MAX
UNIT
1200
ns
This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 7-10. RESETSTATz Switching Characteristics
see Figure 7-10
NO.
PARAMETER
RST16 td(RESET_REQzL-RESETSTATzL)
Delay time, RESET_REQz active (low) to
RESETSTATz active (low)
RST17 td(RESET_REQzH-RESETSTATzH)
Delay time, RESET_REQz inactive (high) to
RESETSTATz inactive (high)
(1)
(2)
MIN
MAX
UNIT
900*T(1)
ns
4040*S(2)
ns
T = Reset Isolation Time (Software Dependent)
S = MCU_OSC0_XI/XO clock period in ns.
Figure 7-10. RESET_REQz and RESETSTATz Timing Requirements and Switching Characteristics
Table 7-11. EMUx Timing Requirements
see Figure 7-11
NO.
PARAMETER
RST18 tsu(EMUx-MCU_PORz)
Setup time, EMU[1:0] before MCU_PORz inactive
(high)
RST19 th(MCU_PORz - EMUx)
Hold time, EMU[1:0] after MCU_PORz inactive
(high)
(1)
MIN
MAX UNIT
3*S(1)
ns
10
ns
S = MCU_OSC0_XI/XO clock period in ns.
Figure 7-11. EMUx Timing Requirements
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Table 7-12. BOOTMODE Timing Requirements
see Figure 7-12
NO.
PARAMETER
RST23 tsu(BOOTMODE-PORz_OUT)
Setup time, BOOTMODE[15:00] before
PORz_OUT high (External MCU PORz event or
Software SW_MAIN_PORz)
RST24 th(PORz_OUT - BOOTMODE)
Hold time, BOOTMODE[15:00] after PORz_OUT
high (External MCU PORz event, or Software
SW_MAIN_PORz)
(1)
MIN
MAX
UNIT
3*S(1)
ns
0
ns
S = MCU_OSC0_XI/XO clock period in ns.
Table 7-13. PORz_OUT Switching Characteristics
see Figure 7-12
NO.
PARAMETER
RST25 td(MCU_PORzL-PORz_OUT)
Delay time, MCU_PORz active (low) to
PORz_OUT active (low)
RST26 td(MCU_PORzH-PORz_OUT)
RST27 tw(PORz_OUTL)
MIN
MAX
UNIT
0
ns
Delay time, MCU_PORz inactive (high) to
PORz_OUT inactive (high)
1840
ns
Pulse Width, PORz_OUT low (MCU_PORz or
SW_MAIN_PORz)
1200
ns
Figure 7-12. BOOTMODE Timing Requirements and PORz_OUT Switching Characteristics
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7.10.3.2 Safety Signal Timing
Tables and figures provided in this section define timing conditions and switching characteristics for
MCU_SAFETY_ERRORn.
Table 7-14. MCU_SAFETY_ERRORn Timing Conditions
PARAMETER
MIN
MAX
UNIT
OUTPUT CONDITIONS
CL
Output load capacitance
30 pF
Table 7-15. MCU_SAFETY_ERRORn Switching Characteristics
see Figure 7-13
NO.
PARAMETER
SFTY1 tc(MCU_SAFETY_ERRORn)
Cycle time minimum, MCU_SAFETY_ERRORn
(PWM mode enabled)
SFTY2 tw(MCU_SAFETY_ERRORn)
Pulse width minimum, MCU_SAFETY_ERRORn
active (PWM mode disabled)(5)
SFTY3
(1)
(2)
(3)
(4)
(5)
td (ERROR_CONDITIONMCU_SAFETY_ERRORnL)
MIN
MAX UNIT
(P*H)+(P*L)(1) (3) (4)
ns
P*R(1) (2)
ns
50*P(1)
ns
Delay time, ERROR CONDITION to
MCU_SAFETY_ERRORn active(5)
P = ESM functional clock
R = Error Pin Counter Pre-Load Register count value
H = Error Pin PWM High Pre-Load Register count value
L = Error Pin PWM Low Pre-Load Register count value
When PWM mode is enabled, MCU_SAFETY_ERRORn stops toggling after SFTY3 and will maintain its value (either high or low) until
the error is cleared. When PWM mode is disabled, MCU_SAFETY_ERRORn is active low.
Figure 7-13. MCU_SAFETY_ERRORn Timing Requirements and Switching Characteristics
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7.10.3.3 Clock Timing
Tables and figures provided in this section define timing conditions, timing requirements, and switching
characteristics for clock signals.
Table 7-16. Clock Timing Conditions
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
0.5
V/ns
OUTPUT CONDITIONS
CL
Output load capacitance
10 ns ≤ tc < 20 ns
10 pF
20 ns ≤ tc
30 pF
Table 7-17. Clock Timing Requirements
see Figure 7-14
NO.
CLK1
MIN
tc(EXT_REFCLK1)
MAX
UNIT
Cycle time minimum, EXT_REFCLK1
10
E*0.55(1)
ns
ns
E*0.55(1)
ns
CLK2
tw(EXT_REFCLK1H)
Pulse Duration, EXT_REFCLK1 high
E*0.45(1)
CLK3
tw(EXT_REFCLK1L)
Pulse Duration, EXT_REFCLK1 low
E*0.45(1)
CLK1
tc(MCU_EXT_REFCLK0)
Cycle time minimum, MCU_EXT_REFCLK0
10
CLK2
tw(MCU_EXT_REFCLK0H)
Pulse Duration, MCU_EXT_REFCLK0 high
F*0.45(2)
F*0.55(2)
ns
Pulse Duration, MCU_EXT_REFCLK0 low
F*0.45(2)
F*0.55(2)
ns
CLK3
(1)
(2)
tw(MCU_EXT_REFCLK0L)
ns
E = EXT_REFCLK1 cycle time
F = MCU_EXT_REFCLK0 cycle time
CLK1
CLK2
CLK3
Input Clock
Figure 7-14. Clock Timing Requirements
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Table 7-18. Clock Switching Characteristics
see Figure 7-15
NO.
CLK4
PARAMETER
tc(SYSCLKOUT0)
MIN
MAX
UNIT
Cycle time minimum,SYSCLKOUT0
8
A*0.6(1)
ns
ns
A*0.6(1)
ns
CLK5
tw(SYSCLKOUT0H)
Pulse Duration, SYSCLKOUT0 high
A*0.4(1)
CLK6
tw(SYSCLKOUT0L)
Pulse Duration, SYSCLKOUT0 low
A*0.4(1)
CLK4
tc(OBSCLK0)
Cycle time minimum, OBSCLK0
5
CLK5
tw(OBSCLK0H)
Pulse Duration, OBSCLK0 high
B*0.45(2)
B*0.55(2)
ns
CLK6
tw(OBSCLK0L)
Pulse Duration,OBSCLK0 low
B*0.45(2)
B*0.55(2)
ns
CLK4
tc(CLKOUT0)
Cycle time minimum, CLKOUT0
20
CLK5
tw(CLKOUT0H)
Pulse Duration, CLKOUT0 high
C*0.4(3)
C*0.6(3)
ns
C*0.4(3)
C*0.6(3)
ns
ns
ns
CLK6
tw(CLKOUT0L)
Pulse Duration,CLKOUT0 low
CLK4
tc(MCU_SYSCLKOUT0)
Cycle time minimum, MCU_SYSCLKOUT0
10
G*0.6(4)
ns
G*0.6(4)
ns
ns
CLK5
tw(MCU_SYSCLKOUT0H)
Pulse Duration, MCU_SYSCLKOUT0 high
G*0.4(4)
CLK6
tw(MCU_SYSCLKOUT0L)
Pulse Duration,MCU_SYSCLKOUT0 low
G*0.4(4)
CLK4
tc(MCU_OBSCLK0)
Cycle time minimum, MCU_OBSCLK0
5
CLK5
tw(MCU_OBSCLK0H)
Pulse Duration, MCU_OBSCLK0 high
H*0.45(5)
H*0.55(5)
ns
Pulse Duration,MCU_OBSCLK0 low
H*0.45(5)
H*0.55(5)
ns
CLK6
(1)
(2)
(3)
(4)
(5)
tw(MCU_OBSCLK0L)
ns
A = SYSCLKOUT0 cycle time
B = OBSCLK0 cycle time
C = CLKOUT0 cycle time
G = MCU_SYSCLKOUT0 cycle time
H = MCU_OBSCLK0 cycle time
CLK4
CLK5
CLK6
Output Clock
Figure 7-15. Clock Switching Characteristics
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7.10.4 Clock Specifications
7.10.4.1 Input Clocks / Oscillators
Various external clock inputs/outputs are needed to drive the device. Summary of these input clock signals is as
follows:
•
MCU_OSC0_XI/MCU_OSC0_XO — Еxternal main crystal interface pins connected to the internal highfrequency oscillator (MCU_HFOSC0), which is the default clock source for internal reference clock
MCU_HFOSC0_CLKOUT.
General purpose clock inputs
– MCU_EXT_REFCLK0 — Optional external system clock input for MCU domain.
– EXT_REFCLK1 — Optional external system clock input for MAIN domain.
– SERDES0_REFCLK0P/N — Optional SERDES0 reference clock input for PCIe.
External CPTS reference clock inputs
– CP_GEMAC_CPTS0_RFT_CLK — CPTS reference clock input.
– CPTS_RFT_CLK — CPTS reference clock input.
•
•
Figure 7-16 shows the external input clock sources and the output clocks to peripherals.
DEVICE
CLKOUT
Reference Clock Output
SYSCLKOUT0
Main Domain System Clock (MAIN_SYSCLK0) divided-by-4
MCU_SYSCLKOUT0
MCU Domain System Clock (MCU_SYSCLK0) divided-by-4
MCU_OSC0_XI
MCU_OSC0_XO
TCK
MCU_RESETz
MCU_PORz
BOOTMODE[15:00]
DDR0_CK0/DDR0_CK0_n
SERDES0_REFCLK0P/N
External main crystal interface pins connected to internal oscillator
which provides reference clock to PLLs within MCU domain
and MAIN domain.
JTAG Clock Input
MCU Warm Reset Input / Device Warm Reset Input
MCU Power ON Reset / Device Power ON Reset
Boot Mode Configuration / Devices Select
DDR Differential Clock Outputs
Optional SERDES0 Reference Clock Input for PCIe
MCU_OBSCLK0 / OBSCLK0
Observation Clock Outputs for MCU Domain Clock / MAIN Domain Clocks
MCU_EXT_REFCLK0 / EXT_REFCLK1
Optional External System Clock Inputs - (MCU Domain) / (MAIN Domain)
CP_GEMAC_CPTS0_RFT_CLK /
CPTS0_RFT_CLK
CPTS Reference Clock Inputs
CP_GEMAC_CPTS0_RFT_CLK / CPTS0_RFT_CLK
J7ES_CLOCK_01
Figure 7-16. Input Clocks Interface
For more information about Input clock interfaces, see Clocking section in Device Configuration chapter in the
device TRM.
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7.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
Figure 7-17 shows the recommended crystal circuit. All discrete components used to implement the oscillator
circuit must be placed as close as possible to the MCU_OSC0_XI and MCU_OSC0_XO pins.
Device
MCU_OSC0_XO
MCU_OSC0_XI
Crystal
CL2
CL1
PCB Ground
AM65x_MCU_OSC_INT_01
Figure 7-17. MCU_OSC0 Crystal Implementation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 7-19 summarizes the
required electrical constraints.
Table 7-19. MCU_OSC0 Crystal Circuit Requirements
PARAMETER
Fxtal
MIN
Crystal Parallel Resonance Frequency
Fxtal
Crystal Frequency Stability and Tolerance
TYP
MAX
25
UNIT
MHz
Ethernet RGMII and RMII
not used
±100
Ethernet RGMII and RMII
using derived clock
±50
ppm
CL1+PCBXI
Capacitance of CL1 + CPCBXI
12
24
pF
CL2+PCBXO
Capacitance of CL2 + CPCBXO
12
24
pF
CL
Crystal Load Capacitance
6
12
pF
Cshunt
Crystal Circuit Shunt Capacitance
ESRxtal
Crystal Effective Series Resistance
(1)
ESRxtal = 30 Ω
25 MHz
7
pF
ESRxtal = 40 Ω
25 MHz
5
pF
ESRxtal = 50 Ω
25 MHz
5
pF
(1)
Ω
The maximum ESR of the crystal is a function of the crystal frequency and shunt capacitance. See the Cshunt parameter.
When selecting a crystal, the system design must consider temperature and aging characteristics of the crystal
based on worst case environment and expected life expectancy of the system.
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Table 7-20 details the switching characteristics of the oscillator.
Table 7-20. MCU_OSC0 Switching Characteristics - Crystal Mode
MAX
UNIT
CXI
XI Capacitance
PARAMETER
MIN
TYP
1.44
pF
CXO
XO Capacitance
1.52
pF
CXIXO
XI to XO Mutual Capacitance
0.01
pF
ts
Start-up Time
4
VDD_CORE (min.)
ms
VDD_CORE
Voltage
VSS
VDDS_OSC (min.)
VDDS_OSC
MCU_OSC0_XO
VSS
tsX
Time
AM65x_MCU_OSC_STARTUP_02
Figure 7-18. MCU_OSC0 Start-up Time
7.10.4.1.1.1 Load Capacitance
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors
CL1, CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to
MCU_OSC0_XI and MCU_OSC0_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the
PCB designer should be able to extract parasitic capacitance for each signal trace. The MCU_OSC0 circuits
and device package have combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic
capacitance values are defined in Table 7-20.
Crystal Circuit
Components
PCB
Signal Traces
Device
MCU_OSC0_XI
CL1
CPCBXI
CXI
CL2
CPCBXO
CXO
MCU_OSC0_XO
AM65x_MCU_OSC_CC_05
Figure 7-19. Load Capacitance
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Load capacitors, CL1 and CL2 in Figure 7-17, should be chosen such that the below equation is satisfied. CL in
the equation is the load specified by the crystal manufacturer.
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to
determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO =
0.5 pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) (CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF
7.10.4.1.1.2 Shunt Capacitance
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for
MCU_OSC0 operating conditions defined in Table 7-19. Shunt capacitance, Cshunt, of the crystal circuit is a
combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal
circuit components to MCU_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB
designer should be able to extract mutual parasitic capacitance between these signal traces. The device
package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined
in Table 7-20.
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can
also be minimized by placing a ground trace between these signals when the layout requires them to be routed
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as
possible when selecting a crystal.
Crystal Circuit
Components
CO
PCB
Signal Traces
Device
MCU_OSC0_XI
CPCBXIXO
CXIXO
MCU_OSC0_XO
AM65x_MCU_OSC_SC_06
Figure 7-20. Shunt Capacitance
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt
capacitance specified by the crystal manufacturer.
Cshunt ≥ CO + CPCBXIXO + CXIXO
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,
CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.
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7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
Figure 7-21 shows the recommended oscillator connections when MCU_OSC0_XI is connected to a 1.8-V
LVCMOS square-wave digital clock source.
Note
A DC steady-state condition is not allowed on MCU_OSC0_XI when the oscillator is powered up. This
is not allowed because MCU_OSC0_XI is internally AC coupled to a comparator that can enter an
unknown state when DC is applied to the input. Therefore, application software must power down
MCU_OSC0 any time MCU_OSC0_XI is not toggling between logic states.
Device
MCU_OSC0_XI
MCU_OSC0_XO
PCB Ground
AM65x_MCU_OSC_EXT_CLK_03
Figure 7-21. 1.8-V LVCMOS-Compatible Clock Input
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7.10.4.2 Output Clocks
The device provides several system clock outputs. Summary of these output clocks are as follows:
•
•
•
•
•
•
MCU_SYSCLKOUT0
– MCU_SYSCLKOUT0 is the MCU domain system clock (MCU_SYSCK0) divided-by-4. This clock output is
provided for test and debug purposes only.
MCU_OBSCLK0
– Observation clock output for test and debug purposes only.
SYSCLKOUT0
– SYSCLKOUT0 is the MAIN domain system clock (MAIN_SYSCLK0) divided-by-4. This clock output is
provided for test and debug purposes only.
CLKOUT0
– CLKOUT0 is the Ethernet subsystem clock (MAIN_PLL0_HSDIV4_CLKOUT) divided-by-5 or dividedby-10. This clock output was provided to source to the external PHY. When configured to operate as
the RMII Clock source (50 MHz) the signal must also be routed back to the RMII_REF_CLK pin for proper
device operation.
OBSCLK0
– Observation clock output for test and debug purposes only.
GPMC_FCLK_MUX
– GPMC_FCLK_MUX is the GPMC0 functional clock (GPMC_FCLK). This clock is provided as an
alternative GPMC interface clock when attached devices require a continuous running clock.
For more information, see Clock Outputs section in Clocking chapter and GPMC Clock Configuration section in
Peripherals chapter in the device TRM.
7.10.4.3 PLLs
Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from
off-chip power-sources.
There is one PLL in the MCU domain:
•
MCU0_PLL
There are six PLLs in the MAIN domain:
•
•
•
•
•
•
ARM0_PLL
MAIN_PLL
PER0_PLL
PER1_PLL
DDR PLL
R5F PLL
Note
For more information, see:
• Device Configuration / Clocking / PLLs section in the device TRM.
• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit
(PRU_ICSSG) section in the device TRM.
Note
The input reference clock (MCU_OSC0_XI / MCU_OSC0_XO) is specified and the lock time is
ensured by the PLL controller, as documented in the Device Configuration chapter in the device TRM.
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7.10.4.4 Recommended System Precautions for Clock and Control Signal Transitions
All clock and strobe signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
Monotonic transitions are more likely to occur with fast signal transitions. It is easy for noise to create nonmonotonic events on a signal with slow transitions. Therefore, avoid slow signal transitions on all clock and
control signals since they are more likely to generate glitches inside the device.
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7.10.5 Peripherals
7.10.5.1 CPSW3G
For more details about features and additional description information on the device Gigabit Ethernet MAC, see
the corresponding subsections within Signal Descriptions and Detailed Description sections.
Note
CPSW3G MDIO0, CPSW3G RMII1, CPSW3G RMII2, and CPSW3G RGMII1 have one or more
signals which can be multiplexed to more than one pin. Timing requirements and switching
characteristics defined in this section are only valid for specific pin combinations known as IOSETs.
Valid pin combinations or IOSETs for these interfaces can be found in the tables of the CPSW3G
IOSETs section.
7.10.5.1.1 CPSW3G MDIO Timing
Table 7-21, Table 7-22, Table 7-23, and Figure 7-22 present timing conditions, requirements, and switching
characteristics for CPSW3G MDIO.
Table 7-21. CPSW3G MDIO Timing Conditions
PARAMETER
MIN
MAX
UNIT
0.9
3.6
V/ns
10
470
pF
0
5
ns
1
ns
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
Propagation delay of each trace
td(Trace Mismatch Delay)
Propagation delay mismatch across all traces
Table 7-22. CPSW3G MDIO Timing Requirements
see Figure 7-22
NO.
PARAMETER
MDIO1 tsu(MDIO_MDC)
Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high
MDIO2 th(MDC_MDIO)
Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high
MIN
MAX
UNIT
45
ns
0
ns
Table 7-23. CPWS3G MDIO Switching Characteristics
see Figure 7-22
NO.
PARAMETER
MIN
MAX
UNIT
MDIO3 tc(MDC)
Cycle time, MDIO[x]_MDC
400
ns
MDIO4 tw(MDCH)
Pulse Duration, MDIO[x]_MDC high
160
ns
MDIO5 tw(MDCL)
Pulse Duration, MDIO[x]_MDC low
160
MDIO7 td(MDC_MDIO)
Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid
-10
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10
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MDIO3
MDIO4
MDIO5
MDIO[x]_MDC
MDIO1
MDIO2
MDIO[x]_MDIO
(input)
MDIO7
MDIO[x]_MDIO
(output)
CPSW2G_MDIO_TIMING_01
Figure 7-22. CPSW3G MDIO Timing Requirements and Switching Characteristics
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7.10.5.1.2 CPSW3G RMII Timing
Table 7-24, Table 7-25, Figure 7-23, Table 7-26, Figure 7-24 Table 7-27, and Figure 7-25 present timing
conditions, requirements, and switching characteristics for CPSW3G RMII.
Table 7-24. CPSW3G RMII Timing Conditions
PARAMETER
MIN
MAX
UNIT
0.18
0.54
V/ns
0.4
1.2
V/ns
3
25
pF
INPUT CONDITIONS
SRI
VDD(1) = 1.8V
Input slew rate
VDD(1)
= 3.3V
OUTPUT CONDITIONS
CL
(1)
Output load capacitance
VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
Table 7-25. RMII[x]_REF_CLK Timing Requirements – RMII Mode
see Figure 7-23
NO.
PARAMETER
DESCRIPTION
MIN
MAX
19.999
20.001
ns
Pulse Duration, RMII[x]_REF_CLK High
7
13
ns
Pulse Duration, RMII[x]_REF_CLK Low
7
13
ns
RMII1
tc(REF_CLK)
Cycle time, RMII[x]_REF_CLK
RMII2
tw(REF_CLKH)
RMII3
tw(REF_CLKL)
UNIT
RMII1
RMII2
RMII[x]_REF_CLK
RMII3
Figure 7-23. CPSW3G RMII[x]_REF_CLK Timing Requirements – RMII Mode
Table 7-26. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
see Figure 7-24
NO.
RMII4
RMII5
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
tsu(RXD-REF_CLK)
Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK
4
ns
tsu(CRS_DV-REF_CLK)
Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK
4
ns
tsu(RX_ER-REF_CLK)
Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK
4
ns
th(REF_CLK-RXD)
Hold time RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK
2
ns
th(REF_CLK-CRS_DV)
Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK
2
ns
th(REF_CLK-RX_ER)
Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK
2
ns
RMII4
RMII5
RMII[x]_REF_CLK
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RX_ER
Figure 7-24. CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements – RMII
Mode
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Table 7-27. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
see Figure 7-25
NO.
RMII6
MIN
MAX
td(REF_CLK-TXD)
PARAMETER
Delay time, RMII[x]_REF_CLK High to RMII[x]_
TXD[1:0] valid
DESCRIPTION
2
10
UNIT
ns
td(REF_CLK-TX_EN)
Delay time, RMII[x]_REF_CLK to RMII[x]_TX_EN
valid
2
10
ns
RMII6
RMII[x]_REF_CLK
RMII[x]_TXD[1:0], RMII[x]_TX_EN
Figure 7-25. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
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7.10.5.1.3 CPSW3G RGMII Timing
Table 7-28, Table 7-29, Table 7-30, Figure 7-26, Table 7-31, Table 7-32, and Figure 7-27 present timing
conditions, requirements, and switching characteristics for CPSW3G RGMII.
Table 7-28. CPSW3G RGMII Timing Conditions
PARAMETER
MIN
MAX
UNIT
2.64
5
V/ns
2
20
pF
RGMII[x]_RXC,
RGMII[x]_RD[3:0],
RGMII[x]_RX_CTL
50
ps
RGMII[x]_TXC,
RGMII[x]_TD[3:0],
RGMII[x]_TX_CTL
50
ps
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch
Delay)
Propagation delay mismatch across all traces
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Table 7-29. RGMII[x]_RXC Timing Requirements – RGMII Mode
see Figure 7-26
NO.
PARAMETER
RGMII1 tc(RXC)
DESCRIPTION
Cycle time, RGMII[x]_RXC
RGMII2 tw(RXCH)
Pulse duration, RGMII[x]_RXC high
RGMII3 tw(RXCL)
Pulse duration, RGMII[x]_RXC low
MODE
MIN
MAX
UNIT
10Mbps
360
440
ns
100Mbps
36
44
ns
1000Mbps
7.2
8.8
ns
10Mbps
160
240
ns
100Mbps
16
24
ns
1000Mbps
3.6
4.4
ns
10Mbps
160
240
ns
100Mbps
16
24
ns
1000Mbps
3.6
4.4
ns
Table 7-30. RGMII[x]_RD[3:0], and RGMII[x]_RX_CTL Timing Requirements – RGMII Mode
see Figure 7-26
NO.
PARAMETER
RGMII4 tsu(RD-RXC)
DESCRIPTION
Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC
high/low
tsu(RX_CTL-RXC)
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC
high/low
RGMII5 th(RXC-RD)
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC
high/low
th(RXC-RX_CTL)
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC
high/low
MODE
MIN
MAX
UNIT
10Mbps
1
ns
100Mbps
1
ns
1000Mbps
1
ns
10Mbps
1
ns
100Mbps
1
ns
1000Mbps
1
ns
10Mbps
1
ns
100Mbps
1
ns
1000Mbps
1
ns
10Mbps
1
ns
100Mbps
1
ns
1000Mbps
1
ns
RGMII1
RGMII2
RGMII[x]_RXC
RGMII3
(A)
RGMII4
RGMII5
(B)
RGMII[x]_RD[3:0]
RGMII[x]_RX_CTL
A.
B.
(B)
1st Half-byte
2nd Half-byte
RXDV
RXERR
RGMII[x]_RXC must be externally delayed relative to the data and control pins.
Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of
RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.
Figure 7-26. CPSW3G RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII
Mode
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Table 7-31. RGMII[x]_TXC Switching Characteristics – RGMII Mode
see Figure 7-27
NO.
PARAMETER
RGMII6 tc(TXC)
DESCRIPTION
Cycle time, RGMII[x]_TXC
RGMII7 tw(TXCH)
Pulse duration, RGMII[x]_TXC high
RGMII8 tw(TXCL)
Pulse duration, RGMII[x]_TXC low
MODE
MIN
MAX
UNIT
10Mbps
360
440
ns
100Mbps
36
44
ns
1000Mbps
7.2
8.8
ns
10Mbps
160
240
ns
100Mbps
16
24
ns
1000Mbps
3.6
4.4
ns
10Mbps
160
240
ns
100Mbps
16
24
ns
1000Mbps
3.6
4.4
ns
Table 7-32. RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
see Figure 7-27
NO.
PARAMETER
RGMII9 tosu(TD-TXC)
DESCRIPTION
Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC
high/low
tosu(TX_CTL-TXC)
Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC
high/low
RGMII10 toh(TXC-TD)
Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC
high/low
toh(TXC-TX_CTL)
Output hold time, RGMII[x]_TX_CTL valid after
RGMII[x]_TXC high/low
MODE
MIN
MAX
UNIT
10Mbps
1.2
ns
100Mbps
1.2
ns
1000Mbps
1.2
ns
10Mbps
1.2
ns
100Mbps
1.2
ns
1000Mbps
1.2
ns
10Mbps
1.2
ns
100Mbps
1.2
ns
1000Mbps
1.2
ns
10Mbps
1.2
ns
100Mbps
1.2
ns
1000Mbps
1.2
ns
RGMII6
RGMII7
RGMII8
(A)
RGMII[x]_TXC
RGMII9
(B)
1st Half-byte
RGMII[x]_TD[3:0]
2nd Half-byte
RGMII10
RGMII[x]_TX_CTL
A.
B.
(B)
TXEN
TXERR
TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of
RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.
Figure 7-27. CPSW3G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics
- RGMII Mode
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7.10.5.1.4 CPSW3G IOSETs
Table 7-33 defines valid pin combinations of each CPSW3G MDIO0 IOSET.
Table 7-33. CPSW3G MDIO0 IOSETs
SIGNALS
IOSET1
BALL NAME
IOSET2
MUXMODE
BALL NAME
MUXMODE
MDIO0_MDIO
PRG0_PRU1_GPO18
4
PRG1_MDIO0_MDIO
4
MDIO0_MDC
PRG0_PRU1_GPO19
4
PRG1_MDIO0_MDC
4
Table 7-34 defines valid pin combinations of each CPSW3G RMII1 and RMII2 IOSET.
Table 7-34. CPSW3G RMII1 and RMII2 IOSETs
SIGNALS
IOSET1
BALL NAME
IOSET2
MUXMODE
BALL NAME
MUXMODE
RMII_REF_CLK(1)
PRG1_PRU0_GPO10
5
PRG0_PRU0_GPO10
5
RMII1_CRS_DV
PRG1_PRU1_GPO19
5
PRG0_PRU1_GPO19
5
RMII1_RX_ER
PRG1_PRU0_GPO9
5
PRG0_PRU0_GPO9
5
RMII1_RXD0
PRG1_PRU1_GPO7
5
PRG0_PRU1_GPO7
5
RMII1_RXD1
PRG1_PRU1_GPO9
5
PRG0_PRU1_GPO9
5
RMII1_TXD0
PRG1_PRU1_GPO10
5
PRG0_PRU1_GPO10
5
RMII1_TXD1
PRG1_PRU1_GPO17
5
PRG0_PRU1_GPO17
5
RMII1_TX_EN
PRG1_PRU1_GPO18
5
PRG0_PRU1_GPO18
5
RMII2_CRS_DV
PRG1_PRU1_GPO13
5
PRG1_PRU1_GPO13
5
RMII2_RX_ER
PRG1_PRU1_GPO4
5
PRG1_PRU1_GPO4
5
RMII2_RXD0
PRG1_PRU1_GPO0
5
PRG1_PRU1_GPO0
5
RMII2_RXD1
PRG1_PRU1_GPO1
5
PRG1_PRU1_GPO1
5
RMII2_TXD0
PRG1_PRU1_GPO11
5
PRG1_PRU1_GPO11
5
RMII2_TXD1
PRG1_PRU1_GPO12
5
PRG1_PRU1_GPO12
5
RMII2_TX_EN
PRG1_PRU1_GPO15
5
PRG1_PRU1_GPO15
5
(1)
RMII_REF_CLK is common to both RMII1 and RMII2. For proper operation, all pin multiplexed
signal assignments must use the same IOSET.
Table 7-35 defines valid pin combinations of each CPSW3G RGMII1 IOSET.
Table 7-35. CPSW3G RGMII1 IOSETs
SIGNALS
IOSET1
BALL NAME
140
IOSET2
MUXMODE
BALL NAME
MUXMODE
RGMII1_TX_CTL
PRG1_PRU0_GPO9
4
PRG1_PRU0_GPO9
4
RGMII1_TXC
PRG1_PRU0_GPO10
4
PRG1_PRU0_GPO10
4
RGMII1_TD0
PRG1_PRU1_GPO7
4
PRG1_PRU1_GPO7
4
RGMII1_TD1
PRG1_PRU1_GPO9
4
PRG1_PRU1_GPO9
4
RGMII1_TD2
PRG1_PRU1_GPO10
4
PRG1_PRU1_GPO10
4
RGMII1_TD3
PRG1_PRU1_GPO17
4
PRG1_PRU1_GPO17
4
RGMII1_RX_CTL
PRG0_PRU0_GPO9
4
PRG1_PRU0_GPO5
4
RGMII1_RXC
PRG0_PRU0_GPO10
4
PRG1_PRU0_GPO8
4
RGMII1_RD0
PRG0_PRU1_GPO7
4
PRG1_PRU1_GPO5
4
RGMII1_RD1
PRG0_PRU1_GPO9
4
PRG1_PRU1_GPO8
4
RGMII1_RD2
PRG0_PRU1_GPO10
4
PRG1_PRU1_GPO18
4
RGMII1_RD3
PRG0_PRU1_GPO17
4
PRG1_PRU1_GPO19
4
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7.10.5.2 DDRSS
For more details about features and additional description information on the device (LP)DDR4 Memory
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 7-36 and Figure 7-28 present switching characteristics for DDRSS.
Table 7-36. DDRSS Switching Characteristics
see Figure 7-28
NO.
1
(1)
PARAMETER
tc(DDR_CKP/
DDR_CKN)
DDR TYPE
Cycle time, DDR_CKP and DDR_CKN
MIN
MAX
LPDDR4
1.25(1)
20
UNIT
ns
DDR4
1.25(1)
1.6
ns
Minimum DDR clock Cycle time will be limited based on the specific memory type (vendor) used in a system and by PCB
implementation. Refer to AM64x\AM243x DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve
maximum DDR frequency.
1
DDR0_CKP
DDR0_CKN
Figure 7-28. DDRSS Switching Characteristics
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.
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7.10.5.3 ECAP
Table 7-37, Table 7-38, Figure 7-29, Table 7-39, and Figure 7-30 present timing conditions, requirements, and
switching characteristics for ECAP.
Table 7-37. ECAP Timing Conditions
PARAMETER
MIN
MAX
UNIT
1
4
V/ns
2
7
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
Table 7-38. ECAP Timing Requirements
see Figure 7-29
NO.
CAP1
(1)
PARAMETER
DESCRIPTION
tw(CAP)
MIN
MAX
(1)
Pulse duration, CAP (asynchronous)
2 + 2P
UNIT
ns
P = sysclk period in ns.
CAP1
CAP
EPERIPHERALS_TIMNG_01
Figure 7-29. ECAP Timings Requirements
Table 7-39. ECAP Switching Characteristics
see Figure 7-30
NO.
CAP2
(1)
PARAMETER
DESCRIPTION
tw(APWM)
MIN
MAX
(1)
Pulse duration, APWMx high/low
-2 + 2P
UNIT
ns
P = sysclk period in ns.
CAP2
APWM
EPERIPHERALS_TIMNG_02
Figure 7-30. ECAP Switching Characteristics
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.
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7.10.5.4 EPWM
Table 7-40, Table 7-41, Figure 7-31, Table 7-42, Figure 7-32, Figure 7-33, and Figure 7-34 present timing
conditions, requirements, and switching characteristics for EPWM.
Table 7-40. EPWM Timing Conditions
PARAMETER
MIN
MAX
UNIT
1
4
V/ns
2
7
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
Table 7-41. EPWM Timing Requirements
see Figure 7-31
NO.
PARAMETER
DESCRIPTION
MIN
UNIT
ns
ns
PWM6
tw(SYNCIN)
Pulse duration, EHRPWM_SYNCI
2+
PWM7
tw(TZ)
Pulse duration, EHRPWM_TZn_IN low
2 + 3P(1)
(1)
MAX
2P(1)
P = sysclk period in ns.
PWM6
EHRPWM_SYNCI
PWM7
EHRPWM_TZn_IN
EPERIPHERALS_TIMNG_07
Figure 7-31. EPWM Timing Requirements
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Table 7-42. EPWM Switching Characteristics
see Figure 7-32, Figure 7-33, and Figure 7-34
NO.
PWM1
PARAMETER
DESCRIPTION
tw(PWM)
MIN
PWM2
tw(SYNCOUT)
Pulse duration, EHRPWM_SYNCO
PWM3
td(TZ-PWM)
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B forced
high/low
PWM4
td(TZ-PWMZ)
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B Hi-Z
PWM5
tw(SOC)
Pulse duration, EHRPWM_SOCA/B output
(1)
MAX
P - 3(1)
Pulse duration, EHRPWM_A/B high/low
P-
UNIT
ns
3(1)
ns
P - 3(1)
11
ns
11
ns
ns
P = sysclk period in ns.
PWM1
EHRPWM_A/B
PWM1
PWM2
EHRPWM_SYNCO
PWM5
EHRPWM_SOCA/B
EPERIPHERALS_TIMNG_04
Figure 7-32. EHRPWM Switching Characteristics
PWM3
EHRPWM_A/B
EHRPWM_TZn_IN
EPERIPHERALS_TIMING_05
Figure 7-33. EHRPWM_TZn_IN to EHRPWM_A/B Forced Switching Characteristics
PWM4
EHRPWM_A/B
EHRPWM_TZn_IN
Figure 7-34. EHRPWM_TZn_IN to EHRPWM_A/B Hi-Z Switching Characteristics
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in
the device TRM.
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7.10.5.5 EQEP
Table 7-43, Table 7-44, Figure 7-35, and Table 7-45 present timing conditions, requirements, and switching
characteristics for EQEP.
Table 7-43. EQEP Timing Conditions
PARAMETER
MIN
MAX
UNIT
1
4
V/ns
2
7
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
Table 7-44. EQEP Timing Requirements
see Figure 7-35
NO.
DESCRIPTION
MIN
ns
ns
(1)
ns
(1)
ns
(1)
ns
Pulse duration, QEP_A/B
2 + 2P
tw(QEPIH)
Pulse duration, QEP_I high
2 + 2P
QEP3
tw(QEPIL)
Pulse duration, QEP_I low
2 + 2P
QEP4
tw(QEPSH)
Pulse duration, QEP_S high
2 + 2P
Pulse duration, QEP_S low
UNIT
(1)
tw(QEP)
QEP2
tw(QEPSL)
MAX
(1)
QEP1
QEP5
(1)
PARAMETER
2 + 2P
P = sysclk period in ns
QEP1
QEP_A/B
QEP2
QEP_I
QEP3
QEP4
QEP_S
QEP5
EPERIPHERALS_TIMNG_03
Figure 7-35. EQEP Timing Requirements
Table 7-45. EQEP Switching Characteristics
NO.
QEP6
PARAMETER
td(QEP-CNTR)
DESCRIPTION
MIN
Delay time, external clock to counter increment
MAX
24
UNIT
ns
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter
in the device TRM.
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7.10.5.6 FSI
Table 7-46, Table 7-47, Figure 7-36, Table 7-48, Figure 7-37, Table 7-49, and Figure 7-38 present timing
conditions, requirements, and switching characteristics for FSI.
Table 7-46. FSI Timing Conditions
PARAMETER
MIN
MAX
UNIT
0.8
4
V/ns
1
7
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
Table 7-47. FSI Timing Requirements
see Figure 7-36
NO.
MIN
FSIR1
tc(RX_CLK)
Cycle time, FSI_RXn_CLK
FSIR2
tw(RX_CLK)
Pulse width, FSI_RXn_CLK low or FSI_RXn_CLK high
FSIR3
tsu(RX_D-RX_CLK)
Setup time, FSI_RXn_D[1:0] valid before FSI_RXn_CLK
FSIR4
th(RX_CLK-RX_D)
Hold time, FSI_RXn_D[1:0] valid after FSI_RXn_CLK
(1)
MAX
20
(1)
0.5P - 1
UNIT
ns
(1)
0.5P + 1
ns
3
ns
2.5
ns
P = FSI_RXn_CLK period in ns.
FSIR1
FSIR2
FSIR2
FSI_RXn_CLK
FSI_RXn_D0
FSI_RXn_D1
FSIR3
FSIR4
Figure 7-36. FSI Timing Requirements
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Table 7-48. FSI Switching Characteristics - FSI Mode
see Figure 7-37
NO.
PARAMETER
FSIT1
tc(TX_CLK)
MODE
Cycle time, FSI_TXn_CLK
MIN
FSI Mode
20
(1)
UNIT
ns
(1)
ns
(1)
0.25P +
(1)
2.5
ns
MIN
MAX
FSIT2
tw(TX_CLK)
Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high
FSI Mode
0.5p + 1
FSIT3
td(TX_CLK-TX_D)
Delay time, FSI_TXn_D[1:0] valid after FSI_TXn_CLK
high or FSI_TXn_CLK low
FSI Mode
0.25P - 2
(1)
MAX
0.5P - 1
P = FSI_TXn_CLK period in ns.
FSIT1
FSIT2
FSIT2
FSI_TXn_CLK
FSI_TXn_D0
FSI_TXn_D1
FSIT3
Figure 7-37. FSI Switching Characteristics - FSI Mode
Table 7-49. FSI Switching Characteristics - SPI Mode
see Figure 7-38
NO.
PARAMETER
FSIT4
tc(TX_CLK)
MODE
Cycle time, FSI_TXn_CLK
SPI Mode
20
(1)
FSIT5
tw(TX_CLK)
Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high
SPI Mode
FSIT6
td(TX_CLKH-TX_D0)
Delay time, FSI_TXn_CLK high to FSI_TXn_D0 valid
SPI Mode
0.5P + 1
ns
(1)
ns
3
ns
0.5P - 1
P-3
SPI Mode
P-2
ns
SPI Mode
Delay time, FSI_TXn_CLK low to FSI_TXn_D1 high
ns
Delay time, FSI_TXn_D1 low to FSI_TXn_CLK high
td(TX_CLK-TX_D1)
(1)
td(TX_D1-TX_CLK)
FSIT8
(1)
FSIT7
(1)
UNIT
P = FSI_TXn_CLK period in ns.
FSIT4
FSIT5
FSIT5
FSI_TXn_CLK
FSIT6
FSI_TXn_D0
FSIT8
FSIT7
FSI_TXn_D1
Figure 7-38. FSI Switching Characteristics - SPI Mode
For more information, see Fast Serial Interface section in Peripherals chapter in the device TRM.
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7.10.5.7 GPIO
Table 7-50, Table 7-51, and Table 7-52 present timing conditions, requirements, and switching characteristics for
GPIO.
The device has three instances of the GPIO module.
• MCU_GPIO0
• GPIO0
• GPIO1
Note
GPIOn_x is generic name used to describe a GPIO signal, where n represents the specific GPIO
module and x represents one of the input/output signals associated with the module.
For additional description information on the device GPIO, see the corresponding subsections within
Signal Descriptions and Detailed Description sections.
Table 7-50. GPIO Timing Conditions
PARAMETER
BUFFER TYPE
MIN
MAX
UNIT
LVCMOS
0.2
6.6
V/ns
I2C OD FS
0.2
0.8
V/ns
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
LVCMOS
3
10
pF
I2C OD FS
3
100
pF
Table 7-51. GPIO Timing Requirements
NO.
PARAMETER
GPIO1 tw(GPIO_IN)
(1)
DESCRIPTION
Pulse width, GPIOn_x
MODE
MIN
1.8 V
2P + 2.6
(1)
3.3 V
2P + 3.5
(1)
MAX
UNIT
ns
ns
P = functional clock period in ns.
Table 7-52. GPIO Switching Characteristics
NO.
PARAMETER
GPIO2 tw(GPIO_OUT)
DESCRIPTION
Pulse width, GPIOn_x
BUFFER TYPE
LVCMOS
I2C OD FS
(1)
MIN
MAX
UNIT
0.975P(1) 3.6
ns
160
ns
P = functional clock period in ns.
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.
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7.10.5.8 GPMC
For more details about features and additional description information on the device General-Purpose Memory
Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Note
GPMC has one or more signals which can be multiplexed to more than one pin. Timing requirements
and switching characteristics defined in this section are only valid for specific pin combinations known
as IOSETs. Valid pin combinations or IOSETs for this interface is shown in Section 7.10.5.8.4.
Table 7-53 presents timing conditions for GPMC.
Table 7-53. GPMC Timing Conditions
PARAMETER
MIN
MAX
UNIT
1.65
4
V/ns
5
20
pF
133 MHz Synchronous Mode
140
360
ps
All other modes
140
720
ps
200
ps
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
Propagation delay of each trace
td(Trace Mismatch
Propagation delay mismatch across all traces
Delay)
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the
device TRM.
7.10.5.8.1 GPMC and NOR Flash — Synchronous Mode
Hold time, input wait GPMC_WAIT[j] valid after output clock GPMC_CLK high (th(clkH-waitV))
Table 7-54 and Table 7-55 present timing requirements and switching characteristics for GPMC and NOR Flash Synchronous Mode.
Table 7-54. GPMC and NOR Flash Timing Requirements — Synchronous Mode
see Figure 7-39, Figure 7-40, and Figure 7-43
MIN
NO.
PARAMETER
F12 tsu(dV-clkH)
F13 th(clkH-dV)
F21 tsu(waitV-clkH)
DESCRIPTION
Setup time, input data
GPMC_AD[n:0](1) valid before
output clock GPMC_CLK high
Hold time, input data
GPMC_AD[n:0](1) valid after output
clock GPMC_CLK high
Setup time, input wait
GPMC_WAIT[j](3) (4) valid before
output clock GPMC_CLK high
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MODE(5)
MAX
MIN
MAX
GPMC_FCLK = GPMC_FCLK = UNIT
100 MHz(2)
133 MHz(2)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.81
1.12
ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.06
3.5
ns
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.29
2.29
ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.29
2.29
ns
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.81
1.12
ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.06
3.5
ns
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Table 7-54. GPMC and NOR Flash Timing Requirements — Synchronous Mode (continued)
see Figure 7-39, Figure 7-40, and Figure 7-43
NO.
PARAMETER
F22 th(clkH-waitV)
MODE(5)
DESCRIPTION
Hold time, input wait
GPMC_WAIT[j](3) (4) valid after
output clock GPMC_CLK high
MIN
MAX
MIN
MAX
GPMC_FCLK = GPMC_FCLK = UNIT
100 MHz(2)
133 MHz(2)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.29
2.29
ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.29
2.29
ns
(1)
(2)
Synchronous Mode supports 16-bit data bus up to 133 MHz and 32-bit data bus up to 100 MHz
GPMC_FCLK select
(3)
(4)
• gpmc_fclk_sel[1:0] = 2b01 to select the 100MHz GPMC_FCLK
• gpmc_fclk_sel[1:0] = 2b00 to select the 133MHz GPMC_FCLK
In GPMC_WAIT[j], j is equal to 0 or 1.
Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see GeneralPurpose Memory Controller (GPMC) section in the device TRM.
For div_by_1_mode:
(5)
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
–
GPMC_CLK frequency = GPMC_FCLK frequency
For not_div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
–
GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)
For GPMC_FCLK_MUX:
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz
For TIMEPARAGRANULARITY_X1:
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
Table 7-55. GPMC and NOR Flash Switching Characteristics – Synchronous Mode
see Figure 7-39, Figure 7-40, Figure 7-41, Figure 7-42, and Figure 7-43
NO.
(17)
MIN
MAX
F0
1 / tc(clk)
Period, output clock GPMC_CLK
(16)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
10.00
7.52
ns
F1
tw(clkH)
Typical pulse duration, output clock
GPMC_CLK high
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
0.475P
- 0.3(15)
0.475P
- 0.3(15)
ns
F1
tw(clkL)
Typical pulse duration, output clock
GPMC_CLK low
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
0.475P
- 0.3(15)
0.475P
- 0.3(15)
ns
F2
td(clkH-csnV)
Delay time, output clock GPMC_CLK
rising edge to output chip select
(14)
GPMC_CSn[i] transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
F - 2.2
F+
3.75
F - 2.2
F+
3.75
ns
F3
td(clkH-CSn[i]V)
Delay time, output clock GPMC_CLK
rising edge to output chip select
(14)
GPMC_CSn[i] invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
E - 2.2
E+
3.18
E - 2.2 E + 4.5
ns
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MODE
MAX
PARAMETER
150
DESCRIPTION
MIN
(3)
100 MHz
(6)
(5)
133 MHz
(6)
(5)
UNIT
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Table 7-55. GPMC and NOR Flash Switching Characteristics – Synchronous Mode (continued)
see Figure 7-39, Figure 7-40, Figure 7-41, Figure 7-42, and Figure 7-43
NO.
DESCRIPTION
(17)
(3)
PARAMETER
MODE
F4
td(aV-clk)
Delay time, output address
GPMC_A[27:1] valid to output clock
GPMC_CLK first edge
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F5
td(clkH-aIV)
Delay time, output clock GPMC_CLK
rising edge to output address
GPMC_A[27:1] invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F6
td(be[x]nV-clk)
Delay time, output lower byte
enable and command latch enable
GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n valid to output
clock GPMC_CLK first edge
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F7
td(clkH-be[x]nIV)
Delay time, output clock GPMC_CLK
rising edge to output lower byte
enable and command latch enable
GPMC_BE0n_CLE, output upper byte
(11)
enable GPMC_BE1n invalid
F7
td(clkL-be[x]nIV)
F7
MIN
MAX
MIN
MAX
100 MHz
133 MHz
B - 2.3 B + 4.5
B - 2.3 B + 4.5
(3)
-2.3
4.5
(3)
ns
4.5
ns
B - 2.3 B + 1.9
B - 2.3 B + 1.9
ns
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
D - D + 1.9
2.3(4)
D - 2.3 D + 1.9
ns
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
(12)
invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
D - 2.3 D + 1.9
D - 2.3 D + 1.9
ns
td(clkL-be[x]nIV).
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
(13)
invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
D - 2.3 D + 1.9
D - 2.3 D + 1.9
ns
F8
td(clkH-advn)
Delay time, output clock GPMC_CLK
rising edge to output address
valid and address latch enable
GPMC_ADVn_ALE transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
G - G + 4.5 G - 2.3 G + 4.5
(7)
2.3(7)
ns
F9
td(clkH-advnIV)
Delay time, output clock GPMC_CLK
rising edge to output address
valid and address latch enable
GPMC_ADVn_ALE invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
D - 2.3 D + 4.5
D - 2.3 D + 4.5
ns
F10 td(clkH-oen)
Delay time, output clock GPMC_CLK
rising edge to output enable
GPMC_OEn_REn transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
H - H + 3.5
2.3(8)
H - 2.3 H + 3.5
ns
F11 td(clkH-oenIV)
Delay time, output clock GPMC_CLK
rising edge to output enable
GPMC_OEn_REn invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
H - 2.3 H + 3.5
H - 2.3 H + 3.5
ns
F14 td(clkH-wen)
Delay time, output clock GPMC_CLK
rising edge to output write enable
GPMC_WEn transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
I - 2.3
F15 td(clkH-do)
Delay time, output clock GPMC_CLK
rising edge to output data
(11)
GPMC_AD[n:0](1) transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F15 td(clkL-do)
Delay time, GPMC_CLK falling
edge to GPMC_AD[n:0](1) data bus
(12)
transition
F15 td(clkL-do).
F17 td(clkH-be[x]n)
(3)
(4)
(4)
(4)
(8)
(3)
(4)
(4)
(4)
(4)
(8)
(8)
I + 4.5
ns
J - 2.3 J + 2.7
J - 2.3 J + 2.7
ns
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 2.7
J - 2.3 J + 2.7
ns
Delay time, GPMC_CLK falling
edge to GPMC_AD[n:0](1) data bus
(13)
transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 2.7
J - 2.3 J + 2.7
ns
Delay time, output clock GPMC_CLK
rising edge to output lower byte
enable and command latch enable
(11)
GPMC_BE0n_CLE transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 1.9
J - 2.3 J + 1.9
ns
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(9)
I + 4.5
-2.3
UNIT
(10)
(10)
(10)
(10)
I - 2.3
(9)
(10)
(10)
(10)
(10)
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Table 7-55. GPMC and NOR Flash Switching Characteristics – Synchronous Mode (continued)
see Figure 7-39, Figure 7-40, Figure 7-41, Figure 7-42, and Figure 7-43
NO.
PARAMETER
(3)
DESCRIPTION
(17)
MODE
MIN
MAX
MIN
100 MHz
MAX
133 MHz
UNIT
F17 td(clkL-be[x]n)
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
(12)
transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 1.9
J - 2.3 J + 1.9
ns
F17 td(clkL-be[x]n).
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
(13)
transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 1.9
J - 2.3 J + 1.9
ns
F18 tw(csnV)
Pulse duration, output chip select
(14)
GPMC_CSn[i] low
Read
Write
F19 tw(be[x]nV)
Pulse duration, output lower byte
enable and command latch enable
GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n low
Read
Write
Pulse duration, output address
valid and address latch enable
GPMC_ADVn_ALE low
F20 tw(advnV)
(1)
(2)
(3)
(4)
(5)
(6)
(10)
(10)
(10)
(10)
A
A
ns
A
A
ns
C
C
ns
C
C
ns
Read
K
K
ns
Write
K
K
ns
Synchronous Mode supports 16-bit data bus up to 133 MHz and 32-bit data bus up to 100 MHz
For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
With n being the page burst access number.
B = ClkActivationTime × GPMC_FCLK(15)
For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
For csn falling edge (CS activated):
•
Case GPMCFCLKDIVIDER = 0:
•
– F = 0.5 × CSExtraDelay × GPMC_FCLK(15)
Case GPMCFCLKDIVIDER = 1:
F = 0.5 × CSExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and
CSOnTime are even)
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(15) otherwise
Case GPMCFCLKDIVIDER = 2:
–
•
(7)
– F = 0.5 × CSExtraDelay × GPMC_FCLK(15) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(15) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
– F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(15) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
For ADV falling edge (ADV activated):
•
Case GPMCFCLKDIVIDER = 0:
•
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(15)
Case GPMCFCLKDIVIDER = 1:
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) otherwise
Case GPMCFCLKDIVIDER = 2:
–
•
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
•
Case GPMCFCLKDIVIDER = 0:
–
152
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15)
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Case GPMCFCLKDIVIDER = 1:
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) otherwise
Case GPMCFCLKDIVIDER = 2:
–
•
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
•
Case GPMCFCLKDIVIDER = 0:
•
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(15)
Case GPMCFCLKDIVIDER = 1:
•
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) otherwise
Case GPMCFCLKDIVIDER = 2:
–
(8)
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
•
Case GPMCFCLKDIVIDER = 0:
•
– H = 0.5 × OEExtraDelay × GPMC_FCLK(15)
Case GPMCFCLKDIVIDER = 1:
•
H = 0.5 × OEExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and
OEOnTime are even)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) otherwise
Case GPMCFCLKDIVIDER = 2:
–
–
–
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(15) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
For OE rising edge (OE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
•
– H = 0.5 × OEExtraDelay × GPMC_FCLK(15)
Case GPMCFCLKDIVIDER = 1:
•
H = 0.5 × OEExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and
OEOffTime are even)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) otherwise
Case GPMCFCLKDIVIDER = 2:
–
(9)
– H = 0.5 × OEExtraDelay × GPMC_FCLK(15) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
For WE falling edge (WE activated):
•
Case GPMCFCLKDIVIDER = 0:
•
– I = 0.5 × WEExtraDelay × GPMC_FCLK(15)
Case GPMCFCLKDIVIDER = 1:
•
I = 0.5 × WEExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and
WEOnTime are even)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) otherwise
Case GPMCFCLKDIVIDER = 2:
–
–
–
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(15) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
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For WE rising edge (WE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
•
– I = 0.5 × WEExtraDelay × GPMC_FCLK (15)
Case GPMCFCLKDIVIDER = 1:
I = 0.5 × WEExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and
WEOffTime are even)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) otherwise
Case GPMCFCLKDIVIDER = 2:
–
•
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
– I = 0.5 × WEExtraDelay × GPMC_FCLK(15) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
J = GPMC_FCLK(15)
First transfer only for CLK DIV 1 mode.
Half cycle; for all data after initial transfer for CLK DIV 1 mode.
Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
P = GPMC_CLK period in ns
Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
For div_by_1_mode:
•
GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
–
GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz
For TIMEPARAGRANULARITY_X1:
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
For no extra_delay:
•
•
•
•
154
GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed
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F1
F0
F1
GPMC_CLK
F2
F3
F18
GPMC_CSn[i]
F4
GPMC_A[MSB:1]
Valid Address
F6
F7
F19
GPMC_BE0n_CLE
F19
GPMC_BE1n
F6
F8
F8
F20
F9
GPMC_ADVn_ALE
F10
F11
GPMC_OEn_REn
F13
F12
GPMC_AD[15:0]
D0
GPMC_WAIT[j]
GPMC_01
A.
B.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-39. GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)
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F1
F0
F1
GPMC_CLK
F2
F3
GPMC_CSn[i]
F4
GPMCA[MSB:1]
Valid Address
F6
F7
GPMC_BE0n_CLE
F7
GPMC_BE1n
F6
F8
F8
F9
GPMC_ADVn_ALE
F10
F11
GPMC_OEn_REn
F13
F13
F12
D0
GPMC_AD[15:0]
F21
F12
D1
D2
D3
F22
GPMC_WAIT[j]
GPMC_02
A.
B.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-40. GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)
F1
F1
F0
GPMC_CLK
F2
F3
GPMC_CSn[i]
F4
Valid Address
GPMC_A[MSB:1]
F17
F6
F17
F17
GPMC_BE0n_CLE
F17
F17
F17
GPMC_BE1n
F6
F8
F8
F9
GPMC_ADVn_ALE
F14
F14
GPMC_WEn
F15
GPMC_AD[15:0]
D0
F15
D1
D2
F15
D3
GPMC_WAIT[j]
GPMC_03
A.
156
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
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B.
SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-41. GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
F1
F0
F1
GPMC_CLK
F2
F3
GPMC_CSn[i]
F6
F7
GMPC_BE0n_CLE
Valid
F6
F7
Valid
GPMC_BE1n
F4
GPMC_A[27:17]
Address (MSB)
F12
F4
GPMC_AD[15:0]
F5
Address (LSB)
F13
D0
F8
D1
F12
D2
F8
D3
F9
GPMC_ADVn_ALE
F10
F11
GPMC_OEn_REn
GPMC_WAIT[j]
GPMC_04
A.
B.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-42. GPMC and Multiplexed NOR Flash — Synchronous Burst Read
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F1
F1
F0
GPMC_CLK
F2
F3
F18
GPMC_CSn[i]
F4
GPMC_A[27:17]
Address (MSB)
F17
F6
F17
F6
F17
F17
GPMC_BE1n
F17
F17
BPMC_BE0n_CLE
F8
F8
F20
F9
GPMC_ADVn_ALE
F14
F14
GPMC_WEn
F15
GPMC_AD[15:0]
Address (LSB)
D0
F22
D1
F15
F15
D2
D3
F21
GPMC_WAIT[j]
GPMC_05
A.
B.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-43. GPMC and Multiplexed NOR Flash — Synchronous Burst Write
158
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7.10.5.8.2 GPMC and NOR Flash — Asynchronous Mode
Table 7-56 and Table 7-57 present timing requirements and switching characteristics for GPMC and NOR Flash
— Asynchronous Mode.
Table 7-56. GPMC and NOR Flash Timing Requirements – Asynchronous Mode
see Figure 7-44, Figure 7-45, Figure 7-46, and Figure 7-48
NO.
FA5
PARAMETER
(1)
DESCRIPTION
MODE
MIN
MAX UNIT
Page mode successive data access time
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
P
FA2
(1)
1
tacc2-pgmode(d)
Page mode first data access time
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
H
ns
tacc1-pgmode(d)
(4)
FA2
(2)
0
ns
H
(3)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
ns
Data access time
(4)
tacc(d)
(1)
(2)
(3)
(4)
(5)
The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active
functional clock edge. FA5 value must be stored inside the AccessTime register bit field.
The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)
H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)
GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
Table 7-57. GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
see Figure 7-44, Figure 7-45, Figure 7-46, Figure 7-47, Figure 7-48, and Figure 7-49
NO.
FA0
FA1
FA3
PARAMETER
tw(be[x]nV)
tw(csnV)
td(csnV-advnIV)
DESCRIPTION
MIN
(15)
MODE
MAX
133 MHz
Pulse duration, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid time
Read
N (12)
Write
(12)
Pulse duration, output chip select GPMC_CSn[i](13)
low
Read
A (1)
Write
A (1)
Delay time, output chip select GPMC_CSn[i](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
Read
B - 2.1
B + 2.1
Write
B - 2.1
B + 2.1
N
(2)
(2)
UNIT
(2)
ns
ns
ns
(2)
FA4
td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn invalid
(Single read)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
C - 2.1
C + 2.1
ns
FA9
td(aV-csnV)
Delay time, output address GPMC_A[27:1] valid to
output chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.1 (9)
J + 2.1
ns
FA10 td(be[x]nV-csnV)
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid to output
chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.1 (9)
J + 2.1
ns
FA12 td(csnV-advnV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
K - 2.1
K + 2.1
ns
FA13 td(csnV-oenV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
L - 2.1
L + 2.1
ns
FA16 tw(aIV)
Pulse duration output address GPMC_A[26:1]
invalid between 2 successive read and write
accesses
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
G (7)
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(3)
(10)
(11)
(3)
(9)
(9)
(10)
(11)
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Table 7-57. GPMC and NOR Flash Switching Characteristics – Asynchronous Mode (continued)
see Figure 7-44, Figure 7-45, Figure 7-46, Figure 7-47, Figure 7-48, and Figure 7-49
NO.
PARAMETER
DESCRIPTION
MIN
(15)
MODE
MAX
133 MHz
FA18 td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn invalid
(Burst read)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA20 tw(aV)
Pulse duration, output address GPMC_A[27:1]
valid - 2nd, 3rd, and 4th accesses
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
D (4)
FA25 td(csnV-wenV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
E - 2.1
E + 2.1
ns
FA27 td(csnV-wenIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F - 2.1 (6)
F + 2.1
ns
FA28 td(wenV-dV)
Delay time, output write enable GPMC_WEn valid
to output data GPMC_AD[15:0] valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.1
ns
FA29 td(dV-csnV)
Delay time, output data GPMC_AD[15:0] valid to
output chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J + 2.1
ns
FA37 td(oenV-aIV)
Delay time, output enable GPMC_OEn_REn valid
to output address GPMC_AD[15:0] phase end
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.1
ns
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
I - 2.1 (8) I + 2.1 (8)
UNIT
(5)
J - 2.1 (9)
ns
ns
(5)
(6)
(9)
For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
with n being the page burst access number
For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
G = Cycle2CycleDelay × GPMC_FCLK(14)
I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay))
× GPMC_FCLK(14)
J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)
K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
–
GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
•
160
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
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OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
GPMC_FCLK
GPMC_CLK
FA5
FA1
GPMC_CSn[i]
FA9
Valid Address
GPMC_A[MSB:1]
FA0
FA10
GPMC_BE0n_CLE
Valid
GPMC_BE1n
Valid
FA0
FA10
FA3
FA12
GPMC_ADVn_ALE
FA4
FA13
GPMC_OEn_REn
Data IN 0
GPMC_AD[15:0]
Data IN 0
GPMC_WAIT[j]
GPMC_06
A.
B.
C.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], jis equal to 0 or 1.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-44. GPMC and NOR Flash — Asynchronous Read — Single Word
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GPMC_FCLK
GPMC_CLK
FA5
FA5
FA1
FA1
GPMC_CSn[i]
FA16
FA9
FA9
GPMC_A[MSB:1]
Address 0
Address 1
FA0
FA10
FA0
FA10
Valid
GPMC_BE0n_CLE
Valid
FA0
GPMC_BE1n
FA0
Valid
FA10
Valid
FA10
FA3
FA3
FA12
FA12
GPMC_ADCn_ALE
FA4
FA13
FA4
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
Data Upper
GPMC_WAIT[j]
GPMC_07
A.
B.
C.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-45. GPMC and NOR Flash — Asynchronous Read — 32–Bit
162
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GPMC_FCLK
GPMC_CLK
FA21
FA20
FA20
FA20
Add1
Add2
Add3
D0
D1
D2
FA1
GPMC_CSn[i]
FA9
Add0
GPMC_A[MSB:1]
Add4
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA12
GPMC_ADVn_ALE
FA18
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
D3
D3
GPMC_WAIT[j]
GPMC_08
A.
B.
C.
D.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by
active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.
FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC
functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first
input page data). FA20 value must be stored in PageBurstAccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-46. GPMC and NOR Flash — Asynchronous Read — Page Mode 4x16–Bit
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GPMC_FCLK
GPMC_CLK
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1]
Valid Address
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
FA29
GPMC_AD[15:0]
Data OUT
GPMC_WAIT[j]
GPMC_09
A.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-47. GPMC and NOR Flash — Asynchronous Write — Single Word
164
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GPMC_FCLK
GPMC_CLK
FA1
FA5
GPMC_CSn[i]
FA9
GPMC_A[27:17]
Address (MSB)
FA0
FA10
GPMC_BE0n_CLE
Valid
FA0
FA10
GPMC_BE1n
Valid
FA3
FA12
GPMC_ADVn_ALE
FA4
FA13
GPMC_OEn_REn
FA29
GPMC_AD[15:0]
FA37
Data IN
Address (LSB)
Data IN
GPMC_WAIT[j]
GPMC_10
A.
B.
C.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-48. GPMC and Multiplexed NOR Flash — Asynchronous Read — Single Word
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GPMC_FCLK
GPMC_CLK
FA1
GPMC_CSn[i]
FA9
GPMC_A[27:17]
Address (MSB)
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
FA29
GPMC_AD[15:0]
FA28
Valid Address (LSB)
Data OUT
GPMC_WAIT[j]
GPMC_11
A.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-49. GPMC and Multiplexed NOR Flash — Asynchronous Write — Single Word
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7.10.5.8.3 GPMC and NAND Flash — Asynchronous Mode
Table 7-58 and Table 7-59 present timing requirements and switching characteristics for GPMC and NAND Flash
— Asynchronous Mode.
Table 7-58. GPMC and NAND Flash Timing Requirements – Asynchronous Mode
see Figure 7-52
NO.
PARAMETER
(1)
GNF12
(1)
(2)
(3)
(4)
tacc(d)
Access time, input data GPMC_AD[15:0]
MIN
(4)
DESCRIPTION
MODE
(3)
MAX
133 MHz
UNIT
(2)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J
ns
The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)
GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
–
GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
Table 7-59. GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
see Figure 7-50, Figure 7-51, Figure 7-52 and Figure 7-53
NO.
PARAMETER
(4)
MODE
MIN
MAX UNIT
GNF0 tw(wenV)
Pulse duration, output write enable GPMC_WEn
valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
A
GNF1 td(csnV-wenV)
Delay time, output chip select GPMC_CSn[i](2)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
B-2
B+2
ns
GNF2 tw(cleH-wenV)
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE high to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
C-2
C+2
ns
GNF3 tw(wenV-dV)
Delay time, output data GPMC_AD[15:0] valid to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
D-2
D+2
ns
GNF4 tw(wenIV-dIV)
Delay time, output write enable GPMC_WEn
invalid to output data GPMC_AD[15:0] invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
E-2
E+2
ns
GNF5 tw(wenIV-cleIV)
Delay time, output write enable GPMC_WEn
invalid to output lower-byte enable and command
latch enable GPMC_BE0n_CLE invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F-2
F+2
ns
GNF6 tw(wenIV-CSn[i]V)
Delay time, output write enable GPMC_WEn
invalid to output chip select GPMC_CSn[i](2)
invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
G-2
G+2
ns
GNF7 tw(aleH-wenV)
Delay time, output address valid and address latch
enable GPMC_ADVn_ALE high to output write
enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
C-2
C+2
ns
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Table 7-59. GPMC and NAND Flash Switching Characteristics – Asynchronous Mode (continued)
see Figure 7-50, Figure 7-51, Figure 7-52 and Figure 7-53
NO.
(4)
PARAMETER
MODE
MIN
MAX UNIT
F-2
F+2
ns
H
ns
I+2
ns
K
ns
GNF8 tw(wenIV-aleIV)
Delay time, output write enable GPMC_WEn
invalid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF9 tc(wen)
Cycle time, write
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF10 td(csnV-oenV)
Delay time, output chip select GPMC_CSn[i](2)
valid to output enable GPMC_OEn_REn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF13 tw(oenV)
Pulse duration, output enable GPMC_OEn_REn
valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF14 tc(oen)
Cycle time, read
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
L
GNF15 tw(oenIV-CSn[i]V)
Delay time, output enable GPMC_OEn_REn
invalid to output chip select GPMC_CSn[i](2)
invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
M-2
(1)
(2)
(3)
(4)
I-2
ns
M+2
ns
A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(3)
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
–
GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
GPMC_FCLK
GNF1
GNF6
GNF2
GNF5
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_ADCn_ALE
GPMC_OEn_REn
GNF0
GPMC_WEn
GNF3
GPMC_AD[15:0]
GNF4
Command
GPMC_12
A.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
Figure 7-50. GPMC and NAND Flash — Command Latch Cycle
168
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GPMC_FCLK
GNF1
GNF6
GNF7
GNF8
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GNF9
GNF0
GPMC_WEn
GNF3
GNF4
GPMC_AD[15:0]
Address
GPMC_13
A.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
Figure 7-51. GPMC and NAND Flash — Address Latch Cycle
GPMC_FCLK
GNF12
GNF10
GNF15
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GNF14
GNF13
GPMC_OEn_REn
GPMC_AD[15:0]
DATA
GPMC_WAIT[j]
GPMC_14
A.
B.
C.
GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-52. GPMC and NAND Flash — Data Read Cycle
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GPMC_FCLK
GNF1
GNF6
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GNF9
GNF0
GPMC_WEn
GNF3
GPMC_AD[15:0]
GNF4
DATA
GPMC_15
A.
`In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
Figure 7-53. GPMC and NAND Flash — Data Write Cycle
170
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7.10.5.8.4 GPMC0 IOSETs
Table 7-60 defines valid pin combinations of each GPMC0 IOSET.
Table 7-60. GPMC0 IOSETs
SIGNALS
IOSET1
BALL NAME
IOSET2
MUXMODE
BALL NAME
MUXMODE
GPMC0_AD0
GPMC0_AD0
0
GPMC0_AD0
0
GPMC0_AD1
GPMC0_AD1
0
GPMC0_AD1
0
GPMC0_AD2
GPMC0_AD2
0
GPMC0_AD2
0
GPMC0_AD3
GPMC0_AD3
0
GPMC0_AD3
0
GPMC0_AD4
GPMC0_AD4
0
GPMC0_AD4
0
GPMC0_AD5
GPMC0_AD5
0
GPMC0_AD5
0
GPMC0_AD6
GPMC0_AD6
0
GPMC0_AD6
0
GPMC0_AD7
GPMC0_AD7
0
GPMC0_AD7
0
GPMC0_AD8
GPMC0_AD8
0
GPMC0_AD8
0
GPMC0_AD9
GPMC0_AD9
0
GPMC0_AD9
0
GPMC0_AD10
GPMC0_AD10
0
GPMC0_AD10
0
GPMC0_AD11
GPMC0_AD11
0
GPMC0_AD11
0
GPMC0_AD12
GPMC0_AD12
0
GPMC0_AD12
0
GPMC0_AD13
GPMC0_AD13
0
GPMC0_AD13
0
GPMC0_AD14
GPMC0_AD14
0
GPMC0_AD14
0
GPMC0_AD15
GPMC0_AD15
0
GPMC0_AD15
0
GPMC0_CLK
GPMC0_CLK
0
GPMC0_CLK
0
GPMC0_ADVn_ALE
GPMC0_ADVn_ALE
0
GPMC0_ADVn_ALE
0
GPMC0_OEn_REn
GPMC0_OEn_REn
0
GPMC0_OEn_REn
0
GPMC0_WEn
GPMC0_WEn
0
GPMC0_WEn
0
GPMC0_BE0n_CLE
GPMC0_BE0n_CLE
0
GPMC0_BE0n_CLE
0
GPMC0_BE1n
GPMC0_BE1n
0
GPMC0_BE1n
0
GPMC0_WAIT0
GPMC0_WAIT0
0
GPMC0_WAIT0
0
GPMC0_WAIT1
GPMC0_WAIT1
0
GPMC0_WAIT1
0
GPMC0_WPn
GPMC0_WPn
0
GPMC0_WPn
0
GPMC0_DIR
GPMC0_DIR
0
GPMC0_DIR
0
GPMC0_CSn0
GPMC0_CSn0
0
GPMC0_CSn0
0
GPMC0_CSn1
GPMC0_CSn1
0
GPMC0_CSn1
0
GPMC0_CSn2
GPMC0_CSn2
0
GPMC0_CSn2
0
GPMC0_CSn3
GPMC0_CSn3
0
GPMC0_CSn3
0
GPMC0_AD16
PRG1_PRU0_GPO0
8
PRG1_PRU0_GPO0
8
GPMC0_AD17
PRG1_PRU0_GPO1
8
PRG1_PRU0_GPO1
8
GPMC0_AD18
PRG1_PRU0_GPO2
8
PRG1_PRU0_GPO2
8
GPMC0_AD19
PRG1_PRU0_GPO3
8
PRG1_PRU0_GPO3
8
GPMC0_AD20
PRG1_PRU0_GPO4
8
PRG1_PRU0_GPO4
8
GPMC0_AD21
PRG1_PRU0_GPO5
8
PRG1_PRU0_GPO5
8
GPMC0_AD22
PRG1_PRU0_GPO6
8
PRG1_PRU0_GPO6
8
GPMC0_AD23
PRG1_PRU0_GPO7
8
PRG1_PRU0_GPO7
8
GPMC0_AD24
PRG1_PRU0_GPO8
8
PRG1_PRU0_GPO8
8
GPMC0_AD25
PRG1_PRU0_GPO9
8
PRG1_PRU0_GPO9
8
GPMC0_AD26
PRG1_PRU0_GPO10
8
PRG1_PRU0_GPO10
8
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Table 7-60. GPMC0 IOSETs (continued)
SIGNALS
172
IOSET1
BALL NAME
IOSET2
MUXMODE
BALL NAME
MUXMODE
GPMC0_AD27
PRG1_PRU0_GPO11
8
PRG1_PRU0_GPO11
8
GPMC0_AD28
PRG1_PRU0_GPO12
8
PRG1_PRU0_GPO12
8
GPMC0_AD29
PRG1_PRU0_GPO13
8
PRG1_PRU0_GPO13
8
GPMC0_AD30
PRG1_PRU0_GPO14
8
PRG1_PRU0_GPO14
8
GPMC0_AD31
PRG1_PRU0_GPO15
8
PRG1_PRU0_GPO15
8
GPMC0_BE2n
PRG1_PRU0_GPO16
8
PRG1_PRU0_GPO16
8
GPMC0_A0
PRG1_PRU0_GPO17
8
PRG0_PRU0_GPO2
9
GPMC0_A1
PRG1_PRU0_GPO18
8
PRG0_PRU0_GPO4
9
GPMC0_A2
PRG1_PRU0_GPO19
8
PRG0_PRU0_GPO8
9
GPMC0_A3
PRG1_PRU1_GPO0
8
PRG0_PRU0_GPO14
9
GPMC0_A4
PRG1_PRU1_GPO1
8
PRG0_PRU0_GPO16
9
GPMC0_A5
PRG1_PRU1_GPO2
8
PRG0_PRU0_GPO18
9
GPMC0_A6
PRG1_PRU1_GPO3
8
PRG0_PRU0_GPO19
9
GPMC0_A7
PRG1_PRU1_GPO4
8
PRG0_PRU1_GPO12
9
GPMC0_A8
PRG1_PRU1_GPO5
8
PRG0_PRU1_GPO13
9
GPMC0_A9
PRG1_PRU1_GPO6
8
PRG0_PRU1_GPO14
9
GPMC0_A10
PRG1_PRU1_GPO7
8
PRG0_PRU1_GPO15
9
GPMC0_A11
PRG1_PRU1_GPO8
8
PRG0_PRU1_GPO16
9
GPMC0_A12
PRG1_PRU1_GPO9
8
PRG0_MDIO0_MDIO
9
GPMC0_A13
PRG1_PRU1_GPO10
8
PRG0_MDIO0_MDC
9
GPMC0_A14
PRG1_PRU1_GPO11
8
PRG0_PRU0_GPO12
9
GPMC0_A15
PRG1_PRU1_GPO12
8
PRG0_PRU0_GPO13
9
GPMC0_A16
PRG1_PRU1_GPO13
8
PRG0_PRU0_GPO15
9
GPMC0_A17
PRG1_PRU1_GPO14
8
PRG0_PRU0_GPO17
9
GPMC0_A18
PRG1_PRU1_GPO15
8
PRG0_PRU1_GPO3
9
GPMC0_A19
PRG1_PRU1_GPO16
8
PRG0_PRU1_GPO6
9
GPMC0_BE3n
PRG1_PRU1_GPO17
8
PRG1_PRU1_GPO17
8
GPMC0_A20
GPMC0_CSn3
4
GPMC0_CSn3
4
GPMC0_A21
GPMC0_WAIT1
4
GPMC0_WAIT1
4
GPMC0_A22
GPMC0_WPn
4
GPMC0_WPn
4
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7.10.5.9 I2C
The device contains six multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was
designed to be compliant to the Philips I2C-bus™ specification version 2.1. However, the device IOs are not
fully compliant to the I2C electrical specification. The speeds supported and exceptions are described per port
below:
• MCU_I2C1, I2C1, I2C2, and I2C3
– Speeds:
• Standard-mode (up to 100 Kbits/s)
– 1.8 V
– 3.3 V
• Fast-mode (up to 400 Kbits/s)
– 1.8 V
– 3.3 V
– Exceptions:
• The IOs associated with these ports are not compliant to the fall time requirements defined in the I2C
specification because they are implemented with higher performance LVCMOS push-pull IOs that were
designed to support other signal functions that could not be implemented with I2C compatible IOs. The
LVCMOS IOs being used on these ports are connected such they emulate open-drain outputs. This
emulation is achieved by forcing a constant low output and disabling the output buffer to enter the Hi-Z
state.
• The I2C specification defines a maximum input voltage VIH of (VDDmax + 0.5 V), which exceeds the
absolute maximum ratings for the device IOs. The system must be designed to ensure the I2C signals
never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.
• MCU_I2C0 and I2C0
– Speeds:
• Standard-mode (up to 100 Kbits/s)
– 1.8 V
– 3.3 V
• Fast-mode (up to 400 Kbits/s)
– 1.8 V
– 3.3 V
• Hs-mode (up to 3.4 Mbit/s)
– 1.8 V
– Exceptions:
• The IOs associated with these ports were not design to support Hs-mode while operating at 3.3 V. So
Hs-mode is limited to 1.8-V operation.
• The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of 0.8
V/ns (or 8E+7 V/s). This limit is more restrictive than the minimum fall time limits defined in the I2C
specification. Therefore, it may be necessary to add additional capacitance to the I2C signals to slow
the rise and fall times such that they do not exceed a slew rate of 0.8 V/ns.
• The I2C specification defines a maximum input voltage VIH of (VDDmax + 0.5 V), which exceeds the
absolute maximum ratings for the device IOs. The system must be designed to ensure the I2C signals
never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.
Refer to the Philips I2C-bus specification version 2.1 for timing details.
For more details about features and additional description information on the device Inter-Integrated Circuit, see
the corresponding subsections within Signal Descriptions and Detailed Description sections.
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7.10.5.10 MCAN
Table 7-61 and Table 7-62 presents timing conditions and switching characteristics for MCAN.
For more details about features and additional description information on the device Controller Area Network
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Note
The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names,
where n represents the specific MCAN module.
Table 7-61. MCAN Timing Conditions
PARAMETER
MIN
MAX
UNIT
2
15
V/ns
5
20
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
Table 7-62. MCAN Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MCAN1
td(MCAN_TX)
Delay time, transmit shift register to MCANn_TX
10
ns
MCAN2
td(MCAN_RX)
Delay time, MCANn_RX to receive shift register
10
ns
For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM.
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7.10.5.11 MCSPI
For more details about features and additional description information on the device Serial Port Interface, see
the corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 7-63 presents timing conditions for MCSPI.
Table 7-63. MCSPI Timing Conditions
PARAMETER
MIN
MAX
UNIT
2
8.5
V/ns
6
12
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
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7.10.5.11.1 MCSPI — Controller Mode
Table 7-64, Figure 7-54, Table 7-65, and Figure 7-55 present timing requirements and switching characteristics
for SPI – Controller Mode.
Table 7-64. MCSPI Timing Requirements – Controller Mode
see Figure 7-54
NO.
PARAMETER
DESCRIPTION
MIN
SM4
tsu(POCI-SPICLK)
Setup time, SPIn_D[x] valid before SPIn_CLK active edge
SM5
th(SPICLK-POCI)
Hold time, SPIn_D[x] valid after SPIn_CLK active edge
MAX
UNIT
2.8
ns
3
ns
PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8
SPI_SCLK (OUT)
SM2
SM9
POL=0
SM1
SM3
SM2
POL=1
SPI_SCLK (OUT)
SM5
SM5
SPI_D[x] (IN)
SM4
SM4
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SM2
SM1
SM8
SPI_SCLK (OUT)
SM3
SM9
POL=0
SM1
SM2
SM3
POL=1
SPI_SCLK (OUT)
SM5
SM4
SM4
Bit n-1
SPI_D[x] (IN)
SM5
Bit n-2
Bit n-3
Bit 1
Bit 0
SPRSP08_TIMING_McSPI_02
Figure 7-54. MCSPI Controller Mode Receive Timing
176
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Table 7-65. MCSPI Switching Characteristics - Controller Mode
see Figure 7-55
NO.
PARAMETER
MIN
MAX
UNIT
SM1
tc(SPICLK)
Cycle time, SPIn_CLK
SM2
tw(SPICLKL)
Pulse duration, SPIn_CLK low
0.5P - 1
SM3
tw(SPICLKH)
Pulse duration, SPIn_CLK high
0.5P - 1
SM6
td(SPICLK-PICO)
Delay time, SPIn_CLK active edge to SPIn_D[x]
-3
SM7
td(CS-PICO)
Delay time, SPIn_CSi active edge to SPIn_D[x]
5
ns
SM8
td(CS-SPICLK)
Delay time, SPIn_CSi active to SPIn_CLK first edge
PHA = 0
B - 4(2)
ns
PHA = 1
A-
4(3)
ns
PHA = 0
A - 4(4)
ns
PHA = 1
B - 4(5)
ns
SM9
(1)
(2)
(3)
(4)
(5)
td(SPICLK-CS)
Delay time, SPIn_CLK last edge to SPIn_CSi inactive
20
ns
(1)
ns
(1)
ns
2.5
ns
P = SPI_CLK period in ns.
T_ref is the period of the McSPI functional clock in ns. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK
clock frequency, controlled by the CLKD and CLKG bit fields in the MSPI_CH(i)CONF register and the EXTCLK bit field in the
MSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MSPI_CH(i)CONF register.
• When Fratio = 1; B = (TCS(i) + 0.5) * T_ref.
• When Fratio ≥ 2 and even value; B = (TCS(i) + 0.5) * Fratio * T_ref.
• When Fratio ≥ 3 and odd value; B = ((TCS(i) * Fratio) + ((Fratio + 1) / 2 )) * T_ref.
T_ref is the period of the McSPI functional clock. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK
clock frequency, controlled by the CLKD and CLKG bit fields in the MSPI_CH(i)CONF register and the EXTCLK bit field in the
MSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MSPI_CH(i)CONF register.
• When Fratio = 1; A = (TCS(i) + 1) * T_ref.
• When Fratio ≥ 2 and even value; A = (TCS(i) + 0.5) * Fratio * T_ref.
• When Fratio ≥ 3 and odd value; A = ((TCS(i) * Fratio) + ((Fratio - 1) / 2 )) * T_ref.
T_ref is the period of the McSPI functional clock. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK
clock frequency, controlled by the CLKD and CLKG bit fields in the MSPI_CH(i)CONF register and the EXTCLK bit field in the
MSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MSPI_CH(i)CONF register.
• When Fratio = 1; A = (TCS(i) + 1) * T_ref.
• When Fratio ≥ 2 and even value; A = (TCS(i) + 0.5) * Fratio * T_ref.
• When Fratio ≥ 3 and odd value; A = ((TCS(i) * Fratio) + ((Fratio + 1) / 2 )) * T_ref.
T_ref is the period of the McSPI functional clock. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK
clock frequency, controlled by the CLKD and CLKG bit fields in the MSPI_CH(i)CONF register and the EXTCLK bit field in the
MSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MSPI_CH(i)CONF register.
•
•
•
When Fratio = 1; B = (TCS(i) + 0.5) * T_ref.
When Fratio ≥ 2 and even value; B = (TCS(i) + 0.5) * Fratio * T_ref.
When Fratio ≥ 3 and odd value; B = ((TCS(i) * Fratio) + ((Fratio - 1) / 2 )) * T_ref.
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PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8
SPI_SCLK (OUT)
SM2
SM9
POL=0
SM1
SM3
SM2
POL=1
SPI_SCLK (OUT)
SM7
SM6
Bit n-1
SPI_D[x] (OUT)
SM6
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SM1
SM2
SM8
SPI_SCLK (OUT)
SM3
SM9
POL=0
SM1
SM2
SM3
POL=1
SPI_SCLK (OUT)
SM6
Bit n-1
SPI_D[x] (OUT)
SM6
Bit n-2
SM6
Bit n-3
SM6
Bit 1
Bit0
SPRSP08_TIMING_McSPI_01
Figure 7-55. MCSPI Controller Mode Transmit Timing
178
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7.10.5.11.2 MCSPI — Peripheral Mode
Table 7-66, Figure 7-56, Table 7-67, and Figure 7-57 present timing requirements and switching characteristics
for SPI – Peripheral Mode.
Table 7-66. MCSPI Timing Requirements – Peripheral Mode
see Figure 7-56
NO.
(1)
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SS1
tc(SPICLK)
Cycle time, SPIn_CLK
20
ns
SS2
tw(SPICLKL)
Pulse duration, SPIn_CLK low
0.45P
(1)
ns
SS3
tw(SPICLKH)
Pulse duration, SPIn_CLK high
0.45P
(1)
ns
SS4
tsu(PICO-SPICLK)
Setup time, SPIn_D[x] valid before SPIn_CLK active edge
5
ns
SS5
th(SPICLK-PICO)
Hold time, SPIn_D[x] valid after SPIn_CLK active edge
5
ns
SS8
tsu(CS-SPICLK)
Setup time, SPIn_CSi valid before SPIn_CLK first edge
5
ns
SS9
th(SPICLK-CS)
Hold time, SPIn_CSi valid after SPIn_CLK last edge
5
ns
P = SPIn_CLK period in ns.
PHA=0
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SPI_SCLK (IN)
SS3
SS9
POL=0
SS1
SS2
SS3
POL=1
SPI_SCLK (IN)
SS5
SS4
SS4
SS5
Bit n-1
SPI_D[x] (IN)
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SPI_SCLK (IN)
SS3
SS9
POL=0
SS1
SS3
SS2
POL=1
SPI_SCLK (IN)
SS4
SS5
SPI_D[x] (IN)
SS4
SS5
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
SPRSP08_TIMING_McSPI_04
Figure 7-56. SPI Peripheral Mode Receive Timing
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Table 7-67. MCSPI Switching Characteristics – Peripheral Mode
see Figure 7-57
NO.
PARAMETER
DESCRIPTION
SS6
td(SPICLK-POCI)
Delay time, SPIn_CLK active edge to SPIn_D[x]
SS7
tsk(CS-POCI)
Delay time, SPIn_CSi active edge to SPIn_D[x]
MIN
MAX
UNIT
2
17.12
ns
20.95
ns
PHA=0
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SPI_SCLK (IN)
SS3
SS9
POL=0
SS1
SS2
SS3
POL=1
SPI_SCLK (IN)
SS7
SS6
Bit n-1
SPI_D[x] (OUT)
SS6
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SPI_SCLK (IN)
SS3
SS9
POL=0
SS1
SS3
SS2
POL=1
SPI_SCLK (IN)
SS6
Bit n-1
SPI_D[x] (OUT)
SS6
Bit n-2
SS6
Bit n-3
SS6
Bit 1
Bit 0
SPRSP08_TIMING_McSPI_03
Figure 7-57. SPI Peripheral Mode Transmit Timing
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7.10.5.12 MMCSD
The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD),
and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at
transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking
for syntactical correctness.
For more details about MMCSD interfaces, see the corresponding MMC0 and MMC1 subsections within Signal
Descriptions and Detailed Description sections.
Note
Some operating modes require software configuration of the MMC DLL delay settings, as shown in
Table 7-68 and Table 7-77.
The modes which show a value of "Tuning" in the ITAPDLYSEL column of Table 7-68 and Table 7-77
require a tuning algorithm to be used for optimizing input timing. Refer to the MMCSD Programming
Guide in the device TRM for more information on the tuning algorithm and configuration of input
delays required to optimize input timing.
For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in
the device TRM.
7.10.5.12.1 MMC0 - eMMC Interface
MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and supports the
following eMMC applications:
• Legacy speed
• High speed SDR
• High speed DDR
• HS200
Table 7-68 presents the required DLL software configuration settings for MMC0 timing modes.
Table 7-68. MMC0 DLL Delay Mapping for all Timing Modes
REGISTER NAME
BIT FIELD
BIT FIELD NAME
MMCSD0_SS_PHY_CTRL_4_REG
[31:24]
[20]
[15:12]
MMCSD0_SS_PHY_CTRL_5_REG
[8]
[4:0]
[17:16]
[10:8]
[2:0]
FRQSEL
CLKBUFSEL
STRBSEL
OTAPDLYENA
OTAPDLYSEL
ITAPDLYENA
ITAPDLYSEL
SELDLYTXCLK
SELDLYRXCLK
MODE
DESCRIPTION
STROBE
DELAY
OUTPUT
DELAY
ENABLE
OUTPUT
DELAY
VALUE
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DLL
DELAY CHAIN
SELECT
DLL REF
FREQUENCY
DELAY
BUFFER
DURATION
Legacy
SDR
8-bit PHY
operating 1.8 V,
25 MHz
0x0
0x0
NA(1)
0x1
0x10
0x1
0x0
0x7
High
Speed
SDR
8-bit PHY
operating 1.8 V,
50 MHz
0x0
0x0
NA(1)
0x1
0xA
0x1
0x0
0x7
High
Speed
DDR
8-bit PHY
operating 1.8 V,
50 MHz
0x0
0x1
0x6
0x1
0x3
0x0
0x4
0x7
HS200
8-bit PHY
operating 1.8 V,
200 MHz
0x0
0x1
0x7
0x1
Tuning(2)
0x0
0x0
0x7
(1)
(2)
NA means Not Applicable
Tuning means this mode requires a tuning algorithm to optimize input timing
Table 7-69 presents timing conditions for MMC0.
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Table 7-69. MMC0 Timing Conditions
PARAMETER
MIN
MAX
UNIT
0.14
1.44
V/ns
0.3
0.9
V/ns
INPUT CONDITIONS
Legacy SDR
SRI
Input slew rate
High Speed SDR
High Speed DDR (CMD)
0.3
0.9
V/ns
0.45
0.9
V/ns
Legacy SDR
1
12
pF
High Speed SDR
1
12
pF
High Speed DDR
1
12
pF
HS200
1
6
pF
126
756
ps
100
ps
8
ps
High Speed DDR (DAT[7:0])
OUTPUT CONDITIONS
CL
Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
td(Trace Mismatch
Delay)
182
Propagation delay of each trace
All modes
Propagation delay mismatch across all
traces
Legacy SDR, High Speed SDR
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7.10.5.12.1.1 Legacy SDR Mode
Table 7-70, Figure 7-58, Table 7-71, and Figure 7-59 present timing requirements and switching characteristics
for MMC0 – Legacy SDR Mode.
Table 7-70. MMC0 Timing Requirements – Legacy SDR Mode
see Figure 7-58
NO.
MIN
MAX
UNIT
LSDR1
tsu(cmdV-clkH)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
1.56
ns
LSDR2
th(clkH-cmdV)
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
5.44
ns
LSDR3
tsu(dV-clkH)
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
1.56
ns
LSDR4
th(clkH-dV)
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
5.44
ns
Figure 7-58. MMC0 – Legacy SDR – Receive Mode
Table 7-71. MMC0 Switching Characteristics – Legacy SDR Mode
see Figure 7-59
NO.
PARAMETER
fop(clk)
Operating frequency, MMC0_CLK
LSDR5
tc(clk)
Cycle time, MMC0_CLK
LSDR6
tw(clkH)
LSDR7
tw(clkL)
LSDR8
LSDR9
MIN
MAX
UNIT
25
MHz
40
ns
Pulse duration, MMC0_CLK high
18.7
ns
Pulse duration, MMC0_CLK low
18.7
ns
td(clkL-cmdV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
-2.3
2.9
ns
td(clkL-dV)
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
-2.3
2.9
ns
Figure 7-59. MMC0 – Legacy SDR – Transmit Mode
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7.10.5.12.1.2 High Speed SDR Mode
Table 7-72, Figure 7-60, Table 7-73, and Figure 7-61 present timing requirements and switching characteristics
for MMC0 – High Speed SDR Mode.
Table 7-72. MMC0 Timing Requirements – High Speed SDR Mode
see Figure 7-60
NO.
MIN
MAX
UNIT
HSSDR1
tsu(cmdV-clkH)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
2.55
ns
HSSDR2
th(clkH-cmdV)
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
2.67
ns
HSSDR3
tsu(dV-clkH)
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
2.55
ns
HSSDR4
th(clkH-dV)
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
2.67
ns
Figure 7-60. MMC0 – High Speed SDR Mode – Receive Mode
Table 7-73. MMC0 Switching Characteristics – High Speed SDR Mode
see Figure 7-61
NO.
PARAMETER
MIN
MAX
UNIT
50
MHz
fop(clk)
Operating frequency, MMC0_CLK
HSSDR5
tc(clk)
Cycle time, MMC0_CLK
20
ns
HSSDR6
tw(clkH)
Pulse duration, MMC0_CLK high
9.2
ns
HSSDR7
tw(clkL)
Pulse duration, MMC0_CLK low
9.2
ns
HSSDR8
td(clkL-cmdV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
-2.3
2.9
ns
HSSDR9
td(clkL-dV)
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
-2.3
2.9
ns
Figure 7-61. MMC0 – High Speed SDR Mode – Transmit Mode
184
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7.10.5.12.1.3 High Speed DDR Mode
Table 7-74, Figure 7-62, Table 7-75, and Figure 7-63 present timing requirements and switching characteristics
for MMC0 – High Speed DDR Mode.
Table 7-74. MMC0 Timing Requirements – High Speed DDR Mode
see Figure 7-62
NO.
MIN
MAX
UNIT
HSDDR1
tsu(cmdV-clk)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
1.62
ns
HSDDR2
th(clk-cmdV)
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
2.52
ns
HSDDR3
tsu(dV-clk)
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition
0.83
ns
HSDDR4
th(clk-dV)
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition
1.76
ns
Figure 7-62. MMC0 – High Speed DDR Mode – Receive Mode
Table 7-75. MMC0 Switching Characteristics – High Speed DDR Mode
see Figure 7-63
NO.
PARAMETER
MIN
MAX
UNIT
50
MHz
fop(clk)
Operating frequency, MMC0_CLK
HSDDR5
tc(clk)
Cycle time, MMC0_CLK
20
ns
HSDDR6
tw(clkH)
Pulse duration, MMC0_CLK high
9.2
ns
HSDDR7
tw(clkL)
Pulse duration, MMC0_CLK low
HSDDR8
td(clk-cmdV)
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
3.31
7.65
ns
HSDDR9
td(clk-dV)
Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition
2.81
6.94
ns
9.2
ns
Figure 7-63. MMC0 – High Speed DDR Mode – Transmit Mode
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7.10.5.12.1.4 HS200 Mode
Table 7-76 and Figure 7-64 present switching characteristics for MMC0 – HS200 Mode.
Table 7-76. MMC0 Switching Characteristics – HS200 Mode
see Figure 7-64
NO.
PARAMETER
fop(clk)
Operating frequency, MMC0_CLK
HS2005
tc(clk)
Cycle time, MMC0_CLK
HS2006
tw(clkH)
HS2007
HS2008
HS2009
MIN
MAX
UNIT
200
MHz
5
ns
Pulse duration, MMC0_CLK high
2.08
ns
tw(clkL)
Pulse duration, MMC0_CLK low
2.08
td(clkL-cmdV)
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
0.99
3.28
ns
td(clkL-dV)
Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition
0.99
3.28
ns
ns
Figure 7-64. MMC0 – HS200 Mode – Transmit Mode
186
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7.10.5.12.2 MMC1 - SD/SDIO Interface
MMC1 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer
Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:
• Default speed
• High speed
• UHS–I SDR12
• UHS–I SDR25
• UHS–I SDR50
• UHS–I SDR104
• UHS–I DDR50
Table 7-77 presents the required DLL software configuration settings for MMC1 timing modes.
Table 7-77. MMC1 DLL Delay Mapping for all Timing Modes
REGISTER NAME
BIT FIELD
BIT FIELD NAME
MMCSD1_SS_PHY_CTRL_4_REG
[20]
[15:12]
OTAPDLYENA OTAPDLYSEL
MMCSD1_SS_PHY_CTRL_5_REG
[8]
[4:0]
[2:0]
ITAPDLYENA
ITAPDLYSEL
CLKBUFSEL
MODE
DESCRIPTION
DELAY
ENABLE
DELAY
VALUE
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DELAY
BUFFER
DURATION
Default
Speed
4-bit PHY operating
3.3 V, 25 MHz
0x1
0x0
0x1
0x0
0x7
High
Speed
4-bit PHY operating
3.3 V, 50 MHz
0x1
0x0
0x1
0x0
0x7
UHS-I
SDR12
4-bit PHY operating
1.8 V, 25 MHz
0x1
0xF
0x1
0x0
0x7
UHS-I
SDR25
4-bit PHY operating
1.8 V, 50 MHz
0x1
0xF
0x1
0x0
0x7
UHS-I
SDR50
4-bit PHY operating
1.8 V, 100 MHz
0x1
0xC
0x1
Tuning(1)
0x7
UHS-I
DDR50
4-bit PHY operating
1.8 V, 50 MHz
0x1
0x9
0x1
Tuning(1)
0x7
UHS-I
SDR104
4-bit PHY operating
1.8, V 200 MHz
0x1
0x6
0x1
Tuning(1)
0x7
(1)
Tuning means this mode requires a tuning algorithm to be used for optimal input timing
Table 7-78 presents timing conditions for MMC1.
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Table 7-78. MMC1 Timing Conditions
PARAMETER
MIN
MAX
UNIT
Default Speed, High Speed
0.69
2.06
V/ns
UHS–I SDR12, UHS–I SDR25
0.34
1.34
V/ns
UHS–I DDR50
1
2
V/ns
UHS–I DDR50
3
10
pF
All other modes
1
10
pF
UHS–I DDR50
240
1134
ps
All other modes
126
1386
ps
20
ps
100
ps
Input Conditions
SRI
Input slew rate
Output Conditions
CL
Output load capacitance
PCB Connectivity Requirements
td(Trace Delay)
td(Trace Mismatch
Delay)
188
Propagation delay of each trace
Propagation delay mismatch across all
traces
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UHS–I DDR50, UHS–I SDR104
All other modes
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
7.10.5.12.2.1 Default Speed Mode
Table 7-79, Figure 7-65, Table 7-80, and Figure 7-66 present timing requirements and switching characteristics
for MMC1 – Default Speed Mode.
Table 7-79. Timing Requirements for MMC1 – Default Speed Mode
see Figure 7-65
NO.
MIN
MAX
UNIT
DS1
tsu(cmdV-clkH)
Setup time, MMC1_CMD valid before MMCi_CLK rising edge
2.15
ns
DS2
th(clkH-cmdV)
Hold time, MMC1_CMD valid after MMC1_CLK rising edge
1.67
ns
DS3
tsu(dV-clkH)
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge
2.15
ns
DS4
th(clkH-dV)
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge
1.67
ns
MMC[x]_CLK
DS1
DS2
DS3
DS4
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-65. MMC1 – Default Speed – Receive Mode
Table 7-80. Switching Characteristics for MMC1 – Default Speed Mode
see Figure 7-66
NO.
PARAMETER
MIN
fop(clk)
Operating frequency, MMC1_CLK
DS5
tc(clk)
Cycle time, MMC1_CLK
DS6
tw(clkH)
DS7
tw(clkL)
DS8
DS9
MAX
UNIT
25
MHz
40
ns
Pulse duration, MMC1_CLK high
18.7
ns
Pulse duration, MMC1_CLK low
18.7
ns
td(clkL-cmdV)
Delay time, MMC1_CLK falling edge to MMC1_CMD transition
-1.8
1.8
ns
td(clkL-dV)
Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition
-1.8
1.8
ns
DS5
DS6
DS7
MMC[x]_CLK
D S8
MMC[x]_CMD
D S9
MMC[x]_DAT[3:0]
Figure 7-66. MMC1 – Default Speed – Transmit Mode
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7.10.5.12.2.2 High Speed Mode
Table 7-81, Figure 7-67, Table 7-82, and Figure 7-68 present timing requirements and switching characteristics
for MMC1 – High Speed Mode.
Table 7-81. Timing Requirements for MMC1 – High Speed Mode
see Figure 7-67
NO.
MIN
MAX
UNIT
HS1
tsu(cmdV-clkH)
Setup time, MMC1_CMD valid before MMC1_CLK rising edge
2.15
ns
HS2
th(clkH-cmdV)
Hold time, MMC1_CMD valid after MMC1_CLK rising edge
1.67
ns
HS3
tsu(dV-clkH)
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge
2.15
ns
HS4
th(clkH-dV)
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge
1.67
ns
MMC[x]_CLK
HS1
H S2
HS3
H S4
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-67. MMC1 – High Speed – Receive Mode
Table 7-82. Switching Characteristics for MMC1 – High Speed Mode
see Figure 7-68
NO.
PARAMETER
MIN
MAX
UNIT
50
MHz
fop(clk)
Operating frequency, MMC1_CLK
HS5
tc(clk)
Cycle time. MMC1_CLK
20
ns
HS6
tw(clkH)
Pulse duration, MMC1_CLK high
9.2
ns
HS7
tw(clkL)
Pulse duration, MMC1_CLK low
9.2
ns
HS8
td(clkL-cmdV)
Delay time, MMC1_CLK falling edge to MMC1_CMD transition
-1.8
1.8
ns
HS9
td(clkL-dV)
Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition
-1.8
1.8
ns
HS5
HS6
HS7
MMC[x]_CLK
H S8
MMC[x]_CMD
H S9
MMC[x]_DAT[3:0]
Figure 7-68. MMC1 – High Speed – Transmit Mode
190
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
7.10.5.12.2.3 UHS–I SDR12 Mode
Table 7-83, Figure 7-69, Table 7-84, and Figure 7-70 present timing requirements and switching characteristics
for MMC1 – UHS-I SDR12 Mode.
Table 7-83. Timing Requirements for MMC1 – UHS-I SDR12 Mode
see Figure 7-69
NO.
MIN
MAX
UNIT
SDR121
tsu(cmdV-clkH)
Setup time, MMC1_CMD valid before MMC1_CLK rising edge
2.35
ns
SDR122
th(clkH-cmdV)
Hold time, MMC1_CMD valid after MMC1_CLK rising edge
1.67
ns
SDR123
tsu(dV-clkH)
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge
2.35
ns
SDR124
th(clkH-dV)
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge
1.67
ns
MMC[x]_CLK
SDR121
SDR122
SDR123
SDR124
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-69. MMC1 – UHS-I SDR12 – Receive Mode
Table 7-84. Switching Characteristics for MMC1 – UHS-I SDR12 Mode
see Figure 7-70
NO.
PARAMETER
MIN
MAX
UNIT
25
MHz
fop(clk)
Operating frequency, MMC1_CLK
SDR125
tc(clk)
Cycle time, MMC1_CLK
SDR126
tw(clkH)
SDR127
tw(clkL)
SDR128
td(clkL-cmdV)
Delay time, MMC1_CLK rising edge to MMC1_CMD transition
1.2
8
ns
SDR129
td(clkL-dV)
Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition
1.2
8
ns
40
ns
Pulse duration, MMC1_CLK high
18.7
ns
Pulse duration, MMC1_CLK low
18.7
ns
SDR125
SDR126
SDR127
MMC[x]_CLK
SDR128
SDR128
SDR129
SDR129
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-70. MMC1 – UHS-I SDR12 – Transmit Mode
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7.10.5.12.2.4 UHS–I SDR25 Mode
Table 7-85, Figure 7-71, Table 7-86, and Figure 7-72 present timing requirements and switching characteristics
for MMC1 – UHS-I SDR25 Mode.
Table 7-85. Timing Requirements for MMC1 – UHS-I SDR25 Mode
see Figure 7-71
NO.
MIN
MAX
UNIT
SDR251
tsu(cmdV-clkH)
Setup time, MMC1_CMD valid before MMC1_CLK rising edge
1.95
ns
SDR252
th(clkH-cmdV)
Hold time, MMC1_CMD valid after MMC1_CLK rising edge
1.67
ns
SDR253
tsu(dV-clkH)
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge
1.95
ns
SDR254
th(clkH-dV)
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge
1.67
ns
MMC[x]_CLK
SDR251
SDR252
SDR253
SDR254
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-71. MMC1 – UHS-I SDR25 – Receive Mode
Table 7-86. Switching Characteristics for MMC1 – UHS-I SDR25 Mode
see Figure 7-72
NO.
PARAMETER
MIN
MAX
UNIT
50
MHz
fop(clk)
Operating frequency, MMC1_CLK
SDR255
tc(clk)
Cycle time, MMC1_CLK
20
ns
SDR256
tw(clkH)
Pulse duration, MMC1_CLK high
9.2
ns
SDR257
tw(clkL)
Pulse duration, MMC1_CLK low
9.2
ns
SDR258
td(clkL-cmdV)
Delay time, MMC1_CLK rising edge to MMC1_CMD transition
2.4
8
ns
SDR259
td(clkL-dV)
Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition
2.4
8
ns
SDR255
SDR256
SDR257
MMC[x]_CLK
SDR258
SDR258
SDR259
SDR259
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-72. MMC1 – UHS-I SDR25 – Transmit Mode
192
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
7.10.5.12.2.5 UHS–I SDR50 Mode
Table 7-87, and Figure 7-73 presents switching characteristics for MMC1 – UHS-I SDR50 Mode.
Table 7-87. Switching Characteristics for MMC1 – UHS-I SDR50 Mode
see Figure 7-73
NO.
PARAMETER
MIN
fop(clk)
Operating frequency, MMC1_CLK
SDR505
tc(clk)
Cycle time, MMC1_CLK
SDR506
tw(clkH)
SDR507
SDR508
SDR509
MAX
UNIT
100
MHz
10
ns
Pulse duration, MMC1_CLK high
4.45
ns
tw(clkL)
Pulse duration, MMC1_CLK low
4.45
td(clkL-cmdV)
Delay time, MMC1_CLK rising edge to MMC1_CMD transition
1.2
6.35
ns
td(clkL-dV)
Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition
1.2
6.35
ns
ns
SDR505
SDR506
SDR507
MMC[x]_CLK
SDR508
SDR508
SDR509
SDR509
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-73. MMC1 – UHS-I SDR50 – Transmit Mode
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7.10.5.12.2.6 UHS–I DDR50 Mode
Table 7-88, and Figure 7-74 present switching characteristics for MMC1 – UHS-I DDR50 Mode.
Table 7-88. Switching Characteristics for MMC1 – UHS-I DDR50 Mode
see Figure 7-74
NO.
PARAMETER
MIN
MAX
UNIT
50
MHz
fop(clk)
Operating frequency, MMC1_CLK
DDR505
tc(clk)
Cycle time, MMC1_CLK
20
ns
DDR506
tw(clkH)
Pulse duration, MMC1_CLK high
9.2
ns
DDR507
tw(clkL)
Pulse duration, MMC1_CLK low
9.2
DDR508
td(clk-cmdV)
Delay time, MMC1_CLK rising edge to MMC1_CMD transition
1.2
6.35
ns
DDR509
td(clk-dV)
Delay time, MMC1_CLK transition to MMC1_DAT[3:0] transition
1.2
6.35
ns
ns
DDR505
DDR506
DDR507
MMC[x]_CLK
DDR508
MMC[x]_CMD
DDR509
DDR509
MMC[x]_DAT[3:0]
Figure 7-74. MMC1 – UHS-I DDR50 – Transmit Mode
194
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7.10.5.12.2.7 UHS–I SDR104 Mode
Table 7-89, and Figure 7-75 present switching characteristics for MMC1 – UHS-I SDR104 Mode.
Table 7-89. Switching Characteristics for MMC1 – UHS-I SDR104 Mode
see Figure 7-75
NO.
PARAMETER
MIN
fop(clk)
Operating frequency, MMC1_CLK
SDR1045
tc(clk)
Cycle time, MMC1_CLK
SDR1046
tw(clkH)
SDR1047
SDR1048
SDR1049
MAX
UNIT
200
MHz
5
ns
Pulse duration, MMC1_CLK high
2.12
ns
tw(clkL)
Pulse duration, MMC1_CLK low
2.12
td(clkL-cmdV)
Delay time, MMC1_CLK rising edge to MMC1_CMD transition
1.08
3.2
ns
td(clkL-dV)
Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition
1.08
3.2
ns
ns
SDR1045
SDR1046
SDR1047
MMC[x]_CLK
SDR1048
SDR1048
SDR1049
SDR1049
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-75. MMC1 – UHS-I SDR104 – Transmit Mode
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
7.10.5.13 CPTS
Table 7-90, Table 7-91, Figure 7-76, Table 7-92, and Figure 7-77 present timing conditions, requirements, and
switching characteristics for CPTS.
Table 7-90. CPTS Timing Conditions
PARAMETER
MIN
MAX
UNIT
0.5
5
V/ns
2
10
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
Table 7-91. CPTS Timing Requirements
see Figure 7-76
NO.
DESCRIPTION
MIN
MAX
UNIT
T1
tw(HWTSPUSHH)
Pulse duration, HWnTSPUSH high
12P(1)
+2
ns
T2
tw(HWTSPUSHL)
Pulse duration, HWnTSPUSH low
12P(1) + 2
ns
T3
tc(RFT_CLK)
Cycle time, RFT_CLK
T4
tw(RFT_CLKH)
Pulse duration, RFT_CLK high
0.45T(2)
ns
Pulse duration, RFT_CLK low
0.45T(2)
ns
T5
(1)
(2)
PARAMETER
tw(RFT_CLKL)
5
8
ns
P = functional clock period in ns.
T = RFT_CLK period in ns.
T1
T2
HWn_TSPUSH
T3
RFT_CLK
T4
T5
Figure 7-76. CPTS Timing Requirements
196
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Table 7-92. CPTS Switching Characteristics
see Figure 7-77
NO.
T6
PARAMETER
tw(TS_COMPH)
DESCRIPTION
SOURCE
MIN
UNIT
36P(1) - 2
ns
T7
tw(TS_COMPL)
Pulse duration, TS_COMP low
36P(1)
-2
ns
T8
tw(TS_SYNCH)
Pulse duration, TS_SYNC high
36P(1) - 2
ns
36P(1)
T9
tw(TS_SYNCL)
Pulse duration, TS_SYNC low
T10
tw(SYNC_OUTH)
Pulse duration, SYNCn_OUT high
TS_SYNC
-2
ns
36P(1) - 2
ns
5P(1) - 2
ns
GENF
T11
tw(SYNC_OUTL)
Pulse duration, SYNCn_OUT low
TS_SYNC
36P(1)
GENF
(1)
MAX
Pulse duration, TS_COMP high
-2
ns
5P(1) - 2
ns
P = functional clock period in ns.
T6
T7
T8
T9
T10
T11
TS_COMP
TS_SYNC
SYNCn_OUT
Figure 7-77. CPTS Switching Characteristics
For more information, see Data Movement Architecture (DMA) chapter in the device TRM.
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SPRSP56F – JANUARY 2021 – REVISED OCTOBER 2023
7.10.5.14 OSPI
OSPI0 offers two data capture modes, PHY mode and Tap mode.
PHY mode uses an internal reference clock to transmit and receive data via a DLL based PHY, where each
reference clock cycle produces a single cycle of OSPI0_CLK for Single Data Rate (SDR) transfers or a half
cycle of OSPI0_CLK for Double Data Rate (DDR) transfers. PHY mode supports four clocking topologies
for the receive data capture clock. Internal PHY Loopback - uses the internal reference clock as the PHY
receive data capture clock. Internal Pad Loopback - uses OSPI0_LBCLKO looped back into the PHY from the
OSPI0_LBCLKO pin as the PHY receive data capture clock. External Board Loopback - uses OSPI0_LBCLKO
looped back into the PHY from the OSPI0_DQS pin as the PHY receive data capture clock. DQS - uses the DQS
output from the attached device as the PHY receive data capture clock. SDR transfers are not supported when
using the Internal Pad Loopback and DQS clocking topologies. DDR transfers are not supported when using the
Internal PHY Loopback or Internal Pad Loopback clocking topologies.
Tap mode uses an internal reference clock with selectable taps to adjusted data transmit and receive capture
delays relative to OSPI0_CLK, which is a divide by 4 of the internal reference clock for SDR transfers or a divide
by 8 of the internal reference clock for DDR transfers. Tap mode only supports one clocking topology for the
receive data capture clock. No Loopback - uses the internal reference clock as the Tap receive data capture
clock. This clocking topology supports a maximum internal reference clock rate of 200 MHz, which produces an
OSPI0_CLK rate up to 50 MHz for SDR mode or 25 MHz for DDR mode.
For more details about features and additional description information on the device Octal Serial Peripheral
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Section 7.10.5.14.1 defines timing requirements and switching characteristics associated with PHY mode and
Section 7.10.5.14.2 defines timing requirements and switching characteristics associated with Tap mode.
Table 7-93 presents timing conditions for OSPI0.
Table 7-93. OSPI0 Timing Conditions
PARAMETER
MODE
MIN
MAX
UNIT
1
6
V/ns
3
10
pF
450
ps
2L(1) - 30
2L(1) + 30
ps
L(1) - 30
L(1) + 30
ps
60
ps
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
td(Trace Mismatch
Delay)
(1)
Propagation delay of OSPI0_CLK trace
No Loopback
Internal PHY Loopback
Internal Pad Loopback
Propagation delay of OSPI0_LBCLKO
trace
External Board Loopback
Propagation delay of OSPI0_DQS trace
DQS
Propagation delay mismatch of
OSPI0_D[7:0] and OSPI0_CSn[3:0]
relative to OSPI0_CLK
All modes
L = Propagation delay of OSPI0_CLK trace
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device
TRM.
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7.10.5.14.1 OSPI0 PHY Mode
7.10.5.14.1.1 OSPI0 With PHY Data Training
Read and write data valid windows will shift due to variation in process, voltage, temperature, and operating
frequency. A data training method may be implemented to dynamically configure optimal read and write timing.
Implementing data training enables proper operation across temperature with a specific process, voltage, and
frequency operating condition, while achieving a higher operating frequency.
Data transmit and receive timing parameters are not defined for the data training use case since they are
dynamically adjusted based on the operating condition.
Table 7-94 defines DLL delays required for OSPI0 with Data Training. Table 7-95, Figure 7-78, Table 7-96, and
Figure 7-79 present timing requirements and switching characteristics for OSPI0 with Data Training.
Table 7-94. OSPI0 DLL Delay Mapping for PHY Data Training
MODE
OSPI_PHY_CONFIGURATION_REG BIT FIELD
DELAY VALUE
Transmit
All modes
PHY_CONFIG_TX_DLL_DELAY_FLD,
(1)
PHY_CONFIG_RX_DLL_DELAY_FLD
(2)
Receive
All modes
(1)
(2)
Transmit DLL delay value determined by training software
Receive DLL delay value determined by training software
Table 7-95. OSPI0 Timing Requirements – PHY Data Training
see Figure 7-78
NO.
MODE
O15
tsu(D-LBCLK)
Setup time, OSPI0_D[7:0] valid before
active OSPI0_DQS edge
O16
th(LBCLK-D)
Hold time, OSPI0_D[7:0] valid after active
OSPI0_DQS edge
(1)
MIN
MAX
UNIT
DDR with DQS
(1)
ns
DDR with DQS
(1)
ns
Minimum setup and hold time requirements for OSPI0_D[7:0] inputs are not defined when Data Training is used to find the optimum
data valid window.
OSPI_DQS
O15
O16
O15
O16
OSPI_D[i:0]
OSPI_TIMING_04
Figure 7-78. OSPI0 Timing Requirements – PHY Data Training, DDR with DQS
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Table 7-96. OSPI Switching Characteristics – PHY Data Training
See Figure 7-79
NO.
O1
tc(CLK)
Cycle time, OSPI0_CLK
O2
tw(CLKL)
Pulse duration, OSPI0_CLK low
O3
(1)
(2)
(3)
(4)
(5)
(6)
PARAMETER
tw(CLKH)
MODE
MIN
MAX
UNIT
1.8V, DDR
6.02
7.52
ns
7.52
7.52
ns
3.3V, DDR
Pulse duration, OSPI0_CLK high
DDR
((0.475P(1)) - 0.3)
DDR
((0.475P(1))
((0.525P(1)) +
(1.025M(2)R(4)) +
(0.11TD(5)) + 1)
ns
ns
- 0.3)
ns
O4
td(CSn-CLK)
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
DDR
((0.475P(1)) +
(0.975M(2)R(4)) +
(0.04TD(5)) - 1)
O5
td(CLK-CSn)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
DDR
((0.475P(1)) +
(0.975N(3)R(4)) (0.04TD(5)) - 1)
((0.525P(1)) +
(1.025N(3)R(4)) (0.11TD(5)) + 1)
ns
O6
td(CLK-D)
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
DDR
(6)
(6)
ns
P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns
M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
R = reference clock cycle time in ns
TD = PHY_CONFIG_TX_DLL_DELAY_FLD
Minimum and maximum delay times for OSPI0_D[7:0] outputs are not defined when Data Training is used to find the optimum data
valid window.
OSPI_CSn
O4
O5
O3
OSPI_CLK
O6
O6
O2
O1
OSPI_D[i:0]
OSPI_TIMING_01
Figure 7-79. OSPI0 Switching Characteristics – PHY DDR Data Training
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7.10.5.14.1.2 OSPI0 Without Data Training
Note
Timing parameters defined in this section are only applicable when data training is not implemented
and DLL delays are configured as described in Table 7-97 and Table 7-100.
7.10.5.14.1.2.1 OSPI0 PHY SDR Timing
Table 7-97 defines DLL delays required for OSPI0 PHY SDR Mode. Table 7-98, Figure 7-80, Figure 7-81, Table
7-99, and Figure 7-82 present timing requirements and switching characteristics for OSPI0 PHY SDR Mode.
Table 7-97. OSPI0 DLL Delay Mapping for PHY SDR Timing Modes
MODE
OSPI_PHY_CONFIGURATION_REG BIT FIELD
DELAY VALUE
Transmit
All modes
PHY_CONFIG_TX_DLL_DELAY_FLD,
0x0
PHY_CONFIG_RX_DLL_DELAY_FLD
0x0
Receive
All modes
Table 7-98. OSPI0 Timing Requirements – PHY SDR Mode
see Figure 7-80 and Figure 7-81
NO.
MODE
MIN
MAX
UNIT
O19
tsu(D-CLK)
Setup time, OSPI0_D[7:0] valid before
active OSPI0_CLK edge
1.8V, SDR with Internal PHY Loopback
4.8
ns
3.3V, SDR with Internal PHY Loopback
5.19
ns
O20
th(CLK-D)
Hold time, OSPI0_D[7:0] valid after active
OSPI0_CLK edge
1.8V, SDR with Internal PHY Loopback
-0.5
ns
3.3V, SDR with Internal PHY Loopback
-0.5
ns
O21
tsu(D-LBCLK)
Setup time, OSPI0_D[7:0] valid before
active OSPI0_DQS edge
1.8V, SDR with External Board Loopback
0.6
ns
3.3V, SDR with External Board Loopback
0.9
ns
O22
th(LBCLK-D)
Hold time, OSPI0_D[7:0] valid after active
OSPI0_DQS edge
1.8V, SDR with External Board Loopback
1.7
ns
3.3V, SDR with External Board Loopback
2.0
ns
OSPI_CLK
O19
O20
OSPI_D[i:0]
OSPI_TIMING_05
Figure 7-80. OSPI0 Timing Requirements – PHY SDR with Internal PHY Loopback
OSPI_DQS
O21
O22
OSPI_D[i:0]
OSPI_TIMING_06
Figure 7-81. OSPI0 Timing Requirements – PHY SDR with External Board Loopback
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Table 7-99. OSPI0 Switching Characteristics – PHY SDR Mode
see Figure 7-82
NO.
PARAMETER
MODE
MIN
1.8V
MAX
UNIT
7
ns
O7
tc(CLK)
Cycle time, OSPI0_CLK
6.03
ns
O8
tw(CLKL)
Pulse duration, OSPI0_CLK low
((0.475P(1)) - 0.3)
ns
tw(CLKH)
Pulse duration, OSPI0_CLK high
((0.475P(1))
ns
O10
td(CSn-CLK)
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
((0.475P(1)) +
((0.525P(1)) +
(0.975M(2)R(4)) - 1) (1.025M(2)R(4)) + 1)
ns
O11
td(CLK-CSn)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
((0.475P(1)) +
((0.525P(1)) +
(0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)
ns
O12
td(CLK-D)
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
O9
(1)
(2)
(3)
(4)
3.3V
- 0.3)
1.8V
-1.16
1.25
ns
3.3V
-1.33
1.51
ns
P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns
M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
R = reference clock cycle time in ns
OSPI_CSn
O10
O9
OSPI_CLK
O11
O7
O8
O12
OSPI_D[i:0]
OSPI_TIMING_02
Figure 7-82. OSPI0 Switching Characteristics – PHY SDR
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7.10.5.14.1.2.2 OSPI0 PHY DDR Timing
Table 7-100 defines DLL delays required for OSPI0 PHY DDR Mode. Table 7-101, Figure 7-83, Table 7-102, and
Figure 7-84 present timing requirements and switching characteristics for OSPI0 PHY DDR Mode.
Table 7-100. OSPI0 DLL Delay Mapping for PHY DDR Timing Modes
MODE
OSPI_PHY_CONFIGURATION_REG BIT FIELD
DELAY VALUE
Transmit
1.8V
PHY_CONFIG_TX_DLL_DELAY_FLD
0x3E
3.3V
PHY_CONFIG_TX_DLL_DELAY_FLD
0x3B
Receive
1.8V, DQS
PHY_CONFIG_RX_DLL_DELAY_FLD
0x15
3.3V, DQS
PHY_CONFIG_RX_DLL_DELAY_FLD
0x3A
All other modes
PHY_CONFIG_RX_DLL_DELAY_FLD
0x0
Table 7-101. OSPI0 Timing Requirements – PHY DDR Mode
see Figure 7-83
NO.
O15
O16
MODE
tsu(D-LBCLK)
th(LBCLK-D)
Setup time, OSPI0_D[7:0] valid before
active OSPI0_DQS edge
Hold time, OSPI0_D[7:0] valid after active
OSPI0_DQS edge
MIN
UNIT
1.8V, DDR with External Board Loopback
0.53
ns
1.8V, DDR with DQS
-0.46
ns
3.3V, DDR with External Board Loopback
1.23
ns
3.3V, DDR with DQS
-0.66
ns
1.8V, DDR with External Board Loopback
1.24(1)
ns
3.59
ns
1.44(1)
ns
7.92
ns
1.8V, DDR with DQS
3.3V, DDR with External Board Loopback
3.3V, DDR with DQS
(1)
MAX
This Hold time requirement is larger than the Hold time provided by a typical OSPI/QSPI/SPI device. Therefore, the trace length
between the SoC and attached OSPI/QSPI/SPI device must be sufficiently long enough to ensure that the Hold time is met at the SoC.
The length of the SoC's external loopback clock (OSPI0_LBCLKO to OSPI0_DQS) may need to be shortened to compensate.
OSPI_DQS
O15
O16
O15
O16
OSPI_D[i:0]
OSPI_TIMING_04
Figure 7-83. OSPI0 Timing Requirements – PHY DDR with External Board Loopback or DQS
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Table 7-102. OSPI0 Switching Characteristics – PHY DDR Mode
see Figure 7-84
NO.
O1
(1)
(2)
(3)
(4)
PARAMETER
tc(CLK)
MODE
MIN
Cycle time, OSPI0_CLK
- 0.3)
ns
O2
tw(CLKL)
Pulse duration, OSPI0_CLK low
O3
tw(CLKH)
Pulse duration, OSPI0_CLK high
((0.475P(1)) - 0.3)
td(CSn-CLK)
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
O5
td(CLK-CSn)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
O6
td(CLK-D)
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
UNIT
ns
((0.475P(1))
O4
MAX
19
ns
((0.475P(1))
((0.525P(1))
(0.975M(2)R(4))) (1.025M(2)R(4)) + 7)
ns
((0.475P(1)) +
(0.975N(3)R(4)) - 7)
((0.525P(1)) +
(1.025N(3)R(4)))
ns
1.8V
-7.71
-1.56
ns
3.3V
-7.71
-1.56
ns
P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns
M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
R = reference clock cycle time in ns
OSPI_CSn
O4
O5
O3
OSPI_CLK
O6
O6
O2
O1
OSPI_D[i:0]
OSPI_TIMING_01
Figure 7-84. OSPI0 Switching Characteristics – PHY DDR
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7.10.5.14.2 OSPI0 Tap Mode
7.10.5.14.2.1 OSPI0 Tap SDR Timing
Table 7-103, Figure 7-85, Table 7-104, and Figure 7-86 present timing requirements and switching
characteristics for OSPI0 Tap SDR Mode.
Table 7-103. OSPI0 Timing Requirements – Tap SDR Mode
see Figure 7-85
NO.
MODE
O19
tsu(D-CLK)
Setup time, OSPI0_D[7:0] valid before
active OSPI0_CLK edge
O20
th(CLK-D)
Hold time, OSPI0_D[7:0] valid after active
OSPI0_CLK edge
(1)
(2)
MIN
MAX
UNIT
No Loopback
(15.4 (0.975T(1)R(2)))
ns
No Loopback
(- 4.3 +
(0.975T(1)R(2)))
ns
T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]
R = reference clock cycle time in ns
OSPI_CLK
O19
O20
OSPI_D[i:0]
OSPI_TIMING_05
Figure 7-85. OSPI0 Timing Requirements – Tap SDR, No Loopback
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Table 7-104. OSPI0 Switching Characteristics – Tap SDR Mode
see Figure 7-86
NO.
O7
PARAMETER
tc(CLK)
MODE
MIN
Cycle time, OSPI0_CLK
MAX
UNIT
20
ns
- 0.3)
ns
O8
tw(CLKL)
Pulse duration, OSPI0_CLK low
((0.475P(1))
O9
tw(CLKH)
Pulse duration, OSPI0_CLK high
((0.475P(1)) - 0.3)
((0.475P(1))
ns
((0.525P(1))
O10
td(CSn-CLK)
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
+
+
(0.975M(2)R(4)) - 1) (1.025M(2)R(4)) + 1)
ns
O11
td(CLK-CSn)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
((0.475P(1)) +
((0.525P(1)) +
(0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)
ns
O12
td(CLK-D)
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
(1)
(2)
(3)
(4)
- 4.25
7.25
ns
P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns
M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
R = reference clock cycle time in ns
OSPI_CSn
O10
O9
OSPI_CLK
O11
O7
O8
O12
OSPI_D[i:0]
OSPI_TIMING_02
Figure 7-86. OSPI0 Switching Characteristics – Tap SDR, No Loopback
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7.10.5.14.2.2 OSPI0 Tap DDR Timing
Table 7-105, Figure 7-87, Table 7-106, and Figure 7-88 present timing requirements and switching
characteristics for OSPI0 Tap DDR Mode.
Table 7-105. OSPI0 Timing Requirements – Tap DDR Mode
see Figure 7-87
NO.
MODE
MIN
MAX
UNIT
O13
tsu(D-CLK)
Setup time, OSPI0_D[7:0] valid before
active OSPI0_CLK edge
No Loopback
(17.04 (0.975T(1)R(2)))
ns
O14
th(CLK-D)
Hold time, OSPI0_D[7:0] valid after active
OSPI0_CLK edge
No Loopback
(- 3.16 +
(0.975T(1)R(2)))
ns
(1)
(2)
T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]
R = reference clock cycle time in ns
OSPI_CLK
O13
O14
O13
O14
OSPI_D[i:0]
OSPI_TIMING_03
Figure 7-87. OSPI0 Timing Requirements – Tap DDR, No Loopback
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Table 7-106. OSPI0 Switching Characteristics – Tap DDR Mode
see Figure 7-88
NO.
O1
(1)
(2)
(3)
(4)
(5)
PARAMETER
tc(CLK)
MODE
MIN
Cycle time, OSPI0_CLK
MAX
UNIT
40
ns
- 0.3)
ns
O2
tw(CLKL)
Pulse duration, OSPI0_CLK low
((0.475P(1))
O3
tw(CLKH)
Pulse duration, OSPI0_CLK high
((0.475P(1)) - 0.3)
ns
((0.475P(1))
((0.525P(1))
O4
td(CSn-CLK)
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
+
+
((0.975M(2)R(5)) - 1) ( 1.025M(2)R(5)) + 1)
O5
td(CLK-CSn)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
((0.475P(1)) +
(0.975N(3)R(5)) - 1)
((0.525P(1)) +
(1.025N(3)R(5)) + 1)
ns
O6
td(CLK-D)
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
(- 5.04 +
(0.975(T(4) + 1)R(5))
- (0.525P(1)))
(3.64 +
(1.025(T(4) + 1)R(5))
- (0.475P(1)))
ns
ns
P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns
M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
T = OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD]
R = reference clock cycle time in ns
OSPI_CSn
O4
O5
O3
OSPI_CLK
O6
O6
O2
O1
OSPI_D[i:0]
OSPI_TIMING_01
Figure 7-88. OSPI0 Switching Characteristics – Tap DDR, No Loopback
7.10.5.15 PCIe
The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the
specification for timing details.
For more details about features and additional description information on the device Peripheral Component
Interconnect Express (PCIe), see the SERDES0 Signal Descriptions and the corresponding subsection within
Detailed Description.
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals
chapter of the device TRM.
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7.10.5.16 PRU_ICSSG
The device has integrated two identical Programmable Real-Time Unit Subsystem and Industrial Communication
Subsystems - Gigabit (PRU_ICSSG), PRU_ICSSG0 and PRU_ICSSG1. The programmable nature of the PRU
cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast
real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks
from the other processor cores in the device.
For more details about features and additional description information on the device PRU_ICSSG, see the
corresponding subsections within Signal Descriptions and Detailed Description sections.
Note
The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU
GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in
the device TRM.
7.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
Note
The PRU_ICSSG PRU signals have different functionality depending on the mode of operation. The
signal naming in this section matches the naming used in the PRU Module Interface section in the
device TRM.
Table 7-107. PRU_ICSSG PRU Timing Conditions
PARAMETER
MIN
MAX
UNIT
1
3
V/ns
2
30
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
7.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
Table 7-108. PRU_ICSSG PRU Switching Characteristics – Direct Output Mode
see Figure 7-89
NO.
PRDO1
PARAMETER
tsk(GPO-GPO)
DESCRIPTION
MIN
MAX
Skew, GPO to GPO
2
UNIT
ns
GPO[n:0]
PRDO1
A.
PRU_TIMING_02
n in GPO[n:0] = 19.
Figure 7-89. PRU_ICSSG PRU Direct Output Timing
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7.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
Table 7-109. PRU_ICSSG PRU Timing Requirements – Parallel Capture Mode
see Figure 7-90 and Figure 7-91
NO.
PARAMETER
DESCRIPTION
PRPC1
tc(CLOCK)
Cycle time, CLOCKIN
PRPC2
tw(CLOCKL)
MIN
MAX
UNIT
20
ns
Pulse duration, CLOCKIN low
0.45P(1)
ns
0.45P(1)
ns
PRPC3
tw(CLOCKH)
Pulse duration, CLOCKIN high
PRPC4
tsu(DATAIN-CLOCK)
Setup time, DATAIN valid before CLOCKIN active edge
4
ns
PRPC5
th(CLOCK-DATAIN)
Hold time, DATAIN valid after CLOCKIN active edge
0
ns
(1)
P = CLOCKIN cycle time in ns
PRPC1
PRPC3
PRPC2
CLOCKIN
DATAIN
PRPC5
PRPC4
PRU_TIMING_03
Figure 7-90. PRU_ICSSG PRU Parallel Capture Timing Requirements – Rising Edge Mode
PRPC1
PRPC3
PRPC2
CLOCKIN
DATAIN
PRPC5
PRPC4
PRU_TIMING_04
Figure 7-91. PRU_ICSSG PRU Parallel Capture Timing Requirements – Falling Edge Mode
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7.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
Table 7-110. PRU_ICSSG PRU Timing Requirements – Shift In Mode
see Figure 7-92
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PRSI1
tw(DATAINH)
Pulse duration, DATAIN high
2P(1) + 2
ns
PRSI2
tw(DATAINL)
Pulse duration, DATAIN low
2P(1) + 2
ns
(1)
P = Internal shift in clock period, defined by PRUn_GPI_DIV0 and PRUn_GPI_DIV1 bit fields in the ICSSG_GPCFGn_REG register.
PRUn represents the respective PRU0 or PRU1 instance.
PRSI1
PRSI2
DATAIN
PRU_TIMING_05
Figure 7-92. PRU_ICSSG PRU Shift In Timing
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Table 7-111. PRU_ICSSG PRU Switching Characteristics – Shift Out Mode
see Figure 7-93
NO.
PARAMETER
PRSO1
DESCRIPTION
tc(CLOCKOUT)
MIN
Cycle time, CLOCKOUT
MAX
10
UNIT
ns
PRSO2L
tw(CLOCKOUTL)
Pulse duration, CLOCKOUT low
0.475P(1)Z(2)
0.3
ns
PRSO2H
tw(CLOCKOUTH)
Pulse duration, CLOCKOUT high
0.475P(1)Y(3) 0.3
ns
PRSO3
(1)
(2)
td(CLOCKOUT-DATAOUT) Delay time, CLOCKOUT to DATAOUT valid
-1
4
ns
P = Software programmable shift out clock period, defined by PRUn_GPO_DIV0 and PRUn_GPO_DIV1 bit fields in the
ICSSG_GPCFGn_REG register, where PRUn represents the respective PRU0 or PRU1 instance.
The Z parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance.
a.
(3)
If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is
an EVEN INTEGER then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1).
b. If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Z equals (PRUn_GPI_DIV0 *
PRUn_GPI_DIV1 + 0.5).
c. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Z equals (PRUn_GPI_DIV0 *
PRUn_GPI_DIV1 + 0.5 * PRUn_GPI_DIV0).
d. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 *
PRUn_GPI_DIV0).
The Y parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance.
a.
b.
c.
d.
If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is
an EVEN INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1).
If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Y equals (PRUn_GPI_DIV0 *
PRUn_GPI_DIV1 - 0.5).
If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Y equals (PRUn_GPI_DIV0 *
PRUn_GPI_DIV1 - 0.5 * PRUn_GPI_DIV0).
If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Y1 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.25 *
PRUn_GPI_DIV0) and Y2 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 * PRUn_GPI_DIV0), where Y1 is the first high
pulse and Y2 is the second high pulse.
PRSO1
PRSO2H
PRSO2L
CLOCKOUT
DATAOUT
PRSO3
PRU_TIMING_06
Figure 7-93. PRU_ICSSG PRU Shift Out Timing
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7.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
Table 7-112. PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing Conditions
PARAMETER
MIN
MAX
UNIT
1
3
V/ns
2
18
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
7.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
Table 7-113. PRU_ICSSG PRU Timing Requirements – Sigma Delta Mode
see Figure 7-94 and Figure 7-95
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PRSD1
tc(SD_CLK)
Cycle time, SDx_CLK
40
ns
PRSD2L
tw(SD_CLKL)
Pulse duration, SDx_CLK low
20
ns
PRSD2H
tw(SD_CLKH)
Pulse duration, SDx_CLK high
20
ns
PRSD3
tsu(SD_D-SD_CLK)
Setup time, SDx_D valid before SDx_CLK active edge
10
ns
PRSD4
th(SD_CLK-SD_D)
Hold time, SDx_D valid before SDx_CLK active edge
5
ns
PRSD1
PRSD2H
SDx_CLK
PRSD2L
SDx_D
PRSD4
PRSD3
PRU_TIMING_07
Figure 7-94. PRU_ICSSG PRU SD_CLK Falling Active Edge
PRSD2L
SDx_CLK
SDx_D
PRSD4
PRSD3
PRU_TIMING_08
Figure 7-95. PRU_ICSSG PRU SD_CLK Rising Active Edge
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Table 7-114. PRU_ICSSG PRU Timing Requirements – Peripheral Interface Mode
see Figure 7-96
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PRPIF1
tw(PIF_DATA_INH)
Pulse duration, PIF_DATA_IN high
2+
(1)
0.475*(4*P)
ns
PRPIF2
tw(PIF_DATA_INL)
Pulse duration, PIF_DATA_IN low
2+
(1)
0.475*(4*P)
ns
(1)
P = 1x (or TX) clock period in ns, defined by PRUn_ED_TX_DIV_FACTOR and PRUn_ED_TX_DIV_FACTOR_FRAC in the
ICSSG_PRUn_ED_TX_CFG_REG register. PRUn represents the respective PRU0 or PRU1 instance.
PRPIF1
PRPIF2
PIF_DATA_IN
PRUPIF_TIMING_01
Figure 7-96. PRU_ICSSG PRU Peripheral Interface Timing Requirements
Table 7-115. PRU_ICSSG PRU Switching Characteristics – Peripheral Interface Mode
see Figure 7-97
NO.
PRPIF3
PARAMETER
DESCRIPTION
tc(PIF_CLK)
MIN
Cycle time, PIF_CLK
UNIT
ns
(1)
ns
(1)
ns
PRPIF4
tw(PIF_CLKH)
Pulse duration, PIF_CLK high
0.475*P
PRPIF5
tw(PIF_CLKL)
Pulse duration, PIF_CLK low
0.475*P
td(PIF_CLK-
Delay time, PIF_CLK fall to PIF_DATA_OUT
PRPIF6
MAX
30
-5
5
ns
-5
5
ns
PIF_DATA_OUT)
PRPIF7
(1)
td(PIF_CLK-PIF_DATA_EN) Delay time, PIF_CLK fall to PIF_DATA_EN
P = 1x (or TX) clock period in ns, defined by PRUn_ED_TX_DIV_FACTOR and PRUn_ED_TX_DIV_FACTOR_FRAC in the
ICSSG_PRUn_ED_TX_CFG_REG register. PRUn represents the respective PRU0 or PRU1 instance.
PRPIF3
PRPIF4
PRPIF5
PIF_CLK
PRPIF6
PIF_DATA_OUT
PRPIF7
PIF_DATA_EN
Figure 7-97. PRU_ICSSG PRU Peripheral Interface Switching Characteristics
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7.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
Table 7-116. PRU_ICSSG PWM Timing Conditions
PARAMETER
MIN
MAX
UNIT
1
4
V/ns
2
7
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
7.10.5.16.2.1 PRU_ICSSG PWM Timing
Table 7-117. PRU_ICSSG PWM Switching Characteristics
see Figure 7-98
NO.
PARAMETER
PRPWM1 tsk(PWM_A-PWM_B)
DESCRIPTION
MIN
Skew, PWM_A to PWM_B
MAX
5
UNIT
ns
PWM_A/B
PRPWM1
PRU_PWM_TIMING_01
Figure 7-98. PRU_ICSSG PWM Timing
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7.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
Table 7-118. PRU_ICSSG IEP Timing Conditions
PARAMETER
MIN
MAX
UNIT
1
3
V/ns
EDC_SYNC_OUTx
EDIO_OUTVALID
2
7
pF
EDIO_DATA_OUT
3
10
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
7.10.5.16.3.1 PRU_ICSSG IEP Timing
Table 7-119. PRU_ICSSG IEP Timing Requirements – Input Validated with SYNC
see Figure 7-99
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PRIEP1
tw(EDC_SYNC_OUTxL)
Pulse duration, EDC_SYNC_OUTx low
20P(1)
-2
ns
PRIEP2
tw(EDC_SYNC_OUTxH)
Pulse duration, EDC_SYNC_OUTx high
20P(1) - 2
ns
tsu(EDIO_DATA_IN-
Setup time, EDIO_DATA_IN valid before EDC_SYNC_OUTx active
edge
20
ns
Hold time, EDIO_DATA_IN valid after EDC_SYNC_OUTx active
edge
20
ns
PRIEP3
EDC_SYNC_OUTx)
PRIEP4
th(EDC_SYNC_OUTxEDIO_DATA_IN)
(1)
P = PRU_ICSSG IEP clock source period in ns.
EDC_SYNC_OUTx
PRIEP2
PRIEP1
PRIEP3
PRIEP4
EDIO_DATA_IN[7:0]
PRU_IEP_TIMING_01
Figure 7-99. PRU_ICSSG IEP SYNC Timing Requirements
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Table 7-120. PRU_ICSSG IEP Switching Characteristics – Digital IOs
see Figure 7-100
NO.
IEPIO1
PARAMETER
DESCRIPTION
tw(EDIO_OUTVALIDL)
MIN
Pulse duration, EDIO_OUTVALID low
14P(1) - 2
32P(1)
IEPIO2
tw(EDIO_OUTVALIDH)
Pulse duration, EDIO_OUTVALID high
IEPIO3
td(EDIO_OUTVALID-
Delay time, EDIO_OUTVALID to EDIO_DATA_OUT
MAX
ns
-2
0
UNIT
ns
18P(1)
ns
5
ns
EDIO_DATA_OUT)
IEPIO4
(1)
tsk(EDIO_DATA_OUT)
EDIO_DATA_OUT skew
P = PRU_ICSSG IEP clock source period in ns.
EDIO_DATA_OUT
IEPIO4
PRU_EDIO_DATA_OUT_TIMING_00
Figure 7-100. PRU_ICSSG IEP Digital IOs Timing Requirements
Table 7-121. PRU_ICSSG IEP Timing Requirements – LATCH_INx
see Figure 7-101
NO.
PRLA1
PRLA2
(1)
PARAMETER
DESCRIPTION
tw(EDC_LATCH_INxL)
tw(EDC_LATCH_INxH)
MIN
MAX
UNIT
Pulse duration, EDC_LATCH_INx low
3P(1) + 2
ns
Pulse duration, EDC_LATCH_INx high
3P(1)
ns
+2
P = PRU_ICSSG IEP clock source period in ns.
PRLA1
EDC_LATCH_INx
PRLA2
PRU_IEP_TIMING_02
Figure 7-101. PRU_ICSSG IEP LATCH_INx Timing Requirements
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7.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
Table 7-122. PRU_ICSSG UART Timing Conditions
PARAMETER
MIN
MAX
UNIT
0.5
5
V/ns
1
30(1)
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
(1)
Output load capacitance
pF
This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the
load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall
times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore,
it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the
device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point
where the minimum data valid time of the attached device is violated.
7.10.5.16.4.1 PRU_ICSSG UART Timing
Table 7-123. PRU_ICSSG UART Timing Requirements
see Figure 7-102
NO.
(1)
(2)
PARAMETER
DESCRIPTION
1
tw(RXD)
Pulse width, receive data bit high or low
2
tw(RXDS)
Pulse width, receive start bit low
MIN
MAX
0.95U(1)
1.05U(1)
(2)
(2)
0.95U(1)
UNIT
ns
ns
(2)
U = UART baud time in ns = 1/programmed baud rate.
This value defines the data valid time, where the input voltage is required to be above VIH or below VIL.
Table 7-124. PRU_ICSSG UART Switching Characteristics
see Figure 7-102
NO.
(1)
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
12
Mbps
f(baud)
Programmed baud rate
3
tw(TXD)
Pulse width, transmit data bit high or low
U(1) - 2
U(1) + 2
ns
4
tw(TXDS)
Pulse width, transmit start bit low
U(1) - 2
U(1) + 2
ns
U = UART baud time in ns = 1/actual baud rate, where the actual baud rate is defined in the UART Baud Rate Settings table of the
device TRM.
2
1
PRGi_UART0_RXD
Start
Bit
VIH
VIL
Data Bits
4
3
PRGi_UART0_TXD
Start
Bit
Data Bits
PRU_UART_TIMING_01_RCVRVIHVIL
Figure 7-102. PRU_ICSSG UART Timing Requirements and Switching Characteristics
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7.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
Table 7-125. PRU_ICSSG ECAP Timing Conditions
PARAMETER
MIN
MAX
UNIT
1
3
V/ns
2
7
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
7.10.5.16.5.1 PRU_ICSSG ECAP Timing
Table 7-126. PRU_ICSSG ECAP Timing Requirements
see Figure 7-103
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PREP1
tw(CAP)
Pulse Duration, CAP (asynchronous)
2P(1)
+2
ns
PREP2
tw(SYNCI)
Pulse Duration, SYNCI (asynchronous)
2P(1) + 2
ns
(1)
P = CORE_CLK period in ns.
PREP1
CAP
PREP2
SYNCI
Figure 7-103. PRU_ICSSG ECAP Timing
Table 7-127. PRU_ICSSG ECAP Switching Characteristics
see Figure 7-104
NO.
PREP3
PREP4
(1)
PARAMETER
DESCRIPTION
tw(APWM)
MIN
2P(1) - 2
Pulse Duration, APWM high/low
tw(SYNCO)
P(1)
Pulse Duration, SYNCO (asynchronous)
-2
MAX
UNIT
ns
ns
P = CORE_CLK period in ns.
PREP3
APWM
PREP4
SYNCO
Figure 7-104. PRU_ICSSG ECAP Switching Characteristics
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7.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem Gigabit (PRU_ICSSG) section in Processors and Accelerators chapter in the device TRM.
7.10.5.16.6.1 PRU_ICSSG MDIO Timing
Table 7-128, Table 7-129, Table 7-130, and Figure 7-105 present timing conditions, requirements, and switching
characteristics for PRU_ICSSG MDIO.
Table 7-128. PRU_ICSSG MDIO Timing Conditions
PARAMETER
MIN
MAX
UNIT
0.9
3.6
V/ns
10
470
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
Table 7-129. PRU_ICSSG MDIO Timing Requirements
see Figure 7-105
NO.
PARAMETER
MIN
MDIO1 tsu(MDIO_MDC)
Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high
MDIO2 th(MDC_MDIO)
Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high
MAX
UNIT
90
ns
0
ns
Table 7-130. PRU_ICSSG MDIO Switching Characteristics
see Figure 7-105
NO.
PARAMETER
MIN
MAX
UNIT
MDIO3 tc(MDC)
Cycle time, MDIO[x]_MDC
400
ns
MDIO4 tw(MDCH)
Pulse Duration, MDIO[x]_MDC high
160
ns
MDIO5 tw(MDCL)
Pulse Duration, MDIO[x]_MDC low
160
ns
MDIO7 td(MDC_MDIO)
Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid
-150
150
ns
MDIO3
MDIO4
MDIO5
MDIO[x]_MDC
MDIO1
MDIO2
MDIO[x]_MDIO
(input)
MDIO7
MDIO[x]_MDIO
(output)
CPSW2G_MDIO_TIMING_01
Figure 7-105. PRU_ICSSG MDIO Timing Requirements and Switching Characteristics
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7.10.5.16.6.2 PRU_ICSSG MII Timing
Note
In order to ensure the MII_G_RT I/O timing values published in the device data sheet, the
PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 1) core clock must be configured for 200 MHz,
225 MHz, or 250 MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1
register must be set to 0h (default value).
Table 7-131, Table 7-132, Figure 7-106, Table 7-133, Figure 7-107, Table 7-134, Figure 7-108, Table 7-135, and
Figure 7-109 present timing conditions, requirements, and switching characteristics for PRU_ICSSG MII.
Table 7-131. PRU_ICSSG MII Timing Conditions
PARAMETER
MIN
MAX
UNIT
0.9
3.6
V/ns
2
20
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
Table 7-132. PRU_ICSSG MII Timing Requirements – MII[x]_RX_CLK
see Figure 7-106
NO.
PARAMETER
DESCRIPTION
PMIR1 tc(RX_CLK)
Cycle time, MII[x]_RX_CLK
PMIR2 tw(RX_CLKH)
Pulse Duration, MII[x]_RX_CLK High
PMIR3 tw(RX_CLKL)
Pulse Duration, MII[x]_RX_CLK Low
MODE
MIN
MAX
UNIT
10 Mbps
399.96
400.04
ns
100 Mbps
39.996
40.004
ns
10 Mbps
140
260
ns
100 Mbps
14
26
ns
10 Mbps
140
260
ns
100 Mbps
14
26
ns
PMIR1
PMIR2
PMIR3
MII_RX_CLK
PRU_MII_RT_TIMING_04
Figure 7-106. PRU_ICSSG MII[x]_RX_CLK Timing
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Table 7-133. PRU_ICSSG MII Timing Requirements – MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER
see Figure 7-107
NO.
PMIR4
PMIR5
PARAMETER
DESCRIPTION
MODE
tsu(RXD-RX_CLK)
Setup time, MII[x]_RXD[3:0] valid before MII[x]_RX_CLK
tsu(RX_DV-RX_CLK)
Setup time, MII[x]_RX_DV valid before MII[x]_RX_CLK
tsu(RX_ER-RX_CLK)
Setup time, MII[x]_RX_ER valid before MII[x]_RX_CLK
tsu(RXD-RX_CLK)
Setup time, MII[x]_RXD[3:0] valid before MII[x]_RX_CLK
tsu(RX_DV-RX_CLK)
Setup time, MII[x]_RX_DV valid before MII[x]_RX_CLK
tsu(RX_ER-RX_CLK)
Setup time, MII[x]_RX_ER valid before MII[x]_RX_CLK
th(RX_CLK-RXD)
Hold time, MII[x]_RXD[3:0] valid after MII[x]_ RX_CLK
th(RX_CLK-RX_DV)
Hold time, MII[x]_RX_DV valid after MII[x]_RX_CLK
th(RX_CLK-RX_ER)
th(RX_CLK-RXD)
th(RX_CLK-RX_DV)
Hold time, MII[x]_RX_DV valid after MII[x]_RX_CLK
th(RX_CLK-RX_ER)
Hold time, MII[x]_RX_ER valid after MII[x]_RX_CLK
MIN
MAX
UNIT
8
ns
8
ns
8
ns
8
ns
8
ns
8
ns
8
ns
8
ns
Hold time, MII[x]_RX_ER valid after MII[x]_RX_CLK
8
ns
Hold time, MII[x]_RXD[3:0] valid after MII[x]_ RX_CLK
8
ns
8
ns
8
ns
10 Mbps
100
Mbps
10 Mbps
100
Mbps
PMIR4
PMIR5
MII_RX_CLK
MII_RXD[3:0],
MII_RX_DV, MII_RX_ER
Figure 7-107. PRU_ICSSG MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER Timing
Table 7-134. PRU_ICSSG MII Timing Requirements – MII[x]_TX_CLK
see Figure 7-108
NO.
PARAMETER
DESCRIPTION
PMIT1
tc(TX_CLK)
Cycle time, MII[x]_TX_CLK
PMIT2
tw(TX_CLKH)
Pulse Duration, MII[x]_TX_CLK High
PMIT3
tw(TX_CLKL)
Pulse Duration, MII[x]_TX_CLK Low
MODE
MIN
MAX
UNIT
10 Mbps
399.96
400.04
ns
100 Mbps
39.996
40.004
ns
10 Mbps
140
260
ns
100 Mbps
14
26
ns
10 Mbps
140
260
ns
100 Mbps
14
26
ns
PMIT1
PMIT3
PMIT2
MII_TX_CLK
Figure 7-108. PRU_ICSSG MII[x]_TX_CLK Timing
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Table 7-135. PRU_ICSSG MII Switching Characteristics – MII[x]_TXD[3:0] and MII[x]_TX_EN
see Figure 7-109
NO.
PMIT4
PARAMETER
DESCRIPTION
MODE
td(TX_CLK-TXD)
Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid
td(TX_CLK-TX_EN)
Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid
td(TX_CLK-TXD)
Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid
td(TX_CLK-TX_EN)
Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid
10 Mbps
100
Mbps
MIN
MAX
0
25
UNIT
ns
0
25
ns
0
25
ns
0
25
ns
PMIT4
MII_TX_CLK
MII_TXD[3:0], MII_TX_EN
Figure 7-109. PRU_ICSSG MII[x]_TXD[3:0], MII[x]_TX_EN Timing
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7.10.5.16.6.3 PRU_ICSSG RGMII Timing
Table 7-136, Table 7-137, Table 7-138, Figure 7-110, Table 7-139, Table 7-140, and Figure 7-111 present timing
conditions, requirements, and switching characteristics for PRU_ICSSG RGMII.
Table 7-136. PRU_ICSSG RGMII Timing Conditions
PARAMETER
MIN
MAX
UNIT
VDD = 1.8V
1.44
5
V/ns
VDD = 3.3V
2.65
5
V/ns
2
20
pF
RGMII[x]_RXC,
RGMII[x]_RD[3:0],
RGMII[x]_RX_CTL
50
ps
RGMII[x]_TXC,
RGMII[x]_TD[3:0],
RGMII[x]_TX_CTL
50
ps
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch
Delay)
224
Propagation delay mismatch across all traces
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Table 7-137. PRU_ICSSG RGMII Timing Requirements – RGMII[x]_RXC
see Figure 7-110
NO.
PARAMETER
RGMII1
RGMII2
RGMII3
tc(RXC)
DESCRIPTION
Cycle time, RGMII[x]_RXC
tw(RXCH)
Pulse duration, RGMII[x]_RXC high
tw(RXCL)
Pulse duration, RGMII[x]_RXC low
MODE
MIN
MAX
UNIT
10 Mbps
360
440
ns
100 Mbps
36
44
ns
1000 Mbps
7.2
8.8
ns
10 Mbps
160
240
ns
100 Mbps
16
24
ns
1000 Mbps
3.6
4.4
ns
10 Mbps
160
240
ns
100 Mbps
16
24
ns
1000 Mbps
3.6
4.4
ns
Table 7-138. PRU_ICSSG RGMII Timing Requirements – RGMII[x]_RD[3:0] and RGMII[x]_RX_CTL
see Figure 7-110
NO.
PARAMETER
RGMII4
tsu(RD-RXC)
MODE
Setup time, RGMII[x]_RD[3:0] valid before RXC high/low
tsu(RX_CTL-RXC)
RGMII5
DESCRIPTION
th(RXC-RD)
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC
high/low
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC
high/low
th(RXC-RX_CTL)
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC
high/low
MIN
MAX
UNIT
10 Mbps
1
ns
100 Mbps
1
ns
1000 Mbps
1
ns
10 Mbps
1
ns
100 Mbps
1
ns
1000 Mbps
1
ns
10 Mbps
1
ns
100 Mbps
1
ns
1000 Mbps
1
ns
10 Mbps
1
ns
100 Mbps
1
ns
1000 Mbps
1
ns
RGMII1
RGMII2
RGMII[x]_RXC
RGMII3
(A)
RGMII4
RGMII5
(B)
RGMII[x]_RD[3:0]
RGMII[x]_RX_CTL
A.
B.
(B)
1st Half-byte
2nd Half-byte
RXDV
RXERR
RGMII[x]_RXC must be externally delayed relative to the data and control pins.
Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of
RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.
Figure 7-110. PRU_ICSSG RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements RGMII Mode
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Table 7-139. PRU_ICSSG RGMII Switching Characteristics – RGMII[x]_TXC
see Figure 7-111
NO.
PARAMETER
RGMII6
RGMII7
RGMII8
tc(TXC)
DESCRIPTION
Cycle time, RGMII[x]_TXC
tw(TXCH)
Pulse duration, RGMII[x]_TXC high
tw(TXCL)
Pulse duration, RGMII[x]_TXC low
MODE
MIN
MAX
UNIT
10 Mbps
360
440
ns
100 Mbps
36
44
ns
1000 Mbps
7.2
8.8
ns
10 Mbps
160
240
ns
100 Mbps
16
24
ns
1000 Mbps
3.6
4.4
ns
10 Mbps
160
240
ns
100 Mbps
16
24
ns
1000 Mbps
3.6
4.4
ns
Table 7-140. PRU_ICSSG RGMII Switching Characteristics – RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL
see Figure 7-111
NO.
PARAMETER
RGMII9
tosu(TD-TXC)
Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC
high/low
tosu(TX_CTL-TXC)
RGMII10
DESCRIPTION
toh(TXC-TD)
Output setup time, RGMII[x]_TX_CTL valid to
RGMII[x]_TXC high/low
Output setup time, RGMII[x]_TD[3:0] valid after
RGMII[x]_TXC high/low
toh(TXC-TX_CTL)
Output setup time, RGMII[x]_TX_CTL valid after
RGMII[x]_TXC high/low
MODE
MIN
MAX
UNIT
10 Mbps
1.2
ns
100 Mbps
1.2
ns
1000 Mbps
1.2
ns
10 Mbps
1.2
ns
100 Mbps
1.2
ns
1000 Mbps
1.2
ns
10 Mbps
1.2
ns
100 Mbps
1.2
ns
1000 Mbps
1.2
ns
10 Mbps
1.2
ns
100 Mbps
1.2
ns
1000 Mbps
1.2
ns
RGMII6
RGMII7
RGMII8
(A)
RGMII[x]_TXC
RGMII9
(B)
1st Half-byte
RGMII[x]_TD[3:0]
2nd Half-byte
RGMII10
RGMII[x]_TX_CTL
A.
B.
(B)
TXEN
TXERR
TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of
RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.
Figure 7-111. PRU_ICSSG RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching
Characteristics - RGMII Mode
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7.10.5.17 Timers
For more details about features and additional description information on the device Timers, see the
corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 7-141. Timer Timing Conditions
PARAMETER
MIN
MAX
UNIT
0.5
5
V/ns
2
10
pF
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
Table 7-142. Timer Input Timing Requirements
see Figure 7-112
NO.
(1)
PARAMETER
DESCRIPTION
MODE
MIN
(1)
ns
(1)
ns
T1
tw(TINPH)
Pulse duration, high
CAPTURE
2 + 4P
T2
tw(TINPL)
Pulse duration, low
CAPTURE
2 + 4P
P = functional clock period in ns.
Table 7-143. Timer Output Switching Characteristics
see Figure 7-112
NO.
T3
T4
(1)
PARAMETER
tw(TOUTH)
tw(TOUTL)
DESCRIPTION
MODE
Pulse duration, high
PWM
Pulse duration, low
MIN
PWM
MAX
UNIT
(1)
ns
(1)
ns
-2 + 4P
-2 + 4P
P = functional clock period in ns.
T1
T2
TIMER_IOx (inputs)
T3
T4
TIMER_IOx (outputs)
TIMER_01
Figure 7-112. Timer Timing Requirements and Switching Characteristics
For more information, see Timers section in Peripherals chapter in the device TRM.
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7.10.5.18 UART
For more details about features and additional description information on the device Universal Asynchronous
Receiver Transmitter, see the corresponding subsections within Signal Descriptions and Detailed Description
sections.
Table 7-144. UART Timing Conditions
PARAMETER
MIN
MAX
UNIT
0.5
5
V/ns
1
30(1)
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
(1)
Output load capacitance
pF
This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the
load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall
times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore,
it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the
device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point
where the minimum data valid time of the attached device is violated.
Table 7-145. UART Timing Requirements
see Figure 7-113
NO.
(1)
(2)
PARAMETER
DESCRIPTION
1
tw(RXD)
Pulse width, receive data bit high or low
2
tw(RXDS)
Pulse width, receive start bit low
MIN
MAX
0.95U(1)
1.05U(1)
(2)
(2)
0.95U(1)
UNIT
ns
ns
(2)
U = UART baud time in ns = 1/programmed baud rate.
This value defines the data valid time, where the input voltage is required to be above VIH or below VIL.
Table 7-146. UART Switching Characteristics
see Figure 7-113
NO.
PARAMETER
DESCRIPTION
f(baud)
(1)
MIN
Programmable baud rate for Main Domain UARTs
Programmable baud rate for MCU Domain UARTs
3
tw(TXD)
Pulse width, transmit data bit high or low
U(1)
4
tw(TXDS)
Pulse width, transmit start bit low
U(1) - 2.2
- 2.2
U(1)
MAX
UNIT
12
Mbps
3.7
Mbps
+ 2.2
ns
ns
U = UART baud time in ns = 1/programmed baud rate.
2
1
UARTi_RXD
Start
Bit
VIH
VIL
Data Bits
4
3
UARTi_TXD
Start
Bit
Data Bits
UART_TIMING_01_RCVRVIHVIL
Figure 7-113. UART Timing Requirements and Switching Characteristics
228
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For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter
in the device TRM.
7.10.5.19 USB
The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the
specification for timing details.
The USB 3.1 GEN1 subsystem is compliant with the Universal Serial Bus (USB) 3.1 Specification, revision 1.0.
Refer to the specification for timing details.
For more details about features and additional description information on the device Universal Serial Bus
Subsystem (USB), see the SERDES0 Signal Descriptions and the corresponding subsection within Detailed
Description.
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7.10.6 Emulation and Debug
For more details about features and additional description information on the device Trace and JTAG interfaces,
see the corresponding subsections within Signal Descriptions and Detailed Description sections.
7.10.6.1 Trace
Table 7-147. Trace Timing Conditions
PARAMETER
MIN
MAX
UNIT
2
5
pF
VDDSHV3 = 1.8V
200
ps
VDDSHV3 =3.3V
100
ps
OUTPUT CONDITIONS
CL
Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch)
Propagation delay mismatch across all traces
Table 7-148. Trace Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
1.8V Mode
DBTR1
tc(TRC_CLK)
Cycle time, TRC_CLK
6.50
ns
DBTR2
tw(TRC_CLKH)
Pulse width, TRC_CLK high
2.50
ns
DBTR3
tw(TRC_CLKL)
Pulse width, TRC_CLK low
2.50
ns
tosu(TRC_DATAV-
Output setup time, TRC_DATA valid to TRC_CLK edge
0.81
ns
Output hold time, TRC_CLK edge to TRC_DATA invalid
DBTR4
TRC_CLK)
DBTR5
toh(TRC_CLK-TRC_DATAI)
0.81
ns
DBTR6
tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge
0.81
ns
DBTR7
toh(TRC_CLK-TRC_CTLI)
0.81
ns
Output hold time, TRC_CLK edge to TRC_CTL invalid
3.3V Mode
DBTR1
tc(TRC_CLK)
Cycle time, TRC_CLK
8.67
ns
DBTR2
tw(TRC_CLKH)
Pulse width, TRC_CLK high
3.58
ns
DBTR3
tw(TRC_CLKL)
Pulse width, TRC_CLK low
3.58
ns
DBTR4
tosu(TRC_DATAV-
Output setup time, TRC_DATA valid to TRC_CLK edge
1.08
ns
Output hold time, TRC_CLK edge to TRC_DATA invalid
TRC_CLK)
DBTR5
toh(TRC_CLK-TRC_DATAI)
1.08
ns
DBTR6
tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge
1.08
ns
DBTR7
toh(TRC_CLK-TRC_CTLI)
1.08
ns
Output hold time, TRC_CLK edge to TRC_CTL invalid
DBTR1
DBTR2
DBTR3
TRC_CLK
(Worst Case 1)
(Ideal)
(Worst Case 2)
DBTR4
DBTR5
DBTR4
DBTR5
DBTR6
DBTR7
DBTR6
DBTR7
TRC_DATA
TRC_CTL
SPRSP08_Debug_01
Figure 7-114. Trace Switching Characteristics
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7.10.6.2 JTAG
Table 7-149. JTAG Timing Conditions
PARAMETER
MIN
MAX
UNIT
0.5
2.0
V/ns
5
15
pF
83.5
1000(1)
ps
100
ps
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
Propagation delay of each trace
td(Trace Mismatch Delay)
Propagation delay mismatch across all traces
(1)
Maximum propagation delay associated with the JTAG signal traces has a significant impact on maximum TCK operating frequency. It
may be possible to increase the trace delay beyond this value, but the operating frequency of TCK must be reduced to account for the
additional trace delay.
Table 7-150. JTAG Timing Requirements
see Figure 7-115
NO.
J1
UNIT
45.5(1)
ns
ns
J2
tw(TCKH)
Pulse width minimum, TCK high
J3
tw(TCKL)
Pulse width minimum, TCK low
0.4P(2)
ns
tsu(TDI-TCK)
Input setup time minimum, TDI valid to TCK high
4
ns
tsu(TMS-TCK)
Input setup time minimum, TMS valid to TCK high
4
ns
th(TCK-TDI)
Input hold time minimum, TDI valid from TCK high
2
ns
th(TCK-TMS)
Input hold time minimum, TMS valid from TCK high
2
ns
J5
(2)
MAX
Cycle time minimum, TCK
0.4P(2)
J4
(1)
MIN
tc(TCK)
The maximum TCK operating frequency assumes the following timing requirements and switching characteristics for the attached
debugger. The operating frequency of TCK must be reduced to provide appropriate timing margin if the debugger exceeds any of these
assumptions.
• Minimum TDO setup time of 2.2 ns relative to the rising edge of TCK
• TDI and TMS output delay in the range of -16.1 ns to 14.1 ns relative to the falling edge of TCK
P = TCK cycle time in ns
Table 7-151. JTAG Switching Characteristics
see Figure 7-115
NO.
PARAMETER
MIN
J6
td(TCKL-TDOI)
Delay time minimum, TCK low to TDO invalid
J7
td(TCKL-TDOV)
Delay time maximum, TCK low to TDO valid
MAX
0
UNIT
ns
14
ns
J1
J3
J2
TCK
J4
J5
J4
J5
TDI / TMS
J6
J7
TDO
Figure 7-115. JTAG Timing Requirements and Switching Characteristics
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8 Detailed Description
8.1 Overview
AM64x is an extension of the Sitara™ industrial-grade family of heterogeneous Arm processors. AM64x is built
for industrial applications, such as motor drives and programmable logic controllers (PLCs), which require a
unique combination of real-time processing and communications with applications processing. AM64x combines
two instances of Sitara’s gigabit TSN-enabled PRU-ICSSG, up to two Arm Cortex-A53 cores, up to four CortexR5F MCUs, and a Cortex-M4F MCU domain.
AM64x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled
Memory banks, configurable SRAM partitioning, and low-latency paths to and from peripherals for rapid data
movement in and out of the SoC. This deterministic architecture allows for AM64x to handle the tight control
loops found in servo drives, while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and
absolute encoder interfaces help enable a number of different architectures found in these systems.
The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Realtime (RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term
Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux
world with the real-time world by enabling isolation between Linux applications and real-time streams through
configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and
the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently.
The PRU_ICSSG in AM64x provides the flexible industrial communications capability necessary to run gigabit
TSN, EtherCAT, PROFINET, EtherNet/IP, and various other protocols. In addition, the PRU_ICSSG also enables
additional interfaces in the SoC including sigma delta decimation filter modules and absolute encoder interfaces.
Functional safety features can be enabled through the MCU domain with an integrated Cortex-M4F and
dedicated peripheral set which can all be shared or isolated from the rest of the SoC. AM64x also supports
secure boot.
Note
For more information on features, subsystems, and architecture of superset device System on Chip
(SoC), see the device TRM.
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8.2 Processor Subsystems
8.2.1 Arm Cortex-A53 Subsystem
The A53SS module supports the following features:
• Dual Core A53 Cluster
– Full ARM v8-A Architecture Compliant
• AArch32 and AArch64 Execution States
• All exception levels EL0-3
• A32 Instruction Set (Previously ARM instruction set)
• T32 instruction set (previously Thumb instruction set)
• A64 Instruction Set
– Advanced SIMD and Floating Point Extensions (NEON)
– ARMv8 Cryptography Extensions
– ARMv8 Cryptography Extensions
– ARM GICv3 architecture
– In-order pipeline with symmetric dual-issue of most instructions
– Harvard L1 with system MMU
• 32 KB Instruction Cache
• 32 KB Data Cache
– 256KB Shared L2 Cache
– Generic Timer(s)
– Debug
• 128-Bit VBUSM Initiator Interfaces (for axi_r and axi_r channels)
• 128-Bit VBUSM Target Interface (for Accelerator Coherency Port)
• 64-bit Grey-coded system input time
• 48-bit Grey-coded debug input time
• 32-bit VBUSP Target Interface for Debug
• Integrated PBIST Controller with BISOR
For more information, see Dual-A53 MPU Subsystem section in Processors and Accelerators chapter in the
device TRM.
8.2.2 Arm Cortex-R5F Subsystem (R5FSS)
The R5FSS is a dual-core implementation of the Arm® Cortex®-R5F processor configured for dual/single-core
operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm®
CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and
various wrappers for protocol conversion and address translation for easy integration into the SoC.
Note
The Cortex®-R5F processor is a Cortex-R5 processor that includes the optional Floating Point Unit
(FPU) extension.
For more information, see Dual-R5F Subsystem (R5FSS) section in Processors and Accelerators chapter in the
device TRM.
8.2.3 Arm Cortex-M4F (M4FSS)
The M4FSS module on the AM64x device provides a safety channel (secondary channel - working in conjunction
with an external microcontroller)- or- a general purpose MCU.
The M4FSS module supports the following features:
• Cortex M4F With MPU
• ARMv7-M architecture
• Support for Nested Vectored Interrupt Controller (NVIC) with 64 inputs
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•
•
•
•
•
•
Ability to executed code from internal or external memories
192 KB of SRAM (I-Code)
64 KB of SRAM (D-Code)
External access to internal memories if allowed
Debug Support Including:
– DAP based Debug to the CPU Core
– Full Debug Features of CPU Core are enabled
– Standard ITM trace
– CTM Cross Trigger
– ETM Trace Support
Fault Detection and Correction
– SECDED ECC protection on I-CODE
– SECDED ECC protection on D-CODE
– Fault Error Interrupt Output
For more information, see Arm Cortex M4F Subsystem (M4FSS) section in Processors and Accelerators chapter
in the device TRM.
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8.3 Accelerators and Coprocessors
8.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
The PRU_ICSSG module supports the following main features:
• 3x PRUs
– General-Purpose PRU (PRU)
– Real-Time PRU(RTU_PRU)
– Transmit PRU (TX_PRU)
• 2x Ethernet MII_G_RT configurable connection to PRUs
– Up to 2x RGMII ports
– Up to 2x MII ports
– RX Classifier
• 2x Industrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functions
• 2x Industrial Ethernet 64-bit timers, each with 10 capture and 16 compare events, along with slow and fast
compensation.
• 1x MDIO
• 1x UART, with a dedicated 192-MHz clock input
• Supports up to 4 sets of 3-phased motor control, with 12 primary and 12 complimentary programmable PWM
outputs.
• Supports up to 9 safety events with optional external trip I/O per PWM set with hardware glitch filter.
• 1x Enhanced Capture Module (ECAP)
• 1x Interrupt Controller (INTC)
– 160 input events supported – 96 external, 64 internal
• Flexible power management support
• Integrated switched central resource with programmable priority
• All memories support ECC
For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem Gigabit (PRU_ICSSG) section in Processors and Accelerators chapter in the device TRM.
8.4 Other Subsystems
8.4.1 PDMA Controller
The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer
needs of peripherals, which perform data transfers using memory mapped registers accessed via a standard
non-coherent bus fabric. The PDMA module is intended to be located close to one or more peripherals which
require an external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and
supporting only statically configured Transfer Request (TR) operations.
The PDMA is only responsible for performing the data movement transactions which interact with the peripherals
themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data
stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of
the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to
a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral.
The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer
complexity at each point in the system to match the requirements of whatever is being transferred to or
from. Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO
dimensioning requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically
for sample size and FIFO depth), hardcoded address maps, and simple triggering capabilities.
Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous
transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and
employs round-robin scheduling between channels in order to share the underlying DMA hardware.
There are five PDMA modules in the device.
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For more information, see PDMA Controller section in DMA Controllers chapter in the device TRM.
8.4.2 Peripherals
8.4.2.1 ADC
The analog-to-digital converter (ADC) module is a single-channel general purpose analog-to-digital converter
with an 8-input analog multiplexer, which supports 12-bit conversion samples from an analog front end (AFE).
There is one ADC module in the device.
For more information, see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.
8.4.2.2 DCC
The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time
execution of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency.
The desired accuracy can be programed based on calculation for each application. The DCC measures the
frequency of a selectable clock source using another input clock as a reference.
The device has seven instances of DCC modules.
For more information, see Dual Clock Comparator (DCC) section in Peripherals chapter in the device TRM.
8.4.2.3 Dual Date Rate (DDR) External Memory Interface (DDRSS)
Integrated in MAIN domain: one instance of DDR Subsystem (DDRSS) is used as an interface to external RAM
devices which can be utilized for storing program or data. DDRSS provides the following main features:
•
•
•
•
•
•
•
•
•
Support of DDR4 / LPDDR4 memory types
16-bit memory bus interface with in-line ECC
System bus interface: little Endian only with 128-bit data width
Configuration bus Interface: little Endian only with 32-bit data width
Support of dual rank configuration
Support of automatic idle power saving mode when no or low activity is detected
Class of Service (CoS) - three latency classes supported
Prioritized refresh scheduling
Statistical counters for performance management
For more information, see DDR Subsystem (DDRSS) section in Peripherals chapter in the device TRM.
8.4.2.4 ECAP
This section describes the Enhanced Capture (ECAP) module for the device.
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.
8.4.2.5 EPWM
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand
and use. The EPWM unit described here addresses these requirements by allocating all needed timing and
control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided;
instead, the EPWM is built up from smaller single channel modules with separate resources and that can
operate together as required to form a system. This modular approach results in an orthogonal architecture and
provides a more transparent view of the peripheral structure, helping users to understand its operation quickly.
In the further description the letter x within a signal or module name is used to indicate a generic EPWM instance
on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the EPWM_x
instance. Thus, EPWM1A and EPWM1B belong to EPWM1, EPWM2A and EPWM2B belong to EPWM2, and so
forth.
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Additionally, the EPWM integration allows this synchronization scheme to be extended to the capture peripheral
modules (ECAP). The number of modules is device-dependent and based on target application needs. Modules
can also operate stand-alone.
The device has six instances of EPWM modules.
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in
the device TRM.
8.4.2.6 ELM
The Error Location Module (ELM) is used with the GPMC. Syndrome polynomials generated on-the-fly when
reading a NAND flash page and stored in GPMC registers are passed to the ELM. A host processor can then
correct the data block by flipping the bits to which the ELM error-location outputs point.
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction process is
delegated to the memory controller. ELM can be also used to support parallel NOR flash or NAND flash.
The General-Purpose Memory Controller (GPMC) probes data read from an external NAND flash and uses
this to compute checksum-like information, called syndrome polynomials, on a per-block basis. Each syndrome
polynomial gives a status of the read operations for a full block, including 512 bytes of data, parity bits,
and an optional spare-area data field, with a maximum block size of 1023 bytes. Computation is based on
a Bose-Chaudhuri-Hocquenghem (BCH) algorithm. The ELM extracts error addresses from these syndrome
polynomials.
For more information, see Error Location Module (ELM) section in Peripherals chapter in the device TRM.
8.4.2.7 ESM
The Error Signaling Module (ESM) aggregates safety-related events and/or errors from throughout the device
into one location. The module can signal both low and high priority interrupts to a processor to deal with a safety
event and/or manipulate an I/O error pin to signal external hardware that an error has occurred. This allows an
external controller to reset the device or keep the system in safe, known state.
For more information, see Error Signaling Module (ESM) section in Peripherals chapter in the device TRM.
8.4.2.8 GPIO
The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be
configured as either inputs or outputs. When configured as an output, user can write to an internal register
to control the state driven on the output pin. When configured as an input, user can obtain the state of the input
by reading the state of an internal register.
In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different
interrupt/event generation modes.
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.
8.4.2.9 EQEP
The Enhanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary
incremental encoder to get position, direction and speed information from a rotating machine for use in high
performance motion and position control system. The disk of an incremental encoder is patterned with a single
track of slots patterns. These slots create an alternating pattern of dark and light lines. The disk count is
defined as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second
track is added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used
to indicate an absolute position. Encoder manufacturers identify the index pulse using different terms such as
index, marker, home position and zero reference.
To derive direction information, the lines on the disk are read out by two different photo-elements that "look"
at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is realized
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with a reticle or mask that restricts the view of the photo-element to the desired part of the disk lines. As the
disk rotates, the two photo-elements generate signals that are shifted 90 degrees out of phase from each other.
These are commonly called the quadrature QEPA and QEPB signals. The clockwise direction for most encoders
is defined as the QEPA channel going positive before the QEPB channel and vice versa.
The encoder wheel typically makes one revolution for every revolution of the motor or the wheel can be at a
geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from the
QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line encoder
directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of 166.6 KHz, so
by measuring the frequency of either the QEPA or QEPB output, the processor can determine the velocity of the
motor.
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter
in the device TRM.
8.4.2.10 General-Purpose Memory Controller (GPMC)
The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with external
memory devices like:
• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
• Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash
devices
• NAND flash
• Pseudo-SRAM devices
For more information, see General-Purpose Memory Controller section in Peripherals chapter in the device
TRM.
8.4.2.11 I2C
The Inter-IC Bus (I2C) interface is implemented using the mshsi2c module. This peripheral implements the
multi-controller I2C bus, which allows serial transfer of 8-bit data to and from other I2C controller and target
devices, through a two-wire interface.
The I2C module supports the following main features:
• Compliant with Philips I2C specification version 2.1
• Supported Speeds:
– Standard mode (up to 100 K bits/s)
– Fast mode (up to 400 K bits/s)
– High-speed mode (up to 3.4 M bits/s), I2C0 and MCU_I2C0 only
• Multi-controller transmitter and target receiver mode
• Multi-controller receiver and target transmitter mode
• Combined controller transmit/receive and receive/transmit modes
• 7-bit and 10-bit device addressing modes
• Built-in 32-byte FIFO for buffered read or write
• Programmable multi-target channel (responds to 4 separates addresses)
• Programmable clock generation
• Support for asynchronous wake-up
• One interrupt line
For more information, see Inter-Integrated Circuit (I2C) Interface section in Peripherals chapter in the device
TRM.
8.4.2.12 MCAN
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed
real-time control with a high level of security. CAN has high immunity to electrical interference and the ability
to self-diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire
network, which provides for data consistency in every node of the system.
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The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN
FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices
can coexist on the same network without any conflict.
The device supports 2 MCAN modules
For more information, see Modular Controller Area Network (MCAN) section in Peripherals chapter in the device
TRM.
8.4.2.13 MCRC Controller
VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the
integrity of a memory system. A signature representing the contents of the memory is obtained when the
contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate
the signature for a set of data and then compare the calculated signature value against a pre-determined good
signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in
parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC
controller compresses each data being read through CPU read data bus.
For more information, see MCRC Controller section in Interprocessor Communication chapter in the device
TRM.
8.4.2.14 MCSPI
The MCSPI module is a multichannel transmit/receive, controller/peripheral synchronous serial bus.
There are total of seven MCSPI modules in the device.
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
8.4.2.15 MMCSD
There are two Multi-Media Card/Secure Digital (MMCSD) modules inside the device - MMCSD0 and MMCSD1.
Each MMCSD module includes one MMCSD Host Controller, where MMCSD0 is associated with MMC0 and
MMCSD1 is associated with MMC1.
The MMCSD Host Controller supports:
• One controller with 8-bit wide data bus
• One controller with 4-bit wide data bus
• Support of eMMC5.1 Host Specification (JESD84-B51)
• Support of SD Host Controller Standard Specification - SDIO 3.00
• Integrated DMA controller supporting SD Advanced DMA - ADMA2 and ADMA3
• eMMC Electrical Standard 5.1 (JESD84-B51)
• Multi-Media card features:
– Backward compatible with earlier eMMC standards
– Legacy MMC SDR: 1.8 V, 8/4/1-bit bus width, 0-25 MHz, 25/12.5/3.125 MB/s
– High Speed SDR: 1.8 V, 8/4/1-bit bus width, 0-50 MHz, 50/25/6.25 MB/s
– High Speed DDR: 1.8 V, 8/4-bit bus width, 0-50 MHz, 100/50 MB/s
– HS200 SDR: 1.8 V, 0-200 MHz, 8/4-bit bus width, 200/100 MB/s
• SD card support: SDIO, SDR12, SDR25, SDR50, DDR50
• System bus interface: CBA 4.0 VBUSM initiator port with 64-bit data width and 64-bit address, little Endian
only
• Configuration bus interface: CBA 4.0 VBUSM with 32-bit data width, 32-bit aligned accesses only, linear
incrementing addressing mode, little Endian only
For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in
the device TRM.
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8.4.2.16 OSPI
The Octal Serial Peripheral Interface (OSPI) module is a kind of Serial Peripheral Interface (SPI) module which
allows single, dual, quad or octal read and write access to external flash devices. This module has a memory
mapped register interface, which provides a direct memory interface for accessing data from external flash
devices, simplifying software requirements.
The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor
wishing to execute code directly from external flash memory), or in an indirect mode where the module is
set-up to silently perform some requested operation, signaling its completion via interrupts or status registers.
For indirect operations, data is transferred between system memory and external flash memory via an internal
SRAM which is loaded for writes and unloaded for reads by a device controller at low latency system speeds.
Interrupts or status registers are used to identify the specific times at which this SRAM should be accessed using
user programmable configuration registers.
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device
TRM.
8.4.2.17 Peripheral Component Interconnect Express (PCIe)
The PCIe subsystem supports the following main features:
• Dual mode – root port (RP) or end point (EP) modes.
• 1-lane configuration with up to 5.0GT/lane.
• 62.5/125 MHz operation on PIPE interface for Gen1/Gen2 respectively
• Constant 32-bit PIPE width for Gen1/Gen2 modes
• Maximum outbound payload size of 128 bytes
• Maximum inbound payload size of 128 bytes
• Maximum remote read request size of 4K bytes
• Maximum number of nonposted outstanding transactions: 8 on each VBUSM interface.
• Four virtual channels (4VC)
• Resizable BAR capability
• SRIS support
• Power Management
– L1 Power Management Substate support
– D1 support
– L1 Power Shutoff support
• Legacy, MSI, and MSI-X interrupt support
• 32 outbound address translation regions
• Precision time measurement (PTM)
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals
chapter in the device TRM.
8.4.2.18 Serializer/Deserializer (SerDes) PHY
Integrated in the MAIN domain is one instance of high-speed differential interface implemented with Serializer/
Deserializer (SerDes) Multi-protocol Multi-link PHY with the following main blocks:
• Single-lane SerDes PHY with common module for peripheral and Tx clocking handling
• Physical coding sub-block for data translation from/to the parallel interface, as well as data encoding/
decoding and symbol alignment
• MUX module for device interface multiplexing into a single SerDes lane (Tx and Rx)
• A wrapper for sending control and reporting status signals from the SerDes and muxes
For more information, see Serializer/Deserializer (SerDes) section in Peripherals chapter in the device TRM.
8.4.2.19 Real Time Interrupt (RTI/WWDT)
This section describes the Real Time Interrupt (RTI) modules with Windowed Watchdog Timer (WWDT)
functionality for the device.
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For more information, see Real Time Interrupt (RTI/WWDT) Module section in Peripherals chapter of the device
TRM.
8.4.2.20 Dual Mode Timer (DMTIMER)
The Dual Mode Timer (DMTIMER) module supports the following main features:
• Interrupts generated on overflow, compare, and capture events
• Free running 32-bit upward counter
• Supported operating modes:
– Compare and capture modes
– Auto-reload mode
– Start-stop mode
• Programmable divider clock source (2n with n=[0:8])
• Dedicated input trigger for capture mode, and dedicated output trigger/PWM (pulse width modulation) signal
• On the fly read/write register (while counting)
• Generate 1-ms tick with 32768-Hz functional clock
For more information, see Timers section in Peripherals chapter in the device TRM.
8.4.2.21 UART
The UART module supports the following main features:
• 16C750 compatibility
• Baud rate from 300 bps up to 12 Mbps (MCU_UART0 and MCU_UART1 limited to 3.7 Mbps)
• Auto-baud between 1200 bps and 115.2 Kbps
• Software/hardware flow control
– Programmable Xon/Xoff characters
– Programmable Auto-RTS and Auto CTS
• Programmable serial interface characteristics
– 5-, 6-, 7-, 8-bit characters
– Even, odd, mark (always 1), space (always 0), or no parity (non-parity bit frame) bit generation and
detection
– 1-, 1.5-, or 2-stop bit generation
• Optional multi-drop transmission
• Configurable time-guard feature
• False start bit detection
• Line break generation and detection
• Modem control functions on UART0 (CTS, RTS, DSR, DTR, RI, and DCD)
• Fully prioritized interrupt system controls
• Internal test and loopback capabilities
• RS-485 External transceiver auto flow control support
For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in
Peripherals chapter in the device TRM.
8.4.2.22 Universal Serial Bus Subsystem (USBSS)
The Universal Serial Bus Subsystem (USBSS) module supports the following main features:
General USB interface:
• Compliant with USB 3.1 specification
• Compliant with xHCI 1.1 specification
• Port configurable as:
– USB host:
• SuperSpeed Gen 1 (5 Gbps)
• High-speed (480 Mbps)
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• Full-speed (12 Mbps)
• Low-speed (1.5 Mbps)
– USB device/peripheral:
• High-speed (480 Mbps)
• Full-speed (12Mbps)
– USB Dual-Role device
USB Host mode features:
• 64 slots
• Up to 96 periodic simultaneous endpoints
• 256 primary streams
• MSI
• Root hub
For more information, see Universal Serial Bus (USB) Subsystem section in Peripherals chapter in the device
TRM.
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9 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Device Connection and Layout Fundamentals
9.1.1 Power Supply
9.1.1.1 Power Supply Designs
The TPS65220 or TPS65219 Power Management IC (PMIC) is recommended for an integrated power solution.
This cost and space optimized solution is designed to power the device and its principal peripherals. For the full
application note and related operational details, refer to Powering the AM64x with the TPS65220 or TPS65219
PMIC.
•
•
•
•
Full device performance entitlement of TPS6522053 as validated on TI Evaluation boards
Factory programmed configurations support power rail load steps, supply voltage accuracies and maximum
load currents with margins
Factory programmed configurations support LPDDR4 and DDR4 memory
Meets all power supply sequencing requirements, refer to Power Supply Sequencing
Note
AM64x also supports discrete power supply topologies and customized power designs to meet various
system requirements.
9.1.1.2 Power Distribution Network Implementation Guidance
The Sitara Processor Power Distribution Networks: Implementation and Analysis provides guidance for
successful implementation of the power distribution network. This includes PCB stackup guidance as well as
guidance for optimizing the selection and placement of the decoupling capacitors. TI only supports designs that
follow the board design guidelines contained in the application report.
9.1.2 External Oscillator
For more information about External Oscillators, see the Clock Specifications section.
9.1.3 JTAG, EMU, and TRACE
Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various
debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target
Connection Guide.
For recommendations on JTAG, EMU, and TRACE routing, see the Emulation and Trace Headers Technical
Reference Manual
9.1.4 Unused Pins
For more information about Unused Pins, see the Pin Connectivity Requirements section.
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9.2 Peripheral- and Interface-Specific Design Information
9.2.1 DDR Board Design and Layout Guidelines
The goal of the AM64x\AM243x DDR Board Design and Layout Guidelines is to make the DDR system
implementation straightforward for all designers. Requirements have been distilled down to a set of layout and
routing rules that allow designers to successfully implement a robust design for the topologies that TI supports.
TI only supports board designs using DDR4 or LPDDR4 memories that follow the guidelines in this document.
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9.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
The following section details the PCB routing guidelines that must be observed when connecting OSPI, QSPI, or
SPI devices.
9.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
•
•
•
•
•
The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
The signal propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to
B) must be ≤ 450 ps (~7cm as stripline or ~8cm as microstrip)
The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-1
Propagation delays and matching:
– (A to B) ≤ 450 ps
– (E to F, or F to E) = ((A to B) ± 60 ps)
A
B
R1
0 Ω*
OSPI/QSPI/SPI
Device Clock Input
OSPI[x]_CLK
OSPI[x]_LBCLKO
OSPI[x]_DQS
E
OSPI[x]_D[y],
OSPI[x]_CSn[z]
OSPI Device DQS
F
OSPI/QSPI/SPI
Device IO[y], CS#
OSPI_Board_01
* 0 Ω resistor (R1), located as close as possible to the OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.
Figure 9-1. OSPI Connectivity Schematic for No Loopback, Internal PHY Loopback, and Internal Pad
Loopback
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9.2.2.2 External Board Loopback
•
•
•
•
•
•
The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
The OSPI[x]_LBCLKO output pin must be looped back to the OSPI[x]_DQS input pin
The signal propagation delay of the OSPI[x]_LBCLKO pin to the OSPI[x]_DQS pin (C to D) must be
approximately twice the propagation delay of the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device
CLK pin (A to B)
The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-2
Propagation delays and matching:
– (C to D) = 2 x ((A to B) ± 30 ps), see the exception note below.
– (E to F, or F to E) = ((A to B) ± 60 ps)
Note
The External Board Loopback hold time requirement (defined by parameter number O16 in Table
7-101, OSPI0 Timing Requirements - PHY DDR Mode) may be larger than the hold time provided by
a typical OSPI/QSPI/SPI device. In this case, the propagation delay of OPSI[x]_LBCLKO pin to the
OSPI[x]_DQS pin (C to D) can be reduced to provide additional hold time.
A
B
R1
0 Ω*
OSPI/QSPI/SPI
Device Clock Input
OSPI[x]_CLK
C
R1
0 Ω*
OSPI[x]_LBCLKO
D
OSPI[x]_DQS
E
OSPI[x]_D[y],
OSPI[x]_CSn[z]
OSPI Device DQS
F
OSPI/QSPI/SPI
Device IO[y], CS#
OSPI_Board_02
* 0 Ω resistor (R1), located as close as possible to the OSPI[x]_CLK and OSPI[x]_LBCLKO pins, is a placeholder for fine tuning, if
needed.
Figure 9-2. OSPI Connectivity Schematic for External Board Loopback
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9.2.2.3 DQS (only available in Octal SPI devices)
•
•
•
•
•
•
The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
The DQS pin of the attached OSPI/QSPI/SPI device must be connected to OSPI[x]_DQS pin
The signal propagation delay from the attached OSPI/QSPI/SPI device DQS pin to the OSPI[x]_DQS pin (D
to C) must be approximately equal to the signal propagation delay from the OSPI[x]_CLK pin to the attached
OSPI/QSPI/SPI device CLK pin (A to B)
The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-3
Propagation delays and matching:
– (D to C) = ((A to B) ± 30 ps)
– (E to F, or F to E) = ((A to B) ± 60 ps)
A
B
R1
0 Ω*
OSPI/QSPI/SPI
Device Clock Input
OSPI[x]_CLK
OSPI[x]_LBCLKO
C
OSPI[x]_DQS
E
OSPI[x]_D[y],
OSPI[x]_CSn[z]
D
OSPI Device DQS
F
OSPI/QSPI/SPI
Device IO[y], CS#
OSPI_Board_03
* 0 Ω resistor (R1), located as close as possible to the OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed.
Figure 9-3. OSPI Connectivity Schematic for DQS
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9.2.3 USB VBUS Design Guidelines
The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as
20 V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to
be 30 V.
The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in
the Figure 9-4), which limits the voltage applied to the actual device pin (USB0_VBUS). The tolerance of these
external resistors should be equal to or less than 1%, and the leakage current of Zener diode at 5 V should be
less than 100 nA.
Device
USBn_VBUS
16.5 kΩ
±1%
3.48 kΩ
±1%
10 kΩ
±1%
VBUS signal
6.8V
(BZX84C6V8 or equivalent)
VSS
VSS
J7ES_USB_VBUS_01
Figure 9-4. USB VBUS Detect Voltage Divider / Clamp Circuit
The USB0_VBUS pin can be considered to be fail-safe because the external circuit in Figure 9-4 limits the input
current to the actual device pin in a case where VBUS is applied while the device is powered off.
9.2.4 System Power Supply Monitor Design Guidelines
The VMON_VSYS pin provides a way to monitor a system power supply. This system power supply is typically
a single pre-regulated power source for the entire system and can be connected to the VMON_VSYS pin via
and external resistor divider circuit. This system supply is monitored by comparing the external voltage divider
output voltage to an internal voltage reference, where a power fail event is triggered when the voltage applied
to VMON_VSYS drops below the internal reference voltage. The actual system power supply voltage trip point
is determined by the system designer when selecting component values used to implement the external resistor
voltage divider circuit.
When building the resistor divider circuit the designer must understand various factors which contribute to
variability in the system power supply monitor trip point. The first thing to consider is the initial accuracy of
the VMON_VSYS input threshold which has a nominal value of 0.45 V, with a variation of ±3%. Precision
1% resistors with similar thermal coefficient are recommended for implementing the resistor voltage divider.
This minimizes variability contributed by resistor value tolerances. Input leakage current associated with
VMON_VSYS must also be considered since any current flowing into the pin creates a loading error on the
voltage divider output. The VMON_VSYS input leakage current can be in the range of 10 nA to 2.5 µA when
applying 0.45 V.
Note
The resistor voltage divider shall be designed such that the output voltage never exceeds the
maximum value defined in the Recommended Operating Conditions section, during normal operating
conditions.
Figure 9-5 presents an example, where the system power supply is nominally 5 V and the maximum trigger
threshold is 5 V - 10%, or 4.5 V.
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For this example, the designer must understand which variables effect the maximum trigger threshold when
selecting resistor values. A device which has a VMON_VSYS input threshold of 0.45 V + 3% needs to be
considered when trying to design a voltage divider that doesn’t trip until the system supply drops 10%. The effect
of resistor tolerance and input leakage also needs to be considered, but the contribution to the maximum trigger
point is not obvious. When selecting component values which produce a maximum trigger voltage, the system
designer must consider a condition where the value of R1 is 1% low and the value of R2 is 1% high combined
with a condition where input leakage current for the VMON_VSYS pin is 2.5 µA. When implementing a resistor
divider where R1 = 4.81 KΩ and R2 = 40.2 KΩ, the result is a maximum trigger threshold of 4.517 V.
Once component values have been selected to satisfy the maximum trigger voltage as described above, the
system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an
output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input
leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result
is a minimum trigger threshold of 4.013 V.
This example demonstrates a system power supply voltage trip point that ranges from 4.013 V to 4.517
V. Approximately 250 mV of this range is introduced by VMON_VSYS input threshold accuracy of ±3%,
approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV
of this range is introduced by loading error when VMON_VSYS input leakage current is 2.5 µA.
The resistor values selected in this example produces approximately 100 µA of bias current through the resistor
divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above can be reduced to about
10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor divider bias
current vs loading error is something the system designer needs to consider when selecting component values.
The system designer must also consider implementing a noise filter on the voltage divider output since
VMON_VSYS has minimum hysteresis and a high-bandwidth response to transients. This can be done by
installing a capacitor across R1 as shown in Figure 9-5. However, the system designer must determine the
response time of this filter based on system supply noise and expected response to transient events.
Device
VMON_VSYS
R2
40.2 kΩ ±1%
R1
4.81 kΩ
±1%
VSYS
(System Power Supply)
C1
Value = Determined by system designer
VSS
SPRSP56_VMON_ER_MON_01
Figure 9-5. System Supply Monitor Voltage Divider Circuit
VMON_1P8_MCU and VMON_1P8_SOC pins provide a way to monitor external 1.8 V power supplies. These
pins must be connected directly to their respective power source. An internal resistor divider with software
control is implemented inside the SoC for each of these pins. Software can program each internal resistor divider
to create appropriate under voltage and over voltage interrupts.
VMON_3P3_MCU and VMON_3P3_SOC pins provide a way to monitor external 3.3 V power supplies. These
pins must be connected directly to their respective power source. An internal resistor divider with software
control is implemented inside the SoC for each of these pins. Software can program each internal resistor divider
to create appropriate under voltage and over voltage interrupts.
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9.2.5 High Speed Differential Signal Routing Guidance
The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed
differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and
spacing limits. TI supports only designs that follow the board design guidelines contained in the application note.
9.2.6 Thermal Solution Guidance
The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful
implementation of a thermal solution for system designs containing this device. This document provides
background information on common terms and methods related to thermal solutions. TI only supports designs
that follow system design guidelines contained in the application note.
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9.3 Clock Routing Guidelines
9.3.1 Oscillator Routing
When designing the printed-circuit board:
• Place all crystal circuit components as close as possible to the respective device pins.
• Route the crystal circuit traces on the outer layer of the PCB and minimize trace lengths to reduce parasitic
capacitance and minimize crosstalk from other signals.
• Place a continuous ground plane on the adjacent layer of the PCB such that it is under all crystal circuit
components and crystal circuit traces.
• Route a ground guard around the crystal circuit components to shield it from any adjacent signals routed on
the same layer as the crystal circuit traces. Insert multiple vias to stitch down the ground guard such that it
does not have any unterminated stubs.
• Route a ground guard between the MCU_OSC0_XI and MCU_OSC0_XO signals to shield the
MCU_OSC0_XI signal from the MCU_OSC0_X0 signal. Insert multiple vias to stitch down the ground guard
such that it does not have any unterminated stubs.
• Connect all crystal circuit ground connections and ground guard connections directly to the adjacent layer
ground plane, and the device VSS ground plane if they are implemented separately on different layers of the
PCB.
Note
Implementing a ground guard between the MCU_OSC0_XI and MCU_OSC0_XO signals is critical
to minimize shunt capacitance between the two signals. Routing these two signals adjacent to each
other without a ground guard between them will effectively reduce the gain of the oscillator amplifier,
which reduces its ability to start oscillation.
GND vias
Device
MCU_OSC0_XI
Cap
Crystal
Cap
GND plane
GND guard
MCU_OSC0_XO
GND vias
Figure 9-6. MCU_OSC0 PCB requirements
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10 Device and Documentation Support
10.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
embedded processor devices and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, AM6442BSFFHAALV). Texas Instruments recommends two of three possible prefix designators for
related support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the device's final electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet final
electrical specifications.
null (BLANK) Production version of the silicon die that is fully qualified and meets final electrical specifications.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
For orderable part numbers of AM64x devices in the ALV package type, see the Package Option Addendum at
the end of this document, the TI website (ti.com), or contact your TI sales representative.
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10.1.1 Standard Package Symbolization
Note
Some devices may have a cosmetic circular marking visible on the top of the device package which
results from the production test process. In addition, some devices may also show a color variation in
the package substrate which results from the substrate manufacturer. These differences are cosmetic
only with no reliability impact.
SITARA
aBBBBBBr
ZfYytPPPQ1
XXXXXXX
G1
YYY
A1 (PIN ONE INDICATOR)
O
Figure 10-1. Printed Device Reference
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10.1.2 Device Naming Convention
Table 10-1. Nomenclature Description
FIELD PARAMETER
FIELD DESCRIPTION
a
Device evolution stage
VALUE
DESCRIPTION
X
Prototype
P
Preproduction (production test flow, no reliability data)
BLANK
Production
AM6442
AM6441
BBBBBB
Base production part
number
AM6422
AM6421
See Table 5-1, Device Comparison
AM6412
AM6411
r
Device revision
Z
Device Speed Grades
f
Y
y
t
PPP
Q1
Features
(see Table 5-1)
Functional Safety
Security
Temperature (1)
Package Designator
Automotive Designator
XXXXXXX
Silicon Revision (SR) 1.0
B
SR 2.0
S
K
See Table 7-1, Speed Grade Maximum Frequency
C
All PRU_ICSSG features are enabled except for industrial
communication support. PRU_ICSSG industrial communication
interfaces include Ethernet networking (MII/RGMII, MDIO), Sigma-Delta
(SD) decimation, and three channel peripheral interface (EnDat 2.2 and
BiSS)
D
Features supported by C, plus PRU_ICSSG industrial communication is
enabled
E
Features supported by D, plus EtherCAT HW Accelerator and CAN-FD
are enabled
F
Features supported by E, plus Pre-integrated Stacks are enabled
G
Non-Functional Safety
F
Functional Safety
G
Non-Secure
H
Secure
A
–40°C to 105°C - Extended Industrial (see Section 7.4, Recommended
Operating Conditions)
I
–40°C to 125°C - Automotive (see Section 7.4, Recommended
Operation Conditions)
ALV
ALV FCBGA-N441 (17.2 mm × 17.2 mm) Package
Q1
Automotive Qualified (AEC - Q100)
BLANK
Standard
Lot Trace Code (LTC)
YYY
(1)
A
Production Code; For TI use only
O
Pin one designator
G1
ECAT—Green package designator
Applies to device max junction temperature.
Note
BLANK in the symbol or part number is collapsed so there are no gaps between characters.
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10.2 Tools and Software
The following Development Tools support development for TI's Embedded Processing platforms:
Development Tools
Code Composer Studio™ Integrated Development Environment Code Composer Studio (CCS) Integrated
Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded
Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded
applications. The tool includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through
each step of the application development flow. Familiar tools and interfaces allow users to get started faster
than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with
advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment
for embedded developers.
SysConfig-PinMux Tool The SysConfig-PinMux Tool is a software tool which provides a Graphical User
Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI
Embedded Processor devices. The tool can be used to automatically calculate the optimal pinmux configuration
to satisfy entered system requirements. The tool generates output C header/code files that can be imported
into software development kits (SDKs) and used to configure customer's software to meet custom hardware
requirements. The Cloud-based SysConfig-PinMux Tool is also available.
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized
distributor.
10.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
The following documents describe the AM64x devices.
Technical Reference Manual
AM64x/AM243x Processors Silicon Revision 1.0 Technical Reference Manual Details the integration, the
environment, the functional description, and the programming models for each peripheral and subsystem in the
AM64x family of devices.
Errata
AM64x/AM243x Processors Silicon Revision 1.0 Silicon Errata Describes the known exceptions to the
functional specifications for the device.
10.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.5 Trademarks
Sitara™, Code Composer Studio™, and TI E2E™ are trademarks of Texas Instruments.
CoreSight™ is a trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Arm® and Cortex® are registered trademarks of Arm Limited.
TrustZone® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
PCI-Express® is a registered trademark of PCI-SIG.
EtherCAT® is a registered trademark of Beckhoff Automation GmbH.
All trademarks are the property of their respective owners.
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10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 Glossary
TI Glossary
256
This glossary lists and explains terms, acronyms, and definitions.
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11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
AM6411BKCGHAALV
ACTIVE
FCBGA
ALV
441
84
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6411B
KCGHAALV
709
AM6411BSCGHAALV
ACTIVE
FCBGA
ALV
441
84
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6411B
SCGHAALV
709
AM6412BKCGHAALVR
ACTIVE
FCBGA
ALV
441
500
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6412B
KCGHAALV
709
AM6412BSCGHAALV
ACTIVE
FCBGA
ALV
441
84
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6412B
SCGHAALV
709
AM6421BSDGHAALVR
ACTIVE
FCBGA
ALV
441
500
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6421B
SDGHAALV
709
AM6421BSEFHAALVR
ACTIVE
FCBGA
ALV
441
500
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6421B
SEFHAALV
709
AM6421BSFFHAALV
ACTIVE
FCBGA
ALV
441
84
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6421B
SFFHAALV
709
AM6421BSFGHAALV
ACTIVE
FCBGA
ALV
441
84
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6421B
SFGHAALV
709
AM6422BSDFHAALVR
ACTIVE
FCBGA
ALV
441
500
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6422B
SDFHAALV
709
AM6422BSDGHAALV
ACTIVE
FCBGA
ALV
441
84
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6422B
SDGHAALV
709
AM6441BSEFHAALV
ACTIVE
FCBGA
ALV
441
84
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6441B
SEFHAALV
709
AM6441BSEGHAALVR
ACTIVE
FCBGA
ALV
441
500
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6441B
SEGHAALV
Addendum-Page 1
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
8-Nov-2023
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
709
AM6441BSFFHAALV
ACTIVE
FCBGA
ALV
441
84
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6441B
SFFHAALV
709
AM6442BSDGHAALV
ACTIVE
FCBGA
ALV
441
84
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6442B
SDGHAALV
709
AM6442BSEFHAALV
ACTIVE
FCBGA
ALV
441
84
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6442B
SEFHAALV
709
AM6442BSEGHAALV
ACTIVE
FCBGA
ALV
441
84
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6442B
SEGHAALV
709
AM6442BSFFHAALV
ACTIVE
FCBGA
ALV
441
84
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6442B
SFFHAALV
709
AM6442BSFGHAALV
ACTIVE
FCBGA
ALV
441
84
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6442B
SFGHAALV
709
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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