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bq24079QW-Q1
SLUSCM2B – OCTOBER 2017 – REVISED NOVEMBER 2018
bq24079QW-Q1 Automotive Qualified 4.1-V Battery Voltage Li-Ion Battery Charger with
NTC Monitoring and Power Path
1 Features
3 Description
•
•
The bq24079QW-Q1 is an integrated Li-ion linear
charger and system power-path management device
targeted at space-constraint automotive applications
such as telematics/eCall. The device can operate
from 4.35 V to 6.4 V and support charge currents up
to 1.5 A. The input voltage range with input
overvoltage
protection
supports
unregulated
adapters. The USB input current limit accuracy and
start up sequence allow the bq24079QW-Q1 to meet
the USB-IF inrush current specification. Additionally,
the input dynamic power management (VIN-DPM)
prevents the system load from crashing incorrectly
configured USB sources.
•
•
•
•
•
•
•
•
Device Information(1)
PART NUMBER
PACKAGE
bq24079QW-Q1
BODY SIZE (NOM)
VQFN (16)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
1kW
1kW
IN
IN
9
•
CHG
•
•
•
The bq24079QW-Q1 features dynamic power-path
management (DPPM) that powers the system while
simultaneously and independently charging the
battery. The DPPM circuit reduces the charge current
when the input current limit causes the system output
to fall to the DPPM threshold; thus, supplying the
system load at all times while monitoring the charge
current separately. This feature along with the 4.1-V
battery regulation voltage helps to extend battery life
time by reducing the number of charge and discharge
cycles on the battery, allowing for proper charge
termination and enabling the system to run with a
defective or absent battery pack.
7
•
Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: -40°C to +125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4A
Fully Compliant USB Charger
– Selectable 100-mA and 500-mA Maximum
Input Current
– 100-mA Maximum Current Limit Ensures
Compliance to USB-IF Standard
– Input Based Dynamic Power Management
(VIN-DPM) for Protection Against Poor USB
Sources
28-V Input Rating with Overvoltage Protection
4.1-V Battery Regulation Voltage
Integrated Dynamic Power-Path Management
(DPPM) Function Simultaneously and
Independently Powers the System and Charges
the Battery
Supports up to 1.5-A Charge Current with Current
Monitoring Output (ISET)
Programmable Input Current Limit up to 1.5 A for
Wall Adapters
Battery Disconnect Function with SYSOFF Input
Programmable Pre-Charge and Fast-Charge
Safety Timers
Reverse Current, Short-Circuit, and Thermal
Protection
NTC Thermistor Input
Proprietary Start Up Sequence Limits Inrush
Current
Status Indication – Charging/Done, Power Good
Small 3 mm × 3 mm 16 Lead VQFN Package with
Wettable Flank
PGOOD
1
13
OUT
10
11
8
EN 2
5
BAT
2
3
1mF
4.7mF
2 Applications
VSS
bq24079QW-Q1
SYSOFF
4.7mF
ISET
ILM
TS
1
TEMP
16
12
4
EN1
PACK+
TMR
15
CE
System
ON/OFF
Control
6
Automotive Telematics
Fleet Management
Display Key/Smart Key
14
•
•
•
SYSTEM
1.18kW
1.13kW
PACK-
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24079QW-Q1
SLUSCM2B – OCTOBER 2017 – REVISED NOVEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
4
5
8.1 Absolute Maximum Ratings .................................... 5
8.2 ESD Ratings.............................................................. 5
8.3 Recommended Operating Conditions...................... 5
8.4 Thermal Information .................................................. 6
8.5 Electrical Characteristics.......................................... 6
8.6 Typical Characteristics ............................................ 11
9
Detailed Description ............................................ 14
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
15
16
27
10 Application and Implementation........................ 28
10.1 Application Information.......................................... 28
10.2 Typical Application – bq24079QW-Q1 Charger
Design Example....................................................... 28
11 Power Supply Recommendations ..................... 34
12 Layout................................................................... 35
12.1 Layout Guidelines ................................................. 35
12.2 Layout Example .................................................... 36
12.3 Thermal Package .................................................. 37
13 Device and Documentation Support ................. 38
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Device Support ....................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
38
38
38
14 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2017) to Revision B
Page
•
Changed HBM ESD Classification Level from H1C to 2 in Features ..................................................................................... 1
•
Changed ESD Ratings HBM to All pins value ±2000 V ........................................................................................................ 5
Changes from Original (October 2017) to Revision A
Page
•
Changed Title ........................................................................................................................................................................ 1
•
Changed Standby current into IN pin MAX from 50 to 55 µA ............................................................................................... 6
2
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SLUSCM2B – OCTOBER 2017 – REVISED NOVEMBER 2018
5 Description (continued)
Additionally, the regulated system input enables instant system turn-on when plugged in even with a totally
discharged battery. The power-path management architecture also permits the battery to supplement the system
current requirements when the adapter cannot deliver the peak system currents, enabling the use of a smaller
adapter.
The battery is charged in three phases: conditioning, constant current, and constant voltage. In all charge
phases, an internal control loop monitors the IC junction temperature and reduces the charge current if the
internal temperature threshold is exceeded. The charger power stage and charge current sense functions are
fully integrated. The charger function has high accuracy current and voltage regulation loops, charge status
display, and charge termination. The input current limit and charge current are programmable using external
resistors.
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3
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SLUSCM2B – OCTOBER 2017 – REVISED NOVEMBER 2018
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6 Device Comparison Table
DEVICE
VOVP
VBAT(REG)
VOUT(REG)
VDPPM
OPTIONAL
FUNCTION
bq24079QW-Q1
6.6 V
4.1 V
5.5 V
4.3 V
SYSOFF
7 Pin Configuration and Functions
ISET
SYSOFF
TMR
IN
15
14
13
8
4
VSS
CE
Pad
7
3
PGOOD
BAT
Thermal
6
2
EN1
BAT
5
1
EN2
TS
16
RGT Package
16 Pin VQFN
Top View
12
ILIM
11
OUT
10
OUT
9
CHG
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
1
I
External NTC Thermistor Input. Connect the TS input to the NTC thermistor in the battery pack. TS monitors a 10kΩ NTC thermistor. For applications that do not utilize the TS function, connect a 10-kΩ fixed resistor from TS to
VSS to maintain a valid voltage level on TS. Do not leave TS pin floating.
BAT
2, 3
I/O
CE
4
I
EN2
5
I
EN1
6
I
PGOOD
7
O
Open-drain Power Good Status Indication Output. PGOOD pulls to VSS when a valid input source is detected.
PGOOD is high-impedance when the input power is not within specified limits. Connect PGOOD to the desired
logic voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication.
VSS
8
–
Ground. Connect to the thermal pad and to the ground rail of the circuit.
CHG
9
O
Open-Drain Charging Status Indication Output. CHG pulls to VSS when the battery is charging. CHG is high
impedance when charging is complete and when charger is disabled. Connect CHG to the desired logic voltage
rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication.
OUT
10, 11
O
System Supply Output. OUT provides a regulated output when the input is below the OVP threshold and above
the regulation voltage. When the input is out of the operation range, OUT is connected to VBAT except when
SYSOFF is high. Connect OUT to the system load. Bypass OUT to VSS with a 4.7-μF to 47-μF ceramic capacitor.
ILIM
12
I
Adjustable Current Limit Programming Input. Connect a 1100-Ω to 8-kΩ resistor from ILIM to VSS to program the
maximum input current (EN2 = 1, EN1 = 0). The input current includes the system load and the battery charge
current. Leaving ILIM unconnected disables all charging.
IN
13
I
Input Power Connection. Connect IN to the external DC supply (AC adapter or USB port). The input operating
range is 4.35 V to 6.6 V. The input can accept voltages up to 26 V without damage but operation is suspended.
Connect bypass capacitor 1 μF to 10 μF to VSS.
NAME
TS
4
NO.
Charger Power Stage Output and Battery Voltage Sense Input. Connect BAT to the positive terminal of the
battery. Bypass BAT to VSS with a 4.7-μF to 47-μF ceramic capacitor.
Charge Enable Active-Low Input. Connect CE to a high logic level to suspend charging. When CE is high, OUT is
active and battery supplement mode is still available. Connect CE to a low logic level to enable the battery
charger. CE is internally pulled down with ~285 kΩ. Do not leave CE unconnected to ensure proper operation.
Input Current Limit Configuration Inputs. Use EN1 and EN2 control the maximum input current and enable USB
compliance. See EN1/EN2 Settings table for the description of the operation states. EN1 and EN2 are internally
pulled down with ≉285 kΩ. Do not leave EN1 or EN2 unconnected to ensure proper operation.
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SLUSCM2B – OCTOBER 2017 – REVISED NOVEMBER 2018
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
TMR
14
I
Timer Programming Input. TMR controls the pre-charge and fast-charge safety timers. Connect TMR to VSS to
disable all safety timers. Connect a 18-kΩ to 72-kΩ resistor between TMR and VSS to program the timers a
desired length. Leave TMR unconnected to set the timers to the default values.
SYSOFF
15
I
System Enable Input. Connect SYSOFF high to turn off the FET connecting the battery to the system output.
When an adapter is connected, charging is also disabled. Connect SYSOFF low for normal operation. SYSOFF is
internally pulled up to VBAT through a large resistor (~5 MΩ). Do not leave SYSOFF unconnected to ensure proper
operation.
ISET
16
I/O
Fast Charge Current Programming Input. Connect a 590-Ω to 8.9-kΩ resistor from ISET to VSS to program the
fast charge current level. Charging is disabled if ISET is left unconnected. While charging, the voltage at ISET
reflects the actual charging current and can be used to monitor charge current. See the Charge Current Translator
section for more details.
Thermal
Pad
–
–
There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The
thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not use the
thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all times.
8 Specifications
Absolute Maximum Ratings (1)
8.1
over the -40°C to 125°C operating free-air temperature range (unless otherwise noted)
Input voltage, VI
Input current, II
MIN
MAX
UNIT
IN (with respect to VSS)
–0.3
28
V
BAT (with respect to VSS)
–0.3
5
V
OUT, EN1, EN2, CE, TS, ISET, PGOOD, CHG, ILIM, TMR,
SYSOFF
–0.3
7
V
1.6
A
5
A
BAT (Discharge mode)
5
A
BAT (Charging mode)
1.5 (2)
A
15
mA
IN
OUT
Output current (Continuous), IO
Output sink current
CHG, PGOOD
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
The IC operational charging life is reduced to 20,000 hours, when charging at 1.5A and 125°C. The thermal regulation feature reduces
charge current if the IC’s junction temperature reaches 125°C; thus without a good thermal design the maximum programmed charge
current may not be reached.
8.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge (1)
Human-body model (HBM), per AEC
Q100-002 (2)
All pins
Charged-device model (CDM), per AEC Q100-011
(1)
(2)
8.3
VI
UNIT
±2000
V
±500
Electrostatic discharge (ESD) measures device sensitivity and immunity to damage caused by assembly line electrostatic discharges.
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Recommended Operating Conditions
MIN
MAX
IN voltage range
4.35
26
UNIT
V
IN operating voltage range
4.35
6.4
V
IIN
Input current, IN pin
1.5
A
IOUT
Current, OUT pin
4.5
A
IBAT
Current, BAT pin (Discharging)
4.5
A
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Recommended Operating Conditions (continued)
MIN
ICHG
Current, BAT pin (Charging)
RILIM
Maximum input current programming resistor
RISET
Fast-charge current programming resistor
(2)
RITERM
Termination current programming resistor
RTMR
Timer programming resistor
(1)
(2)
MAX
UNIT
1.5 (1)
A
1100
8000
Ω
590
8900
Ω
0
15
kΩ
18
72
kΩ
The IC operational charging life is reduced to 20,000 hours, when charging at 1.5A and 125°C. The thermal regulation feature reduces
charge current if the IC’s junction temperature reaches 125°C; thus without a good thermal design the maximum programmed charge
current may not be reached.
Use a 1% tolerance resistor for RISET to avoid issues with the RISET short test when using the maximum charge current setting.
8.4 Thermal Information
bq24079QW-Q1
THERMAL METRIC (1)
RGT (VQFN)
UNIT
16 PIN
RθJA
Junction-to-ambient thermal resistance
43.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
46.3
°C/W
RθJB
Junction-to-board thermal resistance
17.6
°C/W
ψJT
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
17.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5
Electrical Characteristics
Over ambient temperature range (–40°C ≤ TA ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
3.3
MAX
UNIT
INPUT
UVLO
Undervoltage lock-out
VIN: 0 V → 4 V
3.2
Vhys
Hysteresis on UVLO
VIN: 4 V → 0 V
200
VIN(DT)
Input power detection threshold
Input power detected when VIN > VBAT + VIN(DT)
VBAT = 3.6 V, VIN: 3.5 V → 4 V
50
Vhys
Hysteresis on VIN(DT)
VBAT = 3.6 V, VIN: 4 V → 3.5 V
20
tDGL(PGOOD) Deglitch time, input power detected status
Time measured from VIN: 0 V → 5 V with 1-μs
rise time to PGOOD = LO
VOVP
Input overvoltage protection threshold
VIN: 5 V → 7 V
Vhys
Hysteresis on OVP
VIN: 7 V → 5V
tDGL(OVP)
Input overvoltage blanking time (OVP fault
deglitch)
tREC
Input overvoltage recovery time
80
3.4
V
300
mV
135
mV
mV
1.2
6.4
6.6
ms
6.8
V
110
mV
50
μs
1.2
ms
VIN > UVLO and VIN > VBAT + VIN(DT)
1.3
mA
VIN > UVLO and VIN > VBAT + VIN(DT)
520
mV
CE = LO or HI, Input power not detected,
No load on OUT pin, TA ≤ 125°C
4.4
Time measured from VIN: 11 V → 5 V with 1-μs
fall time to PGOOD = LO
ILIM, ISET SHORT CIRCUIT DETECTION (CHECKED DURING STARTUP)
ISC
Current source
VSC
QUIESCENT CURRENT
IBAT(PDWN)
Sleep current into BAT pin
IIN
Standby current into IN pin
ICC
Active supply current, IN pin
6
13
EN1 = HI, EN2 = HI, VIN = 6 V, TA ≤ 125°C
38.8
55
EN1 = HI, EN2 = HI, VIN = 10 V, TA ≤ 125°C
90.2
200
CE = LO, VIN = 6 V, No load on OUT pin,
VBAT > VBAT(REG), (EN1, EN2) ≠ (HI, HI)
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1.5
μA
μA
mA
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SLUSCM2B – OCTOBER 2017 – REVISED NOVEMBER 2018
Electrical Characteristics (continued)
Over ambient temperature range (–40°C ≤ TA ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
300
475
mV
50
100
mV
V
POWER PATH
VDO(IN-OUT)
VDO(BATOUT)
VO(REG)
IINmax
VIN – VOUT
VIN = 4.3 V, IIN = 1 A, VBAT = 4.1 V
VBAT – VOUT
IOUT = 1 A, VIN = 0 V, VBAT > 3 V
OUT pin voltage regulation
VIN > VOUT + VDO(IN-OUT)
5.4
5.5
5.65
EN1 = LO, EN2 = LO
90
95
101
EN1 = HI, EN2 = LO
440
475
500
Maximum input current
EN2 = HI, EN1 = LO
KILIM/RILIM
mA
A
ILIM = 500 mA to 1.5 A
1500
1610
1720
ILIM = 200 mA to 500 mA
1300
1525
1770
KILIM
Maximum input current factor
AΩ
IINmax
Programmable input current limit range
EN2 = HI, EN1 = LO, RILIM = 8 kΩ to 1.1 kΩ
200
VIN-DPM
Input voltage threshold when input current is
reduced
EN2 = LO, EN1 = X
4.35
VDPPM
Output voltage threshold when charging
current is reduced
4.2
VBSUP1
Enter battery supplement mode
VBAT = 3.6 V, RILIM = 1.5 kΩ, RLOAD = 10 Ω → 2 Ω
VOUT ≤
VBAT
–40mV
V
VBSUP2
Exit battery supplement mode
VBAT = 3.6 V, RILIM = 1.5 kΩ, RLOAD = 2 Ω → 10 Ω
VOUT ≥
VBAT–20m
V
V
VO(SC1)
Output short-circuit detection threshold,
power-on
VIN > VUVLO and VIN > VBAT + VIN(DT)
0.8
0.9
1
VO(SC2)
Output short-circuit detection threshold,
supplement mode VBAT – VOUT > VO(SC2)
indicates short-circuit
VIN > VUVLO and VIN > VBAT + VIN(DT)
200
250
300
tDGL(SC2)
Deglitch time, supplement mode short circuit
tREC(SC2)
Recovery time, supplement mode short
circuit
1500
mA
4.5
4.63
V
4.3
4.4
V
V
mV
250
μs
60
ms
BATTERY CHARGER
IBAT
Source current for BAT pin short-circuit
detection
VBAT = 1.5 V
VBAT(SC)
BAT pin short-circuit detection threshold
VBAT rising
VBAT(REG)
Battery charge voltage
VLOWV
Pre-charge to fast-charge transition threshold VIN > VUVLO and VIN > VBAT + VIN(DT)
tDGL1(LOWV)
Deglitch time on pre-charge to fast-charge
transition
25
ms
tDGL2(LOWV)
Deglitch time on fast-charge to pre-charge
transition
25
ms
Battery fast charge current range
VBAT(REG) > VBAT > VLOWV, VIN = 5 V, CE = LO,
EN1 = LO, EN2 = HI
Battery fast charge current
CE = LO, EN1= LO, EN2 = HI,
VBAT > VLOWV, VIN = 5 V, IINmax > ICHG, No load on
OUT pin, Thermal loop and DPPM loop not active
ICHG
KISET
Fast charge current factor
IPRECHG
Pre-charge current
KPRECHG
Pre-charge current factor
ITERM
Termination comparator detection threshold
(internally set)
tDGL(TERM)
Deglitch time, termination detected
VRCH
Recharge detection threshold
tDGL(RCH)
Deglitch time, recharge threshold detected
4
7.5
11
mA
1.6
1.8
2
V
4.059
4.100
4.141
V
2.9
3
3.1
V
100
1500
KISET/RISET
797
890
A
975
AΩ
118
AΩ
KPRECHG/RISET
55
CE = LO, (EN1, EN2) ≠ (LO, LO),
VBAT > VRCH, t < tMAXCH, VIN = 5 V, DPPM loop and
thermal loop not active
CE = LO, (EN1, EN2) = (LO, LO),
VBAT > VRCH, t < tMAXCH, VIN = 5 V, DPPM loop and
thermal loop not active
0.09×ICH
G
88
0.1×ICHG
A
0.11×ICH
G
A
0.027×IC
HG
0.033×ICHG
0.040×IC
HG
25
VIN > VUVLO and VIN > VBAT + VIN(DT)
50
100
ms
145
62.5
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mV
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Electrical Characteristics (continued)
Over ambient temperature range (–40°C ≤ TA ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tDGL(NO-IN)
Delay time, input power loss to OUT LDO
turn-off
VBAT = 3.6 V. Time measured from
VIN: 5 V → 3 V, 1-μs fall time
IBAT(DET)
Sink current for battery detection
VBAT = 2.5 V
tDET
Battery detection timer
BAT high or low
MIN
TYP
MAX
20
5
7.5
UNIT
ms
10
250
mA
ms
BATTERY CHARGING TIMERS
tPRECHG
Pre-charge safety timer value
TMR = floating
1440
1800
2160
s
tMAXCHG
Charge safety timer value
TMR = floating
14400
18000
21600
s
tPRECHG
Pre-charge safety timer value
18 kΩ < RTMR < 72 kΩ
RTMR × KTMR
tMAXCHG
Charge safety timer value
18 kΩ < RTMR < 72 kΩ
10×R TMR ×KTMR
KTMR
Timer factor
36
48
s
s
60
s/kΩ
BATTERY-PACK NTC MONITOR (1)
INTC
NTC bias current
VIN > UVLO and VIN > VBAT + VIN(DT)
VHOT
High temperature trip point
Battery charging, VTS Falling
VHYS(HOT)
Hysteresis on high trip point
Battery charging, VTS Rising from VHOT
VCOLD
Low temperature trip point
Battery charging, VTS Rising
VHYS(COLD)
Hysteresis on low trip point
Battery charging, VTS Falling from VCOLD
tDGL(TS)
Deglitch time, pack temperature fault
detection
TS fault detected to charger disable
71
75
80
μA
270
300
330
mV
2000
2100
30
mV
2200
mV
300
mV
50
ms
125
°C
155
°C
20
°C
THERMAL REGULATION
TJ(REG)
Temperature regulation limit
TJ(OFF)
Thermal shutdown temperature
TJ(OFF-HYS)
Thermal shutdown hysteresis
TJ Rising
LOGIC LEVELS ON EN1, EN2, CE, SYSOFF
VIL
Logic LOW input voltage
0
0.4
V
VIH
Logic HIGH input voltage
1.4
6
V
IIL
Input sink current
VIL= 0 V
1
μA
IIH
Input source current
VIH= 1.4 V
10
μA
ISINK = 5 mA
0.4
V
LOGIC LEVELS ON PGOOD, CHG
VOL
(1)
8
Output LOW voltage
These numbers set trip points of 0°C and 50°C while charging, with 3°C hysteresis on the trip points, with a Vishay Type 2 curve NTC
with an R25 of 10 kΩ.
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VOVP
VOVP - Vhys(OVP)
VIN
Typical Input Voltage
Operating Range
t < tDGL(OVP)
VBAT + VIN(DT)
VBAT + VIN(DT) - Vhys(INDT)
UVLO
UVLO - Vhys(UVLO)
PGOOD
tDGL(PGOOD)
tDGL(OVP)
tDGL(NO-IN)
tDGL(PGOOD)
Figure 1. Power-Up, Power-Down, Power Good Indication
tDGL1(LOWV)
VBAT
VLOWV
t < tDGL1(LOWV)
tDGL1(LOWV)
tDGL2(LOWV)
ICHG
Fast-Charge
Fast-Charge
IPRE-CHG
t < tDGL2(LOWV)
Pre-Charge
Pre-Charge
Figure 2. Pre- to Fast-Charge, Fast- to Pre-Charge Transition – tDGL1(LOWV), tDGL2(LOWV)
VBAT
VRCH
Re-Charge
t < tDGL(RCH)
tDGL(RCH)
Figure 3. Recharge – tDGL(RCH)
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Turn
Q2 OFF
Force
Q2 ON
tREC(SC2)
Turn
Q2 OFF
tREC(SC2)
Force
Q2 ON
VBAT - VOUT
Recover
VO(SC2)
t < tDGL(SC2)
tDGL(SC2)
tDGL(SC2)
t < tDGL(SC2)
Figure 4. OUT Short-Circuit – Supplement Mode
VCOLD
VCOLD - Vhys(COLD)
t < tDGL(TS)
Suspend
Charging
tDGL(TS)
VTS
Resume
Charging
VHOT - Vhys(HOT)
VHOT
Figure 5. Battery Pack Temperature Sensing – TS Pin. Battery Temperature Increasing
10
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8.6 Typical Characteristics
VIN = 6 V, EN1 = 1, EN2 = 0, TA = 25°C, unless otherwise noted.
0.7
500
0.6
Dropout Voltage (mV)
600
IBAT (mA)
400
300
200
100
0
0.5
0.4
0.3
0.2
0.1
0
120
125
130
135
Temperature (oC)
140
145
0
25
50
75
Junction Temperature (°C)
125
100
IL = 1 A
Figure 7. Dropout Voltage vs Temperature
Figure 6. Thermal Regulation
5.75
120
5.70
100
VBAT = 3 V
80
Output Voltage (V)
Dropout Voltage (mV)
5.65
60
VBAT = 3.9 V
40
5.60
5.55
5.50
5.45
5.40
5.35
20
5.30
5.25
0
0
0
25
50
75
Junction Temperature (°C)
100
125
IL = 1 A, No Input Supply
50
75
Junction Temperature (°C)
100
125
VIN = 6 V, IL = 1 A
Figure 8. Dropout Voltage vs Temperature
Figure 9. Output Regulation Voltage vs Temperature bq24079QW-Q1
6.70
1.05
1.03
6.65
VI Rising
Fast Charge Current (A)
Output Voltage Threshold (V)
25
6.60
6.55
VI Falling
6.50
1.01
0.99
0.97
6.45
0
0.95
25
50
75
Junction Temperature (°C)
100
125
6.6 V
3
3.2
3.4
3.6
3.8
Battery Voltage (V)
4
4.2
RISET = 900 Ω
Figure 10. Overvoltage Protection Threshold vs
Temperature
Figure 11. Fastcharge Current vs Battery Voltage
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Typical Characteristics (continued)
310
31.5
305
31
Precharge Current (mA)
Fast Charge Current (mA)
VIN = 6 V, EN1 = 1, EN2 = 0, TA = 25°C, unless otherwise noted.
300
295
290
285
30.5
30
29.5
29
280
3
3.2
3.4
3.6
3.8
Battery Voltage (V)
4
28.5
4.2
2
RISET = 3 kΩ
Dropout Voltage (VIN-VOUT)
VBAT - Regulation Voltage (V)
4.13
4.12
4.11
4.1
4.09
4.08
4.07
4.06
0
20
40
60
80
100
TJ - Junction Temperature (qC)
120
140
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-40
Figure 14. BAT Regulation Voltage vs Temperature
3
0
20
40
60
80
100
TJ - Junction Temperature (qC)
120
140
D002
Figure 15. Dropout Voltage vs Temperature
5.75
110
5.7
100
5.65
VO - Output Voltage (V)
Dropout Voltage (VBAT-VOUT)
-20
D001
120
90
80
70
60
50
40
30
5.6
5.55
5.5
5.45
5.4
5.35
20
5.3
10
0
-40
2.8
Figure 13. Precharge Current vs Battery Voltage
4.14
-20
2.4
2.6
Battery Voltage (V)
RISET = 3 kΩ
Figure 12. Fastcharge Current vs Battery Voltage
4.05
-40
2.2
-20
0
20
40
60
80
100
TJ - Junction Temperature (qC)
120
140
5.25
-40
-20
D003
0
20
40
60
80
100
TJ - Junction Temperature (qC)
120
140
D004
IL = 1 A
Figure 16. Dropout Voltage vs Temperature
12
Figure 17. Output Regulation Voltage vs Temperature
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Typical Characteristics (continued)
VIN = 6 V, EN1 = 1, EN2 = 0, TA = 25°C, unless otherwise noted.
6.7
VI Rising
VI Falling
VI - Input Voltage (V)
6.65
6.6
6.55
6.5
6.45
6.4
-40
-20
0
20
40
60
80
TJ - Junction Temperature (qC)
100
120
D005
Figure 18. Input Voltage vs Temperature
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9 Detailed Description
9.1 Overview
The bq24079QW-Q1 device is an integrated Li-Ion linear charger and system power path management device
targeted at space-limited portable applications. The device powers the system while simultaneously and
independently charging the battery. This feature reduces the number of charge and discharge cycles on the
battery, allows for proper charge termination and enables the system to run with a defective or absent battery
pack. It also allows instant system turn-on even with a totally discharged battery. The input power source for
charging the battery and running the system can be an AC adapter or a USB port. The device features Dynamic
Power Path Management (DPPM), which shares the source current between the system and battery charging,
and automatically reduces the charging current if the system load increases. When charging from a USB port,
the input dynamic power management (VIN-DPM) circuit reduces the input current if the input voltage falls below
a threshold, preventing the USB port from crashing. The power-path architecture also permits the battery to
supplement the system current requirements when the adapter cannot deliver the peak system currents.
14
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9.2 Functional Block Diagram
250mV
VO(SC1)
VBAT
OUT-SC1
t DGL(SC2)
OUT-SC2
Q1
IN
OUT
EN2
Short Detect
225mV
Precharge
VIN-LOW
USB100
USB500
ISET
2.25V
Fastcharge
TJ
ILIM
VREF- ILIM
USB-susp
TJ(REG)
Short Detect
V DPPM
V O(REG)
V OUT
EN2
EN1
Q2
V BAT (REG)
BAT
VBAT
VOUT
CHARGEPUMP
I BIAS- ITERM
SYSOFF
40mV
Supplement
VLOWV
225mV
VRCH
~3V
VBAT(SC)
tDGL(RCH)
tDGL2(LOWV)
VIN
tDGL1(LOWV)
tDGL(TERM)
I TERM-floating
BAT-SC
VBAT + VIN-DT
tDGL(NO-IN)
t DGL(PGOOD)
V UVLO
INTC
V HOT
Charge Control
TS
t DGL(TS)
VCOLD
V OVP
tBLK(OVP)
VDIS(TS)
EN1
EN2
USB Suspend
CE
CHG
Halt timers
VIPRECHG
VICHG
Dynamically
Controlled
Oscillator
Reset timers
PGOOD
V ISET
Fast-Charge
Timer
Timer fault
TMR
Pre-Charge
Timer
~100mV
Timers disabled
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9.3 Feature Description
9.3.1 Undervoltage Lockout (UVLO)
The bq24079QW-Q1 remains in power down mode when the input voltage at the IN pin is below the
undervoltage threshold (UVLO).
During the power down mode, the host commands at the control inputs (CE, EN1 and EN2) are ignored. The Q1
FET connected between IN and OUT pins is off, and the status outputs CHG and PGOOD are high impedance.
The Q2 FET that connects BAT to OUT is ON. (If SYSOFF is high, Q2 is off). During power down mode, the
VOUT(SC2) circuitry is active and monitors for overload conditions on OUT.
9.3.2 Power On
When VIN exceeds the UVLO threshold, the bq24079QW-Q1 powers up. While VIN is below VBAT + VIN(DT), the
host commands at the control inputs (CE, EN1 and EN2) are ignored. The Q1 FET connected between IN and
OUT pins is off, and the status outputs CHG and PGOOD are high impedance. The Q2 FET that connects BAT
to OUT is ON. (If SYSOFF is high, Q2 is off). During this mode, the VOUT(SC2) circuitry is active and monitors for
overload conditions on OUT.
Once VIN rises above VBAT + VIN(DT), PGOOD is driven low to indicate the valid power status and the CE, EN1,
and EN2 inputs are read. The device enters standby mode if (EN1 = EN2 = HI) or if an input overvoltage
condition occurs. In standby mode, Q1 is OFF and Q2 is ON so OUT is connected to the battery input. (If
SYSOFF is high, FET Q2 is off). During this mode, the VOUT(SC2) circuitry is active and monitors for overload
conditions on OUT.
When the input voltage at IN is within the valid range: VIN > UVLO AND VIN > VBAT + VIN(DT) AND VIN < VOVP, and
the EN1 and EN2 pins indicate that the USB suspend mode is not enabled [(EN1, EN2) ≠ (HI, HI)], all internal
timers and other circuit blocks are activated. The device then checks for short-circuits at the ISET and ILIM pins.
If no short conditions exists, the device switches on the input FET Q1 with a 100mA current limit to checks for a
short circuit at OUT. When VOUT is above VO(SC1), the FET Q1 switches to the current limit threshold set by EN1,
EN2 and RILIM and the device enters into the normal operation. During normal operation, the system is powered
by the input source (Q1 is regulating), and the device continuously monitors the status of CE, EN1 and EN2 as
well as the input voltage conditions.
16
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Feature Description (continued)
PGOOD = Hi-Z
CHG = Hi-Z
BATTFET ON
UVLO VOVP for a period
long than tDGL(OVP). When in OVP, the system output (OUT) is connected to the battery and PGOOD is high
impedance. Once the OVP condition is removed, a new power on sequence starts (See the Power On section).
The safety timers are reset and a new charge cycle will be indicated by the CHG output.
9.3.4 Dynamic Power-path Management
The bq24079QW-Q1 features an OUT output that powers the external load connected to the battery. This output
is active whenever a source is connected to IN or BAT when SYSOFF is low. The following sections discuss the
behavior of OUT with a source connected to IN to charge the battery and a battery source only.
9.3.4.1 Input Source Connected (Adapter or USB)
With a source connected, the dynamic power-path management (DPPM) circuitry of the bq24079QW-Q1
monitors the input current continuously. The OUT output for the bq24079QW-Q1 is regulated to a fixed voltage
(VO(REG)). The current into IN is shared between charging the battery and powering the system load at OUT. The
bq24079QW-Q1 has internal selectable current limits of 100 mA (USB100) and 500 mA (USB500) for charging
from USB ports, as well as a resistor-programmable input current limit.
10 μC
50 μC
20 mA/div
USB100 Current Limit
The bq24079QW-Q1 is USB IF compliant for the inrush current testing. The USB spec allows up to 10 μF to be
hard started, which establishes 50 μC as the maximum inrush charge value when exceeding 100 mA. The input
current limit for the bq24079QW-Q1 prevents the input current from exceeding this limit, even with system
capacitances greater than 10 μF. Note that the input capacitance to the device must be selected small enough to
prevent a violation ( VLOWV
No
tPRECHARGE
Elapsed?
Yes
End Charge
Flash CHG
Start Fastcharge
ICHARGE set by ISET
No
IBAT < ITERM
No
t FASTCHARGE
Elapsed?
Yes
End Charge
Flash CHG
Charge Done
CHG = Hi-Z
TD = Low
(’72, ’73 Only)
(’74, ’75 = YES)
(’79QW-Q1 = YES)
No
Yes
Termination Reached
BATTFET Off
Wait for VBAT < VRCH
No
VBAT < VRCH
Yes
Run Battery Detection
Battery Detected?
No
Yes
Figure 23. Battery Charging Flow Diagram
22
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Feature Description (continued)
9.3.5.2 Battery Detection And Recharge
The bq24079QW-Q1 automatically detects if a battery is connected or removed. Once a charge cycle is
complete, the battery voltage is monitored. When the battery voltage falls below VRCH, the battery detection
routine is run. During battery detection, current (IBAT(DET)) is pulled from the battery for a duration tDET to see if the
voltage on BAT falls below VLOWV. If not, charging begins. If it does, then it indicates that the battery is missing or
the protector is open. Next, the precharge current is applied for tDET to close the protector if possible. If VBAT <
VRCH, then the protector closed and charging is initiated. If VBAT > VRCH, then the battery is determined to be
missing and the detection routine continues.
9.3.5.3 Battery Disconnect (SYSOFF Input)
The bq24079QW-Q1 features a SYSOFF input that allows the user to turn the FET Q2 off and disconnect the
battery from the OUT pin. This is useful for disconnecting the system load from the battery, factory programming
where the battery is not installed or for host side impedance track fuel gauging, such as bq27500, where the
battery open circuit voltage level must be detected before the battery charges or discharges. The CHG output
remains low when SYSOFF is high. Connect SYSOFF to VSS, to turn Q2 on for normal operation. SYSOFF is
internally pulled to VBAT through ~5 MΩ resistor.
9.3.5.4 Dynamic Charge Timers (TMR Input)
The bq24079QW-Q1 device contains internal safety timers for the pre-charge and fast-charge phases to prevent
potential damage to the battery and the system. The timers begin at the start of the respective charge cycles.
The timer values are programmed by connecting a resistor from TMR to VSS. The resistor value is calculated
using the following equation:
tPRECHG = KTMR × RTMR
tMAXCHG = 10 × KTMR × RTMR
(4)
(5)
Leave TMR unconnected to select the internal default timers. Disable the timers by connecting TMR to VSS.
Note that timers are suspended when the device is in thermal shutdown, and the timers are slowed proportionally
to the charge current when the device enters thermal regulation.
During the fast charge phase, several events increase the timer durations.
A. The system load current activates the DPPM loop which reduces the available charging current
B. The input current is reduced because the input voltage has fallen to VIN(LOW)
C. The device has entered thermal regulation because the IC junction temperature has exceeded TJ(REG)
During each of these events, the internal timers are slowed down proportionately to the reduction in charging
current. For example, if the charging current is reduced by half, the timer clock is reduced to half the frequency,
and the counter counts half as fast.
If the pre charge timer expires before the battery voltage reaches VLOWV, the bq24079QW-Q1 indicates a fault
condition. Additionally, if the battery current does not fall to ITERM before the fast charge timer expires, a fault is
indicated. The CHG output flashes at approximately 2 Hz to indicate a fault condition. The fault condition is
cleared by toggling CE or the input power, entering/ exiting USB suspend mode, or an OVP event.
9.3.5.5 Status Indicators (PGOOD, CHG)
The bq24079QW-Q1 contains two open-drain outputs that signal its status. The PGOOD output signals when a
valid input source is connected. PGOOD is low when (VBAT + VIN(DT)) < VIN < VOVP. When the input voltage is
outside of this range, PGOOD is high impedance.
The charge cycle after power-up, CE going low or exiting OVP is indicated with the CHG pin on (low - LED on),
whereas all refresh (subsequent) charges will result in the CHG pin off (open - LED off). In addition, the CHG
signals timer faults by flashing at approximately 2 Hz.
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Feature Description (continued)
Table 1. PGOOD Status Indicator
INPUT STATE
PGOOD OUTPUT
VIN < VUVLO
Hi impedance
VUVLO < VIN < VBAT + VIN(DT)
Hi impedance
VBAT + VIN(DT) < VIN < VOVP
Low
VIN > VOVP
Hi impedance
Table 2. CHG Status Indicator
CHARGE STATE
CHG OUTPUT
Charging
Low (for first charge cycle)
Charging suspended by thermal loop
Safety timers expired
Flashing at 2Hz
Charging done
Recharging after termination
Hi impedance
IC disabled or no valid input power
Battery absent
9.3.5.6 Thermal Regulation And Thermal Shutdown
The bq24079QW-Q1 contain a thermal regulation loop that monitors the die temperature. If the temperature
exceeds TJ(REG), the device automatically reduces the charging current to prevent the die temperature from
increasing further. In some cases, the die temperature continues to rise despite the operation of the thermal loop,
particularly under high VIN and heavy OUT system load conditions. Under these conditions, if the die
temperature increases to TJ(OFF), the input FET Q1 is turned OFF. FET Q2 is turned ON to ensure that the
battery still powers the load on OUT. Once the device die temperature cools by TJ(OFF-HYS), the input FET Q1 is
turned on and the device returns to thermal regulation. Continuous overtemperature conditions result in a
"hiccup" mode. During thermal regulation, the safety timers are slowed down proportionately to the reduction in
current limit.
Note that this feature monitors the die temperature of the bq24079QW-Q1. This is not synonymous with ambient
temperature. Self heating exists due to the power dissipated in the IC because of the linear nature of the battery
charging algorithm and the LDO associated with OUT. A modified charge cycle with the thermal loop active is
shown in Figure 24. Battery termination is disabled during thermal regulation.
24
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PRECHARGE
THERMAL
REGULATION
CC FAST
CHARGE
CV TAPER
DONE
VO(REG)
IO(CHG)
Battery Voltage
Battery Current
V(LOWV)
HI-z
I(PRECHG)
I(TERM)
TJ(REG)
IC Junction Temperature, TJ
Figure 24. Charge Cycle Modified by Thermal Loop
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9.3.6 Battery Pack Temperature Monitoring
The bq24079QW-Q1 features an external battery pack temperature monitoring input. The TS input connects to
the NTC thermistor in the battery pack to monitor battery temperature and prevent dangerous over-temperature
conditions. During charging, INTC is sourced to TS and the voltage at TS is continuously monitored. If, at any
time, the voltage at TS is outside of the operating range (VCOLD to VHOT), charging is suspended. The timers
maintain their values but suspend counting. When the voltage measured at TS returns to within the operation
window, charging is resumed and the timers continue counting. When charging is suspended due to a battery
pack temperature fault, the CHG pin remains low and continues to indicate charging.
For applications that do not require the TS monitoring function, connect a 10 kΩ resistor from TS to VSS to set
the TS voltage at a valid level and maintain charging.
The allowed temperature range for 103AT-2 type thermistor is 0°C to 50°C. However, the user may increase the
range by adding two external resistors. See Figure 25 for the circuit details. The values for Rs and Rp are
calculated using the following equations:
-(RTH + RTC ) ±
Rs =
Rp =
æ
ì
üö
VH ´ VC
2
´ (RTC - RTH )ý ÷
çç (RTH +RTC ) - 4 íRTH ´ RTC +
÷
(VH - VC ) ´ ITS
î
þø
è
2
(6)
VH ´ (R TH + RS )
ITS ´ (R TH + RS ) - VH
(7)
Where:
RTH: Thermistor Hot Trip Value found in thermistor data sheet
RTC: Thermistor Cold Trip Value found in thermistor data sheet
VH: IC's Hot Trip Threshold = 0.3 V nominal
VC: IC's Cold Trip Threshold = 2.1 V nominal
ITS: IC's Output Current Bias = 75 µA nominal
NTC Thermsitor Semitec 103AT-4
Rs and Rp 1% values were chosen closest to calculated values
COLD TEMP RESISTANCE
AND TRIP THRESHOLD, Ω (°C)
HOT TEMP RESISTANCE AND
TRIP THRESHOLD, Ω (°C)
EXTERNAL BIAS RESISTOR,
Rs (Ω)
EXTERNAL BIAS RESISTOR,
Rp (Ω)
28000 (–0.6)
4000 (51)
0
∞
28480 (–1)
3536 (55)
487
845000
28480 (–1)
3021 (60)
1000
549000
33890 (–5)
4026 (51)
76.8
158000
33890 (–5)
3536 (55)
576
150000
33890 (–5)
3021 (60)
1100
140000
RHOT and RCOLD are the thermistor resistance at the desired hot and cold temperatures, respectively.
NOTE
Note that the temperature window cannot be tightened more than using only the thermistor
connected to TS, it can only be extended.
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I NTC
bq24079QW-Q1
RS
TS
+
PACK+
TEMP
VCOLD
RP
+
PACK-
VHOT
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Figure 25. Extended TS Pin Thresholds
9.3.7 Half-Wave Adaptors
Some adapters implement a half rectifier topology, which causes the adapter output voltage to fall below the
battery voltage during part of the cycle. To enable operation with adapters under those conditions, the
bq24079QW-Q1 keeps the charger on for at least 20 msec (typical) after the input power puts the part in sleep
mode. This feature enables use of external adapters using 50-Hz networks. The input must not drop below the
UVLO voltage for the charger to work properly. Thus, the battery voltage should be above the UVLO to help
prevent the input from dropping out. Additional input capacitance may be needed.
9.4 Device Functional Modes
9.4.1 Sleep Mode
When the input is between UVLO and VIN(DT), the device enters sleep mode. After entering sleep mode for >20
ms, the internal FET connection between the IN and OUT pin is disabled, and pulling the input to ground will not
discharge the battery other than the leakage on the BAT pin. If one has a full 1000-mAHr battery and the leakage
is 10 μA, then it would take 1000 mAHr/10 μA = 100000 hours (11.4 years) to discharge the battery. The
battery’s self discharge is typically 5 times higher than this.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The bq24079QW-Q1 devices power the system while simultaneously and independently charging the battery.
The input power source for charging the battery and running the system can be an AC adapter or a USB port.
The devices feature dynamic power-path management (DPPM), which shares the source current between the
system and battery charging and automatically reduces the charging current if the system load increases. When
charging from a USB port, the input dynamic power management (VIN-DPM) circuit reduces the input current
limit if the input voltage falls below a threshold, preventing the USB port from crashing. The power-path
architecture also permits the battery to supplement the system current requirements when the adapter cannot
deliver the peak system currents. The bq24079QW-Q1 is configurable to be host controlled for selecting different
input current limits based on the input source connected, or a fully stand alone device for applications that do not
support multiple types of input sources.
10.2 Typical Application – bq24079QW-Q1 Charger Design Example
See Figure 26 for Schematics of the Design Example.
VIN = UVLO to VOVP, IFASTCHG = 800 mA, IIN(MAX) = 1.3 A, Battery Temperature Charge Range = 0°C to 50°C,
6.25 hour Fastcharge Safety Timer
VIN = UVLO to VOVP, IFASTCHG = 800 mA, IIN(MAX) = 1.3 A, ITERM = 110 mA, Battery Temperature Charge
Range = 0°C to 50°C, Safety Timers disabled
VIN = UVLO to VOVP, IFASTCHG = 800 mA, IIN(MAX) = 1.3 A, Battery Temperature Charge Range = 0°C to 50°C,
6.25 hour Fastcharge Safety Timer
28
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Typical Application – bq24079QW-Q1 Charger Design Example (continued)
R4
1.5 kW
R5
1.5 kW
SYSTEM
IN
C1
1 mF
GND
CHG
DC+
PGOOD
Adaptor
OUT
C2
4.7 mF
VSS
bq24079QW-Q1
HOST
EN2
EN1
TS
SYSOFF
CE
BAT
PACK-
R1
46.4 kW
ISET
TMR
C3
4.7 mF
ILM
PACK+
TEMP
R2
1.18 kW
R3
1.13 kW
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Figure 26. Using bq24079QW-Q1 to Disconnect the Battery from the System
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Typical Application – bq24079QW-Q1 Charger Design Example (continued)
10.2.1 Design Requirements
•
•
•
•
•
•
Supply voltage = 5 V
Fast charge current of approximately 800 mA; ISET - pin 16
Input Current Limit =1.3 A; ILIM - pin 12
Termination Current Threshold = 110 mA
Safety timer duration, Fast-Charge = 6.25 hours; TMR – pin 14
TS – Battery Temperature Sense = 10-kΩ NTC (103AT-2)
10.2.2 Detailed Design Procedure
10.2.2.1 Calculations
10.2.2.1.1 Program the Fast Charge Current (ISET):
RISET = KISET / ICHG
KISET = 890 AΩ from the electrical characteristics table.
RISET = 890 AΩ/0.8 A = 1.1125 kΩ
Select the closest standard value, which for this case is 1.13 kΩ. Connect this resistor between ISET (pin 16)
and VSS.
10.2.2.1.2 Program the Input Current Limit (ILIM)
RILIM = KILIM / II_MAX
KILIM = 1550 AΩ from the electrical characteristics table.
RISET = 1550 AΩ / 1.3 A = 1.192 kΩ
Select the closest standard value, which for this case is 1.18 kΩ. Connect this resistor between ILIM (pin 12) and
VSS.
10.2.2.1.3 Program 6.25-hour Fast-Charge Safety Timer (TMR)
RTMR = tMAXCHG / (10 × KTMR )
KTMR = 48 s/kΩ from the electrical characteristics table.
RTMR = (6.25 hr × 3600 s/hr) / (10 × 48 s/kΩ) = 46.8 kΩ
Select the closest standard value, which for this case is 46.4 kΩ. Connect this resistor between TMR (pin 2) and
VSS.
10.2.2.2 TS Function
Use a 10-kΩ NTC thermistor in the battery pack (103AT-2). For applications that do not require the TS
monitoring function, connect a 10-kΩ resistor from TS to VSS to set the TS voltage at a valid level and maintain
charging.
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Typical Application – bq24079QW-Q1 Charger Design Example (continued)
10.2.2.3
CHG and PGOOD
LED Status: connect a 1.5-kΩ resistor in series with a LED between OUT and CHG to indicate charging status.
Connect a 1.5-kΩ resistor in series with a LED between OUT and PGOOD to indicate when a valid input source
is connected.
Processor Monitoring Status: connect a pullup resistor (on the order of 100 kΩ) between the processor’s power
rail and CHG and PGOOD
10.2.2.4 System ON/OFF (SYSOFF)
Connect SYSOFF high to disconnect the battery from the system load. Connect SYSOFF low for normal
operation
10.2.2.5 Selecting In, Out And Bat Pin Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor (ceramic) on the power pin,
input, output and battery pins. Using the values shown on the application diagram, is recommended. After
evaluation of these voltage signals with real system operational conditions, one can determine if capacitance
values can be adjusted toward the minimum recommended values (DC load application) or higher values for fast
high amplitude pulsed load applications. Note if designed high input voltage sources (bad adaptors or wrong
adaptors), the capacitor needs to be rated appropriately. Ceramic capacitors are tested to 2x their rated values
so a 16-V capacitor may be adequate for a 30-V transient (verify tested rating with capacitor manufacturer).
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Typical Application – bq24079QW-Q1 Charger Design Example (continued)
10.2.3 Application Curves
VIN = 6 V, EN1 = 1, EN2 = 0, TA = 25°C, unless otherwise noted.
VIN
5 V/div
VCHG
5 V/div
Charging Initiated
VOUT
4.4 V
1 A/div
500 mV/div
VBAT
3.6 V
IBAT
VPGOOD
5 V/div
2 V/div
VBAT
Battery Inserted
500 mA/div
IBAT
Battery Detection Mode
4 ms/div
400 ms/div
RLOAD = 10 Ω
Figure 27. Adapter Plug-in Battery Connected
VCHG
5 V/div
Figure 28. Battery Detection Battery Inserted
IOUT
500 mA/div
IBAT
500 mA/div
VOUT
4.4 V
200 mV/div
1 A/div
IBAT
VBAT
2 V/div
Battery
Removed
Battery Detection Mode
400 ms/div
400 ms/div
RLOAD = 20 Ω to 9 Ω
Figure 29. Battery Detection Battery Removed
VCE
5 V/div
VCHG
5 V/div
1 V/div
VBAT
3.6 V
IBAT
Mandatory Precharge
500 mA/div
Figure 30. Entering And Exiting DPPM Mode
10 V/div
VIN
VOUT
4.4 V
VBAT
4.1 V
500 mV/div
IBAT
1 A/div
10 ms/div
40 ms/div
VIN = 6 V to 15 V
Figure 31. Charger ON/OF Using CE
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RLOAD = 10 Ω
Figure 32. OVP Fault
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Typical Application – bq24079QW-Q1 Charger Design Example (continued)
VIN = 6 V, EN1 = 1, EN2 = 0, TA = 25°C, unless otherwise noted.
VSYSOFF
VOUT
5.5 V
5 V/div
VSYSOFF
2 V/div
VBAT
4V
VBAT
4V
5 V/div
2 V/div
VOUT
Battery Powering
System
500 mA/div
System Power Off
IBAT
IBAT
500 mA/div
400 ms/div
4 ms/div
VIN = 0 V
VIN = 6 V
Figure 33. System On/off With Input Connected bq24079QW-Q1
Figure 34. System On/off With Input Not Connected bq24079QW-Q1
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11 Power Supply Recommendations
Some adapters implement a half rectifier topology, which causes the adapter output voltage to fall below the
battery voltage during part of the cycle. To enable operation with adapters under those conditions, the
bq24079QW-Q1 keeps the charger on for at least 20 msec (typical) after the input power puts the part in sleep
mode. This feature enables use of external adapters using 50-Hz networks. The input must not drop below the
UVLO voltage for the charger to work properly. Thus, the battery voltage should be above the UVLO to help
prevent the input from dropping out. Additional input capacitance may be needed.
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12 Layout
12.1 Layout Guidelines
•
•
•
•
To obtain optimal performance, the decoupling capacitor from IN to GND (thermal pad) and the output filter
capacitors from OUT to GND (thermal pad) should be placed as close as possible to the bq24079QW-Q1,
with short trace runs to both IN, OUT and GND (thermal pad).
All low-current GND connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
The high current charge paths into IN pin and from the OUT pin must be sized appropriately for the maximum
charge current in order to avoid voltage drops in these traces
The bq24079QW-Q1 is packaged in a thermally enhanced MLP package. The package includes a thermal
pad to provide an effective thermal contact between the IC and the printed circuit board (PCB); this thermal
pad is also the main ground connection for the device. Connect the thermal pad to the PCB ground
connection. Full PCB design guidelines for this package are provided in the application note entitled:
QFN/SON PCB Attachment Application Note (SLUA271).
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12.2 Layout Example
Figure 35.
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12.3 Thermal Package
The bq24079QW-Q1 is packaged in a thermally enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the IC and the printed circuit board (PCB). The power pad should
be directly connected to the VSS pin. Full PCB design guidelines for this package are provided in the application
note entitled: QFN/SON PCB Attachment Application Note (SLUA271). The most common measure of package
thermal performance is thermal impedance (θJA ) measured (or modeled) from the chip junction to the air
surrounding the package surface (ambient). The mathematical expression for θJA is:
θJA = (TJ - T) / P
Where:
TJ = chip junction temperature
T = ambient temperature
P = device power dissipation
Factors that can influence the measurement and calculation of θJA include:
1.
2.
3.
4.
5.
Whether or not the device is board mounted
Trace size, composition, thickness, and geometry
Orientation of the device (horizontal or vertical)
Volume of the ambient air surrounding the device under test and airflow
Whether other surfaces are in close proximity to the device being tested
Due to the charge profile of Li-Ion batteries the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. Typically after fast charge begins the pack voltage
increases to ≉3.4 V within the first 2 minutes. The thermal time constant of the assembly typically takes a few
minutes to heat up so when doing maximum power dissipation calculations, 3.4 V is a good minimum voltage to
use. This is verified, with the system and a fully discharged battery, by plotting temperature on the bottom of the
PCB under the IC (pad should have multiple vias), the charge current and the battery voltage as a function of
time. The fast charge current will start to taper off if the part goes into thermal regulation.
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal
PowerFET. It can be calculated from the following equation when a battery pack is being charged :
P = [V(IN) – V(OUT)] × I(OUT) + [V(OUT) – V(BAT)] × I(BAT)
(7)
The thermal loop feature reduces the charge current to limit excessive IC junction temperature. It is
recommended that the design not run in thermal regulation for typical operating conditions (nominal input voltage
and nominal ambient temperatures) and use the feature for non typical situations such as hot environments or
higher than normal input source voltage. With that said, the IC will still perform as described, if the thermal loop
is always active.
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• QFN/SON PCB Attachment Application Note (SLUA271)
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates — go to the product folder for your device on ti.com. In the
upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information
that has changed (if any). For change details, check the revision history of any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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28-May-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
BQ24079QWRGTRQ1
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
1COC
BQ24079QWRGTTQ1
ACTIVE
VQFN
RGT
16
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
1COC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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