User's Guide
SLUUA18A – October 2012 – Revised February 2014
bq24195/L EVM (PWR193) User’s Guide
1
2
Contents
Introduction ..................................................................................................................
1.1
General Descriptions ..............................................................................................
Test Summary ...............................................................................................................
2.1
Equipment ...........................................................................................................
2.2
Equipment Setup ...................................................................................................
2.3
Procedure ...........................................................................................................
2
2
3
3
5
6
List of Figures
1
Connections of the HPA172 Kit ...........................................................................................
2
Original Test Setup for PWR193 (bq24195/L EVM)
5
3
Main Window of the bq24195x Evaluation Software for bq24195/L
6
4
5
6
7
8
9
10
11
12
...................................................................
.................................................
CHG Mode Ripple and Duty Cycle: VBUS = 5 V, VBAT = 3.7 V ..........................................................
Boost Mode Ripple and Duty Cycle; VBAT = 3.7 V ......................................................................
bq24195/L EVM Top Layer...............................................................................................
bq24195/L EVM Second Layer ..........................................................................................
bq24195/L EVM Third Layer .............................................................................................
bq24195/L EVM Bottom Layer ...........................................................................................
bq24195/L EVM Top Assembly ..........................................................................................
bq24195/L EVM Bottom Assembly ......................................................................................
bq24195/L EVM Schematic ..............................................................................................
5
8
9
11
12
13
14
15
16
17
List of Tables
1
EVM Connections ...........................................................................................................
2
2
Jumper Connections ........................................................................................................
3
3
Recommended Operating Conditions ....................................................................................
3
4
Device ID JEITA Settings ..................................................................................................
9
5
Bill of Materials.............................................................................................................
18
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Introduction
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Introduction
EVM Features
Refer to the data sheet (SLUSB97) for detailed features and operation.
Design Considerations
This EVM has protection circuitry, external to the IC, to protect against applying a power source to the
input (VBUS) when the IC is in boost mode, converting battery power to a 5-VDC PMID output. This is
accomplished by two circuits on the EVM schematic by (1) adding an isolation circuit consisting of Q1, its
drive Q3, to apply input power when available and disconnect it when not available and (2) by pulling OTG
low, with Q2, when the input is available. Pulling OTG low disables the boost-mode operation.
The OTG pin should be pulled low at least a few microseconds before the input power is applied via Q1.
This is accomplished on this EVM by setting the drive resistance for Q2 (OTG ckt.) lower and drive
resistance for Q3 (VBUS connection) higher. The voltage threshold and resistance of the driver along with
the input capacitance of Q2 and Q3 set the desired timing sequencing. Q3 (VBUS turn on) has a
Thevinen-equivalent drive of 72k and for Q2 (OTG ckt.) is 35k, allowing the OTG signal to be pulled low
(disables Boost Mode) prior to the input voltage being applied.
1.1
General Descriptions
The bq24195/L evaluation module is a complete charger module for evaluating an I2C Controlled single
NVDC-1 charge using the bq2419x devices.
The bq24195/L EVM doesn’t include the USB-to-GPIO interface board. To evaluate the bq24195/L EVM
must order USB-to-GPIO interface board separately.
For details, see bq24195/L data sheet.
I/O Description
Table 1 contains the jumper connections for this EVM.
Table 1. EVM Connections
2
Jack
Description
J1–VIN
Input: positive terminal
J1–GND
Input: negative terminal (ground terminal)
J2-SYS
Connected to system
J2-BAT+
Connected to battery pack
J2-GND
Ground
J3
USB-to-GPIO connector (USB Interface Adapter
Connector - HPA172)
J4–INT
INT pin connection
J4– OTG
OTG pin connection
J4-CE
CE pin connection
J4-GND
Ground
J5-PMID
PMID pin connection or power bank output
J5-GND
Ground
J6-TS2
External TS2 pin connection
J6-GND
Ground
J7
Mini_USB Connector
J5-TS2
External TS2 pin connection
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Test Summary
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Table 2 lists the controls and key parameter settings for this EVM.
Table 2. Jumper Connections
Jack
Description
Factory Setting
JP1
TS1 to TS2 connection
Shunt installed
JP2
D- 20k pull down
Shunt not installed
JP3
VSYS pull-up for STAT, CE, INT
Shunt installed
JP4
USB current limit selection pin during buck mode and PSEL is high (JP1-High);
enable pin during boost mode.
In buck mode: OTG = High, IIN limit = 500 mA;
OTG = Low, IIN limit = 100 mA.
The boost mode is activated when the REG01[5:4] = 10 and OTG pin is HIGH.
Shunt not installed
JP5
/CE pin setting: Pull low to enable the charge
(GUI also can pull CE low)
Shunt not installed
JP6
200-Ω short between D+ and D-
Shunt not installed
JP7
TS2 resistor divider pull-up source (REGN) connection
Shunt installed
JP8
Internal 10k to ground to TS2
Shunt installed
JP9
D+ 20k Pull down
Shunt not installed
Table 3 lists the recommended operating conditions for this EVM.
Table 3. Recommended Operating Conditions
Symbol
Description
MIN
TYP
MAX
Unit
Supply voltage, VIN
Input voltage from AC adapter input
3.9
5
6
V
Battery voltage, VBAT
Voltage applied at VBAT terminal
0
3.7
4.25
V
Supply current, IAC
Maximum input current from AC adapter
input
0
3
A
Output current, IOUT
Output current
0
4
A
0
125
°C
Operating junction temperature
range, TJ
2
Test Summary
Section 2.1 – Section 2.3 explain the equipment, the equipment setup, and the test procedures.
2.1
Equipment
Power Supplies
Power supply #1 (PS#1): a power supply capable of supplying 5 V at 1 A is required. While this part can
handle larger voltage and current, it is not necessary for this procedure.
Load #1 (4-Quadrant Supply, Constant Voltage < 4.5 V)
A 0–20 V/0–5 A, > 30-W system, DC electronic load and setting as constant voltage load mode.
Or:
Kepco load: BOP 20–5M, DC 0 to ±20 V, 0 to ±5 A (or higher)
Or:
Real single-cell battery
Load #2 – Use with Boost Mode
PMID-to-GND load, 10 Ω, 5 W or greater
Meters
Six Fluke 75 multimeters, (equivalent or better)
Or:
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Four equivalent voltage meters and two equivalent current meters.
The current meters must be capable of measuring 5 A+ current.
Computer
A computer with at least one USB port and a USB cable. The bq2419xEVM evaluation software must be
properly installed.
USB-to-GPIO Communication Kit (HPA172-USB Interface Adapter)
Software
Unzip the bq2419xEVM_GUI.zip and double-click on the SETUP.EXE file. Follow the installation steps.
The software supports the Windows® XP and Windows 7 operating systems.
4
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2.2
Equipment Setup
1.
2.
3.
4.
Set PS#1 for 5-V DC, 1-A current limit and then turn off the supply.
Connect the output of PS#1 in series with a current meter (multimeter) to J1 (VBUS and GND).
Connect a voltage meter across J1 (VBUS) and J1 (GND).
Turn on the Load, set to constant voltage mode and output to 2.5 V. Turn off (disable) Load. Connect
Load in series with a current meter (multimeter), ground side, to J2 (BAT+ and GND) as shown in
Figure 2.
5. Connect a voltage meter across J2 (BAT+ and GND).
6. Connect the HPA172 USB interface adapter to the computer with a USB mini-cable and to J3 with the
10-pin ribbon cable. The connections are shown in Figure 1.
I/O
USB Interface
Adapter
Texas Instruments
© 2006
USB
To Computer
USB Port
10-pin
Ribbon Cable
‘To EVM’
Figure 1. Connections of the HPA172 Kit
Figure 2 shows the test setup for PWR193.
7. Install shunts as shown in Table 2.
PWR193
bq2419x-EVM
S
J4
Figure 2. Original Test Setup for PWR193 (bq24195/L EVM)
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8. Turn on the computer. Launch the bq2419xEVM evaluation software. The main window of the software
is shown in Figure 3.
Figure 3. Main Window of the bq24195x Evaluation Software for bq24195/L
2.3
Procedure
Follow the steps and verify the outputs and IC for the EVM.
Current Settings
1. Make Sure EQUIPMENT SETUP steps are followed.
ILIM Setting: Set the potentiometer to its lowest value for max input current by connecting an ohmmeter between point TP9 and ground. Turn the screw on the potentiometer counterclockwise until the
resistance drops to its lowest point (approximately 169 Ω, the value of R7)
2. Launch the BQ2419x EVM GUI software, if not already done
3. Turn on PS#1
Measure → V (J2(SYS), J2(GND)) = 4.10 ±300 mV
6
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Charge Voltage and Current Regulation of VIN and Device ID Verification
Follow the steps and verify the outputs and IC for the EVM.
2.3.0.1
Software setup (all of Section 2.3.0.1 is done in the GUI):
1. Device address: bq24195/L (6B)
2.
3.
4.
5.
6.
7.
8.
9.
Click the Read button
Select Disabled for I2C Watchdog Timer Limit
Set Input Voltage Limit to 4.2 V
Set Input Current Limit to 500 mA
Set Charge Voltage Limit to 4.208 V
Set Fast Charge Current, ICHG to 512 mA
Set Pre-Charge Current to 256 mA
Deselect Enable Termination (see the following image)
10. Click the Read button twice
Observe → Everything normal at FAULT box
Observe → D1 (STAT) is on, except the bq24192IEVM
Enable Load#1 from Section 2.2 step 4. Measure the voltage across J2 at two different points: V(J2(SYS),
J2(GND)) and V(J2(BAT), J2(GND))
Measure → V(J2(SYS), J2(GND)) = 3.65 V ±300 mV
Measure → V(J2(BAT), J2(GND)) = 2.5V ±200 mV
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Increase the Constant Voltage Load to 3.7 VDC
Measure → V(J2(SYS), J2(GND)) = 3.75 V ±200 mV
Measure → IBAT = 500 mA ±200 mA
Measure → V(J2(BAT), J2(GND)) = 3.7 V ±200 mV
In the software, set Fast Charge Current, ICHG to 1.012 A
Measure → IIN = 500 mA ±200 mA
Verify Scope Measurements (See Figure 4 – 500 ns/div)
C1 (AC coupled 20 mV/div): Vac_PMID (TP20 to GND) – Ripple excluding high frequency spikes < 10 mV
C2 (5 V/div): Vdc_SW (TP2) - Frequency between 1.25 MHz and 1.5 MHz, duty cycle between 73% and
81%
C3 (AC coupled 20 mV/div): Vac_VSYS (TP3 to GND) - excluding high frequency spikes < 15 mV
CHG Mode: Vbus = 5 V Vbat = 3.7 V
Vsw
C2
Vpmid_AC coupled
C1
Vsys_AC coupled
C3
Figure 4. CHG Mode Ripple and Duty Cycle: VBUS = 5 V, VBAT = 3.7 V
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Switch to Boost Mode
1. Turn off and disconnect PS#1
2. If the constant voltage load connected from BAT+ to GND is not a four-quadrant supply (sources
current) remove the load and use the power source disconnected in step one, set to 3.7 V and 2 A
current limit and connect between BAT+ and GND
3. Apply 10 Ω (5 W or greater) across J5 (PMID(+) to GND(–)
4. Uncheck the OTG Low box in the GUI
5. Select OTG in the Configuration drop-down window
6. Verify VPMID to GND on J5 is between 4.9 V and 5.3 V
7. Verify scope measurement (Figure 5)
C1 (AC coupled 20 mV/div): Vac_PMID (TP20 to GND) – Ripple excluding high-frequency spikes
C2 (5 V/div): Vdc_SW (TP2) - Frequency between 1.2 MHz and 1.7 MHz, Duty cycle between 67%
and 74%
Boost Mode: Vbat = 3.7 V
Vsw
C2
Vprnid_AC coupled
C1
Figure 5. Boost Mode Ripple and Duty Cycle; VBAT = 3.7 V
Verify Device ID JEITA shown in software matches Table 4
Table 4. Device ID JEITA Settings
Assembly Number
EVM Part Number
Device ID
JEITA
PWR193-001
bq24195LEVM-021
100
Disabled
PWR193-002
bq24195EVM-021
100
Disabled
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PCB Layout Guideline
Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the
components minimizing high-frequency current path loop is important to prevent electrical and magnetic
field radiation and high frequency resonant problems. This PCB layout priority list must be followed in the
order presented for proper layout:
1. Place the input capacitor as close as possible to the PMID and GND pin connections and use the
shortest possible copper trace connection or GND plane.
2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a
short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power
ground separately. Connect analog ground and power ground together using power pad as the single
ground connection point or use a 0-Ω resistor to tie analog ground to power ground.
5. Use a single ground connection to tie the charger power ground to the charger analog ground just
beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise
coupling.
6. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground
plane on the other layers.
8. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the
QFN information, refer to SCBA017 and SLUA271.
10
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Board Layout, Schematic, and Bill of Materials
Board Layout
Figure 6 through Figure 11 illustrate the board layouts for this EVM.
Figure 6. bq24195/L EVM Top Layer
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Figure 7. bq24195/L EVM Second Layer
12
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Figure 8. bq24195/L EVM Third Layer
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Figure 9. bq24195/L EVM Bottom Layer
14
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Figure 10. bq24195/L EVM Top Assembly
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Figure 11. bq24195/L EVM Bottom Assembly
16
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Schematic
Figure 12 illustrates the schematic for this EVM.
REGN
J5
C18
2
2
Open
Q3
C21
1 VBUS
2 D+/PSEL
D+
1
10uF
C9
C3
0.1uF
C12
J2
C10
1
1
1
1
1
1
1
JP3
R2
0
PULL-UP
TP4
C11
10uF
TS2
1
SDA
JP1
R6 1
1
1
1
R23 1
PULL-UP
SCL
TS1
PULL-UP
ILIM
200
R8
/CE
R7
169
PULL-UP
J3
10.0k
INT
SYS
121k R19
2
/CE
JP4
Q2
49.9k R25
1
OTG
3
1
J4
R24
768
1
/CE
1
R11
2
Si2312DS
R15
R14
2.21k
10.0k
LTST-C190GKT
VIN
OTG
PULL-UP
10.0k R17
INT
4
J7
C8
10uF
TP3
SYS 16
SYS 15
11 TS1
TS2
12
9 CE
ILIM
7 INT
8 OTG/IUSB
SCL
SDA
1
BAT+
System Output
3.4 - 4.4V, 2.5A
GND
PGND 18
PGND 17
BAT 14
BAT 13
200
R13 200
3
C7
1
2
STAT
INT
OTG
/CE
GND
2
1.0uF
5 SCL
6 SDA
R4
1
3
U1
BQ24195(L)RGE
3 D-/PG
4 STAT
D-
R12
L1
2.2uH
SW 19
1
1
10
9
8
7
6
5
4
3
2
1
47nF
1
1
Si2312DS
2
10uF
1
C14
C22
R5 100k
1.0uF
1.0uF
10.0k
1
C20
C19
BTST 21
SW 20
3
C5
C2
C1
R16
R1
0
24
3
6
5
2
1
7
1
10
1
1
PMID 23
REGN 22
4
8
2
TP20
R3
0
1
TP1
R18 261k
VIN
GND
3.9 to 6V
10uF
VBUS
J1
1
TP2
1
C15
C4
10uF
25
2
C17
10uF
VBUS
1
C16
PWPD
2
SW
C6 4.7uF
TP19
Q1
CSD25302Q2
1
PMID
GND
3.9 to 6V
D1
STAT
PULL-UP
10.0k
JP5
1
1
1
Mini_USB
VIN
1
2
3
4 NC
5
R27
200
R9
20k
D-
2
TS2
2
See BOM for component usage
C13
R20
10.0k
1
JP2
JP9
R26
20k
OTG
1
1
1
TP13
INT
D+
TP17
TP16
TP15
TS1
/CE
TP12
PGND
1
SCL
TP11
STAT
JP8
TP8
TP7
SDA
TP10
ILIM
TP14
R21
30.1k
D+
Not installed
REGN
TP9
1
JP6
1
TP6
TP5
R22
5.23k
J6
TS2
GND
1
1
REGN
JP7
D-
TS2
TP18
PGND
TEST POINTS
1
1
1
Figure 12. bq24195/L EVM Schematic
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Bill of Materials
Table 5 contains the bill of materials.
Table 5. Bill of Materials
18
-001
-002
RefDes
Value
Description
Size
Part
Number
MFR
2
2
C1, C20
1.0 µF
Capacitor, ceramic, 25 V, X7R, 10%
1206
STD
STD
1
1
C10
1.0 µF
Capacitor, ceramic, 10 V, X7R, 10%
0805
STD
STD
1
1
C11
10 µF
Capacitor, ceramic, 10 V, X5R, 10%
0603
STD
STD
1
1
C14
Open
Capacitor, ceramic, 10 V X5R, 10%
0805
STD
STD
0
1
C16
10 µF
Capacitor, ceramic, 10 V, X5R, 10%
1206
STD
STD
0
2
C17, C18
22 µF
Capacitor, ceramic, 10 V, X5R, 20%
1206
STD
STD
3
3
C2, C21, C22
Open
Capacitor, ceramic
0603
STD
STD
2
2
C3, C12
Open
Capacitor, ceramic, 10 V X5R, 10%
1206
STD
STD
2
2
C4, C15
10 µF
Capacitor, ceramic, 25 V, X5R, 10%
0805
STD
STD
1
1
C5
47 nF
Capacitor, ceramic, 16 V, X7R, 10%
0603
STD
STD
1
1
C6
4.7 µF
Capacitor, ceramic, 16 V, X7R, 10%
0603
STD
STD
3
3
C7, C8, C19
10 µF
Capacitor, ceramic, 25 V X5R, 10%
0805
STD
STD
2
2
C9, C13
0.1 µF
Capacitor, ceramic, 25 V, X7R, 10%
0603
STD
STD
1
1
D1
LTST-C190GKT
Diode, LED, green, 2.1 V, 20 mA, 6 mcd
0603
LTST-C190GKT
Lite On
2
2
J1, J5
ED120/2DS
Connector, 15 A, 300 V male 2 pole, 5.08 mm
9 × 12 mm
ED120/2DS
On Shore
Tech
1
1
J2
ED120/3DS
Terminal block, 3 pin, 15 A, 5.1mm
0.60 × 0.35 inch
ED120/3DS
OST
1
1
J3
N2510-6002RB
Connector, male straight 2 × 5 pin, 100 mil
spacing, 4 wall
0.338 × 0.788 in
N2510-6002RB
3M
1
1
J4
ED555/4DS
Terminal block, 4 pin, 6 A, 3.5 mm
0.55 × 0.25 in
ED555/4DS
OST
1
1
J6
PEC02SAAN
Header, Male 2 pin, 100 mil spacing,
0.100 in × 2
PEC02SAAN
Sullins
1
1
J7
A-USB B-M5
Connector, USB-B, mini, 5 pins
0.354 × 0.307 in
A-USB B-M5
9
9
JP1, JP2, JP3,
JP4, JP5, JP6,
JP7, JP8, JP9
PEC02SAAN
Header, Male 2 pin, 100mil spacing,
0.100 in × 2
PEC02SAAN
Sullins
1
1
L1
2.2 µH
Inductor, SMT, 5 A, 37 mΩ
0.204 × 0.216 in
IHLP2020BZER2R2M11
Vishay
1
1
Q1
CSD25302Q2
Trans, P-Channel NexFET, 20 V, 5 A, 56 mΩ
SON 2 × 2
CSD25302Q2
TI
2
2
Q2, Q3
Si2312DS
MOSFET, N-Channel, 20 V, 4.9 A, 33 mΩ
SOT23
Si2312DS
Vishay
1
1
R1
0Ω
Resistor, chip, 1/16W,
0603
STD
STD
1
1
R14
2.21 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
1
R15
10.0 kΩ
Potentiometer, 3/8 cermet, single-turn
0.25 × 0.17 in
3266W-1-103LF
Bourns
1
1
R18
261 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
1
R19
121 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
1
R2
0Ω
Resistor, chip, 0.6W, 1%
2010
STD
STD
1
1
R21
30.1 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
1
R22
5.23 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
1
R24
768 Ω
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
1
R25
49.9 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
1
R3
0Ω
Resistor, chip,1/2W, yy%
1210
STD
STD
4
4
R4, R12, R13,
R27
200 Ω
Resistor, chip, 1/16W, 1%
0603
STD
STD
1
1
R5
100 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
2
2
R6, R23
Open
Resistor, chip, 1/16W
0603
STD
STD
1
1
R7
169 Ω
Resistor, chip, 1/16W, 1%
0603
STD
STD
5
5
R8, R11, R16,
R17, R20
10.0 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
2
2
R9, R26
20 kΩ
Resistor, chip, 1/16W, 1%
0603
STD
STD
17
17
TP1, TP3, TP4,
TP5, TP6, TP7,
TP8, TP9, TP10,
TP11, TP13,
TP14, TP15,
TP16, TP17,
TP19, TP20
5002
Test point, white, thru hole color keyed
0.100 × 0.100 in
5002
Keystone
2
2
TP12, TP18
5001
Test point, black, thru hole color keyed
0.100 × 0.100 in
5001
Keystone
1
1
TP2
131-4244-00
Adaptor, 3.5-mm probe clip ( or 131-5031-00)
0.200 in
131-4244-00
Tektronix
bq24195/L EVM (PWR193) User’s Guide
SLUUA18A – October 2012 – Revised February 2014
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Copyright © 2012–2014, Texas Instruments Incorporated
Test Summary
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Table 5. Bill of Materials (continued)
-001
-002
RefDes
Value
Description
Size
Part
Number
MFR
1
0
U1
BQ24195LRGE
IC, I2C Controlled 2.5A Single Cell USB /
Adaptor Charger With Narrow VDC Power Path
Management and USB OTG
QFN-23
BQ24195LRGE
TI
0
1
U1
BQ24195RGE
IC, I2C controlled 2.5-A single cell USB/adaptor
charger with narrow VDC power-path
management and USB OTG
QFN-24
BQ24195RGE
TI
1
1
--
PCB
3 in × 3 in × 0.031
in
PWR193
Any
1
1
--
Label (See note 5)
1.25 × 0.25 in
THT-13-457-10
Brady
4
4
-
Rubber foot (see note 6)
0.044 × 0.20 in
SJ-5303
3M
Notes:
1. These assemblies are ESD sensitive, observe ESD precautions.
SJ-5303
2. These assemblies must be clean and free from flux and all contaminants. Use of no-clean flux is not acceptable.
3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
4. Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's components.
5. Install label after final wash. Text shall be 8 pt font. Text shall be per Label Information.
6. Install after final wash.
Label Information
Assembly number
Text
PWR193-001
bq24195LEVM-021
PWR193-002
bq24195EVM-021
SLUUA18A – October 2012 – Revised February 2014
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bq24195/L EVM (PWR193) User’s Guide
Copyright © 2012–2014, Texas Instruments Incorporated
19
Revision History
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Revision History
Changes from Original (October 2012) to A Revision .................................................................................................... Page
•
Deleted 12 (V) from TYP column of Supply voltage, VIN in Recommended Operating Conditions table.
.....................
3
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
20
Revision History
SLUUA18A – October 2012 – Revised February 2014
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Copyright © 2012–2014, Texas Instruments Incorporated
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS
Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions:
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO
BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
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ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES.
Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This
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For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT,
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Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the
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FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
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instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If
this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and
on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
For EVMs annotated as IC – INDUSTRY CANADA Compliant
This Class A or B digital apparatus complies with Canadian ICES-003.
Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the
equipment.
Concerning EVMs including radio transmitters
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this
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Concerning EVMs including detachable antennas
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain
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This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum
permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain
greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.
Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.
Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
l'utilisateur pour actionner l'équipement.
Concernant les EVMs avec appareils radio
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout
brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
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l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente
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Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
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【Important Notice for Users of EVMs for RF Products in Japan】
】
This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan
If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:
1.
2.
3.
Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this
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Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with
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http://www.tij.co.jp
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】
本開発キットは技術基準適合証明を受けておりません。
本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
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EVALUATION BOARD/KIT/MODULE (EVM)
WARNINGS, RESTRICTIONS AND DISCLAIMERS
For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished
electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in
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associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end
product.
Your Sole Responsibility and Risk. You acknowledge, represent and agree that:
1.
2.
3.
4.
You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug
Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees,
affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes.
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user guidelines. Exceeding the specified EVM ratings (including but not limited to input and output voltage, current, power, and
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