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bq24292i
SLUSBI4B – APRIL 2013 – REVISED DECEMBER 2016
bq24292i I2C Controlled 4.5A Single Cell USB/Adapter Charger
With Narrow VDC Power Path Management and USB OTG
1
1 Features
•
•
•
•
•
•
•
•
•
•
High Efficiency 4.5A Switch Mode Charger
– 92% Charge Efficiency at 2A, 90% at 4A
– Accelerate Charge Time by Battery Path
Impedance Compensation
Highest Battery Discharge Efficiency with 12mΩ
Battery Discharge MOSFET up to 9A Discharge
Current
Single Input USB-compliant/Adapter Charger
– Support USB Detection Compatible to USB
Battery Charger Spec 1.2
– Input Voltage and Current Limit Supports
USB2.0 and USB 3.0
– Input Current Limit: 100mA, 150mA, 500mA,
900mA, 1.2A, 1.5A, 2A and 3A
3.9V–17V Input Operating Voltage Range
– Support All Kinds of Adapter with Input Voltage
DPM Regulation
Support USB On-The-Go Standard with 5V at
1.3A Synchronous Boost Converter Operation
– 93% 5V Boost Efficiency at 1A
– Fast OTG Startup (22ms typ)
– Hiccup Mode Overcurrent Protection
Narrow VDC (NVDC) Power Path Management
– Instant-on Works with No Battery or Deeply
Discharged Battery
– Ideal Diode Operation in Battery Supplement
Mode
1.5MHz Switching Frequency for Low Profile
Inductor
Autonomous Battery Charging with or without
Host Management
– Battery Charge Enable
– Battery Charge Preconditioning
– Charge Termination and Recharge
High Accuracy (0°C to 125°C)
– ±0.5% Charge Voltage Regulation
– ±7% Charge Current Regulation
– ±7.5% Input Current Regulation
– ±2% Output Regulation in Boost Mode
High Integration
– Power Path Management
– Synchronous Switching MOSFETs
– Integrated Current Sensing
•
•
•
•
– Bootstrap Diode
– Internal Loop Compensation
Safety
– Battery Temperature Sensing and Charging
Safety Timer
– Thermal Regulation and Thermal Shutdown
– Input System Overvoltage Protection
– MOSFET Overcurrent Protection
Charge Status Outputs for LED or Host Processor
Low Battery Leakage Current and Support
Shipping Mode
4mm x 4mm VQFN-24 Package
2 Applications
•
•
•
•
•
Tablet PC
Smart Phone
Portable Audio Speaker
Portable Media Players
Internet Devices
3 Description
The bq24292i is highly-integrated switch-mode
battery charge management and system power path
management devices for single cell Li-Ion and Lipolymer battery in a wide range of smartphone, tablet
and other portable devices.
Device Information(1)
PART NUMBER
PACKAGE
bq24292i
BODY SIZE (NOM)
VQFN (24)
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
bq24292i with PSEL, USB On-The-Go (OTG), No
Thermistor Connections
2.2μH
5V USB
15V Adapter
VBUS
PMID
1μF
SYS: 3.5V-4.35V
SW
47nF
6.8μF
10μF
10μF
BOOT
REGN
4.7μF
SYS
PGND
2.2kW
PG
STAT
VREF
10kW
Host
PHY
10kW
SYS
BAT
10kW
SDA
SCL
INT
OTG
CE
ILIM
10μF
353W
(1.5A max)
REGN
10kW
TS1
TS2
PSEL
10kW
Thermal Pad
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24292i
SLUSBI4B – APRIL 2013 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Requirements ................................................ 9
Switching Characteristics .......................................... 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 25
8.5 Register Map........................................................... 27
9
Application and Implementation ........................ 34
9.1 Application Information............................................ 34
9.2 Typical Application .................................................. 34
10 Power Supply Recommendations ..................... 40
11 Layout................................................................... 40
11.1 Layout Guidelines ................................................. 40
11.2 Layout Example .................................................... 41
12 Device and Documentation Support ................. 42
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
42
42
42
42
42
42
13 Mechanical, Packaging, and Orderable
Information ........................................................... 42
4 Revision History
Changes from Revision A (April 2015) to Revision B
Page
•
Changed VREF to VREGN in Figure 15 ................................................................................................................................. 19
•
Changed VREF to VREGN in Equation 2 ............................................................................................................................... 20
•
Added note to Figure 36 ...................................................................................................................................................... 34
•
Added note to Figure 37 ...................................................................................................................................................... 35
•
Changed last paragraph in Output Capacitor section .......................................................................................................... 36
Changes from Original (April 2013) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
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SLUSBI4B – APRIL 2013 – REVISED DECEMBER 2016
5 Description (Continued)
Its low impedance power path optimizes switch-mode operation efficiency, reduces battery charging time and
extends battery life during discharging phase. The I2C serial interface with charging and system settings makes
the device a truly flexible solution.
The device supports a wide range of input sources, including standard USB host port, USB charging port and
high power DC adapter. To set the default input current limit, the device detects the input source following the
USB battery charging spec 1.2, and takes the results from detection circuit in the system, such as USB PHY
device. The device is compliant with USB 2.0 and USB 3.0 power specifications with input current and voltage
regulation. Meanwhile, the device supports USB On-the-Go operation by providing fast startup and supplying 5V
on the VBUS with a current limit up to 1.3A.
The power path management regulates the system slightly above battery voltage but does not drop below 3.5V
minimum system voltage (programmable). With this feature, the system maintains operation even when the
battery is completely depleted or removed. When the input current limit or voltage limit is reached, the power
path management automatically reduces the charge current to zero. As the system load continues to increase,
the power path discharges the battery until the system power requirement is met. This supplement mode
operation prevents overloading the input source.
The device initiates and complete a charging cycle without software control. It automatically detects the battery
voltage and charges the battery in three phases: pre-conditioning, constant current and constant voltage. At the
end of the charging cycle, the charger automatically terminates when the charge current is below a preset limit in
the constant voltage phase. When the full battery falls below the recharge threshold, the charger will
automatically start another charging cycle.
The device provides various safety features for battery charging and system operation, including dual pack
negative thermistor monitoring, charging safety timer and overvoltage, overcurrent protections. The thermal
regulation reduces charge current when the junction temperature exceeds 120°C (programmable).
The STAT output reports the charging status and any fault conditions. The PG output in the device indicates if a
good power source is present. The INT immediately notifies the host when a fault occurs.
The device is available in a 24-pin, 4x4 mm2 thin VQFN package.
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SLUSBI4B – APRIL 2013 – REVISED DECEMBER 2016
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6 Pin Configuration and Functions
VBUS
PMID
REGN
BTST
SW
SW
RGE Package
24-Pin VQFN with Exposed Thermal Pad
(Top View)
24
23
22
21
20
19
2
17
PGND
3
16
SYS
STAT
4
15
SYS
SCL
5
14
BAT
SDA
6
13
BAT
7
8
9
10
11
12
TS2
PG
TS1
PSEL
ILIM
PGND
CE
18
OTG
1
INT
VBUS
Pin Functions
PIN
TYPE
DESCRIPTION
1,24
P
Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and
PMID with VBUS on source. Place a 1µF ceramic capacitor from VBUS to PGND and place it as close as possible to
IC. (Refer to Application Information Section for details)
PSEL
2
I
Digital
Power source selection input. High indicates a USB host source and Low indicates an adapter source.
PG
3
O
Digital
Open drain active low power good indicator. Connect to the pull up rail via 10kohm resistor. LOW indicates a good
input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current limit is
above 30mA.
STAT
4
O
Digital
Open drain charge status output to indicate various charger operation. Connect to the pull up rail via 10kohm. LOW
indicates charge in progress. HIGH indicates charge complete or charge disabled. When any fault condition occurs,
STAT pin has a 10kΩ resistor to ground.
SCL
5
I
Digital
I2C Interface clock. Connect SCL to the logic rail through a 10kΩ resistor.
SDA
6
I/O
Digital
I2C Interface data. Connect SDA to the logic rail through a 10kΩ resistor.
INT
7
O
Digital
Open-drain Interrupt Output. Connect the INT to a logic rail via 10kΩ resistor. The INT pin sends active low, 256us
pulse to host to report charger device status and fault.
OTG
8
I
Digital
USB current limit selection pin during buck mode, and active high enable pin during boost mode.
NAME
NUMBER
VBUS
In buck mode with USB host (PSEL=High), when OTG = High, IIN limit = 500mA and when OTG = Low, IIN limit =
100mA.
The boost mode is activated when the REG01[5:4]=10 and OTG pin is High.
4
CE
9
I
Digital
Active low Charge Enable pin. Battery charging is enabled when REG01[5:4]=01 and CE pin = Low. CE pin must be
pulled high or low.
ILIM
10
I
Analog
ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 1V. A resistor is connected from ILIM
pin to ground to set the maximum limit as IINMAX = (1V/RILIM) × KILIM. The actual input current limit is the lower one set
by ILIM and by I2C REG00[2:0]. The minimum input current programmed on ILIM pin is 500mA.
TS1
11
I
Analog
Temperature qualification voltage input #1. Connect a negative temperature coefficient thermistor. Program
temperature window with a resistor divider from REGN to TS1 to GND. Charge suspends when either TS pin is out of
range. Recommend 103AT-2 thermistor and do not add decoupling capacitor on TS1 pin.
TS2
12
I
Analog
Temperature qualification voltage input #2. Connect a negative temperature coefficient thermistor. Program
temperature window with a resistor divider from REGN to TS1 to GND. Charge suspends when either TS pin is out of
range. Recommend 103AT-2 thermistor and do not add decoupling capacitor on TS2 pin.
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SLUSBI4B – APRIL 2013 – REVISED DECEMBER 2016
Pin Functions (continued)
PIN
TYPE
DESCRIPTION
13,14
P
Battery connection point to the positive terminal of the battery pack. The internal BATFET is connected between BAT
and SYS. Connect a 10uF closely to the BAT pin.
SYS
15,16
P
System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls below the
minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage. (Refer to
Application Information Section for inductor and capacitor selection)
PGND
17,18
P
Power ground connection for high-current power converter node. Internally, PGND is connected to the source of the
n-channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the
charger. A single point connection is recommended between power PGND and the analog GND near the IC PGND
pin.
SW
19,20
O
Analog
Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and
the drain of the n-channel LSFET. Connect the 0.047µF bootstrap capacitor from SW to BTST.
BTST
21
P
PWM high side driver positive supply. Internally, the BTST is connected to the anode of the boost-strap diode.
Connect the 0.047µF bootstrap capacitor from SW to BTST.
REGN
22
P
PWM low side driver positive supply output. Internally, REGN is connected to the cathode of the boost-strap diode.
For VBUS above 6V, connect 1-µF ceramic capacitor from REGN to analog GND. For VBUS below 6V, connect a
4.7-μF (10V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC.
REGN also serves as bias rail of TS1 and TS2 pins.
PMID
23
O
Analog
Connected to the drain of the reverse blocking MOSFET and the drain of HSFET. Given the total input capacitance,
connect a 1-µF capacitor on VBUS to PGND, and the rest all on PMID to PGND. (See the Application Information
section for details)
Thermal Pad
–
P
NAME
NUMBER
BAT
Exposed pad beneath the IC for heat dissipation. Always solder thermal pad to the board, and have vias on the
thermal pad plane star-connecting to PGND and ground plane for high-current power converter.
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
–2
20
V
PMID, STAT, PG
–0.3
20
V
BTST
–0.3
26
V
–2
20
V
BAT, SYS (converter not switching)
–0.3
6
V
SDA, SCL, INT, OTG, ILIM, REGN, TS1, TS2, CE, PSEL
–0.3
7
V
BTST TO SW
–0.3
7
V
PGND to GND
–0.3
0.3
V
6
mA
VBUS
Voltage range (with respect to
GND)
Output sink current
SW
INT, STAT, PG
Junction temperature
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
MIN
MAX
UNIT
3.9
17 (1)
V
3
A
Output current (SYS)
4.5
A
Battery voltage
4.4
V
Fast charging current
4.5
A
6 (continuous)
9 (peak)
(up to 1 sec duration)
A
85
°C
VIN
Input voltage
IIN
Input current
ISYS
VBAT
IBAT
Discharging current with internal MOSFET
TA
(1)
Operating free-air temperature range
–40
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight
layout minimizes switching noise.
7.4 Thermal Information
bq24292i
THERMAL METRIC (1)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
32.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.8
°C/W
RθJB
Junction-to-board thermal resistance
9.1
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
9.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
7.5 Electrical Characteristics
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QUIESCENT CURRENTS
VVBUS < VUVLO, VBAT = 4.2 V, leakage between
BAT and VBUS
IBAT
Battery discharge current (BAT, SW, SYS)
IVBUS
Input supply current (VBUS)
IOTGBOOST
6
Battery Discharge Current in boost mode
5
µA
High-Z Mode, or no VBUS, BATFET disabled
(REG07[5] = 1), TJ = –40°C – 85°C
12
20
µA
High-Z Mode, or no VBUS, REG07[5] = 0, TJ =
–40°C – 85°C
32
55
µA
VVBUS = 5 V, High-Z mode
15
30
µA
VVBUS = 17 V, High-Z mode
30
50
µA
VVBUS > VUVLO, VVBUS > VBAT, converter not
switching
1.5
3
mA
VVBUS > VUVLO, VVBUS > VBAT, converter switching,
VBAT=3.2V, ISYS=0A
4
mA
VVBUS > VUVLO, VVBUS > VBAT, converter switching,
VBAT=3.8V, ISYS=0A
15
mA
4
mA
VBAT=4.2V, Boost mode, IVBUS = 0A, converter
switching
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Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBUS/BAT POWER UP
VVBUS_OP
VBUS operating range
VVBUS_UVLOZ
VBUS for active I2C, no battery
VVBUS rising
3.9
3.6
17
V
VSLEEP
Sleep mode falling threshold
VVBUS falling, VVBUS-VBAT
35
80
120
mV
VSLEEPZ
Sleep mode rising threshold
VVBUS rising, VVBUS-VBAT
VACOV
VBUS overvoltage rising threshold
VVBUS rising
170
250
350
mV
17.4
18
VACOV_HYST
VBUS Overvoltage Falling Hysteresis
VVBUS falling
V
700
mV
VBAT_UVLOZ
Battery for active I2C, no VBUS
VBAT rising
VBAT_DPL
Battery depletion threshold
VBAT falling
2.4
2.6
V
VBAT_DPL_HY
Battery depletion rising hysteresis
VBAT rising
200
260
mV
VVBUSMIN
Bad adapter detection threshold
VVBUS falling
3.8
V
IBADSRC
Bad adapter detection current source
30
mA
V
2.3
V
POWER PATH MANAGEMENT
VSYS_RANGE
Typical System regulation voltage
ISYS = 0A, Q4 off, VBAT up to 4.2 V,
REG01[3:1]=101, VSYSMIN = 3.5 V
3.5
VSYS_MIN
System voltage output
REG01[3:1]=101, VSYSMIN = 3.5 V
3.55
RON(RBFET)
Internal top reverse blocking MOSFET onresistance
Measured between VBUS and PMID
23
38
RON(HSFET)
Internal top switching MOSFET onresistance between PMID and SW
TJ = –40°C – 85°C
27
35
TJ = –40°C – 125°C
27
45
RON(LSFET)
Internal bottom switching MOSFET onresistance between SW and PGND
TJ = –40°C – 85°C
32
45
TJ = –40°C – 125°C
32
48
VFWD
BATFET forward voltage in supplement
mode
BAT discharge current 10mA
30
mV
VSYS_BAT
SYS/BAT Comparator
VSYS falling
90
mV
VBATGD
Battery good comparator rising threshold
VBAT rising
3.55
V
VBATGD_HYST
Battery good comparator falling threshold
VBAT falling
100
mV
4.35
3.65
V
V
mΩ
mΩ
mΩ
BATTERY CHARGER
VBAT_REG_ACC
Charge voltage regulation accuracy
VBAT = 4.112V and 4.208V
–0.5%
0.5%
VBAT = 3.8V, ICHG = 1792mA, TJ = 25°C
–4%
4%
VBAT = 3.8V, ICHG = 1792mA, TJ = –20°C – 125°C
–7%
7%
150
mA
IICHG_REG_ACC
Fast charge current regulation accuracy
ICHG_20pct
Charge current with 20% option on
VBAT = 3.1V, ICHG = 104mA, REG02=03
75
VBATLOWV
Battery LOWV falling threshold
Fast charge to precharge, REG04[1] = 1
2.6
2.8
2.9
V
VBATLOWV_RISE
Battery LOWV rising threshold
Precharge to fast charge, REG04[1] = 1
2.8
3.0
3.1
V
IPRECHG_ACC
Precharge current regulation accuracy
VBAT = 2.6V, ICHG = 256mA
–20%
ITERM_ACC
Termination current accuracy
ITERM = 256mA, ICHG = 960mA
–20%
VSHORT
Battery Short Voltage
VBAT falling
2
VSHORT_HYST
Battery Short Voltage hysteresis
VBAT rising
200
mV
ISHORT
Battery short current
VBAT VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE/CURRENT REGULATION
VINDPM_REG_ACC
Input voltage regulation accuracy
REG00[6:3]=0110 (4.36V) or 1011 (4.76V)
USB Input current regulation limit, VBUS =
5V, current pulled from SW
IUSB_DPM
–2%
2%
USB100
85
100
mA
USB150
125
150
mA
USB500
440
500
mA
USB900
750
900
mA
1.30
1.55
IADPT_DPM
Input current regulation accuracy
Input current limit 1.5A, REG00[2:0] = 101
IIN_START
Input current limit during system start up
VSYS6V
4.5
V
BOOST MODE OPERATION
VOTG_REG
OTG output voltage
I(VBUS) = 0
VOTG_REG_ACC
OTG output voltage accuracy
I(VBUS) = 0
IOTG
OTG mode output current
VOTG_OVP
OTG overvoltage threshold
IOTG_ILIM
LSFET cycle-by-cycle current limit
IOTG_HSZCP
HSFET under current falling threshold
IRBFET_OCP
RBFET overcurrent threshold
5
–2.5%
REG01[0] = 0
0.5
REG01[0] = 1
1.3
A
A
5.3
3.2
V
2%
5.5
V
4.6
A
100
mA
REG01[0] = 1
1.4
1.8
2.7
REG01[0] = 0
0.6
1.1
1.8
6.4
A
REGN LDO
VREGN
REGN LDO output voltage
IREGN
REGN LDO current limit
8
VVBUS = 10V, IREGN = 40mA
5.6
6
VVBUS = 5V, IREGN = 20mA
4.75
4.8
VVBUS = 10V, VREGN = 3.8V
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50
V
V
mA
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Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC I/O PIN CHARACTERISTICS (OTG, CE, PSEL, STAT, PG)
VILO
Input low threshold
VIH
Input high threshold
0.4
VOUT_LO
Output low saturation voltage
Sink current = 5 mA
IBIAS
High level leakage current
Pull up rail 1.8V
V
1.3
V
0.4
V
1
µA
I2C INTERFACE (SDA, SCL, INT)
VIH
Input high threshold level
VPULLUP = 1.8V, SDA and SCL
VIL
Input low threshold level
VPULLUP = 1.8V, SDA and SCL
1.3
0.4
V
VOL
Output low threshold level
Sink current = 5mA
0.4
V
IBIAS
High-level leakage current
VPULLUP = 1.8V, SDA and SCL
1
µA
V
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
VBUS/BAT POWER UP
tBADSRC
Bad source detection duration
30
ms
BOOST MODE OPERATION
tOTG_DLY
I(VBUS) = 0
From OTG pin high to
VBUS=VOTG_REG
Specified by Design
OTG mode enable delay
22
50
ms
tOTG_OCP_OF OTG mode overcurrent protection off
cycle time
F
32
ms
OTG mode overcurrent protection on
cycle time
100
µs
tOTG_OCP_ON
DIGITAL CLOCK AND WATCHDOG TIMER
fHIZ
Digital crude clock
REGN LDO disabled
15
35
50
kHz
fDIG
Digital clock
REGN LDO enabled
1300
1500
1700
kHz
tWDT
Watchdog timer
REGN LDO enabled
REG05[5:4]=11
136
160
s
I2C INTERFACE (SDA, SCL, INT)
fSCL
SCL clock frequency
400
kHz
7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BATTERY CHARGER
tRECHG
Recharge deglitch time
VBAT falling, REG04[0]=0
20
ms
1
µs
BAT OVERVOLTAGE PROTECTION
tBATOVP
Battery overvoltage deglitch time to
disable charge
THERMAL REGULATION AND THERMAL SHUTDOWN
Thermal shutdown rising deglitch
Temperature increasing delay
1
ms
Thermal shutdown falling deglitch
Temperature decreasing delay
1
ms
PWM OPERATION
FSW
PWM Switching frequency, and
digital clock
1300
1500
1700
kHz
COLD/HOT THERMISTER COMPARATOR
Deglitch time for temperature out of
range detection
VTS > VLTF, or VTS < VTCO, or VTS <
VHTF
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7.8 Typical Characteristics
Table 1. Tables of Figures
FIGURE NO.
Charging Efficiency vs. Charging Current
Figure 1
System Light Load Efficiency vs System Load current
Figure 2
Boost Mode Efficiency vs VBUS Load Current
Figure 3
SYS Voltage Regulation vs System Load
Figure 4
Boost Mode VBUS Voltage Regulation vs VBUS Load Current
Figure 5
SYS Voltage vs Temperature
Figure 6
BAT Voltage vs Temperature
Figure 7
Input Current Limit vs Temperature
Figure 8
Charge Current vs Temperature
Figure 9
95
95
VBUS = 5 V
VBUS = 7 V
VBUS = 9 V
VBUS = 12 V
90
Efficiency (%)
Efficiency (%)
93
91
89
85
80
87
75
85
70
VBUS = 5 V
VBUS = 9 V
0
1
2
3
Load Current (A)
4
0
5
200
300
400
500
Load Current (mA)
600
C012
Figure 2. System Light Load Efficiency vs System Load
Current
Figure 1. Charging Efficiency vs Charging Current
100
100
C011
3.70
VBAT = 3.2 V
VBAT = 3.8 V
3.68
SYS Voltage (V)
Efficiency (%)
95
90
85
3.64
3.62
VBUS = 5 V
VBUS = 17 V
3.60
80
0
500
1000
VBUS Load Current (A)
1500
0
1
2
3
System Load Current (A)
C013
Figure 3. Boost Mode Efficiency vs VBUS Load Current
10
3.66
4
5
C014
Figure 4. SYS Voltage Regulation vs System Load
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5.04
3.80
5.02
3.75
5.00
SYS Voltage (V)
VBUS Voltage (V)
SYSMIN 3.5 V
4.98
4.96
4.94
3.70
3.65
3.60
VBAT = 3.2 V
4.92
3.55
VBAT = 3.8 V
VBAT = 4.2 V
4.90
0
200
400
3.50
600
800
1000
1200
±50
1400
VBUS Load Current (A)
0
50
100
Temperature (ƒC)
C005
Figure 5. Boost Mode VBUS Voltage Regulation vs VBUS
Load Current
150
C001
Figure 6. SYS Voltage vs Temperature
4.25
2000
1800
Input Current Limit (A)
BAT Voltage (V)
4.21
4.17
4.13
4.09
1600
1400
1200
1000
IIN = 500 mA
800
IIN = 1.5 A
600
IIN = 2 A
VREG = 4.112 V
VREG = 4.208 V
4.05
400
±50
0
50
100
±50
150
Temperture (ƒC)
0
50
100
Temperature (ƒC)
C002
Figure 7. BAT Voltage vs Temperature
150
C003
Figure 8. Input Current Limit vs Temperature
5
4.5
Charge Current (A)
4
3.5
3
2.5
2
1.5
1
TREG 80 C
TREG 120 C
0.5
0
40
50
60
70
80
90
100
110
120
Temperature (°C)
130
C009
Figure 9. Charge Current vs Temperature
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8 Detailed Description
8.1 Overview
The bq24292i is an I2C controlled power path management device and a single cell Li-Ion battery charger. It
integrates the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side
switching FET (LSFET, Q3), and BATFET (Q4) between system and battery. The device also integrates the
bootstrap diode for the high-side gate drive.
8.2 Functional Block Diagram
VBUS
PMID
Q1
V(VBUS_UVLOZ)
UVLO
Q1 Gate
Control
V(BATZ) + V(SLEEP)
SLEEP
REGN
REGN
LDO
EN_HIZ
ACOV
V(ACOV)
BTST
FBO
VBUS
VBUS_OVP_BOOST
V(OTG_OVP)
I(Q2)
VINDPM
I(OTG_HSZCP)
IINDPM
I(OTG_ILIM)
Q2_UCP_BOOST
SW
I(Q3)
Q3_OCP_BOOST
BAT
BATOVP
V(BAT_REG) x V(BATOVP)
IC TJ
CONVERTER
CONTROL
Q2
REGN
BAT
TREG
I(LSFET_UCP)
VBAT_REG
SYS
UCP
Q2_OCP
I(Q3)
VSYSMIN
ICHG_REG
EN_HIZ
EN_CHARGE
EN_BOOST
REFRESH
I(Q2)
Q3
PGND
I(HSFET_OCP)
V(BTST-SW)
V(BTST_REFRESH)
SYS
ICHG
VBAT_REG
ICHG_REG
REF
DAC
I(BADSRC)
BAD_SRC
CONVERTER
CONTROL
TSHUT
STATE
MACHINE
ILIM
PSEL
USB Host
Adapter
Detection
USB
Adapter
1.5A
BAT
OTG
RECHRG
INT
BAT
V(BATGD)
V(BAT_REG) - V(RECHG)
BAT
ICHG
ITERM
TERMINATION
STAT
PG
I2C
Interface
SCL
12
SDA
BATSHORT
Q4
IDC
IC TJ
TSHUT
BAT_GD
CHARGE
CONTROL
SUSPEND
STATE
MACHINE BATLOWV
Q4 Gate
Control
V(BATLOWV)
BAT
BATTERY
THERMISTER
SENSING
TS1
TS2
V(SHORT)
BAT
CE
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8.3 Feature Description
8.3.1 Device Power Up
8.3.1.1 Power-On-Reset (POR)
The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS or VBAT rises
above UVLOZ, the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface
is ready for communication and all the registers are reset to default value. The host can access all the registers
after POR.
8.3.1.2 Power Up from Battery without DC Source
If only battery is present and the voltage is above depletion threshold (VBAT_DEPL), the BATFET turns on and
connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDSON in
BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
The device always monitors the discharge current through BATFET. When the system is overloaded or shorted,
the device will immediately turn off BATFET and keep BATFET off until the input source plugs in again.
8.3.1.2.1 BATFET Turn Off
The BATFET can be forced off by the host through I2C REG07[5]. This bit allows the user to independently turn
off the BATFET when the battery condition becomes abnormal during charging. When BATFET is off, there is no
path to charge or discharge the battery.
When battery is not attached, the BATFET should be turned off by setting REG07[5] to 1 to disable charging and
supplement mode.
8.3.1.2.2 Shipping Mode
When end equipment is assembled, the system is connected to battery through BATFET. There will be a small
leakage current to discharge the battery even when the system is powered off. To extend the battery life during
shipping and storage, the device can turn off BATFET so that the system voltage is zero to minimize the leakage.
To keep BATFET off during shipping mode, the host has to disable the watchdog timer (REG05[5:4]=00) and
disable BATFET (REG07[5]=1) at the same time.
Once the BATFET is disabled, the BATFET can be turned on by plugging in adapter.
8.3.1.3 Power Up from DC Source
When the DC source plugs in, the device checks the input source voltage to turn on REGN LDO and all the bias
circuits. It also checks the input current limit before starts the buck converter.
8.3.1.3.1 REGN LDO
The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also
provides bias rail to TS1/TS2 external resistors. The pullup rail of STAT and PG can be connected to REGN as
well.
The REGN is enabled when all of the following conditions are valid:
• VBUS above UVLOZ
• VBUS above battery + VSLEEPZ in buck mode or VBUS below battery + VSLEEPZ in boost mode
• After typical 220ms delay (100ms minimum) is complete
If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The
device draws less than 50µA from VBUS during HIZ state. The battery powers up the system when the device is
in HIZ.
8.3.1.3.2 Input Source Qualification
After REGN LDO powers up, the device checks the current capability of the input source. The input source has
to meet the following requirements to start the buck converter.
1. VBUS voltage below 18V (not in ACOV)
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Feature Description (continued)
2. VBUS voltage above 3.8V when pulling 30mA (poor source detection)
Once the input source passes all the conditions above, the status register REG08[2] goes high and the PG pin
goes low. An INT is asserted to the host.
If the device fails the poor source detection, it will repeat the detection every 2 seconds.
8.3.1.3.3 Input Current Limit Detection
The USB ports on personal computers are convenient charging source for portable devices (PDs). If the portable
device is attached to a USB host, the USB specification requires the portable device to draw limited current
(100mA/500mA in USB 2.0, and 150mA/900mA in USB 3.0). If the portable device is attached to a charging port,
it is allowed to draw up to 1.5A.
After the PG is LOW or REG08[2] goes HIGH, the charger device always runs input current limit detection when
a DC source plugs in unless the charger is in HIZ during host mode.
The device sets input current limit through PSEL and OTG pins.
After the input current limit detection is done, the host can write to REG00[2:0] to change the input current limit.
8.3.1.3.4 PSEL/OTG Pins Set Input Current Limit
The device has PSEL which directly takes the USB PHY device output to decide whether the input is USB host
or charging port.
Table 2. Input Current Limit Detection
PSEL
OTG
INPUT CURRENT LIMIT
REG08[7:6]
HIGH
LOW
100 mA
01
HIGH
HIGH
500 mA
01
LOW
—
1.5A
10
8.3.1.3.5 HIZ State wth 100mA USB Host
In battery charging spec, the good battery threshold is the minimum charge level of a battery to power up the
portable device successfully. When the input source is 100mA USB host, and the battery is above bat-good
threshold (VBATGD), the device follows battery charging spec and enters high impedance state (HIZ). In HIZ state,
the device is in the lowest quiescent state with REGN LDO and the bias circuits off. The charger device sets
REG00[7] to 1, and the VBUS current during HIZ state will be less than 30µA. The system is supplied by the
battery.
Once the charger device enters HIZ state in host mode, it stays in HIZ until the host writes REG00[7]=0. When
the processor host wakes up, it is recommended to first check if the charger is in HIZ state.
In default mode, the charger IC will reset REG00[7] back to 0 when input source is removed. When another
source plugs in, the charger IC will run detection again, and update the input current limit.
8.3.1.3.6 Force Input Current Limit Detection
The host can force the charger device to run input current limit detection by setting REG07[7]=1. After the
detection is complete, REG07[7] will return to 0 by itself.
8.3.1.4 Converter Power-Up
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft-start when ramp up the system rail. When the system rail is below 2.2V, the input
current limit is forced to 100mA. After the system rises above 2.2V, the charger device sets the input current limit
set by the lower value between register and ILIM pin.
As a battery charger, the device deploys a 1.5MHz step-down switching regulator. The fixed frequency oscillator
keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current
and temperature, simplifying output filter design.
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A type III compensation network allows using ceramic capacitors at the output of the converter. An internal sawtooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp
height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.
To improve light-load efficiency, the device switches to PFM control at light load when battery is below minimum
system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is set by the
ratio of SYS and VBUS.
8.3.1.5 Boost Mode Operation from Battery
The device can operate in boost converter mode to support USB On-The-Go (OTG) standard with fast startup
and deliver power from the battery to other portable devices through USB port. The boost mode output current
rating meets the USB On-The-Go 500mA output requirement. The maximum output current is 1.3A. The boost
operation can be enabled only if all of the following conditions are valid:
• BAT above BATLOWV threshold (VBATLOWV set by REG04[1])
• VBUS less than BAT+VSLEEP (in sleep mode)
• Boost mode operation is enabled (OTG pin HIGH and REG01[5:4]=10)
• After tOTG_DLY (22ms typical) delay from boost mode enable
In boost mode, the device employs a 1.5MHz step-up switching regulator. Similar to buck operation, the device
switches from PWM operation to PFM operation at light load to improve efficiency.
During boost mode, the status register REG08[7:6] is set to 11, the VBUS output is 5V and the output current
can reach up to 500mA or 1.3A, selected via I2C (REG01[0]).
Any fault during boost operation, including VBUS overvoltage or overcurrent, sets the fault register REG09[6] to 1
and an INT is asserted.
8.3.2 Power Path Management
The device accommodates a wide range of input sources from USB, wall adapter, to car battery. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.
8.3.2.1 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The
minimum system voltage is set by REG01[3:1]. Even with a fully depleted battery, the system is regulated above
the minimum system voltage (default 3.5V).
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),
and the system is 150mV above the minimum system voltage setting. As the battery voltage rises above the
minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the
VDS of BATFET.
When the battery charging is disabled or terminated, the system is always regulated at 150mV above the
minimum system voltage setting. The status register REG08[0] goes high when the system is in minimum system
voltage regulation.
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4.5
4.3
Charge Enabled
4.1
SYS
(V)
Charge Disabled
3.9
3.7
3.5
Minimum System Voltage
3.3
3.1
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
BAT (V)
Figure 10. V(SYS) vs V(BAT)
8.3.2.2 Dynamic Power Management
To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic
Power Management (DPM), which continuously monitors the input current and input voltage.
When input source is over-loaded, either the current exceeds the input current limit (REG00[2:0]) or the voltage
falls below the input voltage limit (REG00[6:3]). The device then reduces the charge current until the input current
falls below the input current limit and the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to
drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement
mode where the BATFET turns on and battery starts discharging so that the system is supported from both the
input source and battery.
During DPM mode (either VINDPM or IINDPM), the status register REG08[3] will go high.
Figure 11 shows the DPM response with 9V/1.2A adapter, 3.2V battery, 2.8A charge current and 3.4V minimum
system voltage setting.
Voltage
VBUS
9V
SYS
3.6V
3.4V
3.2V
3.18V
BAT
Current
4A
ICHG
3.2A
2.8A
ISYS
1.2A
1.0A
0.5A
IIN
-0.6A
DPM
DPM
Supplement
Figure 11. DPM Response
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8.3.2.3 Supplement Mode
When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is
regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30mV when the current is low.
This prevents oscillation from entering and exiting the supplement mode. As the discharge current increases, the
BATFET gate is regulated with a higher voltage to reduce RDSON until the BATFET is in full conduction. At this
point onwards, the BATFET VDS linearly increases with discharge current. Figure 12 shows the V-I curve of the
BATFET gate regulation operation. BATFET turns off to exit supplement mode when the battery is below battery
depletion threshold.
4.5
4.0
CURRENT (A)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
5
10
15
20
25
30
35
40
45
50
55
V(BAT-SYS) (mV)
Figure 12. BATFET V-I Curve
8.3.3 Battery Charging Management
The device charges 1-cell Li-Ion battery with up to 4.5A charge current for high capacity tablet battery. The 12mΩ
BATFET improves charging efficiency and minimizes the voltage drop during discharging.
8.3.3.1 Autonomous Charging Cycle
With battery charging enabled at POR (REG01[5:4]=01), the device can complete a charging cycle without host
involvement. The device default charging parameters are listed in .
Table 3. Charging Parameter Default Setting
A
•
•
•
•
•
DEFAULT MODE
bq24292i
Charging Voltage
4.112 V
Charging Current
1.024 A
Pre-charge Current
256 mA
Termination Current
256 mA
Temperature Profile
Hot/Cold
Safety Timer
8 hours
new charge cycle starts when the following conditions are valid:
Converter starts
Battery charging is enabled by I2C register bit (REG01[5:4]) = 01 and CE is low
No thermistor fault on TS1 and TS2
No safety timer fault
BATFET is not forced to turn off (REG07[5])
The charger device automatically terminates the charging cycle when the charging current is below termination
threshold and charge voltage is above recharge threshold. When a full battery voltage is discharged below
recharge threshold (REG04[0]), the device automatically starts another charging cycle. After charging is done,
either toggle CE pin or REG01[5:4] will initiate a new charging cycle.
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The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH)
or charging fault (Blinking). The status register REG08[5:4] indicates the different charging phases: 00-charging
disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a
charging cycle is complete, an INT is asserted to notify the host.
The host can always control the charging operation and optimize the charging parameters by writing to the
registers through I2C.
8.3.3.2 Battery Charging Profile
The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the
beginning of a charging cycle, the device checks the battery voltage and applies current.
Table 4. Charging Current Setting
VBAT
CHARGING CURRENT
REG DEFAULT SETTING
REG08[5:4]
3V
REG02[7:2]
1024mA
10
If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will
be less than the programmed value. In this case, termination is temporarily disabled and the charging safety
timer is counted at half the clock rate.
Regulation Voltage
(3.5V – 4.4V)
Battery Voltage
Fast Charge Current
(500mA-4020mA)
Charge Current
VBAT_LOWV (2.8V/3V)
VBAT_SHORT (2V)
IPRECHARGE (128mA-2048mA)
ITERMINATION (128mA-2048mA)
IBATSHORT (100mA)
Trickle Charge
Pre-charge
Fast Charge and Voltage Regulation
Safety Timer
Expiration
Figure 13. Battery Charging Profile
8.3.3.3 Battery Path Impedance IR Compensation
To speed up the charging cycle, we would like to stay in constant current mode as long as possible. In real
system, the parasitic resistance, including routing, connector, MOSFETs and sense resistor in the battery pack,
may force the charger device to move from constant current loop to constant voltage loop too early, extending
the charge time.
The device allows the user to compensate for the parasitic resistance by increasing the voltage regulation set
point according to the actual charge current and the resistance. For safe operation, the user should set the
maximum allowed regulation voltage to REG06[4:2], and the minimum trace parasitic resistance (REG06[7:5]).
(
)
VBATREG_ACTUAL = VBATREG_I2C + lower of ICHRG_ACTUAL × RCOMP and VCLAMP
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8.3.3.4 Thermistor Qualification
The high capacity battery usually has two or more single cells in parallel. The device provides two TS pins to
monitor the thermistor (NTC) in each cell independently.
8.3.3.4.1 Cold/Hot Temperature Window
The device continuously monitors battery temperature by measuring the voltage between the TS pins and
ground, typically determined by a negative temperature coefficient thermistor and an external voltage divider. The
device compares this voltage against its internal thresholds to determine if charging is allowed. To initiate a
charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. During the charge cycle the
battery temperature must be within the VLTF to VTCO thresholds, else the device suspends charging and waits
until the battery temperature is within the VLTF to VHTF range.
REGN
bq2429x
RT1
TS
RT2
RTH
103AT
Figure 14. TS Resistor Network
When the TS fault occurs, the fault register REG09[2:0] indicates the actual condition on each TS pin and an INT
is asserted to the host. The STAT pin indicates the fault when charging is suspended.
TEMPERATURE RANGE TO
INITIATE CHARGE
TEMPERATURE RANGE
DURING A CHARGE CYCLE
VREGN
VREGN
CHARGE SUSPENDED
CHARGE SUSPENDED
VLTF
VLTF
VLTFH
VLTFH
CHARGE at full C
CHARGE at full C
VHTF
VTCO
CHARGE SUSPENDED
CHARGE SUSPENDED
AGND
AGND
Figure 15. TS Pin Thermistor Sense Thresholds
Assuming a 103AT NTC thermistor is used on the battery pack Equation 2, the value RT1 and RT2 can be
determined by using the following equation:
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æ 1
1 ö
VREGN ´ RTHCOLD ´ RTHHOT ´ ç
÷
è VLTF VTCO ø
RT2 =
æV
ö
æV
ö
RTHHOT ´ ç REGN - 1÷ - RTHCOLD ´ ç REGN - 1÷
è VLTF
ø
è VTCO
ø
VREGN
-1
VLTF
RT1 =
1
1
+
RT2 RTHCOLD
(2)
Select 0°C to 45°C range for Li-ion or Li-polymer battery,
RTHCOLD = 27.28 kΩ
RTHHOT = 4.911 kΩ
RT1 = 5.52 kΩ
RT2 = 31.23 kΩ
8.3.3.5 Charging Termination
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is complete, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn back on to engage supplement mode.
When termination occurs, the status register REG08[5:4] is 11, and an INT is asserted to the host. Termination is
temporarily disabled if the charger device is in input current/voltage regulation or thermal regulation. Termination
can be disabled by writing 0 to REG05[7].
8.3.3.5.1 Termination when FORCE_20PCT (REG02[0]) = 1
When REG02[0] is HIGH to reduce the charging current by 80%, the charging current could be less than the
termination current. The charger device termination function should be disabled. When the battery is charged to
fully capacity, the host can disable charging through CE pin or REG01[5:4].
8.3.3.5.2 Termination when TERM_STAT (REG05[6]) = 1
Usually the STAT bit indicates charging complete when the charging current falls below termination threshold.
Write REG05[6]=1 to enable an early “charge done” indication on STAT pin. The STAT pin goes high when the
charge current reduces below 800mA. The charging cycle is still on-going until the current falls below the
termination threshold.
8.3.3.6 Charging Safety Timer
The device has safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety
timer is 2 hours when the battery is below BATLOWV threshold. The user can program fast charge safety timer
through I2C (REG05[2:1]). When safety timer expires, the fault register REG09[5:4] goes 11 and an INT is
asserted to the host. The safety timer feature can be disabled via I2C (REG05[3]). The following actions restart
the safety timer:
The following actions restart the safety timer:
• At the beginning of a new charging cycle
• Toggle the CE pin HIGH to LOW to HIGH (charge enable)
• Write REG01[5:4] from 00 to 01 (charge enable)
• Write REG05[3] from 0 to 1 (safety timer enable)
During input voltage/current regulation, thermal regulation, or when FORCE_20PCT (REG02[0]) bit is set, , the
safety timer counts at half clock rate since the actual charge current is likely to be below the register setting. For
example, if the charger is in input current regulation (IINDPM) throughout the whole charging cycle, and the
safety time is set to 5 hours, the safety timer will expire in 10 hours. This feature can be disabled by writing 0 to
REG07[6].
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It is recommended to disable safety timer first by clearing REG05[3] bit before safety timer configuraiton is
changed. The safety timer can be re-enabled by setting REG05[3] bit.
8.3.3.7 USB Timer when Charging from USB100mA Source
The total charging time in default mode from USB100mA source is limited by a 45-min max timer. At the end of
the timer, the device stops the converter and goes to HIZ.
8.3.4 Status Outputs (PG, STAT, and INT)
8.3.4.1 Power Good Indicator (PG)
The PG in the device goes LOW to indicate a good input source when all of the following conditions are met:
• VBUS above UVLO
• VBUS above battery (not in sleep)
• VBUS below ACOV threshold
• VBUS above 3.8V when 30mA current is applied (not a poor source)
8.3.4.2 Charging Status Indicator (STAT)
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as the application
diagram shows.
Table 5. STAT Pin State
CHARGING STATE
STAT
Charging in progress (including recharge)
LOW
Charging complete
HIGH
Sleep mode, charge disable
HIGH
Charge suspend (Input overvoltage, TS fault, timer fault, input or system
overvoltage)
10kΩ pull down
When a fault occurs, instead of blinking, the STAT pin in the charger device has a 10kΩ pulldown resistor to
ground. When the pullup resistor is 30kΩ, the STAT voltage during fault is 1/4 of the pullup rail.
8.3.4.3 Interrupt to Host (INT)
In some applications, the host does not always monitor the charger operation. The INT notifies the system on the
device operation. The following events will generate 256us INT pulse.
• USB/adapter source identified (through PSEL and OTG pins)
• Good input source detected
– Not in sleep
– Not in ACOV
– Current limit above 30mA
• Input removed or ACOV
• Charge Complete
• Any FAULT event in REG09
When a fault occurs, the charger device sends out INT and latches the fault state in REG09 until the host reads
the fault register. Before the host reads REG09, the charger device would not send any INT upon new faults
except NTC fault (REG09[2:0]). The NTC fault is not latched and always reports the current thermistor
conditions. To read the current fault status, the host has to read REG09 two times consecutively. The 1st reads
fault register status from the last INT and the 2nd reads the current fault register status.
8.3.5 Protections
8.3.5.1 Input Current Limit on ILIM
For safe operation, the device has an additional hardware pin on ILIM to limit maximum input current on ILIM pin.
The input maximum current is set by a resistor from ILIM pin to ground as:
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I INMAX =
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1V
´ KILIM
RILIM
(3)
The actual input current limit is the lower value between ILIM setting and register setting (REG00[2:0]). For
example, if the register setting is 111 for 3A, and ILIM has a 353Ω resistor to ground for 1.5A, the input current
limit is 1.5A. ILIM pin can be used to set the input current limit rather than the register settings.
The device regulates ILIM pin at 1V. If ILIM voltage exceeds 1V, the device enters input current regulation (Refer
to Dynamic Power Path Management section).
The voltage on ILIM pin is proportional to the input current. ILIM pin can be used to monitor the input current
following Equation 4:
V
I IN = ILIM ´ IINMAX
(4)
1V
For example, if ILIM pin sets 2A, and the ILIM voltage is 0.6V, the actual input current 1.2A. If ILIM pin is open,
the input current is limited to zero since ILIM voltage floats above 1V. If ILIM pin is short, the input current limit is
set by the register.
8.3.5.2 Thermal Regulation and Thermal Shutdown
The charger device monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC
surface temperature. When the internal junction temperature exceeds the preset limit (REG06[1:0]), the device
lowers down the charge current. The wide thermal regulation range from 60°C to 120°C allows the user to
optimize the system thermal performance.
During thermal regulation, the actual charging current is usually below the programmed battery charging current.
Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register REG08[1]
goes high.
Additionally, the device has thermal shutdown to turn off the converter. The fault register REG09[5:4] is 10 and
an INT is asserted to the host.
8.3.5.3 Voltage and Current Monitoring in Buck Mode
The charger device closely monitors the input and system voltage, as well as HSFET and LSFET current for safe
buck mode operation.
8.3.5.3.1 Input Overvoltage (ACOV)
The maximum input voltage for buck mode operation is 18V. If VBUS voltage exceeds 18V, the device stops
switching immediately. During input over voltage (ACOV), the fault register REG09[5:4] will be set to 01. An INT
is asserted to the host.
8.3.5.3.2 System Overvoltage Protection (SYSOVP)
The charger device monitors the voltage at SYS. When system overvoltage is detected, the converter is stopped
to protect components connected to SYS from high voltage damage.
8.3.5.4 Overcurrent Protection in Boost Mode
The charger device closely monitors the Q1, Q2(HSFET) and Q3(LSFET) current to ensure safe boost mode
operation. During overcurrent condition, the device will operate in hiccup mode for protection. While in hiccup
mode cycle, the device turns off Q1 FET for tOTG_OCP_OFF (32ms typical) and turns on Q1 FET for
tOTG_OCP_ON(100us typical) in an attempt to restart. If the overcurrent condition is removed, the boost converter
will maintain the Q1 FET on state and the VBUS OTG output will operate normally. When overcurrent condition
continues to exist, the device will repeat the hiccup cycle until overcurrent condition is removed.
8.3.5.4.1 VBUS Overvoltage Protection in Boost Mode
The boost mode regulated output is 5V. When an adapter plugs in during boost mode, the VBUS voltage will rise
above regulation target. Once the VBUS voltage exceeds VOTG_OVP, the charger device stops switching and the
device exits boost mode. The fault register REG09[6] is set high to indicate fault in boost operation. An INT is
asserted to the host.
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8.3.5.5 Battery Protection
8.3.5.5.1 Battery Overcurrent Protection (BATOVP)
The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage
occurs, the charger device immediately disables charge. The fault register REG09[5] goes high and an INT is
asserted to the host.
8.3.5.5.2 Charging During Battery Short Protection
If the battery voltage falls below 2V, the charge current is reduced to 100mA for battery safety.
8.3.5.5.3 System Overcurrent Protection
If the system is shorted or exceeds the overcurrent limit, the BATFET is latched off. DC source insertion on
VBUS is required to reset the latch-off condition and turn on BATFET.
8.3.6 Serial Interface
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2CTM is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP
Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices
can be considered as masters or slaves when performing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device
addressed is considered a slave.
The device operates as a slave device with address 6BH, receiving control inputs from the master device like
micro controller or a digital signal processor. The I2C interface supports both standard mode (up to 100kbits), and
fast mode (up to 400kbits).
Both SDA and SCL are bi-directional lines, connecting to the positive supply voltage via a current source or
pullup resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.
8.3.6.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
SDA
SCL
Data line stable;
Data valid
Change
of data
allowed
Figure 16. Bit Transfer on the I2C Bus
8.3.6.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
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SDA
SDA
SCL
SCL
STOP (P)
START (S)
Figure 17. START and STOP conditions
8.3.6.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data
transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
Acknowledgement
signal from receiver
Acknowledgement
signal from slave
MSB
SDA
SCL
S or Sr
2
1
7
8
START or
Repeated
START
2
1
9
ACK
8
9
ACK
P or Sr
STOP or
Repeated
START
Figure 18. Data Transfer on the I2C Bus
8.3.6.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge 9th clock pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
8.3.6.5 Slave Address and Data Direction Bit
After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction
bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
SDA
SCL
S
1-7
8
9
START
ADDRESS
R/W
ACK
8
1-7
DATA
9
8
1-7
ACK
DATA
9
P
ACK
STOP
Figure 19. Complete Data Transfer
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8.3.6.5.1 Single Read and Write
1
7
1
1
8
1
8
1
1
S
Slave Address
0
ACK
Reg Addr
ACK
Data Addr
ACK
P
Figure 20. Single Write
1
7
1
1
8
1
1
S
Slave Address
0
ACK
Reg Addr
ACK
S
7
1
1
Slave Address
1
ACK
8
1
1
Data
NCK
P
Figure 21. Single Read
If the register address is not defined, the charger IC send back NACK and go back to the idle state.
8.3.6.5.2 Multi-Read and Multi-Write
The charger device supports multi-read and multi-write on REG00 through REG08.
1
7
1
1
8
1
S
Slave Address
0
ACK
Reg Addr
ACK
8
1
8
1
8
1
1
Slave Address
ACK
Data to Addr+1
ACK
Data to Addr+1
ACK
P
Figure 22. Multi-Write
1
7
1
1
8
1
1
7
1
1
S
Slave Address
0
ACK
Reg Addr
ACK
S
Slave Address
1
ACK
8
Data @ Addr
1
8
1
8
1
1
ACK
Data @ Addr+1
ACK
Data @ Addr+1
ACK
P
Figure 23. Multi-Read
The fault register REG09 locks the previous fault and only clears it after the register is read. For example, if
Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the fault when it
is read the first time, but returns to normal when it is read the second time. To verify real time fault, the fault
register REG09 should be read twice to get the real condition. In addition, the fault register REG09 does not
support multi-read or multi-write.
8.4 Device Functional Modes
8.4.1 Host Mode and Default Mode
The device is a host controlled device, but it can operate in default mode without host management. In default
mode, device can be used as an autonomous charger with no host or with host in sleep.
When the charger is in default mode, REG09[7] is HIGH. When the charger is in host mode, REG09[7] is LOW.
After power-on-reset, the device starts in watchdog timer expiration state, or default mode. All the registers are in
the default settings.
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Device Functional Modes (continued)
Any write command to the device transitions the device from default mode to host mode. All the device
parameters can be programmed by the host. To keep the device in host mode, the host has to reset the
watchdog timer by writing 1 to REG01[6] before the watchdog timer expires (REG05[5:4]), or disable watchdog
timer by setting REG05[5:4]=00.
POR
watchdog timer expired
Reset registers
I2C interface enabled
Host Mode
Y
I2C Write?
Start watchdog timer
Host programs registers
N
Default Mode
Reset watchdog timer
Reset registers
N
Y
Reset REG01
bit[6]?
Y
N
I2C Write?
Y
N
Watchdog Timer
Expired?
Figure 24. Watchdog Timer Flow Chart
8.4.1.1 Plug in USB 100mA Source with Good Battery
When the input source is detected as 100mA USB host, and the battery voltage is above batgood threshold
(VBATGD), the charger device enters HIZ state to meet the battery charging spec requirement.
If the charger device is in host mode, it will stay in HIZ state even after the USB100mA source is removed, and
the adapter plugs in. During the HIZ state, REG00[7] is set HIGH and the system load is supplied from battery. It
is recommended that the processor host always checks if the charger IC is in HIZ state when it wakes up. The
host can write REG00[7] to 0 to exit HIZ state.
If the charger is in default mode, when the DC source is removed, the charger device will get out of HIZ state
automatically. When the input source plugs in again, the charger IC runs detection on the input source and
update the input current limit.
8.4.1.2 USB Timer when Charging from USB100mA Source
The total charging time in default mode from USB100mA source is limited by a 45-min max timer. At the end of
the timer, the device stops the converter and goes to HIZ.
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8.5 Register Map
Table 6. Register Map
REGISTER
REGISTER NAME
RESET
REG00
Input Source Control Register
00111101, or 3D
REG01
Power-On Configuration Register
00011011, or 1B
REG02
Charge Current Control Register
00100000, or 20
REG03
Pre-Charge/Termination Current Control Register
00010001, or 11
REG04
Charge Voltage Control Register
10011010, or 9A
REG05
Charge Termination/Timer Control Register
10011010, or 9A
REG06
IR Compensation / Thermal Regulation Control Register
00000011, or 03
REG07
Misc Operation Control Register
01001011, or 4B
REG08
System Status Register
—
REG09
Fault Register
—
REG0A
Vender / Part / Revision Status Register
—
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8.5.1 I2C Registers
Address: 6BH. REG00-07 support Read and Write. REG08-0A are read only.
8.5.1.1 Input Source Control Register REG00 (reset = 00111000, or 3D)
Figure 25. REG00 Input Source Control Register Format
7
EN_HIZ
R/W
6
VINDPM[3]
R/W
5
VINDPM[2]
R/W
4
VINDPM[1]
R/W
3
VINDPM[0]
R/W
2
IINLIM[2]
R/W
1
IINLIM[1]
R/W
0
IINLIM[0]
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. REG00 Input Source Control Register Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
Bit 7
EN_HIZ
R/W
0
0 – Disable, 1 – Enable
Default: Disable (0)
Offset 3.88V, Range: 3.88V-5.08V
Default: 4.44V (0111)
INPUT VOLTAGE LIMIT
Bit 6
VINDPM[3]
R/W
0
640mV
Bit 5
VINDPM[2]
R/W
1
320mV
Bit 4
VINDPM[1]
R/W
1
160mV
Bit 3
VINDPM[0]
R/W
1
80mV
INPUT CURRENT LIMIT (ACTUAL INPUT CURRENT LIMIT IS THE LOWER OF I 2C AND ILIM)
Bit 2
IINLIM[2]
R/W
1
Bit 1
IINLIM[1]
R/W
0
Bit 0
IINLIM[0]
R/W
1
000 – 100mA, 001 – 150mA, 010 –
500mA,
011 – 900mA, 100 – 1.2A, 101 –
1.5A,
110 – 2A, 111 – 3A
Default SDP: 100mA (000)(OTG pin=0) or
500mA (010)
(OTG pin=1)
Default DCP/CDP: 1.5A (101)
8.5.1.2 Power-On Configuration Register REG01 (reset = 00011011, or 1B)
Figure 26. REG01 Power-On Configuration Register Format
7
6
Register Reset I2C Watchdog
Timer Reset
R/W
R/W
5
CHG_CONFIG[1]
4
CHG_CONFIG[0]
3
SYS_MIN[2]
2
SYS_MIN[1]
1
SYS_MIN[0]
0
BOOST_LIM
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. REG01 Power-On Configuration Register Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
NOTE
Bit 7
Register Reset
R/W
0
0 – Keep current register setting,
1 – Reset to default
Default: Keep current register setting (0)
Back to 0 after register reset
Bit 6
I2C Watchdog
Timer Reset
R/W
0
0 – Normal ; 1 – Reset
Default: Normal (0)
Back to 0 after timer reset
00 – Charge Disable, 01 – Charge
Battery,
10/11 – OTG
Default: Charge Battery (01)
Offset: 3.0V, Range 3.0V-3.7V
Default: 3.5V (101)
CHARGER CONFIGURATION
Bit 5
CHG_CONFIG[1]
R/W
0
Bit 4
CHG_CONFIG[0]
R/W
1
MINIMUM SYSTEM VOLTAGE LIMIT
Bit 3
SYS_MIN[2]
R/W
1
0.4V
Bit 2
SYS_MIN[1]
R/W
0
0.2V
Bit 1
SYS_MIN[0]
R/W
1
0.1V
1
0 – 500mA, 1 – 1.3A
BOOST MODE CURRENT LIMIT
Bit 0
28
BOOST_LIM
R/W
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8.5.1.3 Charge Current Control Register REG02 (reset = 00100000, or 20)
Figure 27. REG02 Charge Current Control Register Format
7
ICHG[5]
R/W
6
ICHG[4]
R/W
5
ICHG[3]
R/W
4
ICHG[2]
R/W
3
ICHG[1]
R/W
2
ICHG[0]
R/W
1
Reserved
R/W
0
FORCE_20PCT
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. REG02 Charge Current Control Register Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
NOTE
Offset: 512mA
Range: 512-4544mA
Default: 1024mA (001000)
FAST CHARGE CURRENT LIMIT
Bit 7
ICHG[5]
R/W
0
2048mA
Bit 6
ICHG[4]
R/W
0
1024mA
Bit 5
ICHG[3]
R/W
1
512mA
Bit 4
ICHG[2]
R/W
0
256mA
Bit 3
ICHG[1]
R/W
0
128mA
Bit 2
ICHG[0]
R/W
0
64mA
Bit 1
Reserved
R/W
0
0 - Reserved
Bit 0
FORCE_20PCT
R/W
0
0 – ICHG as REG02[7:2] (Fast
Charge Current Limit) and
REG03[7:4] (Pre-Charge Current
Limit) programmed
1 – ICHG as 20% of REG02[7:2]
(Fast Charge Current Limit) and
50% of REG03[7:4] (Pre-Charge
Current Limit) programmed
Default: (0) ICHG as 20% of REG02[7:2] (Fast
Charge Current Limit) and 50% of REG03[7:4]
(Pre-Charge Current Limit) programmed
8.5.1.4 Pre-Charge/Termination Current Control Register REG 03 (reset = 00010001, or 11)
Figure 28. REG03 Pre-Charge/Termination Current Control Register Format
7
IPRECHG[3]
R/W
6
IPRECHG[2]
R/W
5
IPRECHG[1]
R/W
4
IPRECHG[0]
R/W
3
ITERM[3]
R/W
2
ITERM[2]
R/W
1
ITERM[1]
R/W
0
ITERM[0]
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. REG03 Pre-Charge/Termination Current Control Register Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
NOTE
Offset: 128mA,
Range: 128mA – 640mA
Default: 256mA (0001)
PRE-CHARGE CURRENT LIMIT
Bit 7
IPRECHG[3]
R/W
0
1024mA
Bit 6
IPRECHG[2]
R/W
0
512mA
Bit 5
IPRECHG[1]
R/W
0
256mA
Bit 4
IPRECHG[0]
R/W
1
128mA
TERMINATION CURRENT LIMIT
Bit 3
ITERM[3]
R/W
0
1024mA
Bit 2
ITERM[2]
R/W
0
512mA
Bit 1
ITERM[1]
R/W
0
256mA
Bit 0
ITERM[0]
R/W
1
128mA
Offset: 128mA
Range: 128mA – 2048mA
Default: 256mA (0001)
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8.5.1.5 Charge Voltage Control Register REG04 (reset = 10011010, or 9A)
Figure 29. REG04 Charge Voltage Control Register Format
7
VREG[5]
R/W
6
VREG[4]
R/W
5
VREG[3]
R/W
4
VREG[2]
R/W
3
VREG[1]
R/W
2
VREG[0]
R/W
1
BATLOWV
R/W
0
VRECHG
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. REG04 Charge Voltage Control Register Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
NOTE
Offset: 3.504V
Range: 3.504V – 4.400V (111000)
Default: 4.112V (100110)
CHARGE VOLTAGE LIMIT
Bit 7
VREG[5]
R/W
1
512mV
Bit 6
VREG[4]
R/W
0
256mV
Bit 5
VREG[3]
R/W
0
128mV
Bit 4
VREG[2]
R/W
1
64mV
Bit 3
VREG[1]
R/W
1
32mV
Bit 2
VREG[0]
R/W
0
16mV
BATTERY PRECHARGE TO FAST CHARGE THRESHOLD
Bit 1
BATLOWV
R/W
1
0 – 2.8V, 1 – 3.0V
Default: 3.0V (1)
BATTERY RECHARGE THRESHOLD (BELOW BATTERY REGULATION VOLTAGE)
Bit 0
VRECHG
R/W
0
0 – 100mV, 1 – 300mV
Default: 100mV (0)
8.5.1.6 Charge Termination/Timer Control Register REG05 (reset = 10011010, or 9A)
Figure 30. REG05 Charge Termination/Timer Control Register Format
7
EN_TERM
R/W
6
TERM_STAT
R/W
5
4
WATCHDOG[1] WATCHDOG[0]
R/W
R/W
3
EN_TIMER
R/W
2
1
CHG_TIMER[1] CHG_TIMER[0]
R/W
R/W
0
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. REG05 Charge Termination/Timer Control Register Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
NOTE
0 – Disable, 1 – Enable
Default: Enable termination (1)
0 – Match ITERM,
1 – STAT pin high before actual
termination when charge current
below 800 mA
Default Match ITERM (0)
00 – Disable timer, 01 – 40s, 10 –
80s, 11 – 160s
Default: 40s (01)
1
0 – Disable, 1 – Enable
Default: Enable (1)
00 – 5 hrs, 01 – 8 hrs, 10 – 12 hrs,
11 – 20 hrs
Default: 8hours (01)
(See Charging Safety Timer for details)
CHARGING TERMINATION ENABLE
Bit 7
EN_TERM
R/W
1
TERMINATION INDICATOR THRESHOLD
Bit 6
TERM_STAT
R/W
0
I2C WATCHDOG TIMER SETTING
Bit 5
WATCHDOG[1]
R/W
0
Bit 4
WATCHDOG[0]
R/W
1
CHARGING SAFETY TIMER ENABLE
Bit 3
EN_TIMER
R/W
FAST CHARGE TIMER SETTING
Bit 2
CHG_TIMER[1]
R/W
0
Bit 1
CHG_TIMER[0]
R/W
1
Bit 0
Reserved
R/W
0
30
0 - Reserved
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SLUSBI4B – APRIL 2013 – REVISED DECEMBER 2016
8.5.1.7 IR Compensation / Thermal Regulation Control Register REG06 (reset = 00000011, or 03)
Figure 31. REG06 IR Compensation / Thermal Regulation Control Register Format
7
BAT_COMP[2]
R/W
6
BAT_COMP[1]
R/W
5
BAT_COMP[0]
R/W
4
VCLAMP[2]
R/W
3
VCLAMP[1]
R/W
2
VCLAMP[0]
R/W
1
TREG[1]
R/W
0
TREG[0]
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. REG06 IR Compensation / Thermal Regulation Control Register Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
NOTE
Range: 0 – 70mΩ
Default: 0Ω (000)
IR COMPENSATION RESISTOR SETTING
Bit 7
BAT_COMP[2]
R/W
0
40mΩ
Bit 6
BAT_COMP[1]
R/W
0
20mΩ
Bit 5
BAT_COMP[0]
R/W
0
10mΩ
IR COMPENSATION VOLTAGE CLAMP (ABOVE REGULATION VOLTAGE)
Bit 4
VCLAMP[2]
R/W
0
64mV
Bit 3
VCLAMP[1]
R/W
0
32mV
Bit 2
VCLAMP[0]
R/W
0
16mV
Range: 0 – 112 mV
Default: 0mV (000)
THERMAL REGULATION THRESHOLD
Bit 1
TREG[1]
R/W
1
Bit 0
TREG[0]
R/W
1
00 – 60°C, 01 – 80°C, 10 – 100°C,
11 – 120°C
Default: 120°C (11)
8.5.1.8 Misc Operation Control Register REG07 (reset = 01001011, or 4B)
Figure 32. REG07 Misc Operation Control Register Format
7
DPDM_EN
R/W
6
TMR2X_EN
R/W
5
BATFET_Disable
R/W
4
Reserved
R/W
3
Reserved
R/W
2
Reserved
R/W
1
INT_MASK[1]
R/W
0
INT_MASK[0]
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. REG07 Misc Operation Control Register Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
NOTE
0 – Not in Input source detection;
1 – Force Input source detection
Default: Not in Input source detection (0).
Reset to 0 after detection complete. INT pulse
may not be generated
Set default input current limit from PSEL/OTG pins
Bit 7
DPDM_EN
R/W
0
SAFETY TIMER SETTING DURING INPUT DPM AND THERMAL REGULATION
Bit 6
TMR2X_EN
R/W
1
0 – Safety timer not slowed by 2X
during input DPM or thermal
regulation,
1 – Safety timer slowed by 2X
during input DPM or thermal
regulation
Default: Safety timer slowed by 2X (1)
Default: Allow Q4 turn on(0)
FORCE BATFET OFF
Bit 5
BATFET_Disable
R/W
0
0 – Allow Q4 turn on, 1 – Turn off
Q4
Bit 4
Reserved
R/W
0
0 - Reserved
Bit 3
Reserved
R/W
1
1 - Reserved
Bit 2
Reserved
R/W
0
0 - Reserved
Bit 1
INT_MASK[1]
R/W
1
0 – No INT during CHRG_FAULT,
1 – INT on CHRG_FAULT
Default: INT on CHRG_FAULT (1)
Bit 0
INT_MASK[0]
R/W
1
0 – No INT during BAT_FAULT, 1 –
INT on BAT_FAULT
Default: INT on BAT_FAULT (1)
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8.5.1.9 System Status Register REG08
Figure 33. REG08 System Status Register Format
7
VBUS_STAT[1]
R
6
VBUS_STAT[0]
R
5
CHRG_STAT[1]
R
4
CHRG_STAT[0]
R
3
DPM_STAT
R
2
PG_STAT
R
1
THERM_STAT
R
0
VSYS_STAT
R
LEGEND: R = Read only; -n = value after reset
Table 15. REG08 System Status Register Description
BIT
FIELD
TYPE
DESCRIPTION
Bit 7
VBUS_STAT[1]
R
Bit 6
VBUS_STAT[0]
R
00 – Unknown (no input, or DPDM detection incomplete), 01 – USB host, 10 – Adapter
port, 11 – OTG
Bit 5
CHRG_STAT[1]
R
Bit 4
CHRG_STAT[0]
R
Bit 3
DPM_STAT
R
0 – Not DPM, 1 – VINDPM or IINDPM
Bit 2
PG_STAT
R
0 – Not Power Good, 1 – Power Good
Bit 1
THERM_STAT
R
0 – Normal, 1 – In Thermal Regulation
Bit 0
VSYS_STAT
R
0 – Not in VSYSMIN regulation (BAT>VSYSMIN), 1 – In VSYSMIN regulation
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