User's Guide
SLUUAO5B – August 2013 – Revised April 2014
bq24295EVM-549 (PWR549) User’s Guide
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Contents
Introduction ................................................................................................................... 2
1.1
EVM Features ....................................................................................................... 2
1.2
Design Considerations ............................................................................................. 2
1.3
General Descriptions ............................................................................................... 2
1.4
I/O Description ...................................................................................................... 3
Test Summary ................................................................................................................ 4
2.1
Equipment ........................................................................................................... 4
2.2
Equipment Setup.................................................................................................... 4
2.3
Procedure ............................................................................................................ 6
2.4
Charge Voltage and Current Regulation of VIN and Device ID Verification ................................ 6
PCB Layout Guideline ..................................................................................................... 10
PCB Thermal Design ...................................................................................................... 10
Board Layout, Schematic, and Bill of Materials ........................................................................ 11
5.1
Board Layout ....................................................................................................... 11
5.2
Schematic .......................................................................................................... 13
List of Figures
.................
1
OTG Boost Mode 5-V Output Load Regulation Versus PCB Layer Thickness - Default Setting
2
Connections of the HPA172 Kit ............................................................................................ 5
3
Original Test Setup for PWR549 (bq24295 EVM)
4
Main Window of the bq2429x Evaluation Software
5
6
7
8
9
10
11
12
13
2
...................................................................... 5
..................................................................... 6
Main Window with Enable Termination Unchecked ..................................................................... 7
Buck Mode Switch Node Waveform, VBUS = 5 V, VBAT = 3.7 V .................................................... 8
Buck Mode Input PMID Ripple, VBUS = 5 V, VBAT = 3.7 V........................................................... 8
Buck Mode Output Ripple, VBUS = 5 V, VBAT = 3.7 V ................................................................ 8
Boost Mode Ripple and Duty Cycle; VBAT = 3.7 V ..................................................................... 9
bq24295 EVM Top Layer .................................................................................................. 11
bq24295 EVM Bottom Layer .............................................................................................. 11
bq24295 EVM Top Assembly ............................................................................................. 12
bq24295 EVM Schematic ................................................................................................. 13
List of Tables
1
EVM Connections ............................................................................................................ 3
2
Jumper Connections
3
Switch Settings ............................................................................................................... 3
4
Recommended Operating Conditions ..................................................................................... 3
5
Device ID...................................................................................................................... 9
6
Bill of Materials
........................................................................................................
.............................................................................................................
3
14
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bq24295EVM-549 (PWR549) User’s Guide
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1
Introduction
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1
Introduction
1.1
EVM Features
Refer to the data sheet (SLUSBC1) for detailed features and operation.
1.2
Design Considerations
1. Install the JP1 shunt for proper operation.
2. Disable the watchdog timer if not using the WDG Timer Reset button (illustrated in Figure 4), so the
programmed setting does not reset.
3. The GUI STATUS and FAULT block are helpful in troubleshooting, if the design is having issues.
4. In Boost mode, if not using a battery or power supply with short leads, extra capacitance at J5
(BAT/GND) may be needed.
5. The OTG Low box has to be unchecked and the Enable OTG box must be checked to get into Boost
mode.
6. PWB thickness affects the “On-the-GO” (OTG) Boost Output regulation at load currents over 0.75 A.
An evaluation was performed using different thicknesses of PCBs with the Load Regulation results
shown in Figure 1.
TI recommends using a 4-layer PCB constructed with two 15-mil, 2-oz Cu/layer boards fixed together,
for a total thickness of 31 mils. The 4-layer PCB, has a stack up of a component/routing layer, GND
layer, routing layer and a GND layer. A second choice is a 2-layer, 24-mil PCB, or thinner, with a
component/routing layer and a GND plane layer. The bq24295EVM-549 REV B EVM is built on a 24mil thick PCB.
5.2
5.15
OTG Output Voltage (V)
5.1
5.05
2 Layer, 62 mils
5
2 Layer, 31 mils
4.95
2 Layer, 24 mils
2 Layer, 15 mils
4.9
4 Layer, 2 x 15 mils
4.85
4.8
4.75
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Output Load (A)
Figure 1. OTG Boost Mode 5-V Output Load Regulation Versus PCB Layer Thickness - Default Setting
1.3
General Descriptions
The bq24295 evaluation module is a complete charger module for evaluating an I2C Controlled single
NVDC-1 charge using the bq2419x devices. For details, see bq24295 data sheet (SLUSBC1).
The bq24295 EVM doesn’t include the USB-to-GPIO interface board. To evaluate the bq24295 EVM, the
USB-to-GPIO interface board must be ordered separately. Search ti.com for "USB-to-GPIO".
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Introduction
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1.4
I/O Description
Table 1 contains the EVM connections.
Table 1. EVM Connections
Jack
Description
J1-PMID
PMID pin connection or power bank output
J1-GND
Ground
J2-VBUS
Input: positive terminal
J2-GND
Input: negative terminal (ground terminal)
J3-SYS
Connected to system
J3-GND
Ground
J4
USB-to-GPIO connector (USB Interface
Adapter Connector - HPA172)
J5-BAT+
Connected to battery pack
J5-GND
Ground
J6
Mini_USB connector
J7-INT
INT pin connection
J7-OTG
OTG pin connection
J7-CE
CE pin connection
J7-GND
Ground
Table 2 lists the jumper connections for this EVM.
Table 2. Jumper Connections
Jack
Description
Factory Setting
JP1
VSYS pull-up for STAT, PG, INT, CE, SCL, SDA
Shunt installed
JP2
200-Ω short between D+ and D–
Shunt not installed
JP3
TS1 to GND fault
Shunt not installed
Table 3 lists the switch settings for the EVM.
Table 3. Switch Settings
Switch
Description
Procedure Setting
S2-1
OTG switched to GND: ON
OFF
S2-2
CE switched to GND: ON
OFF
S2-3
TS 10 kΩ switched to GND: ON
ON
S2-4
REGN switched to TS divider: ON
ON
S3
PSEL/PG (left) or D+/D– (Right)
Connection
Right
Table 4 gives the recommended operating conditions for this EVM.
Table 4. Recommended Operating Conditions
Symbol
Description
MIN
TYP
MAX
Unit
Supply voltage, VIN
Input voltage from AC adapter input
3.9
5
6
V
Battery voltage, VBAT
Voltage applied at VBAT terminal
3.7
4.25
V
Supply current, IAC
Maximum input current from AC adapter input
3
A
Output current, IOUT
Output current
4
A
125
°C
Operating junction temperature range, TJ
0
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Test Summary
2
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Test Summary
Section 2.1 – Section 2.3 explains the equipment, the equipment setup, and the test procedures.
2.1
2.1.1
Equipment
Power Supplies
Power supply #1 (PS#1): a power supply capable of supplying 5 V at 1 A is required. While this part can
handle a larger voltage and/or current, it is not necessary for this procedure.
2.1.2
Load #1 (Electronic Load, Constant Voltage < 4.5 V) - Battery Connection
A 0–20 V/0–5 A, > 30-W system, DC electronic load and setting as constant voltage load mode.
Or:
Kepco load: BOP 20–5M, DC 0 to ±20 V, 0 to ±5 A (or higher)
Or:
Real single-cell battery
2.1.3
Load #2 – Use with Boost Mode
PMID-to-GND load, 10 Ω, 5 W or greater
2.1.4
Meters
Five Fluke 75 multimeters, (equivalent or better)
Or:
Three equivalent voltage meters and two equivalent current meters.
The current meters must be capable of measuring 2 A of current.
2.1.5
Computer
A computer with at least one USB port and a USB cable. The bq2429xEVM evaluation software must be
properly installed.
2.1.6
USB-to-GPIO Communication Kit (HPA172-USB Interface Adapter)
2.1.7
Software
Unzip the bq2429xEVM_GUI.zip and double-click on the SETUP.EXE file. Follow the installation steps.
The software supports the Microsoft® Windows® XP and Windows 7 operating systems.
2.2
Equipment Setup
(A) Set PS#1 for 5-V DC, 1-A current limit and then turn off the supply.
(B) Connect the output of PS#1 in series with a current meter (multimeter) to J2 (VBUS and GND), as
shown in Figure 3.
(C) Connect a voltage meter across J2 (VBUS) and J2 (GND).
(D) Turn on the electron Load, set to constant voltage mode and output to 2.5 V. Turn off (disable) Load.
Connect Load to J5 (BAT+ and GND) as shown in Figure 3, via a current meter in the return line of the
load. Connect a voltage meter across J5 (BAT+ and GND).
(E) Connect a voltage meter across J3 (SYS and GND).
(F) Connect HPA172 USB interface adapter to the computer with a USB mini-cable and to J4 with the 10pin ribbon cable. The connections are shown in Figure 2.
4
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Test Summary
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I/O
USB Interface
Adapter
Texas Instruments
© 2006
USB
To Computer
USB Port
10-pin
Ribbon Cable
‘To EVM’
Figure 2. Connections of the HPA172 Kit
(G) Install jumpers as per Table 2.
(H) Set S2 toggle bits as per Table 3, procedure setting column.
Figure 3. Original Test Setup for PWR549 (bq24295 EVM)
(I) Turn on the computer. Launch the bq2429x evaluation software. The main window of the software is
shown in Figure 4.
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Test Summary
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Figure 4. Main Window of the bq2429x Evaluation Software
2.3
Procedure
2.3.1
Current Settings
Make sure EQUIPMENT SETUP steps are followed.
1. ILIM Setting: Set the potentiometer to its lowest value for max input current. Turn the screw on the
potentiometer counterclockwise (Pot should make click sound when fully CCW).
2. Launch BQ2429x EVM GUI application on computer, if not already done.
3. Turn on PS#1
Measure → V (J3(SYS), J3(GND)) = 4.10 ±300 mV
2.4
Charge Voltage and Current Regulation of VIN and Device ID Verification
2.4.1
6
Software setup (all of these steps are done in the GUI):
•
Device address: 6B
•
•
•
•
•
•
Click the Read button two times, one second apart
Select Disabled for I2C Watchdog Timer Limit
Set Input Voltage Limit to 4.2 V
Set Input Current Limit to 500 mA
Set Charge Voltage Limit to 4.208 V
Set Fast Charge Current, ICHG to 512 mA
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•
•
Set Pre-Charge Current Limit to 256 mA
Un-Check Enable Termination (see Figure 5)
Figure 5. Main Window with Enable Termination Unchecked
•
Click the Read button three times, one second apart
Observe → Everything normal at FAULT box
Observe → D1 (STAT) is on
Enable Load #1 from Section 2.1.2. Measure the system and battery voltage.
Measure → V(J3(SYS), J3(GND)) = 3.5 V ±300 mV
Measure → V(J5(BAT), J5(GND)) = 2.5 V ±200 mV
Increase the Load #1 voltage to 3.7 V.
Measure → V(J3(SYS), J3(GND)) = 3.75 V ±200 mV
Measure → IBAT = 500 mA ±200 mA
Measure → V(J5(BAT), J5(GND)) = 3.75 V ±200 mV
In the Software, Select Fast Charge Current, “ICHG” to 1024 mA.
Measure → Iin = 500 mA ±200 mA
2.4.2
Verify the device ID and JEITA shown in the software matches the following table:
Assy Number
EVM Part Number
Device ID
JEITA
PWR549-001
bq24295EVM-549
bq24295
Disabled
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Test Summary
2.4.3
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Verify Scope Measurements (see Figure 6 through Figure 8 – 500 ns/div):
Connect scope probe ground lead to Ground J1-GND (make sure lead is short), probe and verify the
following waveforms, as shown in Figure 6 through Figure 8.
Figure 6) Buck Mode Switch Node Waveform - (2 VDC/div): TP left of inductor L1
Figure 7) Buck Mode Input PMID Ripple - (AC coupled 20 mV/div): Right side of C2 Cap
Figure 8) Buck Mode Output System Ripple – (AC coupled 50 mV/div): top side of C12 cap
Measure → Figure 6 – SW node Frequency between 1.25 MHz and 1.6 MHz,
Measure → Figure 6 – SW node Duty cycle between 71 and 81%.
Measure → Figure 7 - PMID AC Ripple < 15 mV excluding high frequency spikes
Measure → Figure 8 - SYS AC Ripple < 10 mV excluding high frequency spikes
Figure 6. Buck Mode Switch Node Waveform, VBUS = 5
V, VBAT = 3.7 V
Figure 7. Buck Mode Input PMID Ripple, VBUS = 5 V,
VBAT = 3.7 V
Figure 8. Buck Mode Output Ripple, VBUS = 5 V, VBAT = 3.7 V
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2.4.4
Verify Device ID Using GUI Software and Table 5.
Table 5. Device ID
2.4.5
Assembly Number
EVM Part Number
Device ID
PWR549-001
bq24295EVM-549
bq24295
Switch to Boost Mode
1. Turn off and disconnect PS#1. May be used in step 2, if needed.
2. Move the voltmeter from J2 (VBUS/GND) to J1 (PMID/GND).
3. If the constant voltage supply connected between BAT+ and GND, from above, is not a 4 quadrant
supply (can source current) then this needs to be replaced with a power source set to 3.7 VDC that
can source current. Connect new power source, if necessary, that is set to 3.7 V and turn on.
4. Apply 10 ohms (5 W or greater) across J1 (PMID(+) to GND(–))
5. Click the GUI read button two times to make sure the latest data is read.
6. Disable the “I2C watchdog timer Limit” if set to a time.
7. Uncheck the “Enable Charge” Box if checked.
8. Uncheck the “OTG Low” box in the GUI.
9. Check the “Enable OTG” if un-checked.
10. Verify switch node waveform
11. Verify PMID to GND on J1 is between 4.9 V and 5.3 V (See Figure 9).
CH2 (5 V/div): SW Node – (Left Side of inductor to GND)
Measure → SW Frequency (TP2) - Frequency between 1.1 MHz and 1.5 MHz, (Period = 1 / fsw)
Measure → SW Duty cycle (TP2) - Duty cycle between 26 and 33%. (tVSW_LOW / period)
Figure 9. Boost Mode Ripple and Duty Cycle; VBAT = 3.7 V
2.4.6
Turn off Power Source connected to BAT+ and GND.
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PCB Layout Guideline
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PCB Layout Guideline
Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the
components minimizing high-frequency current path loop is important to prevent electrical and magnetic
field radiation and high frequency resonant problems. This PCB layout priority list must be followed in the
order presented for proper layout:
1. Place the input capacitor as close as possible to the PMID and GND pin connections and use the
shortest possible copper trace connection or GND plane.
2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a
short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power
ground separately. Connect analog ground and power ground together using power pad as the single
ground connection point or use a 0-Ω resistor to tie analog ground to power ground.
5. Use a single ground connection to tie the charger power ground to the charger analog ground just
beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise
coupling.
6. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground
plane on the other layers.
8. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the
QFN information, refer to SCBA017 and SLUA271.
4
PCB Thermal Design
The IC is one of the major heat dissipation components on the EVM, and is cooled with thermal
PowerPAD vias connected to the bottom layer. The copper pour on the bottom layer is 1 in x 2 in
representing a thermal design of this size. Note how there are very few routing etches in the bottom layer
and that they are positioned to maximize (not impede) the flow of heat away from the IC. All good thermal
designs have at least one layer of 2-oz copper (without cuts) to spread the heat (conduction) across the
PCB so it can be dissipated into the air (convection) with minimal heat rise.
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Board Layout, Schematic, and Bill of Materials
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5
Board Layout, Schematic, and Bill of Materials
5.1
Board Layout
Figure 10 through Figure 12 illustrate the board layouts for this EVM.
Figure 10. bq24295 EVM Top Layer
Figure 11. bq24295 EVM Bottom Layer
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Board Layout, Schematic, and Bill of Materials
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Figure 12. bq24295 EVM Top Assembly
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5.2
Schematic
Figure 13 illustrates the schematic for this EVM.
J1
PMID
1
2
PMID
GND
REGN
ED555/2DS
C1
10μF
GND
C2
10μF
DNP DNP
C3
C4
1μ F
0.1μF
C5
4.7μF
GND
Vbus Input Range: 4.5V to 6V
GND
J3
J2
1
2
VBUS
GND
DNP
C7
10uF
ED555/2DS
GND
DNP
C8
C9
1uF
0.1uF
2
1
L1
2.2uH
C6
0.047μF
VIN
DNP DNP
C10
C11
0.1μF 1μF
C12
10μF
DNP
DNP
C13
C14
C15
10μF
10μF
10μF
System Output
GND
ED555/2DS
R3
0
GND
GND
6
R10
10.0k
USB Micro Connector
R19
200
DNP
D2
Green
SW
21
20
SW
BTST
23
22
REGN
19
GND
BAT
15
J5
14
Battery Pack Connection -Single Cell
GND
ED555/2DS
DNP
C18
1uF
PULLUP
R13
10.0k
R14
130
R16
10.0k
D1
Green
1
GND
2
SKRKAEE010
R15
10.0k
R17
5.23k
INT
1
PULLUP
STAT
R20
10.0k
1
TS
R22
768
R21
10k
2
GND
JP3
PEC02SAAN
5
2
V-
2
1
R8
0
13
OTG
PG
JP2
PEC02SAAN
4
NC
16
C17
10μF
TS
R18
2.21k
/CE
D-
3
BAT
PULLUP
S1
DNP
R12
2.21k
VIN
2
DP
SDA
17
OTG
1
DM
BAT
PULLUP
J6
V+
SCL
2
JP1
PEC02SAAN
QON
R7
10.0k
SDA
PSEL
/CE
200
N2510-6002RB
N2510-6002RB
PULLUP
SYS
INT
SCL
SYS
STAT
1
18
12
5
D-
TS
R6
10
200
9
8
R9
7
200
6
5
4
R2
3 GND
R11 200
2
1
200 R5
4
SCL
SDA
PGND
7
USB Interface Adapter Connection
3
STAT
J4
D+
ILIM
2
D+/PSEL
PGND
11
CAS-220TA
U1
bq24295RGE
PAD
VBUS
10
1
D-
CE
6
PG
9
3
D+
24
5
PMID
4
2
VBUS
1
OTG
PSEL
D+/PSEL
sys
8
S3
1 S2
2
3
4
D+
GND
CONN_USB-B_MINI
56579-0519
R4
10.0k
GND
8
7
6
5
TS
R1
30.1k
C16
0.1μF
OTG
/CE
TS
REGN
A6S-4104-H
GND
J7
1
2
3
4
INT
OTG
/CE
GND
ED555/4DS
GND
Logo?
PCB
LOGO
FID1
Texas Instruments
FID2
FID3
Figure 13. bq24295 EVM Schematic
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Board Layout, Schematic, and Bill of Materials
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Bill of Materials
Table 6 contains the bill of materials.
Table 6. Bill of Materials
Designator
Qty
Value
Description
PackageReference
PartNumber
Manufacturer
C1, C2
2
10uF
CAP, CERM, 10uF, 25V, +/-10%, X5R, 1206
1206
GRM31CR61E106KA12L
MuRata
C5
1
4.7uF
CAP, CERM, 4.7uF, 16V, +/-10%, X5R, 0603
0603
GRM188R61C475KAAJ
MuRata
C6
1
0.047uF
CAP, CERM, 0.047uF, 25V, +/-10%, X7R, 0603
0603
GRM188R71E473KA01D
MuRata
C8
1
1uF
CAP, CERM, 1uF, 25V, +/-10%, X7R, 0603
0603
GRM188R71E105KA12D
MuRata
C12, C13
2
10uF
CAP, CERM, 10uF, 16V, +/-10%, X5R, 0805
0805
GRM21BR61C106KE15L
MuRata
C16
1
0.1uF
CAP, CERM, 0.1uF, 25V, +/-10%, X7R, 0603
0603
GRM188R71E104KA01D
MuRata
C17
1
10uF
CAP, CERM, 10uF, 10V, +/-10%, X5R, 0603
0603
C1608X5R1A106M
TDK
D1
1
Green
LED, Green, SMD
1.6x0.8x0.8mm
LTST-C190GKT
Lite-On
FID1, FID2, FID3
0
Fiducial mark. There is nothing to buy or mount.
Fiducial
N/A
N/A
J1, J2, J3, J5
4
Terminal Block, 6A, 3.5mm Pitch, 2-Pos, TH
7.0x8.2x6.5mm
ED555/2DS
On-Shore Technology, Inc.
J4
1
N2510-6002RB
Connector, Male Straight 2x5 pin, 100mil spacing, 4 Wall
0.338 x 0.788 inch
N2510-6002RB
3M
J6
1
56579-0519
Connector, USB-B, Mini, 5-pins
0.354 X 0.307 Inches
56579-0519
Molex
J7
1
Terminal Block, 6A, 3.5mm Pitch, 4-Pos, TH
14x8.2x6.5mm
ED555/4DS
On-Shore Technology, Inc.
JP1, JP2, JP3
3
PEC02SAAN
Header, Male 2-pin, 100mil spacing,
0.100 inch x 2
PEC02SAAN
Sullins
L1
1
2.2uH
Inductor, SMT, 5A,
0.204 x 0.216 inch
IHLP2020BZER2R2M11
Vishay
R1
1
30.1k
RES, 30.1k ohm, 1%, 0.1W, 0603
0603
CRCW060330K1FKEA
Vishay-Dale
R2, R5, R6, R9, R11,
R19
6
200
RES, 200 ohm, 1%, 0.1W, 0603
0603
CRCW0603200RFKEA
Vishay-Dale
R3
1
0
RES, 0 ohm, 5%, 0.1W, 0603
0603
CRCW06030000Z0EA
Vishay-Dale
R4, R7, R10, R13, R15,
R16, R20
7
10.0k
RES, 10.0k ohm, 1%, 0.1W, 0603
0603
CRCW060310K0FKEA
Vishay-Dale
R8
1
0
RES, 0 ohm, 5%, 0.25W, 1206
1206
CRCW12060000Z0EA
Vishay-Dale
R14
1
130
RES, 130 ohm, 1%, 0.1W, 0603
0603
CRCW0603130RFKEA
Vishay-Dale
R17
1
5.23k
RES, 5.23k ohm, 1%, 0.1W, 0603
0603
CRCW06035K23FKEA
Vishay-Dale
R18
1
2.21k
RES, 2.21k ohm, 1%, 0.1W, 0603
0603
CRCW06032K21FKEA
Vishay-Dale
R21
1
10k
Potentiometer, 3/8 Cermet, Single-Turn
0.25x0.17 inch
3266W-1-103LF
Bourns
R22
1
768
RES, 768 ohm, 1%, 0.1W, 0603
0603
CRCW0603768RFKEA
Vishay-Dale
S1
1
Switch, Push Button, SMD
2.9x2x3.9mm SMD
SKRKAEE010
Alps
S2
1
DIP Switch, 4 position slide actuator, SPST, SMD
SMT DIP switch
A6S-4104-H
Omron Electronic Components
S3
1
SLIDE SWITCH DPDT .1A, SMT
SWITCH, 5.4x2.5x3.9mm
CAS-220TA
Copal Electronics
U1
1
I2C Controlled 4A Single Cell Charger with Adjustable Voltage & 1.5A Synchronous Boost
Operation, RGE0024H
RGE0024H
bq24295RGE
Texas Instruments
-
1
929950-00
Shunt, 100-mil, Black
0.100
929950-00
3M
-
1
PWR549
1.7x2 inch 2 layer 2oz. PCB
2.5x2.5inch
PCB
Any
C3, C11, C18
0
1uF
CAP, CERM, 1uF, 25V, +/-10%, X7R, 0603
0603
GRM188R71E105KA12D
MuRata
C4, C9, C10
0
0.1uF
CAP, CERM, 0.1uF, 25V, +/-10%, X7R, 0603
0603
GRM188R71E104KA01D
MuRata
C7, C14, C15
0
10uF
CAP, CERM, 10uF, 25V, +/-10%, X5R, 1206
1206
GRM31CR61E106KA12L
MuRata
D2
0
Green
LED, Green, SMD
1.6x0.8x0.8mm
LTST-C190GKT
Lite-On
14
bq24295EVM-549 (PWR549) User’s Guide
SLUUAO5B – August 2013 – Revised April 2014
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Copyright © 2013–2014, Texas Instruments Incorporated
Board Layout, Schematic, and Bill of Materials
www.ti.com
Table 6. Bill of Materials (continued)
Designator
Qty
Value
Description
PackageReference
PartNumber
Manufacturer
R12
0
2.21k
RES, 2.21k ohm, 1%, 0.1W, 0603
0603
CRCW06032K21FKEA
Vishay-Dale
Notes: Unless otherwise noted in the Alternate PartNumber and/or Alternate Manufacturer columns, all parts may be substituted with equivalents.
SLUUAO5B – August 2013 – Revised April 2014
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bq24295EVM-549 (PWR549) User’s Guide
Copyright © 2013–2014, Texas Instruments Incorporated
15
Revision History
www.ti.com
Revision History
Changes from A Revision (September 2014) to B Revision .......................................................................................... Page
•
Added step 6 to design configurations section ........................................................................................ 2
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
16
Revision History
SLUUAO5B – August 2013 – Revised April 2014
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