BQ3285LFSS-A1TRG4

bq3285E/L Real-Time Clock (RTC) Features ➤ BCD or binary format for clock and calendar data General Description ➤ Direct clock/calendar replacement for IBM® AT-compatible computers and other applications ➤ Calendar in day of the week, day of the month, months, and years, with automatic leap-year adjustment The CMOS bq3285E/L is a lowpower microprocessor peripheral providing a time-of-day clock and 100-year calendar with alarm features and battery operation. The bq3285L supports 3V systems. Other bq3285E/L features include three maskable interrupt sources, square-wave output, and 242 bytes of general nonvolatile storage. ➤ Functionally compatible with the DS1285 - Closely matches MC146818A pin configuration ➤ Time of day in seconds, minutes, and hours - ➤ 2.7–3.6V operation (bq3285L); 4.5–5.5V operation (bq3285E) 12- or 24-hour format Optional daylight saving adjustment ➤ 242 bytes of general nonvolatile storage ➤ Programmable square wave output ➤ 32.768kHz output for power management ➤ Three individually maskable interrupt event flags: ➤ System wake-up capability— alarm interrupt output active in battery-backup mode ➤ Less than 0.5µA load under battery operation ➤ Selectable Intel or Motorola bus timing - Periodic rates from 122µs to 500ms - Time-of-day alarm once per second to once per day - End-of-clock update cycle ➤ 24-pin plastic DIP, SOIC, or SSOP ➤ 14 bytes for clock/calendar and control Pin Connections 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 The bq3285E/L write-protects the clock, calendar, and storage registers during power failure. A backup battery then maintains data and operates the clock and calendar. The bq3285E/L is a fully compatible real-time clock for IBM AT-compatible computers and other applications. The only external components are a 32.768kHz crystal and a backup battery. Pin Names AD0–AD7 MOT X1 X2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS A 32.768kHz output is available for sustaining power-management activities. Wake-up capability is provided by an alarm interrupt, which is active in battery-backup mode. VCC SQW EXTRAM RCL BC INT RST DS VSS R/W AS CS Multiplexed address/ RST Reset input data input/output SQW Square wave output MOT Bus type select input EXTRAM Extended RAM enable CS Chip select input RCL RAM clear input AS Address strobe input BC 3V backup cell input DS Data strobe input X1–X2 Crystal inputs R/W Read/write input VCC Power supply INT Interrupt request VSS Ground output 24-Pin DIP or SOIC/SSOP PN3285E1.eps SLUS004A -DECEMBER 1993 - REVISED MAY 2004 1 bq3285E/L Block Diagram AD0–AD7 Pin Descriptions MOT Bus type select input The bq3285E/L bus cycle consists of two phases: the address phase and the datatransfer phase. The address phase precedes the data-transfer phase. During the address phase, an address placed on AD0–AD7 and EXTRAM is latched into the bq3285E/L on the falling edge of the AS signal. During the data-transfer phase of the bus cycle, the AD0–AD7 pins serve as a bidirectional data bus. MOT selects bus timing for either Motorola or Intel architecture. This pin should be tied to VCC for Motorola timing or to VSS for Intel timing (see Table 1). The setting should not be changed during system operation. MOT is internally pulled low by a 30KΩ resistor. Table 1. Bus Setup AS Bus Type MOT DS R/W AS Level Equivalent Equivalent Equivalent Motorola VCC DS, E, or Φ2 R/W Intel VSS RD, MEMR, or I/OR WR, MEMW, or ALE I/OW Multiplexed address/data input/ output Address strobe input AS serves to demultiplex the address/data bus. The falling edge of AS latches the address on AD0–AD7 and EXTRAM. This demultiplexing process is independent of the CS signal. For DIP and SOIC packages with MOT = VSS, the AS input is provided a signal similar to ALE in an Intel-based system. AS 2 bq3285E/L DS EXTRAM Data strobe input Enables 128 bytes of additional nonvolatile SRAM. It is connected internally to a 30K Ω pull-down resistor. To access the RTC registers, EXTRAM must be low. When MOT = VCC, DS controls data transfer during a bq3285E/L bus cycle. During a read cycle, the bq3285E/L drives the bus after the rising edge on DS. During a write cycle, the falling edge on DS is used to latch write data into the chip. RCL Read/write input When MOT = VCC, the level on R/W identifies the direction of data transfer. A high level on R/W indicates a read bus cycle, whereas a low on this pin indicates a write bus cycle. BC When MOT = VSS, R/W is provided a signal similar to WR, MEMW, or I/OW in an Intel-based system. The rising edge on R/W latches data into the bq3285E/L. CS Chip select input Upon power-up, a voltage within the VBC range must be present on the BC pin for the oscillator to start up. Interrupt request output INT is an open-drain output. This allows alarm INT to be valid in battery-backup mode. To use this feature, INT must be connected to a power supply other than VCC. INT is asserted low when any event flag is set and the corresponding event enable bit is also set. INT becomes high-impedance whenever register C is read (see the Control/Status Registers section). SQW 3V backup cell input BC should be connected to a 3V backup cell for RTC operation and storage register nonvolatility in the absence of system power. When VCC slews down past VBC (3V typical), the integral control circuitry switches the power source to BC. When VCC returns above VBC, the power source is switched to VCC. CS should be driven low and held stable during the data-transfer phase of a bus cycle accessing the bq3285E/L. INT RAM clear input A low level on the RCL pin causes the contents of each of the 242 storage bytes to be set to FF(hex). The contents of the clock and control registers are unaffected. This pin should be used as a user-interface input (pushbutton to ground) and not connected to the output of any active component. RCL input is only recognized when held low for at least 125ms in the presence of VCC. Using RAM clear does not affect the battery load. This pin is connected internally to a 30KΩ pull-up resistor. When MOT = VSS, the DS input is provided a signal similar to RD, MEMR, or I/OR in an Intel-based system. The falling edge on DS is used to enable the outputs during a read cycle. R/W Extended RAM enable RST Reset input The bq3285E/L is reset when RST is pulled low. When reset, INT becomes high impedance, and the bq3285E/L is not accessible. Table 4 in the Control/Status Registers section lists the register bits that are cleared by a reset. Square-wave output Reset may be disabled by connecting RST to VCC. This allows the control bits to reta i n th e i r s ta te s th ro u g h p o w erdown/power-up cycles. SQW may output a programmable frequency square-wave signal during normal (VCC valid) system operation. Any one of the 13 specific frequencies may be selected through register A. This pin is held low when the square-wave enable bit (SQWE) in register B is 0 (see the Control/Status Registers section). X1–X2 Crystal inputs The X1–X2 inputs are provided for an external 32.768kHz quartz crystal, Daiwa DT-26 or equivalent, with 6pF load capacitance. A trimming capacitor may be necessary for extremely precise time-base generation. A 32.768kHz output is enabled by setting the SQWE bit in register B to 1 and the 32KE bit in register C to 1 after setting OSC2–OSC0 in register A to 011 (binary). In the absence of a crystal, a 32.768kHz waveform can be fed into the X1 input. 3 bq3285E/L dar locations during the update cycle at the end of each update period (see Figure 2). The alarm flag bit may also be set during the update cycle. Functional Description Address Map The bq3285E/L copies the local register updates into the user buffer accessed by the host processor. When a 1 is written to the update transfer inhibit bit (UTI) in register B, the user copy of the clock and calendar bytes remains unchanged, while the local copy of the same bytes continues to be updated every second. The bq3285E/L provides 14 bytes of clock and control/status registers and 242 bytes of general nonvolatile storage. Figure 1 illustrates the address map for the bq3285E/L. Update Period The update-in-progress bit (UIP) in register A is set tBUC time before the beginning of an update cycle (see Figure 2). This bit is cleared and the update-complete flag (UF) is set at the end of the update cycle. The update period for the bq3285E/L is one second. The bq3285E/L updates the contents of the clock and calen- Figure 1. Address Map Figure 2. Update Period Timing and UIP 4 bq3285E/L c. Programming the RTC Write the appropriate value to the hour format (HF) bit. The time-of-day, alarm, and calendar bytes can be written in either the BCD or binary format (see Table 2). 2. Write new values to all the time, alarm, and calendar locations. These steps may be followed to program the time, alarm, and calendar: 3. Clear the UTI bit to allow update transfers. 1. On the next update cycle, the RTC updates all 10 bytes in the selected format. Modify the contents of register B: a. Write a 1 to the UTI bit to prevent transfers between RTC bytes and user buffer. b. Write the appropriate value to the data format (DF) bit to select BCD or binary format for all time, alarm, and calendar bytes. Table 2. Time, Alarm, and Calendar Formats Range Address RTC Bytes Decimal Binary Binary-Coded Decimal 0 Seconds 0–59 00H–3BH 00H–59H 1 Seconds alarm 0–59 00H–3BH 00H–59H 2 Minutes 0–59 00H–3BH 00H–59H 3 Minutes alarm 0–59 00H–3BH 00H–59H Hours, 12-hour format 1–12 01H–OCH AM; 81H–8CH PM 01H–12H AM; 81H–92H PM Hours, 24-hour format 0–23 00H–17H 00H–23H Hours alarm, 12-hour format 1–12 01H–OCH AM; 81H–8CH PM 01H–12H AM; 81H–92H PM Hours alarm, 24-hour format 0–23 00H–17H 00H–23H 6 Day of week (1=Sunday) 1–7 01H–07H 01H–07H 7 Day of month 1–31 01H–1FH 01H–31H 8 Month 1–12 01H–0CH 01H–12H 9 Year 0–99 00H–63H 00H–99H 4 5 5 bq3285E/L Square-Wave Output n The bq3285E/L divides the 32.768kHz oscillator frequency to produce the 1Hz update frequency for the clock and calendar. Thirteen taps from the frequency divider are fed to a 16:1 multiplexer circuit. The output of this mux is fed to the SQW output and periodic interrupt generation circuitry. The four least-significant bits of register A, RS0–RS3, select among the 13 taps (see Table 3). The square-wave output is enabled by writing a 1 to the square-wave enable bit (SQWE) in register B. A 32.768kHz output may be selected by setting OSC2–OSC0 in register A to 011 while SQWE = 1 and 32KE = 1. n The update-ended interrupt, which occurs at the end of each update cycle. Each of the three interrupt events is enabled by an individual interrupt-enable bit in register B. When an event occurs, its event flag bit in register C is set. If the corresponding event enable bit is also set, then an interrupt request is generated. The interrupt request flag bit (INTF) of register C is set with every interrupt request. Reading register C clears all flag bits, including INTF, and makes INT high-impedance. Two methods can be used to process bq3285E/L interrupt events: Interrupts n The bq3285E/L allows three individually selected interrupt events to generate an interrupt request. These three interrupt events are: n The alarm interrupt, programmable to occur once per second to once per day, is active in battery-backup mode, providing a “wake-up” feature. n The periodic interrupt, programmable to occur once every 122µs to 500ms. Enable interrupt events and use the interrupt request output to invoke an interrupt service routine. Do not enable the interrupts and use a polling routine to periodically check the status of the flag bits. The individual interrupt sources are described in detail in the following sections. Table 3. Square-Wave Frequency/Periodic Interrupt Rate Register A Bits Square Wave OSC1 OSC0 RS3 RS2 RS1 RS0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 256 Hz 3.90625 ms 0 1 0 0 0 1 0 128 Hz 7.8125 ms 0 1 0 0 0 1 1 8.192 kHz 122.070 µs 0 1 0 0 1 0 0 4.096 kHz 244.141 µs 0 1 0 0 1 0 1 2.048 kHz 488.281 µs 0 1 0 0 1 1 0 1.024 kHz 976.5625 µs 0 1 0 0 1 1 1 512 Hz 1.95315 ms 0 1 0 1 0 0 0 256 Hz 3.90625 ms 0 1 0 1 0 0 1 128 Hz 7.8125 ms 0 1 0 1 0 1 0 64 Hz 15.625 ms 0 1 0 1 0 1 1 32 Hz 31.25 ms 0 1 0 1 1 0 0 16 Hz 62.5 ms 0 1 0 1 1 0 1 8 Hz 125 ms 0 1 0 1 1 1 0 4 Hz 250 ms 0 1 0 1 1 1 1 2 Hz 500 ms 0 1 1 X X X Frequency Units Periodic Interrupt OSC2 None X 6 32.768 Period Units None kHz same as above defined by RS3–RS0 bq3285E/L Periodic Interrupt Update Cycle Interrupt The mux output used to drive the SQW output also drives the interrupt-generation circuitry. If the periodic interrupt event is enabled by writing a 1 to the periodic interrupt enable bit (PIE) in register C, an interrupt request is generated once every 122µs to 500ms. The period between interrupts is selected by the same bits in register A that select the square wave frequency (see Table 3). Setting OSC2–OSC0 in register A to 011 does not affect the periodic interrupt timing. The update cycle ended flag bit (UF) in register C is set to a 1 at the end of an update cycle. If the update interrupt enable bit (UIE) of register B is 1, and the update transfer inhibit bit (UTI) in register B is 0, then an interrupt request is generated at the end of each update cycle. Accessing RTC bytes The EXTRAM pin must be low to access the RTC registers. Time and calendar bytes read during an update cycle may be in error. Three methods to access the time and calendar bytes without ambiguity are: Alarm Interrupt The alarm interrupt is active in battery-backup mode, providing a “wake-up” capability. During each update cycle, the RTC compares the hours, minutes, and seconds bytes with the three corresponding alarm bytes. If a match of all bytes is found, the alarm interrupt event flag bit, AF in register C, is set to 1. If the alarm event is enabled, an interrupt request is generated. n n An alarm byte may be removed from the comparison by setting it to a “don’t care” state. An alarm byte is set to a “don’t care” state by writing a 1 to each of its two most-significant bits. A “don’t care” state may be used to select the frequency of alarm interrupt events as follows: n n n n n If none of the three alarm bytes is “don’t care,” the frequency is once per day, when hours, minutes, and seconds match. If only the hour alarm byte is “don’t care,” the frequency is once per hour, when minutes and seconds match. Enable the update interrupt event to generate interrupt requests at the end of the update cycle. The interrupt handler has a maximum of 999ms to access the clock bytes before the next update cycle begins (see Figure 3). Poll the update-in-progress bit (UIP) in register A. If UIP = 0, the polling routine has a minimum of tBUC time to access the clock bytes (see Figure 3). Use the periodic interrupt event to generate interrupt requests every tPI time, such that UIP = 1 always occurs between the periodic interrupts. The interrupt handler has a minimum of tPI/2 + tBUC time to access the clock bytes (see Figure 3). Oscillator Control When power is first applied to the bq3285E/L and VCC is above VPFD, the internal oscillator and frequency divider are turned on by writing a 010 pattern to bits 4 through 6 of register A. A pattern of 011 behaves as 010 but additionally transforms register C into a read/write register. This allows the 32.768kHz output on the square wave pin to be turned on. A pattern of 11X turns the oscillator on, but keeps the frequency divider disabled. Any other pattern to these bits keeps the oscillator off. If only the hour and minute alarm bytes are “don’t care,” the frequency is once per minute, when seconds match. If the hour, minute, and second alarm bytes are “don’t care,” the frequency is once per second. Figure 3. Update-Ended/Periodic Interrupt Relationship 7 bq3285E/L Register A provides: Power-Down/Power-Up Cycle n The bq3285E and bq3285L power-up/power-down cycles are different. The bq3285L continuously monitors VCC for out-oftolerance. During a power failure, when VCC falls below VPFD (2.53V typical), the bq3285L write-protects the clock and storage registers. The power source is switched to BC when VCC is less than VPFD and BC is greater than VPFD, or when VCC is less than VBC and VBC is less than VPFD. RTC operation and storage data are sustained by a valid backup energy source. When VCC is above VPFD, the power source is VCC. Writeprotection continues for tCSR time after VCC rises above VPFD. RS0–RS3 - Frequency Select 7 - 7 - 0 RS0 n 2 RS2 1 RS1 0 RS0 5 OS1 4 OS0 3 - 2 - 1 - 0 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - This read-only bit is set prior to the update cycle. When UIP equals 1, an RTC update cycle may be in progress. UIP is cleared at the end of each update cycle. This bit is also cleared when the update transfer inhibit (UTI) bit in register B is 1. Register A programs: n 6 OS2 7 UIP 1 RS1 3 RS3 UIP - Update Cycle Status Register A Register A Bits 4 3 2 OS0 RS3 RS2 4 - These three bits control the state of the oscillator and divider stages. A pattern of 010 enables RTC operation by turning on the oscillator and enabling the frequency divider. A pattern of 011 behaves as 010 but additionally transforms register C into a read/write register. This allows the 32.768kHz output on the square wave pin to be turned on. A pattern of 11X turns the oscillator on, but keeps the frequency divider disabled. When 010 is written, the RTC begins its first update after 500ms. The four control/status registers of the bq3285E/L are accessible regardless of the status of the update cycle (see Table 4). 5 OS1 5 - OS0–OS2 - Oscillator Control Control/Status Registers 6 OS2 6 - These bits select one of the 13 frequencies for the SQW output and the periodic interrupt rate, as shown in Table 3. The bq3285E continuously monitors VCC for out-of-tolerance. During a power failure, when VCC falls below VPFD (4.17V typical), the bq3285E write-protects the clock and storage registers. When VCC is below VBC (3V typical), the power source is switched to BC. RTC operation and storage data are sustained by a valid backup energy source. When VCC is above VBC, the power source is VCC. Write-protection continues for tCSR time after VCC rises above VPFD. 7 UIP Status of the update cycle. The frequency of the square-wave and the periodic event rate. Oscillator operation. Table 4. Control/Status Registers Loc. Reg. (Hex) Read Write 1 Bit Name and State on Reset 7 (MSB) 6 5 4 3 2 A 0A Yes Yes UIP na OS2 na OS1 na OS0 na B 0B Yes Yes UTI na PIE 0 AIE 0 UIE 0 SQWE 0 C 0C Yes No2 INTF 0 PF 0 AF 0 UF 0 - 0 D 0D Yes No na - 0 - 0 - 0 - 0 Notes: VRT RS3 0 (LSB) na RS2 na RS1 na na = not affected. 1. Except bit 7. 2. Read/write only when OSC2–OSC0 in register A is 011 (binary). 8 1 DF na 32KE na - 0 HF RS0 na na DSE na - 0 - 0 - 0 - 0 bq3285E/L SQWE - Square-Wave Enable Register B 7 UTI 6 PIE 5 AIE Register B Bits 4 3 2 UIE SQWE DF 1 HF 7 - 0 DSE 6 - 5 - 4 - 3 SQWE 2 - 1 - 0 - 1 - 0 - This bit enables the square-wave output: Register B enables: 1 = Enabled n Update cycle transfer operation n Square-wave output n Interrupt events n Daylight saving adjustment 0 = Disabled and held low UIE - Update Cycle Interrupt Enable 7 - 6 - 5 - 4 UIE 3 - 2 - Register B selects: n This bit enables an interrupt request due to an update ended interrupt event: Clock and calendar data formats All bits of register B are read/write. 1 = Enabled DSE - Daylight Saving Enable 7 - 6 - 5 - 4 - 0 = Disabled 3 - 2 - 1 - 0 DSE The UIE bit is automatically cleared when the UTI bit equals 1. AIE - Alarm Interrupt Enable This bit enables daylight-saving time adjustments when written to 1: n n 7 - On the last Sunday in October, the first time the bq3285E/L increments past 1:59:59 AM, the time falls back to 1:00:00 AM. 5 - 4 - 3 - 2 - 1 HF 0 - 7 - 1 - 0 - 6 PIE 5 - 4 - 3 - 2 - 1 - 0 - This bit enables an interrupt request due to a periodic interrupt event: 0 = 12-hour format 1 = Enabled DF - Data Format 5 - 2 - PIE - Periodic Interrupt Enable 1 = 24-hour format 6 - 3 - 0 = Disabled This bit selects the time-of-day and alarm hour format: 7 - 4 - 1 = Enabled HF - Hour Format 6 - 5 AIE This bit enables an interrupt request due to an alarm interrupt event: On the first Sunday in April, the time springs forward from 2:00:00 AM to 3:00:00 AM. 7 - 6 - 0 = Disabled 4 - 3 - 2 DF 1 - 0 - This bit selects the numeric format in which the time, alarm, and calendar bytes are represented: 1 = Binary 0 = BCD 9 bq3285E/L UTI - Update Transfer Inhibit 7 UTI 6 - 5 - 4 - PF - Periodic Event Flag 3 - 2 - 1 - This bit is set to a 1 every tPI time, where tPI is the time period selected by the settings of RS0–RS3 in register A. Reading register C clears this bit. 0 - 7 - This bit inhibits the transfer of RTC bytes to the user buffer: 6 PF 5 - 4 - 3 - 2 - 1 - 0 - 1 = Inhibits transfer and clears UIE INTF - Interrupt Request Flag 0 = Allows transfer This flag is set to a 1 when any of the following is true: Register C AIE = 1 and AF = 1 PIE = 1 and PF = 1 7 6 5 INTF - Register C is the read-only event status register. 7 INTF 6 PF Register C Bits 5 4 3 2 AF UF 0 32KE 1 0 0 0 4 - 3 - 2 - 1 - 0 - UIE = 1 and UF = 1 Bits 0, 1, 3 - Unused Bits Reading register C clears this bit. These bits are always set to 0. Register D Register D is the read-only data integrity status register. 7 - 6 - 5 - 4 - 3 0 2 - 1 0 0 0 Bits 0–6 - Unused Bits These bits are always set to 0. 32KE - 32kHz Enable Output VRT - Valid RAM and Time Register D Bits 7 6 5 4 3 VRT 0 0 0 0 This bit may be set to a 1 only when the OSC2–OSC0 bits in register A are set to 011. Setting OSC2–OSC0 to 7 - 6 - 5 - 4 - 3 - 2 32KE 1 - 0 - 2 0 1 0 0 0 1 0 0 0 1 = Valid backup energy source anything other than 011 clears this bit. If SQWE in register B and 32KE are set, a 32.768kHz waveform is output on the square wave pin. 0 = Backup energy source is depleted 7 - UF - Update Event Flag This bit is set to a 1 at the end of the update cycle. 7 - 6 - 5 - 4 UF 3 - 2 - 1 - 0 - AF - Alarm Event Flag This bit is set to a 1 when an alarm event occurs. Reading register C clears this bit. 7 - 6 - 5 AF 4 - 3 - 2 - 1 - 0 - 10 5 0 4 0 3 0 2 0 When the backup energy source is depleted (VRT = 0), data integrity of the RTC and storage registers is not guaranteed. 7 VRT Reading register C clears this bit. 6 0 6 - 5 - 4 - 3 - 2 - 1 - 0 - bq3285E/L Absolute Maximum Ratings—bq3285E Symbol Parameter Value Unit Conditions VCC DC voltage applied on VCC relative to VSS -0.3 to 7.0 V VT DC voltage applied on any pin excluding VCC relative to VSS -0.3 to 7.0 V VT ≤ VCC + 0.3 TOPR 0 to +70 °C Commercial Operating temperature TSTG Storage temperature -55 to +125 °C TBIAS Temperature under bias -40 to +85 °C TSOLDER Soldering temperature 260 °C Note: For 10 seconds Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. Absolute Maximum Ratings—bq3285L Symbol Parameter Value Unit Conditions VCC DC voltage applied on VCC relative to VSS -0.3 to 6.0 V VT DC voltage applied on any pin excluding VCC relative to VSS -0.3 to 6.0 V VT ≤ VCC + 0.3 TOPR Operating temperature 0 to +70 °C Commercial TSTG Storage temperature -55 to +125 °C TBIAS Temperature under bias -40 to +85 °C TSOLDER Soldering temperature 260 °C Note: For 10 seconds Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. 11 bq3285E/L Recommended DC Operating Conditions—bq3285E (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit VCC Supply voltage 4.5 5.0 5.5 V VSS Supply voltage 0 0 0 V VIL Input low voltage -0.3 - 0.8 V VIH Input high voltage 2.2 - VCC + 0.3 V VBC Backup cell voltage 2.5 - 4.0 V Note: Typical values indicate operation at TA = 25°C. Recommended DC Operating Conditions—bq3285L (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit VCC Supply voltage 2.7 3.15 3.6 V VSS Supply voltage 0 0 0 V VIL Input low voltage -0.3 - 0.6 V VIH Input high voltage 2.2 - VCC + 0.3 V VBC Backup cell voltage 2.4 - 4.0 V Note: Typical values indicate operation at TA = 25°C. Crystal Specifications—bq3285E/L (DT-26 or Equivalent) Symbol Parameter Minimum Typical Maximum Unit - 32.768 - kHz 6 - pF 25 30 °C -0.042 ppm/°C fO Oscillation frequency CL Load capacitance - TP Temperature turnover point 20 k Parabolic curvature constant - - Q Quality factor 40,000 70,000 - R1 Series resistance - - 45 KΩ pF C0 Shunt capacitance - 1.1 1.8 C0/C1 Capacitance ratio - 430 600 DL Drive level - - 1 µW ∆f/fO Aging (first year at 25°C) - 1 - ppm 12 bq3285E/L DC Electrical Characteristics—bq3285E (TA = TOPR, VCC = 5V ± 10%) Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes ILI Input leakage current - - ±1 µA VIN = VSS to VCC ILO Output leakage current - - ±1 µA AD0–AD7, INT, and SQW in high impedance, VOUT = VSS to VCC VOH Output high voltage 2.4 - - V IOH = -2.0 mA VOL Output low voltage - - 0.4 V IOL = 4.0 mA ICC Operating supply current - 7 15 mA Min. cycle, duty = 100%, IOH = 0mA, IOL = 0mA ICCSB Standby supply current - 300 - µA VIN = VSS or VCC, CS ≥ VCC - 0.2 VSO Supply switch-over voltage - VBC - V ICCB Battery operation current - 0.3 0.5 µA VPFD Power-fail-detect voltage 4.0 4.17 4.35 V IRCL Input current when RCL = VSS. - - 185 µA Internal 30K pull-up Input current when MOT = VCC - - -185 µA Internal 30K pull-down Input current when MOT = VSS - - 0 µA Internal 30K pull-down Input current when EXTRAM = VCC - - -185 µA Internal 30K pull-down Input current when EXTRAM = VSS - - 0 µA Internal 30K pull-down VBC = 3V, TA = 25°C IMOTH IXTRAM Note: Typical values indicate operation at TA = 25°C, VCC = 5V or VBC = 3V. 13 bq3285E/L DC Electrical Characteristics—bq3285L (TA = TOPR, VCC = 3.15V ± 0.45V) Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes ILI Input leakage current - - ±1 µA VIN = VSS to VCC ILO Output leakage current - - ±1 µA AD0–AD7 and INT in high impedance, VOUT = VSS to VCC VOH Output high voltage 2.2 - - V IOH = -1.0 mA VOL Output low voltage - - 0.4 V IOL = 2.0 mA ICC Operating supply current - 5 9 mA Min. cycle, duty = 100%, IOH = 0mA, IOL = 0mA ICCSB Standby supply current - 100 - µA VIN = VSS or VCC, CS ≥ VCC - 0.2 - VPFD - V VBC > VPFD VSO Supply switch-over voltage - VBC - V VBC < VPFD VBC = 3V, TA = 25°C, VCC < VBC ICCB Battery operation current - 0.3 0.5 µA VPFD Power-fail-detect voltage 2.4 2.53 2.65 V IRCL Input current when RCL = VSS. - - 120 µA Internal 30K pull-up Input current when MOT = VCC - - -120 µA Internal 30K pull-down Input current when MOT = VSS - - 0 µA Internal 30K pull-down Input current when EXTRAM = VCC - - -120 µA Internal 30K pull-down Input current when EXTRAM = VSS - - 0 µA Internal 30K pull-down IMOTH IXTRAM Note: Typical values indicate operation at TA = 25°C, VCC = 3V. 14 bq3285E/L Capacitance—bq3285E/L (TA = 25°C, F = 1MHz, VCC = 5.0V) Symbol Parameter Minimum Typical Maximum Unit Conditions CI/O Input/output capacitance - - 7 pF VOUT = 0V CIN Input capacitance - - 5 pF VIN = 0V Note: This parameter is sampled and not 100% tested. It does not include the X1 or X2 pin. AC Test Conditions—bq3285E Parameter Test Conditions Input pulse levels 0 to 3.0 V Input rise and fall times 5 ns Input and output timing reference levels 1.5 V (unless otherwise specified) Output load (including scope and jig) See Figures 4 and 5 Figure 4. Output Load A—bq3285E Figure 5. Output Load B—bq3285E 15 bq3285E/L AC Test Conditions—bq3285L Parameter Test Conditions Input pulse levels 0 to 2.3 V Input rise and fall times 5 ns Input and output timing reference levels 1.2 V (unless otherwise specified) Output load (including scope and jig) See Figures 6 and 7 Figure 6. Output Load A—bq3285L Figure 7. Output Load B—bq3285L 16 bq3285E/L Read/Write Timing—bq3285E (TA = TOPR, VCC = 5V ± 10%) Symbol Parameter Minimum Typical Maximum Unit tCYC Cycle time 160 - - ns tDSL DS low or RD/WR high time 80 - - ns tDSH DS high or RD/WR low time 55 - - ns tRWH R/W hold time 0 - - ns tRWS R/W setup time 10 - - ns tCS Chip select setup time 5 - - ns tCH Chip select hold time 0 - - ns tDHR Read data hold time 0 - 25 ns tDHW Write data hold time 0 - - ns tAS Address setup time 20 - - ns tAH Address hold time 5 - - ns tDAS Delay time, DS to AS rise 10 - - ns tASW Pulse width, AS high 30 - - ns tASD Delay time, AS to DS rise (RD/WR fall) 35 - - ns tOD Output data delay time from DS rise (RD fall) - - 50 ns tDW Write data setup time 30 - - ns tBUC Delay time before update cycle - 244 - µs tPI Periodic interrupt time interval - - - - tUC Time of update cycle - 1 - µs 17 Notes See Table 3 bq3285E/L Read/Write Timing—bq3285L (TA = TOPR, VCC = 3.15V ± 0.45V) Symbol Parameter Minimum Typical Maximum Unit tCYC Cycle time 270 - - ns tDSL DS low or RD/WR high time 135 - - ns tDSH DS high or RD/WR low time 90 - - ns tRWH R/W hold time 0 - - ns tRWS R/W setup time 15 - - ns tCS Chip select setup time 8 - - ns tCH Chip select hold time 0 - - ns tDHR Read data hold time 0 - 40 ns tDHW Write data hold time 0 - - ns tAS Address setup time 30 - - ns tAH Address hold time 15 - - ns tDAS Delay time, DS to AS rise 15 - - ns tASW Pulse width, AS high 50 - - ns tASD Delay time, AS to DS rise (RD/WR fall) 55 - - ns tOD Output data delay time from DS rise (RD fall) - - 100 ns tDW Write data setup time 50 - - ns tBUC Delay time before update cycle - 244 - µs tPI Periodic interrupt time interval - - - - tUC Time of update cycle - 1 - µs 18 Notes See Table 3 bq3285E/L Motorola Bus Read/Write Timing—bq3285E/L 19 bq3285E/L Intel Bus Read Timing—bq3285E/L Intel Bus Write Timing—bq3285E/L 20 bq3285E/L Power-Down/Power-Up Timing—bq3285E (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit tF VCC slew from 4.5V to 0V 300 - - µs tR VCC slew from 0V to 4.5V 100 - - µs tCSR CS at VIH after power-up 20 - 200 ms Conditions Internal write-protection period after VCC passes VPFD on power-up. Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode may affect data integrity. Power-Down/Power-Up Timing—bq3285E 21 bq3285E/L Power-Down/Power-Up Timing—bq3285L (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit tF VCC slew from 2.7V to 0V 300 - - µs tR VCC slew from 0V to 2.7V 100 - - µs tCSR CS at VIH after power-up 20 - 200 ms Conditions Internal write-protection period after VCC passes VPFD on power-up. Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode may affect data integrity. Power-Down/Power-Up Timing—bq3285L 22 bq3285E/L Interrupt Delay Timing—bq3285E/L (TA = TOPR) Minimum Typical Maximum tRSW Symbol Reset pulse width Parameter 5 - - µs tIRR INT release from RST - - 2 µs tIRD INT release from DS - - 2 µs Interrupt Delay Timing—bq3285E/L 23 Unit bq3285E/L 24-Pin DIP (P) 24-Pin DIP (0.600" DIP) Inches Millimeters Dimension Min. Max. Min. Max. A 0.160 0.190 4.06 4.83 A1 0.015 0.040 0.38 1.02 B 0.015 0.022 0.38 0.56 B1 0.045 0.065 1.14 1.65 C 0.008 0.013 0.20 0.33 D 1.240 1.280 31.50 32.51 E 0.600 0.625 15.24 15.88 E1 0.530 0.570 13.46 14.48 e 0.600 0.670 15.24 17.02 G 0.090 0.110 2.29 2.79 L 0.115 0.150 2.92 3.81 S 0.070 0.090 1.78 2.29 24-Pin SOIC (S) 24-Pin S (0.300" SOIC) Inches B e D E Millimeters Dimension Min. Max. Min. Max. A 0.095 0.105 2.41 2.67 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.008 0.013 0.20 0.33 D 0.600 0.615 15.24 15.62 E 0.290 0.305 7.37 7.75 e 0.045 0.055 1.14 1.40 H 0.395 0.415 10.03 10.54 L 0.020 0.040 0.51 1.02 H A C .004 A1 L 24 bq3285E/L 24-Pin SSOP (SS) 24-Pin SS (0.150" SSOP) Inches Dimension Min. Max. Min. Max. A 0.061 0.068 1.55 1.73 A1 0.004 0.010 0.10 0.25 B 0.008 0.012 0.20 0.30 C 0.007 0.010 0.18 0.25 D 0.337 0.344 8.56 8.74 E 0.150 0.157 3.81 3.99 e 25 Millimeters .025 BSC 0.64 BSC H 0.230 0.244 5.84 6.20 L 0.016 0.035 0.41 0.89 bq3285E/L Data Sheet Revision History Change No. Page No. Description Nature of Change 1 8 Register C, bit 2 Was 0; is na (not affected) 1 18 Output data delay time tOD Was 80 ns max; is 100 ns max 2 1, 24, 26 Package option change Lst time buy for some package options. 3 1, 24, 26 Package option change Removed PLCC and added industrial SSOP package options 4 1, 11 Package option change Industrial package option removed Note: Change 1 = Jan. 1995 B “Final” changes from Dec. 1993 A “Preliminary”. Change 2 = Jan. 1999 C changes from Jan. 1995 B Change 3 = Apr. 1999 D changes from Jan. 1999 C. Change 4 = May 2004 (SLUS004A) changes from Apr. 1999 D 26 bq3285E/L Ordering Information bq3285E/L Temperature: blank = Commercial (0 to +70°C) Package Option: P = 24-pin plastic DIP (0.600) S = 24-pin SOIC (0.300) SS= 24-pin SSOP (0.150) Device: bq3285E Real-Time Clock with 242 bytes of general storage or bq3285L Real-Time Clock with 242 bytes of general storage (3V operation) bq3285L only available in 24-pin SSOP (0.150). 27 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) BQ3285ES ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 3285ES -B2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of