BQ51222YFPT

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 bq51222 Dual Mode 5-W (WPC v1.2 and PMA) Single Chip Wireless Power Receiver 1 Features 3 Description • The bq51222 device is a fully contained wireless power receiver capable of operating in both the Wireless Power Consortium (WPC) Qi and Power Matters Alliance (PMA) protocols which allows a wireless power system to work with both inductive charging standards. The bq51222 device provides a single device power conversion (rectification and regulation) as well as the digital control and communication for both standards. It also has autonomous detection of protocol and requires no additional active devices. The bq51222 device complies with the WPC v1.2 and PMA communication protocol. Together with the WPC or a PMA primaryside controller, the bq51222 device enables a complete wireless power transfer system for a wireless power supply solution. The receiver allows for synchronous rectification, regulation and control and communication to all exist in a market-leading form factor, efficiency, and solution size. Robust 5-W Solution with 50% Lower Losses for Improved Thermals – Inductorless Receiver for Lowest Height Profile Solution – Adjustable Output Voltage (4.5 to 8 V) for Coil and Thermal Optimization – Fully Synchronous Rectifier with 96% Efficiency – 97% Efficient Post Regulator – 79% System Efficiency at 5 W WPC v1.2 and PMA Compliant Communication Patented Transmitter Pad Detect Function Improves User Experience I2C Communication with Host 1 • • • 2 Applications • • • • Smart Phones, Tablets, and Headsets Wi-Fi Hotspots Power Banks Other Handheld Devices Device Information(1) PART NUMBER bq51222 PACKAGE DSBGA (42) BODY SIZE (MAX) 3.586 mm × 2.874 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. SPACER Simplified Schematic Dual Mode Efficiency 5-V Out 90 bq51222 System Load AD-EN AD 80 OUT CCOMM1 70 C4 COMM1 CBOOT1 R7 RECT C1 RECT Efficiency (%) BOOT1 C3 AC1 R6 VO_REG C2 VIREG AC2 CBOOT2 R9 R8 BOOT2 COMM2 CCLAMP1 z z TMEM CLAMP2 NTC HOST C5 CLAMP1 30 SCL CM_ILIM SDA FOD 20 PMA Duracell TX WPC A1 TX 0 LPRB2 R5 40 10 LPRB1 TERM ILIM 50 TS/CTRL CCOMM2 CCLAMP2 60 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 IOUT (A) 1 1.1 1.2 D001 PGND R1 RFOD Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 4 5 5 5 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 8.1 Overview ................................................................... 9 8.2 Functional Block Diagram ....................................... 11 8.3 Feature Description................................................. 12 8.4 Device Functional Modes........................................ 18 8.5 Register Maps ......................................................... 22 9 Application and Implementation ........................ 28 9.1 Application Information............................................ 28 9.2 Typical Applications ................................................ 29 10 Power Supply Recommendations ..................... 41 11 Layout................................................................... 42 11.1 Layout Guidelines ................................................. 42 11.2 Layout Example .................................................... 42 12 Device and Documentation Support ................. 43 12.1 12.2 12.3 12.4 12.5 12.6 Device Support .................................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 43 43 43 43 43 43 13 Mechanical, Packaging, and Orderable Information ........................................................... 43 4 Revision History Changes from Original (July 2016) to Revision A • 2 Page Changed from Product Preview to Production Data............................................................................................................... 1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 5 Device Comparison Table DEVICE MODE bq51221 Dual (WPC v1.1, PMA) Adjustable output voltage, highest system efficiency, I2C MORE bq51222 Dual (WPC v1.2, PMA) Adjustable output voltage, highest system efficiency, I2C bq51021 WPC v1.1 Adjustable output voltage, highest system efficiency, I2C bq51020 WPC v1.1 Adjustable output voltage, highest system efficiency, standalone 6 Pin Configuration and Functions YFP Package 42-Pin DSBGA Top View A1 PGND A2 PGND A3 PGND A4 PGND A5 PGND A6 PGND B1 AC1 B2 AC1 B3 AC1 B4 AC2 B5 AC2 B6 AC2 C1 BOOT1 C2 RECT C3 RECT C4 RECT C5 RECT C6 BOOT2 D1 OUT D2 OUT D3 OUT D4 OUT D5 OUT D6 OUT E1 CLAMP1 E2 AD E3 /AD_EN E4 SCL E5 VIREG E6 CLAMP2 F1 COMM1 F2 FOD F3 LPRBEN TERM F4 SDA F5 LPRB1 WPG F6 COMM2 G1 VO_REG G2 ILIM G3 CM_ILIM G4 TS/CTRL G5 TMEM G6 LPRB2 PD_DET Pin Functions PIN NAME NUMBER TYPE DESCRIPTION AC1 B1, B2, B3 I AC2 B4, B5, B6 I AD E2 I Adapter sense pin AD-EN E3 O Push-pull driver for PFET that can pass AD input to the OUT pin; used for adapter mux control BOOT1 C1 O BOOT2 C6 O COMM1 F1 O COMM2 F6 O CLAMP1 E1 O CLAMP2 E6 O CM_ILIM G3 I Enables or disables communication current limit; can be pulled high or low to disable or enable communication current limit FOD F2 I Input that is used for scaling the received power message ILIM G2 I/O AC input power from receiver resonant tank Bootstrap capacitors for driving the high-side FETs of the synchronous rectifier Open-drain FETs used to communicate with primary by varying reflected impedance Open-drain FETs used to clamp the secondary voltage by providing low impedance across secondary Output current or overcurrent level programming pin Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 3 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com Pin Functions (continued) PIN NAME LPRB 1 F5 LPRB 2 G6 OUT TYPE NUMBER DESCRIPTION O Open drain – active to help drive RECT voltage high at light load on a PMA TX D1, D2, D3, D4, D5, D6 O Output pin, used to deliver power to the load PD_DET G6 O Open drain output that allows user to sense when receiver is on transmitter PGND A1, A2, A3, A4, A5, A6 — Power and logic ground RECT Filter capacitor for the internal synchronous rectifier C2, C3, C4, C5 O SCL E4 I SDA F4 I TERM, LPRBEN F3 I Sets termination current as a percentage of IILIM as TERM pin. When TERM resistor is populated, LPRB pins are enabled with appropriate function TMEM G5 O TMEM allows capacitor to be connected to GND so energy from transmitter ping can be stored to retain memory of state TS/CTRL G4 I Temperature sense. Can be pulled high to send end power transfer (EPT) or end of charge (EOC) to TX VIREG E5 I Rectifier voltage feedback VO_REG G1 I Sets the regulation voltage for output WPG F5 O Open-drain output that allows user to sense when power is transferred to load SCL and SDA are used for I2C communication 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted) (1) (2) MIN MAX AC1, AC2 –0.8 20 RECT, COMM1, COMM2, OUT, LPRB1, LPRB2, CLAMP1, CLAMP2, WPG, PD_DET –0.3 20 AD, AD-EN –0.3 30 BOOT1, BOOT2 –0.3 20 SCL, SDA, TERM, CM_ILIM, FOD, TS/CTRL, ILIM, TMEM, VIREG, VO_REG, LPRBEN –0.3 7 Input current AC1, AC2 (RMS) 2.5 Output current OUT 1.5 A Output sink current LPRB1, LPRB2 15 mA Output sink current COMM1, COMM2 Input voltage UNIT V A 1 A Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) (2) 4 All voltages are with respect to the PGND pin, unless otherwise noted. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 7.2 ESD Ratings VALUE V(ESD) (1) (1) (2) (3) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (2), 100 pF, 1.5 kΩ ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (3) ±500 UNIT V Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VRECT RECT voltage range IOUT Output current IAD-EN Sink current ICOMM COMMx sink current TJ Junction temperature MIN MAX 4 10 V 1 A 0 UNIT 1 mA 500 mA 125 ºC 7.4 Thermal Information bq51222 THERMAL METRIC (1) YFP (DSBGA) UNIT 42 PINS RθJA Junction-to-ambient thermal resistance (2) 49.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance (3) 0.2 °C/W 6.1 °C/W 1.4 °C/W 6 °C/W N/A °C/W (4) RθJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter (5) ψJB Junction-to-board characterization parameter (6) RθJC(bot) (1) (2) (3) (4) (5) (6) (7) Junction-to-case (bottom) thermal resistance (7) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 5 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com 7.5 Electrical Characteristics ILOAD = IOUT, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.9 VUVLO Undervoltage lockout VRECT: 0 to 3 V 2.8 VHYS-UVLO Hysteresis on UVLO VRECT: 3 to 2 V 393 VRECT-OVP Input overvoltage threshold VRECT: 5 to 16 V VHYS-OVP Hysteresis on OVP VRECT: 16 to 5 V VRECT(REG) Voltage at RECT pin set by communication with primary VRECT(TRACK ) VRECT regulation above VOUT 14.6 15.1 VILIM = 1.2 V ILOAD-HYS ILOAD hysteresis for dynamic I falling VRECT thresholds as a % of IILIM LOAD VRECT-DPM Rectifier under voltage protection, restricts IOUT at VRECT-DPM VRECT-REV Rectifier reverse voltage protection with a supply at the output ILPRB1-dis ILPRB2-dis V mV 15.6 1.5 VOUT + 0.12 UNIT V V VOUT + 2 140 V mV 4% 3 3.1 3.2 V VRECT-REV = VOUT – VRECT, VOUT = 10 V 8.8 9.2 V Current at which LPRB1 is disabled IOUT 0 to 200 mA 125 mA Current at which LPRB2 is disabled IOUT 0 to 400 mA 322 mA QUIESCENT CURRENT IOUT(standby) Quiescent current at the output V ≤ 5 V, 0°C ≤ TJ ≤ 85°C when wireless power is disabled OUT 20 35 µA 215 230 Ω ILIM SHORT CIRCUIT RILIM-SHORT Highest value of RILIM resistor considered a fault (short). Monitored for IOUT > 100 mA tDGL-Short Deglitch time transition from ILIM short to IOUT disable ILIM_SC ILIM-SHORT,OK enables the ILIM short comparator when IOUT is greater than this value ILOAD: 0 to 200 mA Hysteresis for ILIM-SHORT,OK comparator ILOAD: 200 to 0 mA 20 mA Maximum output current limit Maximum ILOAD that can be delivered for 1 ms when ILIM is shorted 3.7 A ILIMSHORT,OK HYSTERESIS IOUT-CL RILIM: 200 to 50 Ω. IOUT latches off, cycle power to reset 1 110 125 ms 140 mA OUTPUT ILOAD = 1000 mA VO_REG Feedback voltage set point KILIM RILIM = KILIM / IILIM, where IILIM is Current programming factor for the hardware current limit hardware short circuit protection IOUT = 850 mA IOUT_RANGE Current limit programming range ICOMM Output current limit during communication ILOAD = 1 mA 6 0.5013 0.5075 0.4951 0.5014 0.5076 842 IOUT ≥ 400 mA IOUT – 50 100 mA ≤ IOUT < 400 mA IOUT + 50 Hold off time for the communication current limit during startup mA mA None 1 Submit Documentation Feedback V AΩ 1500 IOUT < 100 mA tHOLD-OFF 0.495 s Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 Electrical Characteristics (continued) ILOAD = IOUT, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TS/CTRL VTS-Bias TS bias voltage (internal) ITS-Bias < 100 µA and communication is active (periodically driven, see tTS/CTRLMeas) VCTRL-HI CTRL pin threshold for a high VTS/CTRL: 50 to 150 mV TTS/CTRL- Time period of TS/CTRL measurements, when TS is being driven TS bias voltage is only driven when power packets are sent Meas VTS-HOT 1.8 90 Voltage at TS pin when device shuts down 105 V 120 mV 1700 ms 0.38 V 155 °C 20 °C THERMAL PROTECTION TJ(OFF) Thermal shutdown temperature TJ(OFF-HYS) Thermal shutdown hysteresis OUTPUT LOGIC LEVELS ON WPG VOL Open drain WPG pin ISINK = 5 mA 550 mV IOFF,STAT WPG leakage current when disabled VWPG = 20 V 1 µA COMM1 and COMM2 VRECT = 2.6 V COMM PIN RDSON(COMM) ƒCOMM Signaling frequency on COMMx pin for WPC IOFF,COMM COMMx pin leakage current 1 Ω 2.00 VCOMM1 = 20 V, VCOMM2 = 20 V Kb/s 1 µA CLAMP PIN RDS- CLAMP1 and CLAMP2 0.5 Ω ON(CLAMP) ADAPTER ENABLE VAD-EN VAD rising threshold voltage VAD 0 V to 5 V VAD-EN-HYS VAD-EN hysteresis VAD 5 V to 0 V IAD Input leakage current VRECT = 0 V, VAD = 5 V RAD_EN-OUT Pullup resistance from AD-EN to OUT when adapter mode is disabled and VOUT > VAD VAD = 0 V, VOUT = 5 V VAD_EN-ON Voltage difference between VAD VAD = 5 V, 0°C ≤ TJ ≤ 85°C and VAD-EN when adapter mode VAD = 9 V, 0°C ≤ TJ ≤ 85°C is enabled 3.5 3.6 3.8 450 V mV 50 μA 230 350 Ω 4 4.5 5 V 3 6 7 V SYNCHRONOUS RECTIFIER ISYNC-EN IOUT at which the synchronous rectifier enters half synchronous IOUT: 200 mA to 0 mA mode ISYNC-EN- Hysteresis for IOUT,RECT-EN (fullsynchronous mode enabled) 100 mA IOUT 0 mA to 200 mA 40 mA High-side diode drop when the rectifier is in half synchronous mode IAC-VRECT = 250 mA, and TJ = 25°C 0.7 V VIL Input low threshold level SDA V(PULLUP) = 1.8 V, SDA VIH Input high threshold level SDA V(PULLUP) = 1.8 V, SDA VIL Input low threshold level SCL V(PULLUP) = 1.8 V, SCL VIH Input high threshold level SCL V(PULLUP) = 1.8 V, SCL HYST VHS-DIODE I2C I2C speed Typical 0.4 1.4 V 0.4 1.4 Product Folder Links: bq51222 V V 100 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated V kHz 7 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com 7.6 Typical Characteristics Temperature = 25°C (unless otherwise noted) 60 0.5015 50 Quiescent Current (PA) 0.50155 VO_REG (V) 0.50145 0.5014 0.50135 0.5013 30 20 10 0.50125 0.5012 0.0001 0 0.001 0.01 Load Current (A) 0.1 1 4 845 2.865 8 9 D002 2.85 2.835 VUVLO (V) 835 830 825 820 2.82 2.805 2.79 2.775 815 2.76 810 2.745 350 450 550 650 750 Load Current (mA) 850 2.73 -60 950 -40 -20 0 D001 20 40 60 Temperature (qC) 80 100 120 140 D004 Figure 4. VUVLO as a Function of Junction Temperature Figure 3. KILIM as a Function of Load Current 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 VO_REG (V) VO_REG (V) 7 Figure 2. Quiescent Current as a Function of Output Voltage 2.88 840 0.5 0.4 0.5 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 0 1 2 3 4 I2C Code 5 6 7 0 D001 Register 0x01 (B0, B1, B2) 1-mA Load 1 2 3 4 I2C Code 5 6 7 D001 Register 0x01 (B0, B1, B2) 1-A Load Figure 5. Register 0x01 control of VO_REG 8 6 VOUT (V) 850 805 250 5 D001 Figure 1. Output Voltage Feedback as a Function of Load KILIM 40 Submit Documentation Feedback Figure 6. Register 0x01 control of VO_REG Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 8 Detailed Description 8.1 Overview Both WPC and PMA wireless power systems consist of a charging pad (primary, transmitter) and the secondaryside equipment (receiver). There are coils in the charging pad and secondary equipment, which magnetically couple to each other when the receiver is placed on the transmitter. Power is transferred from the primary to the secondary by transformer action between the coils. The receiver can achieve control over the amount of power transferred by getting the transmitter to change the field strength by changing the frequency, or duty cycle, or voltage rail energizing the primary coil. The receiver equipment communicates with the primary by modulating the load seen by the primary. This load modulation results in a change in the primary coil current or primary coil voltage, or both, which is measured and demodulated by the transmitter. In WPC, the system communication is digital — packets that are transferred from the secondary to the primary. Differential bi-phase encoding is used for the packets. The bit rate is 2 kb/s. Various types of communication packets are defined. These include identification and authentication packets, error packets, control packets, power usage packets, and end power transfer packets, among others. An PMA-compliant receiver communicates based on continuous transmission of signals from the receiver to the transmitter. The PMA specification defines six different communications symbols. These are increment (INC), decrement (DEC), no change (NoCh), end of charge (EOC), MsgBit, and a symbol for future use. Each PMA receiver has a unique PMA RXID, which is a 6-byte unique message that is sent to the PMA TX at startup. Power AC to DC Drivers bq51222 Rectification Voltage/ Current Conditioning System Load Communication Controller V/I Sense Controller Transmitter Battery Charger LI-Ion Battery Receiver Figure 7. Dual Mode Wireless Power System Indicating the Functional Integration of the bq51222 Family The bq51222 device integrates fully-compliant WPC v1.2 and PMA communication protocols in order to streamline the dual mode receiver designs (no extra software development required). Other unique algorithms such as Dynamic Rectifier Control are integrated to provide best-in-class system efficiency while keeping the smallest solution size of the industry. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 9 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com Overview (continued) As a WPC system, when the receiver shown in Figure 7 is placed on the charging pad, the secondary coil couples to the magnetic flux generated by the coil in the transmitter, which consequently induces a voltage in the secondary coil. The internal synchronous rectifier feeds this voltage to the RECT pin, which in turn feeds the LDO which feeds the output. The bq51222 device identifies and authenticates itself to the primary using the COMMx pins, switching on and off the COMM FETs, and hence switching in and out COMM capacitors. If the authentication is successful, the primary remains powered-up. The bq51222 device measures the voltage at the RECT pin, calculates the difference between the actual voltage and the desired voltage VRECT(REG), and sends back error packets to the transmitter. This process goes on until the input voltage settles at VRECT(REG) MAX. During a load change, the dynamic rectifier algorithm sets the targets specified by targets between VRECT(REG) MAX and VRECT(REG) MIN shown in Table 1. This algorithm enhances the transient response of the power supply. After the voltage at the RECT pin is at the desired value, a pass FET is enabled. The voltage control loop ensures that the output voltage is maintained at VOUT(REG), powering the downstream charger. The bq51222 device meanwhile continues to monitor the input voltage, and keeps sending control error packets (CEP) to the primary on average every 250 ms. If a large transient occurs, the feedback to the primary speeds up to 32-ms communication periods to converge on an operating point in less time. If the receiver shown in Figure 7 is used with a PMA transmitter, the bq51222 device identifies itself to the PMA transmitter using the COMMx pins. If sufficient power is delivered to the bq51222 device to wake up the device, it responds by modulating the power signal according to the PMA communication protocol. Prior to enabling the output, the bq51222 device transmits an RXID message. This is a unique identification message that is controlled through an IEEE sanctioned database and every bq51222 device comes programmed with its own unique RXID that can be read back using I2C. See I2C register map in Register Maps for details on the location of the RXID. The bq51222 device then monitors the voltage at the RECT pin. If there is a difference between the actual voltage and the desired voltage VRECT(REG), the device sends a PMA DEC or PMA INC signal to the PMA transmitter to control the RECT voltage to be within the desired window. The receiver regulates VRECT to a desired window of operation shown in Figure 15. 10 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 8.2 Functional Block Diagram I OUT VREF,ILIM VILIM + _ + _ RECT VOUT,FB VOUT,REG VO_REG VREF,IABS VIABS,FB + _ VIN,FB VIN,DPM + _ ILIM AD + _ VREFAD,OVP BOOT2 + _ BOOT1 VREFAD,UVLO AD-EN AC1 AC2 Sync Rectifier Control VIREG TS COMM1 COMM2 DATA_ OUT ADC CLAMP1 VBG,REF VIN,FB VOUT,FB VILIM VIABS,FB TS/CTRL VIABS,REF VIC,TEMP VFOD CLAMP2 Digital Control OVP LPRB1 or WPG + _ VFOD VRECT VOVP,REF SCL SCL LPRB2 or PD _ DET FOD SDA SDA 50 µA CM_ILIM TERM LPRBEN or TERM + _ TMEM PGND ILIM Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 11 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com 8.3 Feature Description 8.3.1 Dynamic Rectifier Control WPC Mode Only The Dynamic Rectifier Control algorithm offers the end system designer optimal transient response for a given maximum output current setting. This is achieved by providing enough voltage headroom across the internal regulator (LDO) at light loads in order to maintain regulation during a load transient. The WPC system has a relatively slow global feedback loop where it can take up to 150 ms to converge on a new rectifier voltage target. Therefore, a transient response is dependent on the loosely coupled transformer's output impedance profile. The Dynamic Rectifier Control allows for a 1.5-V change in rectified voltage before the transient response is observed at the output of the internal regulator (output of the bq51222 device). A 1-A application allows up to a 2-Ω output impedance. The Dynamic Rectifier Control behavior is illustrated in Figure 13 where RILIM is set to 680 Ω. 8.3.2 Dynamic Power Scaling WPC Mode Only The Dynamic Power Scaling feature allows for the loss characteristics of the bq51222 device to be scaled based on the maximum expected output power in the end application. This effectively optimizes the efficiency for each application. This feature is achieved by scaling the loss of the internal LDO based on a percentage of the maximum output current. Note that the maximum output current is set by the KILIM term and the RILIM resistance (where RILIM = KILIM / IILIM). The flow diagram in Figure 13 shows how the rectifier is dynamically controlled (Dynamic Rectifier Control) based on a fixed percentage of the IILIM setting. Table 1 summarizes how the rectifier behavior is dynamically adjusted based on two different RILIM settings. The table is shown for IMAX, which is typically lower than IILIM (about 20% lower). See RILIM Calculations for more details. Table 1. Dynamic Rectifier Regulation OUTPUT CURRENT PERCENTAGE RILIM = 1400 Ω IMAX = 0.5 A RILIM = 700 Ω IMAX = 1.0 A VRECT 0 to 10% 0 to 0.05 A 0 to 0.1 A VOUT + 2 10 to 20% 0.05 to 0.1 A 0.1 to 0.2 A VOUT + 1.68 20 to 40% 0.1 to 0.2 A 0.2 to 0.4 A VOUT + 0.56 >40% >0.2 A >0.4 A VOUT + 0.12 Dynamic Rectifier Control shows the shift in the dynamic rectifier control behavior based on the two different RILIM settings. With the rectifier voltage (VRECT) being the input to the internal LDO, this adjustment in the Dynamic Rectifier Control thresholds dynamically adjusts the power dissipation across the LDO where: PDIS VRECT VOUT ˜ IOUT (1) Figure 40 shows how the system efficiency is improved due to the Dynamic Power Scaling feature. Note that this feature balances efficiency with optimal system transient response. 12 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 8.3.3 VO_REG and VIREG Calculations WPC and PMA Modes The bq51222 device allows the designer to set the output voltage by setting a feedback resistor divider network from the OUT pin to the VO_REG pin as seen in Figure 8. The resistor divider network should be chosen so that the voltage at the VO_REG pin is 0.5 V at the desired output voltage. This applies to the default I2C code for VO_REG shown in I2C register 0x01 shown in Table 5 (Bits B0, B1, B2). RECT OUT R7 R9 VIREG R8 VO_REG R6 NTC R3 R4 LPRB1 LPRB2 Figure 8. VO_REG Network Figure 9. VIREG Network (For PMA) Choose the desired output voltage VOUT and R6: 0.5 V K VO VOUT R6 (2) K VO u R7 1 K VO (3) After R6 and R7 are chosen, the same divider network is attached to VIREG pin from RECT to GND, as shown in Figure 9. R9 = R7 and R8 = R6. LPRB1 and LPRB2 are two additional pins that are used to implement a back cover solution and are used for PMA (see Figure 55). In a back cover solution where the system designer cannot depend on the characteristics of the downstream charger in the phone, these pins can be used to boost the rectifier at a lower power (Low Power Rectifier Boost), so that the system is able to survive a load transient from 0 mA to the maximum current by boosting the rectifier during low power output that the system is designed for. See resistor calculations for LPRB1 and LPRB2: in the bq51222 web page "Tools & software" tab. The Excel file not only provides how to calculate the LPRB resistor values but also assists with other calculations. The Excel file can be accessed at www.ti.com/product/bq51222/toolssoftware. Table 2. LPRB Condition Table IOUT LPRB1 LPRB2 0 mA < IOUT < 100 mA ON ON 100 mA < IOUT < 350 mA OFF ON 350 mA < IOUT < Maximum current OFF OFF The LPRB1 and LPRB2 resistors can be omitted in an embedded solution where the system designer is in control of the voltage at which the downstream charger can regulate the input current to prevent the input from collapsing in a load transient (VIN-DPM). The functionality of LPRB1 and LPRB2 can be reverted to WPG and PD_DET by not populating the TERM resistor. In this case, the host enables the charge complete on the TS/CTRL pin by pulling this pin high. For the back cover solution, the TERM resistor is populated and this enables LPRB1 and LPRB2 functionality. The functionality can be seen in Table 2. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 13 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com 8.3.4 RILIM Calculations WPC and PMA Modes The bq51222 device includes a means of providing hardware overcurrent protection (IILIM) through an analog current regulation loop. The hardware current limit provides an extra level of safety by clamping the maximum allowable output current (for example, current compliance). The RILIM resistor size also sets the thresholds for the dynamic rectifier levels providing efficiency tuning per each application’s maximum system current. The calculation for the total RILIM resistance is as follows: RILIM = KILIM / IILIM R1 = RILIM – RFOD (4) (5) RILIM allows for the ILIM pin to reach 1.2 V at an output current equal to IILIM. When choosing RILIM, two options are possible. If the user's application requires an output current equal to or greater than the external IILIM that the circuit is designed for (input current limit on the charger where the receiver device is tied higher than the external IILIM), ensure that the downstream charger is capable of regulating the voltage of the input into which the receiver device output is tied to by lowering the amount of current being drawn. This ensures that the receiver output does not drop to 0 V. Such behavior is referred to as Dynamic Power Management (VIN-DPM) in TI chargers. Unless such behavior is enabled on the charger, the charger will pull the output of the receiver device to ground when the receiver device enters current regulation. If the user's applications are designed to extract less than the IILIM (1-A maximum), typical designs should leave a design margin of at least 10%, so that the voltage at ILIM pin reaches 1.2 V when 10% more than maximum current is drawn from the output. Such a design would have input current limit on the charger lower than the external ILIM of the receiver device. In both cases however, the charger must be capable of regulating the current drawn from the device to allow the output voltage to stay at a reasonable value. This same behavior is also necessary during the WPC communication. The following calculations show how such a design is achieved: RILIM = KILIM / (1.1 × IILIM) R1 = RILIM – RFOD (6) (7) where ILIM is the hardware current limit. When referring to the application diagram shown in Typical Applications, RILIM is the sum of the R1 and RFOD resistance (that is, the total resistance from the ILIM pin to GND). RFOD is chosen according to the application. The tool for calculating RFOD can be obtained by contacting your TI representative. Use RFOD to allow the receiver implementation to comply with WPC v1.2 requirements related to received power accuracy. 8.3.5 Adapter Enable Functionality WPC and PMA Modes The bq51222 device can also help manage the multiplexing of adapter power to the output and can shut off the TX when the adapter is plugged in and is above the VAD-EN. After the adapter is plugged in and the output turns off, the RX device sends an EOC to the TX. In this case, the AD_EN pins are then pulled to approximately 4 V below AD, which allows the device turn on the back-to-back PMOS connected between AD and OUT (Figure 54). Both the AD and AD-EN pins are rated at 30 V, while the OUT pin is rated at 20 V. It must also be noted that it is required to connect a back-to-back PMOS between AD and OUT so that voltage is blocked in both directions. Also, when AD mode is enabled, no load can be pulled from the RECT pin as this could cause an internal device overvoltage in the bq51222 device. 8.3.6 Turning Off the Transmitter WPC and PMA Modes Both specifications allow the receiver to turn off the transmitter and put the system in a low-power standby mode. There are two different ways to accomplish this with the bq51222 device. In both modes, the EPT charge complete (WPC) or end of charge (PMA) can be sent to the TX by pulling the TS pin high (above 1.4 V). The bq51222 device will then sense this and send the appropriate signal to the TX, thus putting the TX in a low power standby mode. 14 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 8.3.6.1 WPC End Power Transfer (EPT) The WPC allows for a special command to terminate power transfer from the TX termed EPT packet. The v1.2 specifies the following reasons and their responding data field value in Table 3. Table 3. End Power Transfer Codes in WPC REASON VALUE CONDITION (1) Unknown 0x00 AD > 3.6 V Charge Complete 0x01 TS/CTRL = 1 Internal Fault 0x02 TJ > 150°C or RILIM < 215 Ω Over Temperature 0x03 TS < VTS-HOT, or TS/CTRL < 100 mV (2) Over Voltage 0x04 VRECT target does not converge (3) (1) (2) (3) Over Current 0x05 Not sent Battery Failure 0x06 Not sent Reconfigure 0x07 Not sent No Response 0x08 Not sent The Condition column corresponds to the case where the bq51222 device will send the WPC EPT command. The TS < VTS-HOT condition refers to using an external thermistor for temperature control. The TS/CTRL < 100 mV condition refers to driving the TS/CTRL pin from an external GPIO. If the voltage on the RECT pin does not reach the required value (typically 8 V) within 64 error packets during startup (weak coil coupling), the receiver sends EPT-OV and the transmitter will shut off. 8.3.6.2 PMA EOC PMA EOC is a state where the bq51222 device disables the output and sends EOC frequency to terminate the power transfer on a PMA transmitter. This can be done by setting the TERM pin resistor so that the voltage on the TERM pin is higher than the ILIM pin at the desired termination current. This TERM resistor method of sending the EOC to the transmitter only works with PMA TX. After the TERM resistor is populated, it also changes the behavior of the LPRBx pins. Check the section on LPRBx resistors for more information. Another way to send an EOC to the PMA TX is to pull the TS pin above 1.4 V through an external pullup. 8.3.7 CM_ILIM WPC Mode Only Communication current limit is a feature that allows for error free communication to happen between the RX and TX in the WPC mode. This is done by decoupling the coil from the load transients by limiting the output current during communication with the TX. The communication current limit is set according to Table 4. The communication current limit can be disabled by pulling CM_ILIM pin high (> 1.4 V) or enabled by pulling the CM_ILIM pin low. There is an internal pulldown that enables communication current limit when the CM_ILIM pin is left floating. Table 4. Communication Current Limit Table IOUT COMMUNICATION CURRENT LIMIT 0 mA < IOUT < 100 mA None 100 mA < IOUT < 400 mA IOUT + 50 mA 400 mA < IOUT < Max current IOUT – 50 mA Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 15 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com When the communication current limit is enabled, the amount of current that the load can draw is limited. If the charger in the system does not have a VIN-DPM feature, the output of the receiver will collapse if communication current limit is enabled. In order to disable Communication Current Limit, pull CM_ILIM pin high. 8.3.8 PD_DET and TMEM PD_DET is only available in WPC mode. This is an open-drain pin that goes low based on the voltage of the TMEM pin. When the voltage of TMEM is higher than 1.6 V, PD_DET will be low. The voltage on the TMEM pin depends on capturing the energy from the digital ping from the transmitter and storing it on the C5 capacitor in Figure 10. After the receiver sends an EPT (charge complete), the transmitter shuts down and goes into a lowpower mode. However, it will continue to check if the receiver would like to renegotiate a power transfer by periodically performing the digital ping. The energy from the digital ping can be stored on the TMEM pin until the next digital ping refreshes the capacitor. A bleedoff resistor RMEM can be chosen in parallel with C5 that sets the time constant so that the TMEM pin will fall below 1.6 V once the next ping timer expires. The duration between digital pings is indeterminate and depends on each transmitter manufacturer. TMEM RMEM C5 Figure 10. TMEM Configuration Set capacitor on C5 = TMEM to 2.2 µF. Resistor RMEM across C5 can be set by understanding the duration between digital pings (tping). Set the resistor such that: tping RMEM C5 (8) 8.3.9 TS, Both WPC and PMA The bq51222 device includes a ratio metric external temperature sense function. The temperature sense function has a low ratio metric threshold which represents a hot condition. TI recommends an external temperature sensor in order to provide safe operating conditions for the receiver product. This pin is best used for monitoring the surface that can be exposed to the end user (for example, place the negative temperature coefficient (NTC) resistor closest to the user touch point on the back cover). A resistor in series or parallel can be inserted to adjust the NTC to match the trip point of the device. The implementation in Figure 11 shows the series-parallel resistor implementation for setting the threshold at which VTS-HOT is reached. Once VTS-HOT is reached, the device will send an EPT – overtemperature signal for a WPC transmitter or an EOC signal to a transmitter depending on the mode the device is operating in. An Excel tool to assist with defining the correct resistor values is available on the bq51222 web folder under 'Tools & Software'. The Excel file can be found at www.ti.com/product/bq5122PMA2/toolssoftware. VTSB (1.8 V) R2 20 k TS/CTRL R1 NTC R3 Figure 11. NTC Resistor Setup 16 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 Figure 11 shows a parallel resistor setup that can be used to adjust the trip point of VTS-HOT. After the NTC is chosen and RNTCHOT at VTS-HOT is determined from the data sheet of the NTC, Equation 9 can be used to calculate R1 and R3. In many cases depending on the NTC resistor, R1 or R3 can be omitted. When calculating VTS-HOT, omit R1 by setting it to 0 Ω, and omit R3 by setting it to 10 MΩ. VTS HOT 1.8 V u RNTCHOT R1 u R3 RNTCHOT R1 R3 RNTCHOT R1 u R3 RNTCHOT R1 R3 R2 (9) 8.3.10 I2C Communication WPC and PMA Modes The bq51222 device allows for I2C communication with the internal CPU. In case the I2C is not used, ground SCL and SDA. See Register Maps for more information. 8.3.11 Input Overvoltage WPC and PMA Modes If the input voltage suddenly increases in potential for some condition (for example a change in position of the equipment on the charging pad), the voltage-control loop inside the bq51222 device becomes active, and prevents the output from going beyond VOUT(REG). The receiver then starts sending back error packets every 30 ms until the input voltage comes back to an acceptable level, and then maintains the error communication every 250 ms. If the input voltage increases in potential beyond VRECT-OVP, the device switches off the LDO and informs the primary to bring the voltage back to VRECT(REG). In addition, a proprietary voltage protection circuit is activated by means of CCLAMP1 and CCLAMP2 that protects the device from voltages beyond the maximum rating of the device. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 17 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com 8.4 Device Functional Modes In WPC mode, at startup operation, the bq51222 device must comply with proper handshaking in order to be granted a power contract from the WPC transmitter. The transmitter initiates the handshake by providing an extended digital ping after analog ping detects an object on the transmitter surface. If a receiver is present on the transmitter surface, the receiver then provides the signal strength, configuration, and identification packets to the transmitter (see volume 1 of the WPC specification for details on each packet). These are the first three packets sent to the transmitter. The only exception is if there is a true shutdown condition on the AD, or TS/CTRL pins where the receiver shuts down the transmitter immediately. See Table 3 for details. After the transmitter has successfully received the signal strength, configuration, and identification packets, the receiver is granted a power contract and is then allowed to control the operating point of the power transfer. With the use of the bq51222 device Dynamic Rectifier Control algorithm, the receiver will inform the transmitter to adjust the rectifier voltage above 8 V prior to enabling the output supply. This method enhances the transient performance during system startup. For the startup flow diagram details, see Figure 12. Tx Powered without Rx Active Tx Extended Digital Ping AD/TS-CTRL EPT Condition? Yes Send EPT packet with reason value No Identification & Configuration & SS, Received by Tx? No Yes Power Contract Established. All proceeding control is dictated by the Rx. Yes VRECT < 8 V? Send control error packet to increase VRECT No Startup operating point established. Enable the Rx output. Rx Active Power Transfer Stage Figure 12. Wireless Power Startup Flow Diagram on WPC TX 18 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 Device Functional Modes (continued) After the startup procedure has been established, the receiver will enter the active power transfer stage. This is considered the main loop of operation. The Dynamic Rectifier Control algorithm determines the rectifier voltage target based on a percentage of the maximum output current level setting (set by KILIM and the RILIM). The receiver will send control error packets in order to converge on these targets. As the output current changes, the rectifier voltage target dynamically changes. As a note, the feedback loop of the WPC system is relatively slow, it can take up to 150 ms to converge on a new rectifier voltage target. It should be understood that the instantaneous transient response of the system is open loop and dependent on the receiver coil output impedance at that operating point. The main loop also determines if any conditions in Table 3 are true in order to discontinue power transfer. Figure 13 shows the active power transfer loop. Rx Active Power Transfer Stage Rx Shutdown conditions per the EPT Table? Yes Send EPT packet with reason value Tx Powered without Rx Active No Yes Is VILIM < 0.1 V? VRECT target = VO + 2 V. Send control error packets to converge. No Yes VRECT target = VO + 1.3 V. Send control error packets to converge. Is VILIM < 0.2 V? No Yes VRECT target = VO + 0.6 V. Send control error packets to converge. Is VILIM < 0.4 V? No VRECT target = VO + 0.12 V. Send control error packets to converge. Measure Received Power and Send Value to Tx Figure 13. Active Power Transfer Flow Diagram on WPC TX Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 19 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com Device Functional Modes (continued) In PMA mode, during startup operation, PMA transmitter generates a digital ping in a predefined structure regarding the frequencies and timing. If the power delivered during the digital ping is sufficient to wake up the bq51222 device, it responds by modulating the power signal according to the PMA communication protocol. If the transmitter receives a valid PMA signal from the receiver, it continues to the identification phase, without removing the power signal. The receiver continues to send PMA DEC or PMA INC signals until target VRECT is achieved, and after desired VRECT is achieved, the bq51222 device sends a PMA NoCh signal to indicate that no further change is needed in transmitter frequency. Please note unlike the WPC mode receiver, in PMA mode, the bq51222 device will continue to send the PMA NoCh signal if the target VRECT is within a defined voltage range. This means that the device will regulate the VRECT voltage within an acceptable window. This can be seen in Figure 15. Standby NO RX REMOVED RX DETECTED? YES RX REMOVED DIGITAL PING RX REMOVED IDENTIFICATION RX REMOVED GUARD TIME EXPIRED? NO Only 2 attempts allowed YES RX REMOVED POWER TRANSFER EOC Figure 14. Active Power Transfer Flow Diagram on PMA TX Type 1 Optimized rectification voltage is key to maintaining high efficiency on the bq51222. Figure 15 indicates the control and communication protocol between the receiver and the transmitter. The bq51222 sends an increment signal (INC) for increasing the operating frequency of the transmitter to decrease the transferred power if the rectification voltage is above VREFHI_H. INC signals will occur until the rectification voltage is below VREFHI_L. If the rectification voltage is below VREFLO_L then the bq51222 will send a decrease signal (DEC) to the transmitter which will decrease the frequency resulting in increased power delivery. VREFLO_H is the hysteresis 20 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 Device Functional Modes (continued) level for terminating the DEC signal. A no change signal (NoCh) is sent when the rectification voltage is between VREFLO_H and VREFHI_L indicating there is no need to increase or decrease the transferred power. Additionally, the Hysteresis zones can be NoCh depending on the direction entered. For example, if the rectification voltage moves through VREFHI_L to enter Hysteresis, the NoCh command is sent. If the same Hysteresis zone is entered through VREFHI_H then the INC will continue to be sent until it reaches VREFHI_L where the NoCh signal will commence. The device will not react to a change in load while the rectification voltage falls within the indicated levels (VREFHI_H > VRECT > VREFLO_L). When a load change occurs sufficient to move VRECT outside this range, the appropriate signal (INC or DEC) will be sent. INC VREFHI_H Hysteresis VREFHI_L NoCh VREFLO_H VREFLO_L Hysteresis DEC Figure 15. PMA Active Power Control Diagram Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 21 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com 8.5 Register Maps Locations 0x01 and 0x02 can be written to any time. Locations 0xE0 to 0xFF are only functional when VRECT > VUVLO. When VRECT goes below VUVLO, locations 0xE0 to 0xFF are reset. 8.5.1 Wireless Power Supply Current Register 1 (address = 0x01) [reset = 00000001] Figure 16. Wireless Power Supply Current Register Format 7 Reserved R/W 6 Reserved R/W 5 Reserved R/W 4 Reserved R/W 3 Reserved R/W 2 VOREG2 R/W 1 VOREG1 R/W 0 VOREG0 R/W LEGEND: R/W = Read/Write Table 5. Wireless Power Supply Current Register 1 Field Descriptions Bit Field Type Reset Description Reserved R/W 00000 Not used B2 VOREG2 R/W 0 B1 VOREG1 R/W 0 450, 500, 550, 600, 650, 700, 750, or 800 mV Changes VO_REG target B0 VOREG0 R/W 1 B7:B3 8.5.2 Wireless Power Supply Current Register 2 (address = 0x02) [reset = 00000111 ] Figure 17. Wireless Power Supply Current Register 2 Format 7 Reserved R/W 6 Reserved R/W 5 Reserved R/W 4 Reserved R/W 3 Reserved R/W 2 IOREG2 R/W 1 IOREG1 R/W 0 IOREG0 R/W LEGEND: R/W = Read/Write Table 6. Wireless Power Supply Current Register 2 Register Field Descriptions Bit Field Type Reset Description Reserved R/W 00000 Not used B2 IOREG2 R/W 1 B1 IOREG1 R/W 1 B0 IOREG0 R/W 1 10%, 20%,30%, 40%, 50%, 60%, 90%, and 100% of IILIM current based on configuration 000, 001, ... 111 B7:B3 22 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 8.5.3 I2C Mailbox Register (address = 0xE0) [reset = 10000000 ] Figure 18. I2C Mailbox Register Format 7 USER_PKT_D ONE R 6 5 USER_PKT_ERR 4 FOD Mailer 3 ALIGN Mailer 2 FOD Scaler 1 Reserved 0 Reserved R R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only Table 7. I2C Mailbox Register Field Descriptions Bit Field Type Reset Description B7 USER_PKT_DONE R 1 Set bit to 0 to send proprietary packet with header in 0xE2. CPU checks header to pick relevant payload from 0xF1 to 0xF4 This bit will be set to 1 after the user packet with the header in register 0xE2 is sent. USER_PKT_ERR R 00 00 01 10 11 B4 FOD Mailer R/W 0 Not used B3 ALIGN Mailer R/W 0 Setting this bit to 1 will enable alignment aid mode where the CEP = 0 will be sent until this bit is set to 0 (or CPU reset occurs) B2 FOD Scaler R/W 0 Not used,write to 0 if register is written Reserved R/W 00 Not used B6:B5 B1:B0 = No error in sending packet = Error: no transmitter present = Illegal header found: packet will not be sent = Error: not defined yet 8.5.4 Wireless Power Supply FOD RAM Register (address = 0xE1) [reset =00000000 ] Figure 19. Wireless Power Supply FOD RAM Register Format 7 ESR_ENABLE R/W 6 OFF_ENABLE R/W 5 RoFOD5 R/W 4 RoFOD4 R/W 3 RoFOD3 R/W 2 RsFOD2 R/W 1 RsFOD1 R/W 0 RsFOD0 R/W LEGEND: R/W = Read/Write Table 8. Wireless Power Supply FOD RAM Register Field Descriptions (1) Bit Field Type Reset Description (1) B7 ESR_ENABLE R/W 0 Enables I2C based ESR in received power, Enable = 1, Disable = 0 B6 OFF_ENABLE R/W 0 Enables I2C based offset power, Enable = 1, Disable = 0 B5 RoFOD5 R/W 0 B4 RoFOD4 R/W 0 B3 RoFOD3 R/W 0 000 – 0 mW 001 – +39 mW 010 – +78 mW 011 – +117 mW 100 – +156 mW 101 – +195 mW 110 – +234 mW 111 – +273 mW The value is added to received power message B2 RsFOD2 R/W 0 B1 RsFOD1 R/W 0 B0 RsFOD0 R/W 0 000 – ESR 001 – ESR 010 – ESR × 2 011 – ESR × 3 100 – ESR x 4 101 – ESR 110 – ESR 111 – ESR x 0.5 A non-zero value will change the I2R calculation resistor and offset in the received power calculation by a factor shown in the table. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 23 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com 8.5.5 Wireless Power User Header RAM Register (address = 0xE2) [reset = 00000000] Figure 20. Wireless Power User Header RAM Register Format 7 HEADER7 R/W 6 HEADER6 R/W 5 HEADER5 R/W 4 HEADER4 R/W 3 HEADER3 R/W 2 HEADER2 R/W 1 HEADER1 R/W 0 HEADER0 R/W LEGEND: R/W = Read/Write Table 9. Wireless Power User Header RAM Register Field Descriptions Bit B7:B0 (1) Field Type Reset Description (1) HEADER R/W 00000000 Proprietary packet 8-bit header Must write a valid header to enable proprietary package. As soon as mailer (0xE0) is written, payload bytes are sent on the next available communication slot as determined by CPU. Once payload is sent, the mailer (USER_PKT_DONE) is set to 1. 8.5.6 Wireless Power USER VRECT Status RAM Register (address = 0xE3) [reset = 00000000] This register reads back the VRECT voltage with LSB = 46 mV. Figure 21. Wireless Power USER VRECT Status RAM Register Format 7 VRECT7 R 6 VRECT6 R 5 VRECT5 R 4 VRECT4 R 3 VRECT3 R 2 VRECT2 R 1 VRECT1 R 0 VRECT0 R LEGEND: R = Read only Table 10. Wireless Power USER VRECT Status RAM Register Field Descriptions 24 Bit Field Type Reset Description B7 VRECT7 R 0 B6 VRECT6 R 0 VRECT voltage Range – 0 V to 12 V, LSB = 46 mV B5 VRECT5 R 0 B4 VRECT4 R 0 B3 VRECT3 R 0 B2 VRECT2 R 0 B1 VRECT1 R 0 B0 VRECT0 R 0 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 8.5.7 Wireless Power VOUT Status RAM Register (address = 0xE4) [reset = 00000000] This register reads back the VOUT voltage with LSB = 46 mV. Figure 22. Wireless Power VOUT Status RAM Register Format 7 VOUT7 R/W 6 VOUT6 R/W 5 VOUT5 R/W 4 VOUT4 R/W 3 VOUT3 R/W 2 VOUT2 R/W 1 VOUT1 R/W 0 VOUT0 R/W LEGEND: R/W = Read/Write Table 11. Wireless Power VOUT Status RAM Register Field Descriptions Bit Field Type Reset Description B7 VOUT7 R/W 0 B6 VOUT6 R/W 0 VOUT voltage LSB = 46 mV B5 VOUT5 R/W 0 B4 VOUT4 R/W 0 B3 VOUT3 R/W 0 B2 VOUT2 R/W 0 B1 VOUT1 R/W 0 B0 VOUT0 R/W 0 8.5.8 Wireless Power REC PWR Byte Status RAM Register (address = 0xE8) [reset = 00000000] This register reads back the received power with LSB = 39 mW. Figure 23. Wireless Power REC PWR Byte Status RAM Register Format 7 RECPWR7 R/W 6 RECPWR6 R/W 5 RECPWR5 R/W 4 RECPWR4 R/W 3 RECPWR3 R/W 2 RECPWR2 R/W 1 RECPWR1 R/W 0 RECPWR0 R/W LEGEND: R/W = Read/Write Table 12. Wireless Power REC PWR Byte Status RAM Register Field Descriptions Bit B7:B0 Field Type Reset Description RECPWR R/W 00000000 Received Power LSB = 39 mW 8.5.9 Wireless Power Mode Indicator Register (address = 0xEF) [reset = 00000000] This register reads back the MODE (WPC or PMA) based on the Transmitter. Figure 24. Wireless Power Mode Indicator Register Format 7 Reserved R/W 6 ALIGN R 5 Reserved R/W 4 Reserved R/W 3 Reserved R/W 2 Reserved R/W 1 Reserved R/W 0 MODE R LEGEND: R/W = Read/Write; R = Read only Table 13. Wireless Power Mode Indicator Register Field Descriptions Bit Field Type Reset Description B7 Reserved Read / Write 0 Not Used B6 ALIGN Status Read 0 Alignment mode = 1, Normal operation = 0 (Status bit) Reserved Read / Write 00000 Not Used Mode Read 0 PMA = 1, WPC = 0 (Status bit) B5:B1 B0 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 25 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com 8.5.10 Wireless Power Prop Packet Payload RAM Byte 0 Register (address = 0xF1) [reset = 00000000] Figure 25. Wireless Power Prop Packet Payload RAM Byte 0 Register Format 7 PL0_7 R/W 6 PL0_6 R/W 5 PL0_5 R/W 4 PL0_4 R/W 3 PL0_3 R/W 2 PL0_2 R/W 1 PL0_1 R/W 0 PL0_0 R/W LEGEND: R/W = Read/Write Table 14. Wireless Power Prop Packet Payload RAM Byte 0 Register Field Descriptions Bit Field Type Reset Description B7:B0 PL0 R/W 00000000 Proprietary Packet Byte 0 content 8.5.11 Wireless Power Prop Packet Payload RAM Byte 1 Register (address = 0xF2) [reset = 00000000] Figure 26. Wireless Power Prop Packet Payload RAM Byte 1 7 PL1_7 R/W 6 PL1_6 R/W 5 PL1_5 R/W 4 PL1_4 R/W 3 PL1_3 R/W 2 PL1_2 R/W 1 PL1_1 R/W 0 PL1_0 R/W LEGEND: R/W = Read/Write Table 15. Wireless Power Prop Packet Payload RAM Byte 1 Field Descriptions Bit Field Type Reset Description B7:B0 PL1 R/W 00000000 Proprietary Packet Byte 1 content 8.5.12 Wireless Power Prop Packet Payload RAM Byte 2 Register (address = 0xF3) [reset = 00000000] Figure 27. Wireless Power Prop Packet Payload RAM Byte 2 Register Format 7 PL2_7 R/W 6 PL2_6 R/W 5 PL2_5 R/W 4 PL2_4 R/W 3 PL2_3 R/W 2 PL2_2 R/W 1 PL2_1 R/W 0 PL2_0 R/W LEGEND: R/W = Read/Write Table 16. Wireless Power Prop Packet Payload RAM Byte 2 Register Field Descriptions Bit Field Type Reset Description B7:B0 PL2 R/W 00000000 Proprietary Packet Byte 2 content 8.5.13 Wireless Power Prop Packet Payload RAM Byte 3 Register (address = 0xF4) [reset = 00000000] Figure 28. Wireless Power Prop Packet Payload RAM Byte 3 Register Format 7 PL3_7 R/W 6 PL3_6 R/W 5 PL3_5 R/W 4 PL3_4 R/W 3 PL3_3 R/W 2 PL3_2 R/W 1 PL3_1 R/W 0 PL3_0 R/W LEGEND: R/W = Read/Write Table 17. Wireless Power Prop Packet Payload RAM Byte 3 Register Field Descriptions 26 Bit Field Type Reset Description B7:B0 PL3 R/W 00000000 Proprietary Packet Byte 3 content Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 8.5.14 RXID Readback Register (address = 0xF5 - 0xFA) [reset = see Table 18 note] Registers 0xF5 to 0xFA store the RXID that can be read back when VRECT > VUVLO. Figure 29. RXID Readback Register Format 7 Reserved R 6 Reserved R 5 Reserved R 4 Reserved R 3 Reserved R 2 Reserved R 1 Reserved R 0 Reserved R LEGEND: R = Read only Table 18. RXID Readback Register Field Descriptions Bit B7:B0 (1) Field Type Reserved R Reset (1) Description RXID Reset value is programmed at TI factory as a unique ID for each device. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 27 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The bq51222 device is a dual mode device which complies with both WPC v1.2 and PMA standards. This allows a system designer to design a system that complies with both wireless power standards. There are several tools available for the design of the system. These tools may be obtained by checking the product page at www.ti.com/product/bq51222. The following sections detail how to design a dual mode RX system. 28 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 9.2 Typical Applications 9.2.1 Dual Mode Design (WPC and PMA Compliant) Power Supply 5-V Output with 1-A Maximum Current bq51222 System Load AD-EN AD OUT CCOMM1 C4 COMM1 CBOOT1 R7 BOOT1 RECT C1 RECT C3 AC1 R6 VO_REG C2 COIL R9 VIREG AC2 CBOOT2 R8 BOOT2 TS/CTRL COMM2 z z CCOMM2 CCLAMP2 CCLAMP1 TMEM CLAMP2 NTC R3 R4 HOST C5 CLAMP1 LPRB1 LPRB2 TERM SCL CM_ILIM SDA ILIM R5 FOD R1 ROS PGND RECT Copyright © 2016, Texas Instruments Incorporated RFOD Figure 30. Dual Mode Schematic using bq51222 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 29 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com Typical Applications (continued) 9.2.1.1 Design Requirements Table 19. Design Parameters DESIGN PARAMETER EXAMPLE VALUE VOUT 5V IOUT MAXIMUM 1A MODE WPC and PMA 9.2.1.2 Detailed Design Procedure To • • • start the design procedure, start by determining the following. Mode of operation – in this case dual mode (WPC and PMA) Output voltage Maximum output current 9.2.1.2.1 Output Voltage Set Point The output voltage of the bq51222 device can be set by adjusting a feedback resistor divider network. The resistor divider network is used to set the voltage gain at the VO_REG pin. The device is intended to operate where the voltage at the VO_REG pin is set to 0.5 V. This value is the default setting and can be changed through I2C. In Figure 31, R6 and R7 are the feedback network for the output voltage sense. OUT C4 R7 R6 VO_REG Figure 31. Voltage Gain for Feedback K VO R6 0.5 V VOUT (10) K VO u R7 1 K VO (11) Choose R7 to be a standard value. In this case, care should be taken to choose R6 and R7 to be fairly large values so as to not dissipate excessive amount of power in the resistors and thereby lower efficiency. KVO is set to be 0.5 / 5 = 0.1, choose R7 to be 102 kΩ, and thus R6 to be 11.3 kΩ. After R6 and R7 are chosen, the same values should be used on R8 and R9. This allows the device to regulate the rectifier in the PMA mode to accurately track the output voltage when the output voltage is changed through I2C. 9.2.1.2.2 Output and Rectifier Capacitors Set C4 between 1 µF and 4.7 µF. This example uses 1 µF. Set C3 between 4.7 µF and 22 µF. This example uses 20 µF. 30 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 9.2.1.2.2.1 TMEM Set C5 to 2.2 µF. In order to determine the bleed off resistor, the WPC transmitters for which the PD_DET is being set for needs to be determined. After the ping timing (time between two consecutive digital pings after EPT charge complete is sent) is determined, the bleedoff resistor can be determined. This example uses TI transmitter EVMs as the use case. In this case the time between pings is 5 s. In order to set the time constant using Equation 8, it is set to 5.6 MΩ. 9.2.1.2.3 Maximum Output Current Set Point ILIM FOD1 R1 ROS RECT RFOD Figure 32. Current Limit Setting for bq51222 The bq51222 device includes a means of providing hardware overcurrent protection by means of an analog current regulation loop. The hardware current limit provides a level of safety by clamping the maximum allowable output current (for example, a current compliance). The RILIM resistor size also sets the thresholds for the dynamic rectifier levels and thus providing efficiency tuning per each application’s maximum system current. The calculation for the total RILIM resistance is as follows: R IL IM R1 K IL IM I IL IM R IL IM (12) R FO D (13) The RILIM will allow for the ILIM pin to reach 1.2 V at an output current equal to IILIM. When choosing RILIM, two options are possible. If the application requires an output current equal to or greater than external ILIM that the circuit is designed for (input current limit on the charger where the RX is delivering power to is higher than the external ILIM), ensure that the downstream charger is capable of regulating the voltage of the input into which the RX device output is tied to by lowering the amount of current being drawn. This will ensure that the RX output does not collapse. Such behavior is referred to as VIN-DPM in TI chargers. Unless such behavior is enabled on the charger, the charger will pull the output of the RX device to ground when the RX device enters current regulation. If the applications are designed to extract less than the ILIM (1-A maximum), typical designs should leave a design margin of at least 20% so that the voltage at ILIM pin reaches 1.2 V when 20% more than maximum current of the system is drawn from the output of the RX. Such a design would have input current limit on the charger lower than the external ILIM of the RX device. In both cases however, the charger must be capable of regulating the current drawn from the device to allow the output voltage to stay at a reasonable value. This same behavior is also necessary during the WPC v1.2 Communication. See Communication Current Limit for more details. The following calculations show how such a design is achieved: KILIM RILIM 1.2 u I ILIM (14) R1 R IL IM R FO D (15) When referring to the application diagram shown in Figure 32, RILIM is the sum of the R1 and RFOD resistance (that is, the total resistance from the ILIM pin to GND). RFOD is chosen according to the FOD application note that can be obtained by contacting your TI representative. This is used to allow the RX implementation to comply with WPC v1.2 requirements related to received power accuracy. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 31 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com Also note that in many applications, the resistor ROS is needed in order to comply with WPC v1.2 requirements. In such a case, the offset on the FOD pin from the voltage on RFOD can cause a shift in the calculation that can reduce the expected current limit. Therefore, it is always a good idea to check the output current limit after FOD calibration is performed according to the FOD section shown below. Unfortunately, because the RECT voltage is not deterministic, and depends on transmitter operation to a certain degree, it is not possible to determine R1 with ROS present in a deterministic manner. In this example, set maximum current for the example to be 1000 mA. To set IILIM = 1.2 A to allow for the 20% margin. R IL IM 840 700 : 1 .2 (16) 9.2.1.2.4 TERM Resistor The TERM resistor is used to set the termination threshold on the RX. The device will send an EPT Charge Complete, or EOC message to the transmitter and thus allow for the system to go into a low standby mode. This is also mandated through PMA specification. By picking a resistor to ground from the TERM pin the system designer can set the termination threshold. The device will send the EPT/EOC message, when the voltage on the ILIM pin goes below the voltage on the TERM pin. The designer can therefore set a resistor on the TERM pin that will determine the threshold. R5 VIL IM _ T E R M 50 u 10 6 (17) Typically, one can use RILIM to set R5 resistor such that at the desired current, on OUT pin, VILIM_TERM can be reached. However, this can be made indeterministic because of the presence of the Ros resistor that is used to comply with WPC v1.2 FOD requirements. Therefore, the system designer is suggested to measure the voltage on the ILIM pin at the output current where he would like to set the termination. This voltage on the ILIM pin is termed as VILIM_TERM. In the design example, to set 50 mA, measure VILIM_TERM. After this is done, set the resistor R5 using the equation Equation 17. 9.2.1.2.5 Setting LPRB1 and LPRB2 Resistors VIREG R8 R3 R4 LPRB1 LPRB2 Figure 33. Setting Low Power Rectifier Boost LPRB1 and LPRB2 are multifunction pins. Depending on whether the termination resistor is used or not, the LPRB pins will change function. This allows the designer to optimize the PMA design for efficiency or transient performance. Table 20. LPRB Setup for Different Applications IMPLEMENTATION 32 TERM RESISTOR BALL NUMBER F5 Backcover Populated LPRB1 LPRB2 Embedded Not populated WPG PD_DET Submit Documentation Feedback BALL NUMBER G6 Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 For more information on how to set the TERM resistor, see TERM Resistor. The LPRBx boosts the rectifier voltage to a higher voltage, and thus it sets the transmitter in PMA mode to operate in frequency or load line that can sustain load step which is part of the PMA certification process. LPRB1 is used to boost the rectifier voltage at low power (output current below about 95 mA). LPRB2 is used to boost the rectifier voltage when output current is below about 310 mA). Both pins are connected to VIREG through resistors, R3 and R4 as shown in Setting LPRB1 and LPRB2 Resistors. These two values depend on the coil and the output voltage choice. Also, the allowable voltage drop also defined by the board manufacturer can allow you to set the voltage in these modes to optimize the efficiency and transient response. To design R3 and R4, set a window of VRECT to boost the operating frequency of the TX a 0-mA load and 100 mA Good starting points are: 7.3 to 7.8 V for 0 to 100 mA and 6.7 to 7.3 V for 100 to 400 mA Now, find the values of R3 and R4 that can provide the chosen window. The lower and upper reference of VIREG is 0.4906 and 0.5318 V Calculate VRECT as follows using the TI tool provided in the product folder under the "Tools & sofware" tab. Figure 34. LPRB Resistor Calculations 9.2.1.2.6 I2C The I2C lines are used to communicate with the device. In order to enable the I2C, they can be pulled up to an internal host bus. When not in use as in Figure 55, tie them to GND. The device address is 0x6C. 9.2.1.2.7 Communication Current Limit Communication current limit allows the device to communicate with the transmitter in an error free manner by decoupling the coil from load transients on the OUT pin during WPC communication. In some cases this communication current limit feature is not desirable. In this design, the user enables the communication current limit. This is done by tying the CM_ILIM pin to GND. In the case that this is not needed, the CM_ILIM pin can be tied to OUT pin to disable the communication current limit. In this case, take care that the voltage on the CM_ILIM pin does not exceed the maximum rating of the pin. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 33 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com 9.2.1.2.8 Receiver Coil The receiver coil design is the most open and interesting part of the system design. The choice of the receiver inductance, shape, and materials all intimately influence the parameters themselves in an intertwined manner. This design can be complicated and involves optimizing many different aspects; refer to the user's guide for the EVM (SLUUAX6). The typical choice of the inductance of the receiver coil for a dual mode 5-V solution is between 6 to 8 µH. 9.2.1.2.9 Series and Parallel Resonant Capacitors Resonant capacitors C1 and C2 are set according to WPC specification. Although this is a dual mode solution, the PMA does not specify an exact resonance frequency for the resonant capacitors and in fact does not specify that resonant capacitors are indeed needed. The equations for calculating the values of the resonant capacitors are shown: -1 2 é ù C1 = ê fS ´ 2p ´ L'S ú ë û -1 é 2 1ù C2 = ê fD ´ 2p ´ LS ú C1 ûú ëê ( ) ( ) (18) 9.2.1.2.10 Communication, Boot and Clamp Capacitors Set CCOMMx to a value ranging from C1 / 8 to C1 / 3. The higher the value of the communication capacitors, the easier it is to comply with PMA specification. However, higher capacitors do lower the overall efficiency of the system. Make sure these are X7R ceramic material and have a minimum voltage rating of 25 V. Set CBOOTx to be 15 nF. Make sure these are X7R ceramic material and have a minimum voltage rating of 25 V. Set CCLAMPx to be 470 nF. Make sure these are X7R ceramic material and have a minimum voltage rating of 25 V. 34 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 9.2.1.3 Application Curves Ch3: unused Ch4: IOUT, 200 mA 400 ms/Div Ch1: VOUT, 1 V Ch2: VRECT, 1 V Figure 35. bq51222 No Load Start-up on a WPC TX Ch3: unused Ch4: IOUT, 200 mA 2 ms/Div Received Power (mW) Figure 36. 0-mA to 1000-mA Step on a WPC TX 5000 5 4500 0 4000 -5 3500 -10 3000 -15 2500 -20 2000 -25 1500 -30 1000 -35 Min Max Difference 500 -40 0 0 Ch1: VOUT, 1 V Ch2: VRECT, 1 V Ch3: unused Ch4: unused 2 ms/Div 200 800 1000 -45 1200 D001 VRECT (V) Figure 38. Received Power Variation (mW) vs IOUT (mA) on a WPC TX 7.5 7.25 7 6.75 6.5 6.25 6 5.75 5.5 5.25 5 4.75 4.5 4.25 4 700 : 1400 : 0 Ch3: unused Ch4: unused 600 IOUT (mA) Data taken over approximately 3 minutes Figure 37. 1000-mA to 0-mA Load Dump on a WPC TX Ch1: TS, 1 V Ch2: unused 400 Differene in Max and Min Messages Ch1: VOUT, 1 V Ch2: VRECT, 1 V 200 400 ms/Div 400 600 IOUT (mA) 800 1000 1200 D001 RILIM = 700 Ω RILIM = 1400 Ω Figure 39. TS Voltage Bias without TS Resistor Figure 40. Rectifier Regulation on a WPC TX Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 35 bq51222 www.ti.com 90 200 80 190 70 180 Frequency (kHz) Efficiency (%) SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 60 50 40 30 170 160 150 140 130 20 120 10 110 0 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 IOUT (A) 1 1.1 1.2 0 200 400 D001 VOUT = 5 V 600 IOUT (mA) 800 1000 1200 D001 VOUT = 5 V TX: bq500210EVM-689, RX: bq51222EVM-520 Figure 41. bq51222 WPC Efficiency on a WPC TX Figure 42. Frequency Range on a WPC TX 5.06 8 VRECT ASC VRECT DEC 7.5 5.04 5.02 7 VO_REG (V) VRECT (V) 5 6.5 6 5.5 4.98 4.96 4.94 5 4.92 4.5 4.9 4.88 4 0 200 400 600 IOUT (mA) 800 1000 0 1200 D013 200 400 600 IOUT (mA) 800 1000 1200 D001 RILIM = 700 Ω TX: bq500210EVM-689, RX: bq51222EVM-520 Figure 44. Output Regulation on a WPC TX Figure 43. Dynamic Regulation on a WPC TX 555 VO_REG VRECT 554 553 IOUT (mA) 552 551 550 549 548 547 546 545 2.5 3 3.5 4 Voltage (V) 4.5 5 D015 Ch1: PMA communication, 5 V Ch2: IOUT, 1 A Figure 45. RECT Foldback in Current Limit on a WPC TX 36 Submit Documentation Feedback Ch3: VRECT, 5 V Ch4: VOUT, 2 V 50 ms/Div Figure 46. Startup on a PMA TX Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 Ch1: unused Ch2: IOUT, 500 mA Ch3: VRECT, 2 V Ch4: VOUT, 2 V 2 ms/Div Ch1: unused Ch2: IOUT, 500 mA 2 ms/Div Figure 48. Load Dump from 1000 mA to 0 mA on PMA TX 290 8 280 7.2 270 6.4 Increment Decrement 5.6 260 VRECT (V) Frequency (kHz) Figure 47. Load Step from 0 mA to 1000 mA on PMA TX Ch3: VRECT, 2 V Ch4: VOUT, 2 V 250 240 230 4.8 4 3.2 2.4 220 1.6 With LPRB1 and LPRB2 With LPRB1 Without LPRB1 and LPRB2 210 0.8 0 200 0 200 400 600 Load (mA) 800 1000 0 1200 200 400 D016 600 IOUT (mA) 800 1000 1200 D001 VOUT = 5 V TX: Duracell Powermat, RX: bq51222EVM-520 Figure 49. Frequency of Operation on a PMA TX Figure 50. VRECT on a PMA TX 5.05 5.04 5.03 VOUT (V) 5.02 5.01 5 4.99 4.98 4.97 4.96 4.95 0 Ch1: unused Ch2: unused Ch3: unused Ch4: TS, 500 mV 500 ms/Div Figure 51. TS Measurement on a PMA TX 200 400 600 IOUT (mA) 800 1000 1200 D001 Figure 52. Output Voltage Regulation on a PMA TX Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 37 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com 5.5 5.0 VRECT (V) 4.5 4.0 3.5 3.0 2.5 2.5 3.0 3.5 4.0 4.5 VOUT (V) 5.0 5.5 C001 PMA mode, operating in current limit IILIM = 1 A Figure 53. VRECT Tracks VOUT 38 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 9.2.2 Embedded in System Board When the bq51222 device is implemented as an embedded device on the system board, LPRBEN (TERM) pin is floated and WPG and PD_DET are set to their function. When LPRBEN has a resistor to ground to enable TERM, PD_DET becomes LPRB1 and WPG becomes LPRB2. This second configuration with TERM enabled is preferred for a back cover implementation. A back cover implementation is one where the receiver device and receiver coil are contained in the back cover of the mobile phone where the receiver is being implemented. With an embedded implementation (one where only the coil is in the mobile device back cover and the receiver device is on the main motherboard for the mobile phone and is controlled by the host controller device in the phone), the expectation is that the host controller (PMIC or Charger) will use the TS/CTRL pin to establish termination and associated EPT or EOC. System Load Q1 bq51222 AD-EN AD OUT CCOMM1 C4 COMM1 RECT CBOOT1 R7 BOOT1 RECT C1 R9 C3 AC1 R6 COIL VO_REG C2 R8 VIREG AC2 CBOOT2 BOOT2 TS/CTRL COMM2 z z CCOMM2 CCLAMP2 CCLAMP1 TMEM CLAMP2 HOST NTC C5 CLAMP1 WPG PD _ DET GPIO LPRBEN SCL SCL CM_ILIM SDA SDA ILIM FOD R1 PGND ROS RECT RFOD Copyright © 2016, Texas Instruments Incorporated Figure 54. bq51222 Embedded in a System Board Refer to Dual Mode Design (WPC and PMA Compliant) Power Supply 5-V Output with 1-A Maximum Current for all design details. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 39 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com 9.2.3 bq51222 Implemented in Back Cover When the bq51222 device is implemented as a back cover solution, set TERM resistor to enable PMA term and LPRB1 and LPRB2 functions are automatically enabled. In this implementation, the bq51222 device can autonomously determine if EOC can be established because the termination current has been reached. In this configuration, PD_DET becomes LPRB1 and WPG becomes LPRB2. This allows the RECT voltage to be controlled at different levels so that transient performance from light load to maximum current can be optimized. bq51222 System Load AD-EN AD OUT CCOMM1 C4 COMM1 CBOOT1 BOOT1 R7 RECT C1 RECT C3 AC1 R6 VO_REG C2 COIL VIREG AC2 CBOOT2 R9 R8 BOOT2 TS/CTRL COMM2 z z CCOMM2 CCLAMP2 CCLAMP1 TMEM CLAMP2 NTC R3 R4 HOST C5 CLAMP1 LPRB1 LPRB2 TERM SCL CM_ILIM SDA FOD ILIM R5 R1 ROS PGND RECT RFOD Copyright © 2016, Texas Instruments Incorporated Figure 55. bq51222 Implemented in a Back Cover Refer to Dual Mode Design (WPC and PMA Compliant) Power Supply 5-V Output with 1-A Maximum Current for all design details. 40 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 10 Power Supply Recommendations These devices are intended to be operated within the ranges shown in the Recommended Operating Conditions. Because the system involves a loosely coupled inductor set up, the voltages produced on the receiver are a function of the inductances and the available magnetic field. Ensure that the design in the worst case keeps the voltages within the Absolute Maximum Ratings. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 41 bq51222 SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 www.ti.com 11 Layout 11.1 Layout Guidelines • • • • • • Keep the trace resistance as low as possible on AC1, AC2, and OUT. Detection and resonant capacitors need to be as close to the device as possible. COMM, CLAMP, and BOOT capacitors need to be placed as close to the device as possible. Via interconnect on GND net is critical for appropriate signal integrity and proper thermal performance. High frequency bypass capacitors need to be placed close to RECT and OUT pins. ILIM and FOD resistors are important signal paths and the loops in those paths to GND must be minimized. Signal and sensing traces are the most sensitive to noise; the sensing signal amplitudes are usually measured in mV, which is comparable to the noise amplitude. Make sure that these traces are not being interfered by the noisy and power traces. AC1, AC2, BOOT1, BOOT2, COMM1, and COMM2 are the main source of noise in the board. These traces should be shielded from other components in the board. It is usually preferred to have a ground copper area placed underneath these traces to provide additional shielding. Also, make sure they do not interfere with the signal and sensing traces. The PCB should have a ground plane (return) connected directly to the return of all components through vias (two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). For a 1-A fast charge current application, the current rating for each net is as follows: • AC1 = AC2 = 1.2 A • OUT = 1 A • RECT = 100 mA (RMS) • COMMx = 300 mA • CLAMPx = 500 mA • All others can be rated for 10 mA or less 11.2 Layout Example AD is also a power trace. Keep the trace resistance as low as possible on AC1, AC2, and OUT. Isolate noisy traces using GND trace. Place signal and sensing components as close as possible to the IC. It is always a good practice to place high frequency bypass capacitors next to RECT and OUT. 42 Place detection and resonant capacitors Cd and Cs here. The via interconnect is important and must be optimized near the power pad of the IC and the GND for good thermal dissipation. Submit Documentation Feedback Place COMM, CLAMP, and BOOT capacitors as close as possible to the IC terminals. Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 bq51222 www.ti.com SLUSCL5A – JULY 2016 – REVISED AUGUST 2016 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: bq51222 43 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) BQ51222YFPR ACTIVE DSBGA YFP 42 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 BQ51222 BQ51222YFPT ACTIVE DSBGA YFP 42 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 BQ51222 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of