BQ79616-Q1, BQ79614-Q1, BQ79612-Q1
SLUSE81D – AUGUST 2020 – REVISED SEPTEMBER 2022
BQ79616-Q1, BQ79614-Q1, BQ79612-Q1 Functional Safety-Compliant Automotive
16S/14S/12S Battery Monitor, Balancer and Integrated Hardware Protector
1 Features
2 Applications
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Qualified for automotive applications
AEC-Q100 Qualified with the following results:
– Device temperature grade 1: –40°C to +125°C
ambient operating temperature range
– Device HBM ESD classification level 2
– Device CDM ESD classification level C4B
Functional Safety-Compliant
– Developed for functional safety applications
– Documentation to aid ISO 26262 system design
– Systematic capability up to ASIL D
– Hardware capability up to ASIL D
+/- 1.5mV ADC accuracy
Pin-package and software compatible device
family:
– Stackable monitor 16S (BQ79616-Q1,
BQ79656-Q1), 14S (BQ79614-Q1, BQ79654Q1), and 12S (BQ79612-Q1, BQ79652-Q1)
– Standalone monitor 48 V system (BQ75614Q1)
Built-in redundancy path for voltage and
temperature diagnostics
Highly accurate cell voltage measurements within
128 µs for all cell channels
Integrated post-ADC configurable digital low-pass
filters
Supports bus bar connection and measurement
Built-in host-controlled hardware reset to emulate
POR-like device reset
Supports internal cell balancing
– Balancing current at 240 mA
– Built-in balancing thermal management with
automatic pause and resume control
Isolated differential daisy chain communication
with optional ring architecture
Embedded fault signal and heartbeat through
communication line
UART/SPI host interface/communication bridge
device BQ79600-Q1
Built-in SPI master
Battery Management System (BMS) in hybrid and
electric powertrain systems
Energy storage battery packs with Battery
Management Systems
•
3 Description
BQ79612-Q1, BQ79614-Q1 and BQ79616-Q1 provide
high-accuracy cell voltage measurements in less than
200 μs for 12S, 14S and 16S battery modules in
high-voltage battery management systems in HEV/EV.
The family of monitors offers different channel
options in the same package type, providing pinto-pin compatibility and supporting high reuse of
the established software and hardware across any
platform. The integrated front-end filters enable the
system to implement with simple, low voltage rating,
differential RC filters on the cell input channels. The
integrated, post-ADC, low-pass filters enable filtered,
DC-like, voltage measurements for better state of
charge (SOC) calculation. This device supports
autonomous internal cell balancing with temperature
monitoring to auto-pause and resume balancing to
avoid an overtemperature condition.
Device Information
PART
NUMBER(1)
PACKAGE
BODY SIZE (NOM)
BQ79612-Q1
BQ79614-Q1
HTQFP (64-pin)
10.00 mm × 10.00 mm
BQ79616-Q1
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Battery
Modules
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+
+
+
+
+
+
+
+
+
+
+
12 V
DC-DC
To CAN
Bus
MCU
Balance and Filter Components
Balance and Filter Components
BQ7961x
bq79600
BQ7961x
bq79600
BQ79600
bq79600
NFAULT
NFAULT
UART or
SPI
UART or
SPI
COML
Isolation
Components
COMH
COML
COMH
COML
COMH
Capactive
Level-shifted Differential Interface
Optional Ring Connection
Simplified System Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
+
BQ79616-Q1, BQ79614-Q1, BQ79612-Q1
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SLUSE81D – AUGUST 2020 – REVISED SEPTEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 4
6 Device Comparison Table...............................................5
7 Pin Configuration and Functions...................................6
8 Specifications................................................................ 11
8.1 Absolute Maximum Ratings...................................... 11
8.2 ESD Ratings..............................................................11
8.3 Recommended Operating Conditions....................... 11
8.4 Thermal Information..................................................12
8.5 Electrical Characteristics...........................................12
8.6 Timing Requirements................................................ 17
8.7 Typical Characteristics.............................................. 21
9 Detailed Description......................................................22
9.1 Overview................................................................... 22
9.2 Functional Block Diagram......................................... 22
9.3 Feature Description...................................................24
9.4 Device Functional Modes........................................103
9.5 Register Maps......................................................... 112
10 Application and Implementation.............................. 191
10.1 Application Information......................................... 191
10.2 Typical Applications.............................................. 191
11 Power Supply Recommendations............................203
12 Layout.........................................................................204
12.1 Layout Guidelines................................................. 204
12.2 Layout Example.................................................... 207
13 Device and Documentation Support........................211
13.1 Device Support......................................................211
13.2 Receiving Notification of Documentation Updates 211
13.3 Support Resources............................................... 211
13.4 Trademarks........................................................... 211
13.5 Electrostatic Discharge Caution............................ 211
13.6 Glossary................................................................ 211
14 Mechanical, Packaging, and Orderable
Information.................................................................. 212
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (June 2021) to Revision D (September 2022)
Page
• Changed from Restricted to Public..................................................................................................................... 1
• Additional supply current when TSREF is enabled...........................................................................................12
• DVDD output voltage........................................................................................................................................ 12
• NEG5V pin voltage........................................................................................................................................... 12
• Diagnostic measurements resolution................................................................................................................12
• Added paragraph to Section 9.3.1.2 ................................................................................................................ 24
• Changed 380μs to 1.35ms in Section 9.3.1.6 ..................................................................................................25
• Added Note to Section 9.3.2.1.3.1 ...................................................................................................................29
• Deleted as in the Main ADC path and added Note to Section 9.3.2.2.1.1 .......................................................32
• Changed text in Section 9.3.2.3 .......................................................................................................................36
• Changed latch to load in Section 9.3.3.3.3 ...................................................................................................... 42
• Added text to Section 9.3.5 ..............................................................................................................................48
• Changed above to below in Figure 9-23 ..........................................................................................................49
• Changed Figure 9-25 to show response frame start time is after TX_HOLF_OFF expiration time.................. 50
• Changed Read to Write in Table 9-9 ................................................................................................................52
• Changed Figure 9-27 to the correct bit-width per byte..................................................................................... 54
• Added tprog_otp = 100ms and During this time no data communications is allowed to step 4 in Table 9-26 .....80
• Changed BQ79606-Q1 to BQ7961X-Q1 in Section 9.3.6.4 .............................................................................81
• Deleted Rcb resistor in Figure 9-56 ............................................................................................................... 100
• Multiple bits in Section 9.5.4.3.11 updated with Bit is self-cleared and added text.........................................129
• Changed bit setting 11 to Reserved in Section 9.5.4.5.1 ...............................................................................134
• Changed bit 6 to Reserved and changed bit 5 to 0 = Dynamic Alignment in Section 9.5.4.5.8 .................... 136
• Added sourced from TSREF regulator voltage and Default Reset setting 4% to COOLOFF[2:0] and sourced
from TSREF regulator voltage and Default Reset setting 24% to OTCB_THR[3:0] in Section 9.5.4.7.5 ...... 155
• Added This bit is self clearing to BAL_TIME_GO in Section 9.5.4.7.8 .......................................................... 156
• Added sourced from TSREF regulator voltage. and Default Reset setting 80% to UT_THR[2:0] and sourced
from TSREF regulator voltage. and Default Reset setting 39% to OT_THR[4:0] in Section 9.5.4.8.5 .......... 158
• Updated correct register names in Section 9.5.4.13.3 ...................................................................................170
• Added Note to UART_MIRROR_EN in Section 9.5.4.14.2 ............................................................................178
2
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•
•
•
•
SLUSE81D – AUGUST 2020 – REVISED SEPTEMBER 2022
Changed cap value to 2.2 μF and fixed isolator pinout in Figure 10-1 .......................................................... 191
Changed content, Figure 10-7, Figure 10-8, and Figure 10-9 in Section 10.2.1.2.7.2 .................................. 197
Changed cap values to 2.2 μF in Figure 10-11 ..............................................................................................200
Changed Figure 12-3 .....................................................................................................................................206
Changes from Revision B (April 2021) to Revision C (June 2021)
Page
• Changed BQ79614-Q1 and BQ79612-Q1 from Product Preview to Production Data........................................1
Changes from Revision A (December 2020) to Revision B (April 2021)
Page
• Added (2) (3) ...................................................................................................................................................... 11
• Added (2) .......................................................................................................................................................... 11
• Added (3) .......................................................................................................................................................... 11
• Added MAIN_ADC_CAL1, MAIN_ADC_CAL2 register to Section 9.3.2.1.3.1 ................................................ 29
• Changed CUST_CRC_LO reset value from 0x73 to 0xF3 in Section 9.5.1 ...................................................112
• Added content to MAIN_MODE[1:0] description in Section 9.5.4.5.7 ............................................................136
• Added content to AUX_MODE[1:0] description in Section 9.5.4.5.9 ............................................................. 136
• Changed From: This bit is set if [MSK_COMP] = 1 To: This bit is set if [MSK_COMP] = 0 for
FAULT_COMP_ADC = in Section 9.5.4.13.1 .................................................................................................168
• Added content to Common-mode choke and ESD diode (optional) descriptions in Table 10-4 .................... 197
• Changed content for Transformer description and added content to ESD diode (optional) description in Table
10-5 ................................................................................................................................................................197
Changes from Revision * (August 2020) to Revision A (December 2020)
Page
• Changed from Advance Information to Production Data.................................................................................... 1
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5 Description (continued)
The inclusion of the isolated, bidirectional, daisy chain ports supports both capacitor- and transformer-based
isolation, allowing the use of the most effective components for centralized or distribution architectures
commonly found in the xEV powertrain system. This device also includes eight GPIOs or auxiliary inputs that can
be used for external thermistor measurements.
Host communication to the BQ7961x-Q1 family of devices can be connected via the device's dedicated UART
interface or through a communication bridge device, BQ79600. Additionally, an isolated, differential daisy-chain
communication interface allows the host to communicate with the entire battery stack over a single interface.
in the event of a communication line break, the daisy-chain communication interface is configurable to a ring
architecture that allows the host to talk to devices at either end of the stack.
4
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SLUSE81D – AUGUST 2020 – REVISED SEPTEMBER 2022
6 Device Comparison Table
DEVICE
STATUS
DESCRIPTION
BQ79616-Q1
Production Data
Supports 6S to 16S battery modules
BQ79614-Q1
Production Data
Supports 6S to 14S battery modules
BQ79612-Q1
Production Data
Supports 6S to 12S battery modules
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Product Folder Links: BQ79616-Q1 BQ79614-Q1 BQ79612-Q1
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SLUSE81D – AUGUST 2020 – REVISED SEPTEMBER 2022
7 Pin Configuration and Functions
6
TSREF
DVDD
49
RX
DVSS
TX
52
50
GPIO8
53
51
GPIO7
GPIO4
58
54
GPIO3
59
55
GPIO2
60
GPIO5
GPIO1
61
GPIO6
NFAULT
62
56
BBN
63
57
BBP
64
PAP Package
64-Pin HTQFP
Top View
BAT
1
48
NPNB
CB16
2
47
LDOIN
VC16
3
46
CVSS
CB15
4
45
CVDD
VC15
5
44
NEG5V
CB14
6
43
COMHP
VC14
7
42
COMHN
CB13
8
VC13
9
CB12
VC12
BQ79616-Q1
41
COMLN
40
COMLP
10
39
AVSS
11
38
AVDD
CB11
12
37
REFHP
VC11
13
36
REFHM
CB10
14
35
VC0
VC10
15
34
CB0
CB9
16
33
VC1
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17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VC9
CB8
VC8
CB7
VC7
CB6
VC6
CB5
VC5
CB4
VC4
CB3
VC3
CB2
VC2
CB1
64-HTQFP (PAP)
10 mm x 10 mm
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SLUSE81D – AUGUST 2020 – REVISED SEPTEMBER 2022
TSREF
DVDD
49
RX
DVSS
TX
52
50
GPIO8
53
51
GPIO7
GPIO4
58
54
GPIO3
59
55
GPIO2
60
GPIO5
GPIO1
61
GPIO6
NFAULT
62
56
BBN
63
57
BBP
64
PAP Package
64-Pin HTQFP
Top View
BAT
1
48
NPNB
NC
2
47
LDOIN
NC
3
46
CVSS
NC
4
45
CVDD
NC
5
44
NEG5V
CB14
6
43
COMHP
VC14
7
42
COMHN
CB13
8
VC13
9
CB12
VC12
BQ79614-Q1
41
COMLN
40
COMLP
10
39
AVSS
11
38
AVDD
CB11
12
37
REFHP
VC11
13
36
REFHM
CB10
14
35
VC0
VC10
15
34
CB0
CB9
16
33
VC1
27
28
29
30
CB3
VC3
CB2
VC2
CB1
TX
RX
TSREF
DVSS
DVDD
52
51
50
49
32
26
VC4
31
25
CB4
22
CB6
24
21
VC7
VC5
20
CB7
23
19
VC8
CB5
18
CB8
VC6
17
VC9
64-HTQFP (PAP)
10 mm x 10 mm
BBP
BBN
NFAULT
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
64
63
62
61
60
59
58
57
56
55
54
53
PAP Package
64-Pin HTQFP
Top View
BAT
1
48
NPNB
NC
2
47
LDOIN
NC
3
46
CVSS
NC
4
45
CVDD
NC
5
44
NEG5V
NC
6
43
COMHP
NC
7
42
COMHN
NC
8
NC
9
BQ79612-Q1
64-HTQFP (PAP)
10 mm x 10 mm
41
COMLN
40
COMLP
25
26
27
28
29
30
31
32
VC4
CB3
VC3
CB2
VC2
CB1
VC1
CB4
CB0
33
24
34
16
VC5
15
CB9
23
VC10
CB5
VC0
VC6
35
22
14
CB6
REFHM
CB10
21
36
VC7
13
20
REFHP
VC11
CB7
37
19
AVDD
12
18
VC12
CB11
VC8
AVSS
38
17
39
11
CB8
10
VC9
CB12
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SLUSE81D – AUGUST 2020 – REVISED SEPTEMBER 2022
Table 7-1. Pin Functions
PIN
NAME
BQ79616
8
BQ79614
BQ79612
No.
TYPE
DESCRIPTION
BAT
BAT
BAT
1
P
Power supply input and top of module measurement input. Connect to the top cell of the
battery module.
NPNB
NPNB
NPNB
48
P
Connect to the base of an external NPN transistor.
LDOIN
LDOIN
LDOIN
47
P
6-V preregulated analog power supply input/sense pin. Connect to the emitter of the external
NPN transistor and connect a 0.1-µF decoupling capacitor to CVSS.
AVDD
AVDD
AVDD
38
P
5-V regulated output. AVDD supplies the internal analog circuits. Bypass AVDD with a
capacitor to AVSS.
AVSS
AVSS
AVSS
39
GND
Analog ground. Ground connection for internal analog circuits. Connect DVSS, CVSS,
REFHM, and AVSS externally.
NEG5V
NEG5V
NEG5V
44
P
Negative 5-V charge pump used for daisy chain and Main ADC. Connect with a capacitor to
CVSS.
DVDD
DVDD
DVDD
49
P
1.8-V regulated output. DVDD supplies the internal digital circuits. Bypass DVDD with a
capacitor to DVSS.
DVSS
DVSS
DVSS
50
GND
Digital ground. Ground connection for internal digital logics. Connect DVSS, CVSS, REFHM,
and AVSS externally.
CVDD
CVDD
CVDD
45
P
5-V daisy chain communication and I/Os power supply. CVDD supplies the stack daisy chain
communication transceiver circuit and the I/O pins. This power supply also supports an
additional 10-mA external load in ACTIVE and SLEEP.
CVSS
CVSS
CVSS
46
GND
Daisy chain communication ground. Ground connection for internal daisy chain transceivers.
Connect DVSS, CVSS, REFHM, and AVSS externally.
TSREF
TSREF
TSREF
51
P
5-V bias voltage for NTC thermistor. Connect TSREF to the top of the NTC resistor divider
network to the GPIOs when they are configured for NTC temperature monitoring. Bypass
TSREF with a capacitor to CVSS.
REFHP
REFHP
REFHP
37
P
Precision reference output pin. Bypass with a capacitor to REFHM.
REFHM
REFHM
REFHM
36
GND
Precision reference ground. Ground connection for the internal precision reference. Connect
DVSS, CVSS, REFHM, and AVSS externally.
VC16
NC
NC
3
I
Cell voltage sense input. Connect to the positive terminal of cell 16. Connect a differential
RC filter to VC15. Tie unused NC pins in BQ79614 and BQ79612 to BAT pin as explained in
Cell Connections.
VC15
NC
NC
5
I
Cell voltage sense input. Connect to the positive terminal of cell 15. Connect a differential
RC filter to VC14.Tie unused NC pins in BQ79614 and BQ79612 to BAT pin as explained in
Cell Connections.
VC14
VC14
NC
7
I
Cell voltage sense input. Connect to the positive terminal of cell 14. Connect a differential
RC filter to VC13.Tie unused NC pins in BQ79612 to BAT pin as explained in Cell
Connections.
VC13
VC13
NC
9
I
Cell voltage sense input. Connect to the positive terminal of cell 13. Connect a differential
RC filter to VC12. Tie unused NC pins in BQ79612 to BAT pin as explained in Cell
Connections.
VC12
VC12
VC12
11
I
Cell voltage sense input. Connect to the positive terminal of cell 12. Connect a differential
RC filter to VC11.
VC11
VC11
VC11
13
I
Cell voltage sense input. Connect to the positive terminal of cell 11. Connect a differential
RC filter to VC10.
VC10
VC10
VC10
15
I
Cell voltage sense input. Connect to the positive terminal of cell 10. Connect a differential
RC filter to VC9.
VC9
VC9
VC9
17
I
Cell voltage sense input. Connect to the positive terminal of cell 9. Connect a differential RC
filter to VC8.
VC8
VC8
VC8
19
I
Cell voltage sense input. Connect to the positive terminal of cell 8. Connect a differential RC
filter to VC7.
VC7
VC7
VC7
21
I
Cell voltage sense input. Connect to the positive terminal of cell 7. Connect a differential RC
filter to VC6.
VC6
VC6
VC6
23
I
Cell voltage sense input. Connect to the positive terminal of cell 6. Connect a differential RC
filter to VC5.
VC5
VC5
VC5
25
I
Cell voltage sense input. Connect to the positive terminal of cell 5. Connect a differential RC
filter to VC4.
VC4
VC4
VC4
27
I
Cell voltage sense input. Connect to the positive terminal of cell 4. Connect a differential RC
filter to VC3.
VC3
VC3
VC3
29
I
Cell voltage sense input. Connect to the positive terminal of cell 3. Connect a differential RC
filter to VC2.
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SLUSE81D – AUGUST 2020 – REVISED SEPTEMBER 2022
Table 7-1. Pin Functions (continued)
PIN
NAME
BQ79616
BQ79614
BQ79612
No.
TYPE
DESCRIPTION
VC2
VC2
VC2
31
I
Cell voltage sense input. Connect to the positive terminal of cell 2. Connect a differential RC
filter to VC1.
VC1
VC1
VC1
33
I
Cell voltage sense input. Connect to the positive terminal of cell 1. Connect a differential RC
filter to VC0.
VC0
VC0
VC0
35
I
Cell voltage sense input. Connect to the negative terminal of cell 1. Connect a differential
RC filter to AVSS.
CB16
NC
NC
2
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 16 with a differential RC filter to CB15. The filter
resistor also sets the internal balance current. Tie unused CB16 pin via RC to BAT pin and
tie unused NC pins in BQ79614 and BQ79612 to BAT pin as explained in Cell Connections.
CB15
NC
NC
4
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 15 with a differential RC filter to CB14. The filter
resistor also sets the internal balance current. Tie unused NC pins in BQ79614 and
BQ79612 to BAT pin as explained in Cell Connections.
CB14
CB14
NC
6
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 14 with a differential RC filter to CB13. The filter
resistor also sets the internal balance current. Tie unused NC pins in BQ79612 to BAT pin
as explained in Cell Connections.
CB13
CB13
NC
8
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 13 with a differential RC filter to CB12. The filter
resistor also sets the internal balance current. Tie unused NC pins in BQ79612 to BAT pin
as explained in Cell Connections.
CB12
CB12
CB12
10
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 12 with a differential RC filter to CB11. The filter
resistor also sets the internal balance current.
CB11
CB11
CB11
12
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 11 with a differential RC filter to CB10. The filter
resistor also sets the internal balance current.
CB10
CB10
CB10
14
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 10 with a differential RC filter to CB9. The filter resistor
also sets the internal balance current.
CB9
CB9
CB9
16
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 9 with a differential RC filter to CB8. The filter resistor
also sets the internal balance current.
CB8
CB8
CB8
18
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 8 with a differential RC filter to CB7. The filter resistor
also sets the internal balance current.
CB7
CB7
CB7
20
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 7 with a differential RC filter to CB6. The filter resistor
also sets the internal balance current.
CB6
CB6
CB6
22
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 6 with a differential RC filter to CB5. The filter resistor
also sets the internal balance current.
CB5
CB5
CB5
24
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 5 with a differential RC filter to CB4. The filter resistor
also sets the internal balance current.
CB4
CB4
CB4
26
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 4 with a differential RC filter to CB3. The filter resistor
also sets the internal balance current.
CB3
CB3
CB3
28
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 3 with a differential RC filter to CB2. The filter resistor
also sets the internal balance current.
CB2
CB2
CB2
30
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 2 with a differential RC filter to CB1. The filter resistor
also sets the internal balance current.
CB1
CB1
CB1
32
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect
this pin to the positive terminal of cell 1 with a differential RC filter to CB0. The filter resistor
also sets the internal balance current.
CB0
CB0
CB0
34
I/O
Cell balance connection. This pin is connected to the internal cell balancing FET. Connect to
the negative terminal of cell 1 with differential RC filter to AVSS. The filter resistor also sets
the internal balance current.
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Table 7-1. Pin Functions (continued)
PIN
NAME
BQ79616
BQ79614
BQ79612
No.
TYPE
DESCRIPTION
BBP
BBP
BBP
64
I
Bus bar connection. With BBP and BBN connecting to each end of a bus bar, this channel
provides a differential input to the ADC measurement with a 5x gain.
BBN
BBN
BBN
63
I
Bus bar connection. With BBP and BBN connecting to each end of a bus bar, this channel
provides a differential input to the ADC measurement with a 5x gain.
RX
RX
RX
52
I
UART receiver input. Pull up to CVDD with an external resistor and connect the device RX
to the TX output of the host MCU. If unused (for example, for stack devices), connect RX to
CVDD.
TX
TX
TX
53
O
UART transmitter output. Connect device TX to RX input of the host MCU and will be pulled
up from the host side. If unused (for example, for stack devices), leave it floating.
COMHP
COMHP
COMHP
43
I/O
COMHN
COMHN
COMHN
42
I/O
Vertical bidirectional communication interface for daisy chain connection. High side (north
side) differential I/O. Will connect to the low side (south side) COMLP and COMLN of the
lower adjacent device in the daisy chain configuration. If unused, connect COMHP and
COMHN with a 1kΩ resistor.
COMLP
COMLP
COMLP
40
I/O
COMLN
COMLN
COMLN
41
I/O
NFAULT
NFAULT
NFAULT
62
O
Fault indication output. Active low. If used on the base device, pull up NFAULT to CVDD with
a pullup resistor and connect NFAULT to host MCU GPIO. If unused, leave it unconnected.
GPIO1
GPIO1
GPIO1
61
I/O
General purpose input/output, configuration options are:
GPIO2
GPIO2
GPIO2
60
I/O
•
GPIO3
GPIO3
GPIO3
59
I/O
GPIO4
GPIO4
GPIO4
58
I/O
•
For external DC voltage measurement, configured as input to ADC.
GPIO5
GPIO5
GPIO5
57
I/O
•
Generic digital input/output.
•
Use as I/O for SPI master.
GPIO6
GPIO6
GPIO6
56
I/O
GPIO7
GPIO7
GPIO7
55
I/O
GPIO8
GPIO8
GPIO8
54
I/O
10
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Vertical bidirectional communication interface for daisy chain connection. Low side (south
side) differential I/O. Will connect to the high side (north side) COMHP and COMHN of
the upper adjacent device in the daisy chain configuration. If unused, connect COMLP and
COMLN with a 1kΩ resistor.
For external NTC thermistor connection, connect NTC thermistor to the pin and pull up
to TSREF. Used as input to ADC and OT and UT hardware comparators.
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SLUSE81D – AUGUST 2020 – REVISED SEPTEMBER 2022
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Input Voltage
MIN
MAX
UNIT
BAT, VC* (except VC0), CB* (except CB0),
NFAULT, BBP, BBN to AVSS (2) (3)
–0.3
100
V
CB0, VC0 to AVSS
–0.3
5.5
V
VCn to VCn-1, n = 1 to 16 (2)
–80
80
V
(3)
CBn to CBn-1, n = 1 to 16
–0.3
16
V
BBP to BBN
–80
80
V
LDOIN to AVSS
–0.3
9
V
NPNB to AVSS
–0.3
10
V
AVDD to AVSS
–0.3
5.5
V
DVDD to DVSS
–0.3
1.98
V
CVDD to CVSS
–0.3
6
V
TSREF to AVSS
–0.3
5.5
V
REFHP to REFHM
–0.3
5.5
V
NEG5V to AVSS
–5.5
0
V
TX, RX to AVSS
–0.3
6
V
COMHP, COMHN, COMLP, COMLN to CVSS
–20
20
V
COMHP to COMHN, COMLP to COMLN
–5.5
5.5
V
GPIO* to AVSS
–0.3
5.5
V
75oC
CB* current
Max of 8 cell in balancing at
240
mA
I/O current
GPIO*, RX, TX current
10
mA
TOTP_PROG
Device will not start OTP programming above
this temperature
55
°C
TA
Ambient temperature
–40
130
°C
TJ
Junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
ambient
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
VC pin voltage has to meet criteria of both VCn to AVSS as well as VCn to VCn-1.
CB pin voltage has to meet criteria of both CBn to AVSS as well as CBn to CBn-1.
8.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002(1)
V(ESD)
(1)
Electrostatic
discharge
Charged device model (CDM), per AEC
Q100-011
UNIT
±2000
All Pins
±500
Other pins (1, 16, 17, 32, 33, 48, 49, 64)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VBAT_RANG
E
Total module voltage, full functionality, no OTP programming
9
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NOM
MAX
80
UNIT
V
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8.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
VBAT_OTP_R
ANGE
VCELL_RAN
GE
NOM
MAX
UNIT
Total module voltage, full functionality, OTP programming allow
11
80
V
VCn - VCn-1, where n = 2 to 16
–1
5
V
0
5
V
VC1 - VC0
VC0, CB0 to AVSS
-0.3
5
V
VC1, VC2, CB1, CB2 to AVSS
-0.3
80
V
VCn, CBn to AVSS, where n = 3 to 16
VBB_RANGE VBBP - VBBN
3
80
V
-600
800
mV
VCB_RANGE CBn - CBn-1, where n = 1 to 16
0
5
V
VIO_RANGE
0
CVDD
V
0.2
4.8
V
VGPIO_RAN
GE
RX, TX, NFAULT
GPIOn input, where n = 1 to 8
IIO
GPIOn, RX, TX, where n = 1 to 8
TA
Operation temperature
5
–40
mA
125
°C
8.4 Thermal Information
BQ7961x-Q1
THERMAL METRIC
PAP (HTQFP)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
21.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
8.7
°C/W
RθJB
Junction-to-board thermal resistance
7.9
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
7.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.1
°C/W
8.5 Electrical Characteristics
over operating -40℃ to 125℃ free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
137
152
°C
129
°C
THERMAL SHUTDOWN
TSHUT
Thermal shutdown (rising direction)
130
TSHUT_FALL
Thermal shutdown (falling direction)
112
TSHUT_HYS
Thermal shutdown (rising - falling
direction)
TWARN_RANGE
Thermal warning Threshold (rising
direction)
TWARN_HYS
Thermal warning hysteresis (falling
direction)
TWARN_ACC
Thermal warning accuracy (+/-)
20
85
°C
115
°C
10
°C
5
°C
SUPPLY CURRENTS
ISHDN
Supply current in SHUTDOWN mode
ISLP(IDLE)
12
Baseline supply current in SLEEP
mode. No fault, no protector
comparator, no cell balancing
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Sum of both IBAT and ILDOIN
16
23
µA
Sum of both IBAT and ILDOIN
TA = -20℃ to 65℃
120
160
µA
220
µA
Sum of both IBAT and ILDOIN
TA = -40℃ to 125℃
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SLUSE81D – AUGUST 2020 – REVISED SEPTEMBER 2022
8.5 Electrical Characteristics (continued)
over operating -40℃ to 125℃ free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10.4
11.6
mA
IACT(IDLE)
Baseline supply current in ACTIVE
mode
Sum of both IBAT and ILDOIN
No fault, no communication, no
protector comparator, no cell balancing
ICB_EN
Additional supply current when cell
balancing is on
At least 1 cell balancing FET is on,
OTCB is enabled. Other functions are
inactive
1
1.5
mA
IPROTCOMP
Additional supply current when
protector comparator is on
Either OV/UV/OT/UT protector is
enabled. Other functions are inactive
20
60
µA
SLEEP Mode, no load on TSREF pin
100
ITSREF
IADC
IBAT
One ADC on, and conversion is in
Additional supply current when ADC is progress. Other functions are inactive
enabled
2 ADCs on, and conversion is in
progress. Other functions are inactive
Supply current goes into BAT pin
µA
0.4
0.6
mA
0.6
0.9
mA
ACTIVE Mode
150
µA
SLEEP Mode
25
µA
5
µA
SHUTDOWN Mode
ICOMT
Additional supply current during daisy- Use transformer isolation for daisychain broadcast read of 128-byte data chain interface
10
mA
ICOMC
Additional supply current during daisy- Use capacitor or capacitor and choke
chain broadcast read of 128-byte data isolation for daisy-chain interface
10
mA
IOW_SINK
Sink current for open wire test, applies
to VC1 to VC16 and CB1 to CB 16
380
500
600
µA
IOW_SOURCE
Source current for open wire test,
applies to VC0 and CB0
380
500
600
µA
ILEAK
Leakage current on VC, CB pins
0.1
µA
VC, CB pins with ADC off.
Supplies (LDOIN)
VLDOIN
LDOIN voltage
No OTP programming
5.9
6
6.1
V
OTP programming
7.9
8
8.1
V
4.9
5
Supplies (CVDD)
ACTIVE and SLEEP mode
VCVDD
CVDD output voltage
5.1
V
3.95
6
V
SHUTDOWN mode, max external
Iload = 5mA
3.4
5.5
V
30
mV
SHUTDOWN mode, no external Iload
VCVDD_LDRG
CVDD load regulation
ACTIVE/SLEEP mode, max external
Iload = 10mA
–30
VCVDD_OV
CVDD OV threshold
ACTIVE/SLEEP mode, max external
Iload = 10mA
5.3
5.5
5.7
V
VCVDD_OVHYS
CVDD OV Hystersis
ACTIVE/SLEEP mode, max external
Iload = 10mA
130
150
170
mV
VCVDD_UV
CVDD UV threshold
VCVDD_UVHYS
CVDD UV Hystersis
VCVDD_ILIMIT
SHUTDOWN mode
3.5
V
ACTIVE/SLEEP mode, max external
Iload = 10mA
4.3
CVDD current limit
ACTIVE, SLEEP
35
60
85
VAVDD
AVDD output voltage
CSUPPLIES = 1µF, ACTIVE mode
4.85
5
5.21
VAVDD_OV
AVDD OV threshold
CSUPPLIES = 1µF, ACTIVE mode
5.25
5.5
5.7
V
VAVDD_OVHYS
AVDD OV Hystersis
CSUPPLIES = 1µF, ACTIVE mode
135
155
165
mV
VAVDD_UV
AVDD UV threshold
CSUPPLIES = 1µF, ACTIVE mode
4.25
4.45
4.6
V
4.45
4.65
260
V
mV
mA
Supplies (AVDD)
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8.5 Electrical Characteristics (continued)
over operating -40℃ to 125℃ free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VAVDD_UVHYS
AVDD UV Hystersis
CSUPPLIES = 1µF, ACTIVE mode
VAVDD_ILIMIT
AVDD current limit
CSUPPLIES = 1µF
MIN
TYP
MAX
UNIT
235
340
430
mV
10
30
50
mA
Supplies (DVDD)
VDVDD
CSUPPLIES = 1µF, ACTIVE mode
1.72
1.8
1.88
V
VDVDD_OV
DVDD OV threshold
CSUPPLIES = 1µF, ACTIVE mode
1.95
2.1
2.3
V
VDVDD_OVHYS
DVDD OV Hystersis
CSUPPLIES = 1µF, ACTIVE mode
40
65
120
mV
VDVDD_UV
DVDD UV threshold
CSUPPLIES = 1µF, ACTIVE mode
1.623
1.65
1.71
V
VDVDD_UVHYS
DVDD UV Hystersis
CSUPPLIES = 1µF, ACTIVE mode
15
50
73
mV
VDVDD_ILIMIT
DVDD current limit
13
30
53
mA
4.975
5
5.025
Supplies (TSREF)
VTSREF
TSREF output voltage
CSUPPLIES = 1µF, ACTIVE mode
VTSREF_LDRG
TSREF load regulation
Iload = 4mA, CSUPPLIES = 1µF, ACTIVE
mode
–30
VTSREF_OV
TSREF OV threshold
Iload = 4mA, CSUPPLIES = 1µF, ACTIVE
mode
5.2
VTSREF_OVHYS
TSREF OV Hystersis
Iload = 4mA, CSUPPLIES = 1µF, ACTIVE
mode
VTSREF_UV
TSREF UV threshold
VTSREF_UVHYS
VTSREF_ILIMIT
V
30
mV
5.6
5.8
V
98
110
120
mV
Iload = 4mA, CSUPPLIES = 1µF, ACTIVE
mode
4.0
4.2
4.4
V
TSREF UV Hystersis
Iload = 4mA, CSUPPLIES = 1µF, ACTIVE
mode
300
350
400
mV
TSREF current limit
Device in ACTIVE Mode
15
30
52
mA
CNEG5V = 0.1µF
-5.0
-4.6
-4.5
V
Negative Charge Pump (NEG5V)
VNEG5V
VNEG5V_UV
NEG5V UV threshold (rising)
CNEG5V = 0.1µF
-4.1
-3.5
-3.0
V
VNEG5V_UVRECOV
NEG5V UV Recovery
CNEG5V = 0.1µF
-4.3
-3.8
-3.3
V
RDSON
Internal cell balance FET Rdson
VCn > 2.8V, where n = 1 to 16;
-40oC
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