CD54HC02, CD74HC02
CD74HC02
SCHS125D – MARCH 1998 CD54HC02,
– REVISED DECEMBER
2020
SCHS125D – MARCH 1998 – REVISED DECEMBER 2020
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CDx4HC02 Quadruple 2-Input Positive-NOR Gates
1 Features
3 Description
•
•
•
This device contains four independent 2-input NOR
gates. Each gate performs the Boolean function
Y = A + B in positive logic.
•
•
Buffered inputs
Wide operating voltage range: 2 V to 6 V
Wide operating temperature range:
–55°C to +125°C
Supports fanout up to 10 LSTTL loads
Significant power reduction compared to LSTTL
logic ICs
2 Applications
•
•
Alarm / tamper detect circuit
S-R latch
Device Information
PART NUMBER
SOIC (14)
8.65 mm × 3.90 mm
CD74HC02E
PDIP (14)
19.30 mm × 6.40 mm
CD54HC02F
CDIP (14)
19.94 mm × 7.62 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
1Y
1
14
VCC
1A
2
13
4Y
3
12
4
11
4B
4A
5
10
3Y
2B
6
9
3B
GND
7
8
3A
2A
BODY SIZE (NOM)
CD74HC02M
(1)
1B
2Y
PACKAGE(1)
Device functional pinout
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2020 Texas Instruments
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SCHS125D – MARCH 1998 – REVISED DECEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Switching Characteristics ...........................................5
6.7 Operating Characteristics .......................................... 6
6.8 Typical Characteristics................................................ 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Balanced CMOS Push-Pull Outputs........................... 8
8.4 Standard CMOS Inputs...............................................8
8.5 Clamp Diode Structure................................................8
8.6 Device Functional Modes............................................9
9 Application and Implementation.................................. 10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................13
11 Layout........................................................................... 13
11.1 Layout Guidelines................................................... 13
11.2 Layout Example...................................................... 13
12 Device and Documentation Support..........................14
12.1 Documentation Support.......................................... 14
12.2 Receiving Notification of Documentation Updates..14
12.3 Support Resources................................................. 14
12.4 Trademarks............................................................. 14
12.5 Electrostatic Discharge Caution..............................14
12.6 Glossary..................................................................14
13 Mechanical, Packaging, and Orderable
Information.................................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2003) to Revision D (December 2020)
Page
• Updated to new data sheet format......................................................................................................................1
• HCT device removed to separate data sheet - SCHS400 ................................................................................. 1
• RθJA increased for the D package from 80 to 133.6 ℃/W and decreased for the N package from 86 to 65
℃/W....................................................................................................................................................................5
2
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5 Pin Configuration and Functions
1Y
1
14
VCC
1A
2
13
4Y
1B
3
12
4B
2Y
4
11
4A
2A
5
10
3Y
2B
6
9
3B
GND
7
8
3A
Figure 5-1. D, N, or J Package
14-Pin SOIC, PDIP, or CDIP
Top View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1Y
1
Output
1A
2
Input
Channel 1, Output Y
Channel 1, Input A
1B
3
Input
Channel 1, Input B
2Y
4
Output
2A
5
Input
Channel 2, Input A
2B
6
Input
Channel 2, Input B
GND
7
—
3A
8
Input
Channel 3, Input A
3B
9
Input
Channel 3, Input B
3Y
10
Output
4A
11
Input
Channel 4, Input A
4B
12
Input
Channel 4, Input B
4Y
13
Output
VCC
14
—
Channel 2, Output Y
Ground
Channel 3, Output Y
Channel 4, Output Y
Positive Supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp current(2)
VI < –0.5 V or VI > VCC +
0.5 V
IOK
Output clamp current(2)
VO < –0.5 V or VO > VCC +
0.5 V
±20
mA
IO
Continuous output current
VO > –0.5 V or VO < VCC +
0.5 V
±25
mA
±50
mA
Plastic package
150
°C
Hermetic package or die
175
°C
SOIC - lead tips only
300
°C
150
°C
Continuous current through VCC or GND
Junction temperature(3)
TJ
Lead temperature (soldering 10s)
Tstg
(1)
(2)
(3)
Storage temperature
–65
±20
mA
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Guaranteed by design.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC = 2 V
VIH
High Level Input Voltage
VCC = 4.5 V
VCC = 6 V
NOM
3.15
UNIT
V
4.2
VCC = 2 V
0.5
VIL
Low Level Input Voltage
VCC
Supply voltage
2
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 4.5 V
1.35
VCC = 6 V
tt
TA
Input transition time
5
6
500
VCC = 6 V
400
–55
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V
1000
VCC = 4.5 V
Operating free-air temperature
V
1.8
VCC = 2 V
4
MAX
1.5
125
ns
°C
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6.4 Thermal Information
CD74HC02
THERMAL
METRIC(1)
N (PDIP)
D (SOIC)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
65.0
133.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
52.7
89.0
°C/W
RθJB
Junction-to-board thermal resistance
44.7
89.5
°C/W
ΨJT
Junction-to-top characterization parameter
32.3
45.5
°C/W
ΨJB
Junction-to-board characterization parameter
44.5
89.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VCC
25°C
MIN
2V
IOH = –20
µA
VOH
High-level
output voltage
VI = VIH or
IOH = –4
VIL
mA
IOL = 20
µA
Low-level output VI = VIH or
voltage
VIL
MAX
MIN
TYP
–55°C to 125°C
MAX
MIN
1.9
1.9
1.9
4.5 V
4.4
4.4
4.4
6V
5.9
5.9
5.9
4.5 V
3.98
3.84
3.7
6V
5.48
5.34
5.2
TYP
UNIT
MAX
V
IOH = –5.2
mA
VOL
TYP
–40°C to 85°C
2V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
0.1
0.1
0.1
IOL = 4 mA 4.5 V
6V
0.26
0.33
0.4
IOL = 5.2
mA
6V
0.26
0.33
0.4
V
II
Input leakage
current
VI = VCC or 0
6V
±0.1
±1
±1
µA
ICC
Supply current
VI = VCC or
IO = 0
0
6V
2
20
40
µA
Ci
Input
capacitance
5V
10
10
10
pF
6.6 Switching Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
tpd
Propagation delay
FROM
A or B
A or B
TO
Y
Y
TEST
CONDITIO
NS
CL = 50 pF
CL = 15 pF
Operating free-air temperature (TA)
VCC
25°C
–40°C to 85°C
–55°C to 125°C
MIN TYP MAX
MIN TYP MAX
MIN TYP MAX
2V
90
115
135
4.5 V
18
23
27
6V
15
20
23
5V
UNIT
ns
7
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over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
tt
FROM
Transition-time
TO
Y
Operating free-air temperature (TA)
TEST
CONDITIO
NS
VCC
CL = 50 pF
25°C
–40°C to 85°C
–55°C to 125°C
MIN TYP MAX
MIN TYP MAX
MIN TYP MAX
2V
75
95
110
4.5 V
15
19
22
6V
13
16
19
UNIT
ns
6.7 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
Power dissipation capacitance
No load
per gate
Cpd
VCC
MIN
5V
TYP
MAX UNIT
26
pF
6.8 Typical Characteristics
TA = 25°C
0.3
7
VOL Output Low Voltage (V)
VOH Output High Voltage (V)
6
5
4
3
2
2-V
4.5-V
6-V
1
0
0.25
0.2
0.15
0.1
0.05
0
0
1
2
3
4
IOH Output High Current (mA)
5
6
Figure 6-1. Typical output voltage in the high state
(VOH)
6
2-V
4.5-V
6-V
0
1
2
3
4
IOL Output Low Current (mA)
5
6
Figure 6-2. Typical output voltage in the low state
(VOL)
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
VCC
Input
50%
50%
0V
From Output
Under Test
tPHL(1)
tPLH(1)
VOH
CL(1)
Output
50%
50%
VOL
(1) CL includes probe and test-fixture capacitance.
tPLH(1)
tPHL(1)
Figure 7-1. Load Circuit for Push-Pull Outputs
VOH
Output
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-2. Voltage Waveforms Propagation Delays
90%
VCC
90%
Input
10%
10%
tr(1)
0V
tf(1)
90%
VOH
90%
Output
10%
10%
tr(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 7-3. Voltage Waveforms, Input and Output Transition Times
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8 Detailed Description
8.1 Overview
This device contains four independent 2-input NOR gates. Each gate performs the Boolean function Y = A + B
in positive logic.
8.2 Functional Block Diagram
xA
xY
xB
Figure 8-1. Logic Diagram (Positive Logic) for the CD74HC02
8.3 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.4 Standard CMOS Inputs
This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically
modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case
resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the
maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined by the
input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification
will result in excessive power consumption and could cause oscillations. More details can be found in
Implications of Slow or Floating CMOS Inputs.
Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated at
VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down resistor can be
added to provide a valid input voltage during these times. The resistor value will depend on multiple factors,
however a 10-kΩ resistor is recommended and will typically meet all requirements.
8.5 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical
Placement of Clamping Diodes for Each Input and Output.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
8
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VCC
Device
+IIK
+IOK
Logic
Input
-IIK
Output
-IOK
GND
Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output
8.6 Device Functional Modes
Table 8-1. Function Table
INPUTS
A
OUTPUT
B
Y
L
L
H
H
X
L
X
H
L
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
In this application, the CD74HC02 is used to create an active-low SR latch. The two additional gates can be
used for a second active-low SR latch, individually used for their logic function, or the inputs can be grounded
and both channels left unused. This device is used to drive the tamper indicator LED and provide one bit of data
to the system controller. When the tamper switch outputs LOW, the output Q becomes HIGH. This output
remains HIGH until the system controller addresses the event and sends a LOW signal to the R input which
returns the Q output back to LOW.
9.2 Typical Application
System
Controller
R
Q
R1
R2
Tamper
Switch
S
Tamper
Indicato r
Figure 9-1. Typical application diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the CD74HC02 plus the maximum static supply current, ICC, listed in Electrical Characteristics and
any transient current required for switching. The logic device can only source as much current as is provided by
the positive supply source. Be sure not to exceed the maximum total current through VCC listed in the Absolute
Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
CD74HC02 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient current
required for switching. The logic device can only sink as much current as can be sunk into its ground connection.
Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum Ratings.
The CD74HC02 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of the
datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed 50
pF.
The CD74HC02 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state, the
output voltage in the equation is defined as the difference between the measured output voltage and the supply
voltage at the VCC pin.
10
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Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
CD74HC02, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ resistor
value is often used due to these factors.
The CD74HC02 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in the
Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the CD74HC02 to
the receiving device(s).
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
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9.2.3 Application Curve
R
S
Q
Figure 9-2. Application timing diagram
12
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to the
device
1Y
1
14
VCC
1A
2
13
4Y
1B
3
12
4B
2Y
4
11
4A
2A
5
10
3Y
2B
6
9
3B
GND
7
8
3A
Unused
output left
floating
Unused
inputs tied to
VCC
Figure 11-1. Example layout for the CD74HC02.
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
14
This glossary lists and explains terms, acronyms, and definitions.
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Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: CD54HC02 CD74HC02
CD54HC02, CD74HC02
www.ti.com
SCHS125D – MARCH 1998 – REVISED DECEMBER 2020
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: CD54HC02 CD74HC02
15
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CD54HC02F
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54HC02F
Samples
CD54HC02F3A
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8404101CA
CD54HC02F3A
Samples
CD74HC02E
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC02E
Samples
CD74HC02M
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC02M
Samples
CD74HC02M96
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 125
HC02M
Samples
CD74HC02ME4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC02M
Samples
CD74HC02MG4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC02M
Samples
CD74HC02MT
ACTIVE
SOIC
D
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC02M
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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