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CSD85302L
SLPS561 – NOVEMBER 2015
CSD85302L 20 V Dual N-Channel NexFET™ Power MOSFET
1 Features
•
•
•
•
•
•
1
Text added for spacing
Common Drain Configuration
Low On-Resistance
Small Footprint of 1.35 mm × 1.35 mm
Pb Free and Halogen Free
RoHS Compliant
ESD HBM Protection >2.5 kV
Product Summary
TA = 25°C
20
V
Qg
Gate Charge Total (4.5 V)
6
nC
Qgd
Gate Charge Gate-to-Drain
RS1S2(on)
1.4
nC
VGS(th)
This 20 V, 18.7 mΩ, 1.35 mm × 1.35 mm LGA Dual
NexFET™ power MOSFET is designed to minimize
resistance in the smallest footprint. Its small footprint
and common drain configuration make the device
ideal for battery-powered applications in small
handheld devices.
20
mΩ
18.7
Threshold Voltage
mΩ
0.9
V
DEVICE
QTY
MEDIA
PACKAGE
SHIP
CSD85302L
3000
CSD85302LT
250
7-Inch
Reel
1.35 × 1.35 mm Land Grid
Array (LGA) Package
Tape and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
TA = 25°C
Top View
S1
S2
mΩ
Ordering Information(1)
3 Description
G1
29
Source-to-Source On-Resistance VGS = 4.5 V
VGS = 6.5 V
USB Type-C/PD
Battery Management
Battery Protection
UNIT
Source-to-Source Voltage
VGS = 2.5 V
2 Applications
•
•
•
TYPICAL VALUE
VS1S2
G2
VALUE
UNIT
VS1S2
Source-to-Source Voltage
20
V
VGS
Gate-to-Source Voltage
±10
V
IS
Continuous Source Current(1)
7
A
ISM
Pulsed Source Current(2)
37
A
PD
Power Dissipation(1)
1.7
W
V(ESD)
Human Body Model (HBM)
2.5
kV
TJ,
Tstg
Operating Junction and
Storage Temperature Range
–55 to 150
°C
(1) Typical RθJA = 75°C/W when mounted on a 1 inch2, 2 oz. Cu
pad on a 0.06 inch thick FR4 PCB.
(2) Max RθJA = 90°C/W, pulse duration ≤100 μs, duty cycle ≤1%
Configuration
Source 1
Source 2
Gate 1
Gate 2
.
.
RDS(on) vs VGS
Gate Charge
8
TC = 25°C, I S = 2 A
TC = 125°C, I S = 2 A
54
VGS - Gate-to-Source Voltage (V)
RS1S2(on) - On-State Resistance (m:)
60
48
42
36
30
24
18
12
6
0
IS1S2 = 2 A
7 VS1S2 = 10 V
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage (V)
9
10
D007
0
2
4
6
8
Qg - Gate Charge (nC)
10
12
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD85302L
SLPS561 – NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
6.1
6.2
6.3
6.4
1
1
1
2
3
7
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1
7.2
7.3
7.4
Device and Documentation Support.................... 7
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
Package Dimensions ................................................ 8
Recommended PCB Pattern..................................... 9
Recommended Stencil Pattern ................................. 9
Q3A Tape and Reel Information ............................. 10
4 Revision History
2
DATE
REVISION
NOTES
November 2015
*
Initial release.
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SLPS561 – NOVEMBER 2015
5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVS1S2
Source-to-source voltage
VGS = 0 V, IS = 250 μA
IS1S2
Source-to-source leakage current
VGS = 0 V, VS1S2 = 16 V
IGSS
Gate-to-source leakage current
VS1S2 = 0 V, VGS = 6 V
VGS(th)
Gate-to-source threshold voltage
20
V
VS1S2 = 0 V, VGS = 10V
RS1S2(on)
gfs
VS1S2 = VGS, IS = 250 μA
Source-to-source on-resistance
Transconductance
1
μA
0.5
µA
4
µA
0.68
0.9
1.3
V
VGS = 2.5 V, IS = 2 A
20
29
36
mΩ
VGS = 4.5 V, IS = 2 A
14
20
24
mΩ
VGS = 6.5 V, IS = 2 A
13
18.7
22.5
mΩ
VS1S2 = 2 V, IS = 2 A
19
S
DYNAMIC CHARACTERISTICS (1)
Ciss
Input capacitance
Coss
Output capacitance
718
933
pF
92
120
Crss
pF
Reverse transfer capacitance
61
79
pF
Qg
Gate charge total (4.5 V)
6.0
7.8
nC
Qgd
Gate charge gate-to-drain
1.4
nC
Qgs
Gate charge gate-to-source
1.2
nC
Qg(th)
Gate charge at Vth
0.6
nC
Qoss
Output charge
2.3
nC
td(on)
Turn-on delay time
37
ns
tr
Rise time
54
ns
td(off)
Turn-off delay time
173
ns
tf
Fall time
99
ns
(1)
VGS = 0 V, VS1S2 = 10 V, ƒ = 1 MHz
VS1S2 = 10 V, IS = 2 A
VS1S2 = 10 V, VGS = 0 V
VS1S2 = 10 V, VGS = 4.5 V,
IS1S2 = 2 A, RG = 0 Ω
Charge and timing values specified are per single FET.
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
THERMAL METRIC
RθJA
(1)
(2)
Junction-to-ambient thermal resistance (1)
Junction-to-ambient thermal resistance
(2)
2
MIN
TYP
MAX
UNIT
75
°C/W
175
°C/W
2
Device mounted on FR4 material with 1 inch (6.45 cm ), 2 oz. (0.071 mm thick) Cu.
Device mounted on FR4 material with minimum Cu mounting area.
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SLPS561 – NOVEMBER 2015
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5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
20
18
IS1S2 - Source-to-Source Current (A)
IS1S2 - Source-to-Source Current (A)
20
16
14
12
10
8
6
4
VG1S1 = 2.5 V
VG1S1 = 4.5 V
VG1S1 = 6.5 V
2
0
TC = 125°C
TC = 25°C
TC = -55°C
16
12
8
4
0
0
0.1
0.2
0.3
0.4
0.5
0.6
VS1S2 - Source-to-Source Voltage (V)
0.7
0.8
0
D002
VG2S2 = 9 V
1
1.5
2
VGS - Gate-to-Source Voltage (V)
VS1S2 = 5 V
Figure 2. Saturation Characteristics
4
0.5
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2.5
D003
VG2S2 = 9 V
Figure 3. Transfer Characteristics
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SLPS561 – NOVEMBER 2015
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
10000
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
7
6
C - Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
8
5
4
3
2
1000
100
1
10
0
0
2
4
6
8
Qg - Gate Charge (nC)
IS = 2 A
10
0
12
4
8
12
16
VS1S2 - Source-to-Source Voltage (V)
D004
Figure 5. Capacitance
60
RS1S2(on) - On-State Resistance (m:)
1.2
VGS(th) - Threshold Voltage (V)
D005
VS1S2 = 6 V
Figure 4. Gate Charge
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
-75
20
TC = 25°C, I S = 2 A
TC = 125°C, I S = 2 A
54
48
42
36
30
24
18
12
6
0
-50
-25
0
25
50
75 100
TC - Case Temperature (°C)
125
150
0
175
1
2
D006
3
4
5
6
7
8
VGS - Gate-to-Source Voltage (V)
9
10
D007
IS = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Source-to-Source Resistance vs
Gate-to-Source Voltage
1.4
100
VGS = 2.5 V
VGS = 6.5 V
IS1S2 - Source-to-Source Current (A)
Normalized On-State Resistance
1.5
1.3
1.2
1.1
1
0.9
0.8
0.7
-75
-50
-25
0
25
50
75 100
TC - Case Temperature (qC)
125
150
175
10
1
0.1
DC
10 s
0.01
0.01
1s
100 ms
10 ms
1 ms
0.1
1
10
VS1S2 - Source-to-Source Voltage (V)
D008
IS = 2 A
100
D009
Single pulse, max RθJA = 90°C/W
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Maximum Safe Operating Area
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Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
IS1S2 - Source-to-Source Current (A)
8
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
100 125
TA - Ambient Temperature (°C)
150
175
D010
Typical RθJA = 75°C/W
Figure 10. Maximum Source Current vs Temperature
6
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SLPS561 – NOVEMBER 2015
6 Device and Documentation Support
6.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.2 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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SLPS561 – NOVEMBER 2015
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Package Dimensions
1.35
1.27
A
B
PIN 1 INDEX AREA
1.35
1.27
C
0.22 MAX
SEATING PLANE
2X 0.66
2X 0.25
2X 0.41
2X
0.26
0.24
0.015
C B
A
3
2
2X 0.33
2X 0.74
2X 0.41
2X
0.42
0.40
1
4
(R0.08) TYP
2X
0.58
0.56
0.015
C A
B
Pin Configuration
PIN NUMBER
NAME
1
G1
2
S2
3
G2
4
S1
Text added for spacing
1. All linear dimensions are in millimeters.
8
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SLPS561 – NOVEMBER 2015
7.2 Recommended PCB Pattern
METAL UNDER
SOLDER MASK
2X (0.57)
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
1
4
2X (0.41)
2X (0.41)
PKG
2X (0.74)
2X (0.33)
2
3
(R0.05) TYP
2X ( 0.25)
2X (0.25)
2X (0.41)
PKG
2X (0.66)
Land Pattern Example
Solder Mask Defined
Scale: 50X
7.3 Recommended Stencil Pattern
SOLDER MASK OPENING
TYP
2X (0.51)
(R0.05) TYP
1
4
2X (0.37)
2X (0.41)
2X (0.74)
PKG
2X (0.33)
2
3
METAL
ALL AROUND
TYP
2X (0.25)
2X ( 0.25)
2X (0.41)
PKG
2X (0.66)
Solder Paste Example
Based on 0.1 mm thick stencil
Pads 2 and 4: 81% printed on solder coverage by area
Scale: 80X
1. All linear dimensions are in millimeters.
2. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
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7.4 Q3A Tape and Reel Information
1.42
±0.05
Pin 1 Orientation
W
+0.30
±0.10
8.00
B0
±0.05
1.42
A0
P1
Cavity
4.00
±0.10
2º max
All Measurements in
Millimeters (mm)
0.29
±0.05
K0
Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. MSL1 260°C (IR and convection) PbF-reflow compatible
10
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CSD85302L
ACTIVE
PICOSTAR
YME
4
3000
RoHS & Green
NIAU
Level-1-260C-UNLIM
-55 to 150
85302
CSD85302LT
ACTIVE
PICOSTAR
YME
4
250
RoHS & Green
NIAU
Level-1-260C-UNLIM
-55 to 150
85302
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of