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CSD87355Q5D
SLPS575A – MARCH 2016 – REVISED SEPTEMBER 2017
CSD87355Q5D Synchronous Buck NexFET™ Power Block
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The CSD87355Q5D NexFET™ power block is an
optimized design for synchronous buck applications
offering high-current, high-efficiency, and highfrequency capability in a small 5-mm × 6-mm outline.
Optimized for 5-V gate drive applications, this product
offers a flexible solution capable of offering a highdensity power supply when paired with any 5-V gate
drive from an external controller/driver.
1
Half-Bridge Power Block
92.5% System Efficiency at 25 A
Up to 45-A Operation
High-Frequency Operation (Up to 1.5 MHz)
High-Density SON 5-mm × 6-mm Footprint
Optimized for 5-V Gate Drive
Low Switching Losses
Ultralow Inductance Package
RoHS Compliant
Halogen Free
Pb-Free Terminal Plating
TEXT ADDED FOR SPACING
Top View
2 Applications
•
•
•
•
Synchronous Buck Converters
– High-Frequency Applications
– High-Current, Low Duty Cycle Applications
Multiphase Synchronous Buck Converters
POL DC-DC Converters
IMVP, VRM, and VRD Applications
8
VSW
7
VSW
3
6
VSW
4
5
VIN
1
VIN
2
TG
TGR
PGND
(Pin 9)
BG
P0116-01
.
Ordering Information(1)
Device
Media
Qty
Package
Ship
CSD87355Q5D
13-Inch Reel
2500
CSD87355Q5DT
7-Inch Reel
250
SON 5 mm × 6 mm
Plastic Package
Tape and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
Typical Power Block Efficiency and Power Loss
VIN
VDD
BOOT
VDD
VIN
ENABLE
PWM
ENABLE
LL
PWM
DRVL
TGR
BG
Control
FET
VSW
Sync
FET
PGND
Driver IC
CSD87355Q5D
VOUT
Efficiency (%)
DRVH
GND
TG
96
11
94
10
92
9
90
8
88
7
VGS = 5 V
VIN = 12 V
VOUT = 1.3 V
LOUT = 0.29 PH
fSW = 500 kHz
TA = 25qC
86
84
82
80
6
5
4
3
78
2
76
1
74
0
5
10
15
20
25
30
Output Current (A)
Power Loss (W)
Typical Circuit
35
40
0
45
D000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD87355Q5D
SLPS575A – MARCH 2016 – REVISED SEPTEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
3
3
3
3
3
4
5
7
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Power Block Performance ........................................
Electrical Characteristics...........................................
Typical Power Block Device Characteristics.............
Typical Power Block MOSFET Characteristics.........
Application and Implementation ........................ 10
6.1 Application Information............................................ 10
6.2 Typical Application .................................................. 13
7
Layout ................................................................... 15
7.1 Layout Guidelines ................................................... 15
7.2 Layout Example ...................................................... 16
8
Device and Documentation Support.................. 17
8.1
8.2
8.3
8.4
9
Community Resources............................................
Trademarks .............................................................
Electrostatic Discharge Caution ..............................
Glossary ..................................................................
17
17
17
17
Mechanical, Packaging, and Orderable
Information ........................................................... 18
9.1 Q5D Package Dimensions...................................... 18
9.2 Land Pattern Recommendation .............................. 19
9.3 Stencil Recommendation ........................................ 19
4 Revision History
Changes from Original (March 2016) to Revision A
Page
•
Added footnote for ZDS(ON) in the Electrical Characteristics table. ......................................................................................... 4
•
Deleted the Q5D Tape and Reel Information section .......................................................................................................... 19
2
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Copyright © 2016–2017, Texas Instruments Incorporated
CSD87355Q5D
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SLPS575A – MARCH 2016 – REVISED SEPTEMBER 2017
5 Specifications
5.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.8
30
V
TG to TGR
–8
10
V
BG to PGND
–8
10
V
120
A
VIN to PGND
Voltage
Pulsed current rating, IDM (2)
Power dissipation, PD
Avalanche energy EAS
12
W
Sync FET, ID = 89 A, L = 0.1 mH
396
mJ
Control FET, ID = 50 A, L = 0.1 mH
125
mJ
150
°C
Operating junction temperature, TJ
(1)
(2)
–55
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
Pulse duration ≤ 50 µS. Duty cycle ≤ 0.01.
5.2 Handling Ratings
Tstg
Storage temperature range
MIN
MAX
UNIT
–55
150
°C
5.3 Recommended Operating Conditions
TA = 25° (unless otherwise noted)
VGS
Gate drive voltage
VIN
Input supply voltage
ƒSW
Switching frequency CBST = 0.1 μF (min)
MIN
MAX
4.5
10
V
27
200
V
1500
Operating current
TJ
UNIT
Operating temperature
kHz
45
A
125
°C
5.4 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA
RθJC
(1)
(2)
Junction-to-ambient thermal resistance (min Cu)
MIN
TYP
MAX
UNIT
(1) (2)
102
°C/W
Junction-to-ambient thermal resistance (max Cu) (1) (2)
50
°C/W
Junction-to-case thermal resistance (top of package) (2)
20
°C/W
2
°C/W
Junction-to-case thermal resistance (PGND pin)
2
(2)
cm2)
2
Device mounted on FR4 material with 1 inch (6.45
Cu.
RθJC is determined with the device mounted on a 1 inch (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
5.5 Power Block Performance
TA = 25° (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power loss, PLOSS (1)
VIN = 12 V, VGS = 5 V, VOUT = 1.3 V,
IOUT = 25 A, ƒSW = 500 kHz,
LOUT = 0.29 µH, TJ = 25ºC
2.8
W
VIN quiescent current, IQVIN
TG to TGR = 0 V ,BG to PGND = 0 V
10
µA
(1)
Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5 V driver IC.
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5.6 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
Q1 CONTROL FET
MIN
TYP
Q2 SYNC FET
MAX
MIN
TYP MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 24 V
Gate-to-source leakage current
VDS = 0 V,
VGS = +10 / –8 V
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, IDS = 250 μA
ZDS(ON) (1)
Drain-to-source ON impedance
VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 25 A,
ƒSW = 500 kHz,
LOUT = 0.29 µH
3.9
0.9
mΩ
gfs
Transconductance
VDS = 3 V, IDS = 20 A
90
151
S
IGSS
30
30
1.00
V
1
1
μA
100
100
nA
1.20
V
1.90
0.75
DYNAMIC CHARACTERISTICS
CISS
Input capacitance
VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz
1430
1860
3570 4640
pF
1730 2240
pF
COSS
Output capacitance
716
930
CRSS
Reverse transfer capacitance
25
32
52
67
RG
Series gate resistance
0.6
1.2
0.7
1.4
Ω
Qg
Gate charge total (4.5 V)
10.5
13.7
24.3
31.5
nC
Qgd
Gate charge – gate-to-drain
Qgs
Gate charge – gate-to-source
Qg(th)
Gate charge at Vth
QOSS
Output charge
td(on)
Turn on delay time
tr
Rise time
td(off)
Turn off delay time
tf
Fall time
VDS = 15 V,
IDS = 20 A
VDS = 15 V, VGS = 0 V
VDS = 15 V, VGS = 4.5 V,
IDS = 20 A, RG = 2 Ω
pF
2.3
4.1
nC
3.2
5.6
nC
1.7
2.8
nC
18
40
nC
8
10
ns
18
14
ns
13
27
ns
3
6
ns
DIODE CHARACTERISTICS
VSD
Diode forward voltage
IDS = 20 A, VGS = 0 V
0.8
Qrr
Reverse recovery charge
82
nC
Reverse recovery time
Vdd = 17 V, IF = 20 A,
di/dt = 300 A/μs
43
trr
23.8
32.3
ns
(1)
0.8
1.0
V
Equivalent based on application testing. See Application and Implementation section for details.
HD
LD
HD
LG
LD
5x6 QFN TTA MIN Rev1
5x6 QFN TTA MIN Rev1
Max RθJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of
2 oz. (0.071-mm thick)
Cu.
HG
Max RθJA = 102°C/W
when mounted on
minimum pad area of
2 oz. (0.071-mm thick)
Cu.
HS
LG
LS
HG
M0189-01
4
1.0
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HS
LS
M0190-01
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SLPS575A – MARCH 2016 – REVISED SEPTEMBER 2017
5.7 Typical Power Block Device Characteristics
TJ = 125°C, unless stated otherwise. The Typical Power Block System Characteristic curves Figure 3, , and Figure 4 are
based on measurements made on a PCB design with dimensions of 4” (W) × 3.5” (L) × 0.062” (H) and 6 copper layers of 1oz. copper thickness. See Application and Implementation for detailed explanation.
10
1.1
9
1
Power Loss, Normalized
Power Loss (W)
8
7
6
5
4
3
2
0.9
0.8
0.7
0.6
1
0
0
5
10
VIN = 12 V
ƒSW = 500 kHz
15
20
25
30
Output Current (A)
35
40
0.5
-50
45
VGS = 5 V
LOUT = 0.29 µH
VOUT = 1.3 V
25
50
75
100
Junction Temperature (qC)
VGS = 5 V
LOUT = 0.29 µH
125
150
D002
VOUT = 1.3 V
Figure 2. Normalized Power Loss vs Temperature
50
45
45
40
40
35
35
Output Current (A)
Output Current (A)
Figure 1. Power Loss vs Output Current
30
25
20
15
400 LFM
200 LFM
100 LFM
Nat. conv.
5
0
VIN = 12 V
ƒSW = 500 kHz
50
10
-25
D001
30
25
20
15
10
5
0
0
0
10
20
VIN = 12 V
ƒSW = 500 kHz
30
40
50
60
Ambient Temperature (qC)
VGS = 5 V
LOUT = 0.29 µH
70
80
90
VOUT = 1.3 V
Figure 3. Safe Operating Area (SOA) – Thermal Airflow
Measurement PCB Vertical Mount
Copyright © 2016–2017, Texas Instruments Incorporated
0
15
30
D003
VIN = 12 V
ƒSW = 500 kHz
45
60
75
90
Board Temperature (qC)
VGS = 5 V
LOUT = 0.29 µH
105
120
135
D005
VOUT = 1.3 V
Figure 4. Typical Safe Operating Area (SOA)
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Typical Power Block Device Characteristics (continued)
13.9
1.3
10.4
1.2
7.0
1.1
3.5
1
0.0
0.9
-3.5
0.8
50
200
350
VGS = 5 V
IOUT = 45 A
1.3
10.0
1.25
8.3
1.2
6.7
1.15
5.0
1.1
3.3
1.05
1.7
1
0.0
0.95
-7.0
500 650 800 950 1100 1250 1400 1550
Switching Frequency (kHz)
D006
VIN = 12 V
LOUT = 0.29 µH
11.7
-1.7
0.9
0
VOUT = 1.3 V
19.3
1.4
12.9
1.2
6.4
1
0.0
0.8
0.5
1.3
VIN = 12 V
LOUT = 0.29 µH
2.1
2.9
3.7
Output Voltage (V)
VGS = 5 V
IOUT = 45 A
4.5
-6.4
5.3
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12
Input Voltage (V)
-3.3
18
15
D007
VOUT = 1.3 V
IOUT = 45 A
LOUT = 0.29 µH
1.1
3.4
1.075
2.5
1.05
1.7
1.025
0.8
1
0.0
0.975
-0.8
0.95
-1.7
0.925
10
150
290
D008
ƒSW = 500 kHz
Figure 7. Normalized Power Loss vs. Output Voltage
6
6
Figure 6. Normalized Power Loss vs Input Voltage
Power Loss, Normalized
1.6
SOA Temperature Adj. (qC)
Power Loss, Normalized
25.7
3
VIN = 12 V
ƒSW = 500 kHz
Figure 5. Normalized Power Loss vs Switching Frequency
1.8
SOA Temperature Adj. (qC)
1.4
1.35
VIN = 12 V
ƒSW = 500 kHz
430
570
710
850
Output Inductance (nH)
VGS = 5 V
IOUT = 45 A
990
SOA Temperature Adj. (qC)
17.4
Power Loss, Normalized
1.5
SOA Temperature Adj. (qC)
Power Loss, Normalized
TJ = 125°C, unless stated otherwise. The Typical Power Block System Characteristic curves Figure 3, , and Figure 4 are
based on measurements made on a PCB design with dimensions of 4” (W) × 3.5” (L) × 0.062” (H) and 6 copper layers of 1oz. copper thickness. See Application and Implementation for detailed explanation.
-2.5
1130
D009
VOUT = 1.3 V
Figure 8. Normalized Power Loss vs Output Inductance
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SLPS575A – MARCH 2016 – REVISED SEPTEMBER 2017
5.8 Typical Power Block MOSFET Characteristics
100
100
90
90
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
TA = 25°C, unless stated otherwise.
80
70
60
50
40
30
20
VGS = 4.5 V
VGS = 6.0 V
VGS = 8.0 V
10
80
70
60
50
40
30
20
VGS = 4.5 V
VGS = 6.0 V
VGS = 8.0 V
10
0
0
0
0.1
0.2
0.3
0.4
VDS - Drain-to-Source Voltage (V)
0.5
0
0.04
0.08
0.12
0.16
VDS - Drain-to-Source Voltage (V)
D010
Figure 9. Control MOSFET Saturation
Figure 10. Sync MOSFET Saturation
TC = 125° C
TC = 25° C
TC = -55° C
10
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
D011
100
100
1
0.1
0.01
TC = 125° C
TC = 25° C
TC = -55° C
10
1
0.1
0.01
0.001
0.001
0
0.5
1
1.5
2
2.5
VGS - Gate-to-Source Voltage (V)
3
0
3.5
0.5
D012
1
1.5
2
VGS - Gate-to-Source Voltage (V)
2.5
D013
VDS = 5 V
VDS = 5 V
Figure 12. Sync MOSFET Transfer
Figure 11. Control MOSFET Transfer
8
8
7
7
VGS - Gate-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
0.2
6
5
4
3
2
1
0
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
Qg - Gate Charge (nC)
ID = 20 A
16
18
VDD = 15 V
Figure 13. Control MOSFET Gate Charge
Copyright © 2016–2017, Texas Instruments Incorporated
20
D014
0
4
8
12
16 20 24 28 32
Qg - Gate Charge (nC)
ID = 20 A
36
40
44
D015
VDD = 15 V
Figure 14. Sync MOSFET Gate Charge
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Typical Power Block MOSFET Characteristics (continued)
TA = 25°C, unless stated otherwise.
1000
1000
C - Capacitance (pF)
10000
C - Capacitance (pF)
10000
100
10
100
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
1
0
3
6
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
ƒ = 1 MHz
27
30
0
3
6
D016
VGS = 0
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
ƒ = 1 MHz
Figure 15. Control MOSFET Capacitance
27
30
D017
VGS = 0
Figure 16. Sync MOSFET Capacitance
1.8
1.3
VGS(th) - Threshold Voltage (V)
VGS(th) - Threshold Voltage (V)
1.2
1.6
1.4
1.2
1
0.8
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.6
-75
-50
-25
0
25
50
75 100
TC - Case Temperature (° C)
125
150
0.3
-75
175
-50
-25
D018
ID = 250 µA
Figure 17. Control MOSFET VGS(th)
150
175
D019
Figure 18. Sync MOSFET VGS(th)
8
TC = 25° C, I D = 20 A
TC = 125° C, I D = 20 A
12
RDS(on) - On-State Resistance (m:)
RDS(on) - On-State Resistance (m:)
125
ID = 250 µA
14
10
8
6
4
2
TC = 25° C, I D = 20 A
TC = 125° C, I D = 20 A
7
6
5
4
3
2
1
0
0
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage (V)
9
Figure 19. Control MOSFET RDS(ON) vs VGS
8
0
25
50
75 100
TC - Case Temperature (° C)
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D020
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage (V)
9
10
D021
Figure 20. Sync MOSFET RDS(ON) vs VGS
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SLPS575A – MARCH 2016 – REVISED SEPTEMBER 2017
Typical Power Block MOSFET Characteristics (continued)
TA = 25°C, unless stated otherwise.
1.6
VGS = 4.5 V
VGS = 8.0 V
Normalized On-State Resistance
Normalized On-State Resistance
1.6
1.4
1.2
1
0.8
0.6
-75
-50
-25
0
25
50
75 100
TC - Case Temperature (qC)
ID = 20 A
125
150
VGS = 4.5 V
VGS = 8.0 V
1.4
1.2
1
0.8
0.6
-75
175
VGS = 8 V
Figure 21. Control MOSFET Normalized RDS(ON)
0
25
50
75 100
TC - Case Temperature (qC)
125
150
175
D023
VGS = 8 V
Figure 22. Sync MOSFET Normalized RDS(ON)
100
TC = 25qC
TC = 125qC
10
ISD - Source-to-Drain Current (A)
ISD - Source-to-Drain Current (A)
-25
ID = 20 A
100
1
0.1
0.01
0.001
0.0001
TC = 25qC
TC = 125qC
10
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
1
0
D024
Figure 23. Control MOSFET Body Diode
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
1
D025
1000
IAV - Peak Avalanche Current (A)
TC = 25q C
TC = 125q C
100
10
1
0.01
0.2
Figure 24. Sync MOSFET Body Diode
1000
IAV - Peak Avalanche Current (A)
-50
D022
0.1
TAV - Time in Avalanche (ms)
1
D026
Figure 25. Control MOSFET Unclamped Inductive Switching
Copyright © 2016–2017, Texas Instruments Incorporated
TC = 25q C
TC = 125q C
100
10
0.01
0.1
TAV - Time in Avalanche (ms)
1
D027
Figure 26. Sync MOSFET Unclamped Inductive Switching
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6 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application Information
The CSD87355Q5D NexFET power block is an optimized design for synchronous buck applications using 5-V
gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems
centric environment. System level performance curves such as Power Loss, Safe Operating Area, and
normalized graphs allow engineers to predict the product performance in the actual application.
6.1.1 Equivalent System Performance
Many of today's high performance computing systems require low power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s Synchronous Buck Topology. In particular, there has been an
emphasis in improving the performance of the critical Power Semiconductor in the Power Stage of this
application (see Figure 27). As such, optimization of the power semiconductors in these applications, needs to go
beyond simply reducing RDS(ON).
Power Stage
Components
Input
Supply
+
-
Power Block
Components
Ci
Control
FET
Driver
PWM
Driver
Switch
Node
Lo
Sync
FET
Co
IL
Load
Figure 27.
10
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Application Information (continued)
The CSD87355Q5D is part of TI’s Power Block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the Control FET and Sync FET connections (see Figure 28). A key
challenge solved by TI’s patented packaging technology is the system level impact of Common Source
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
and modification of switching loss equations are outlined in TI’s Application Note SLPA009.
Input
Supply
RPCB
CESR
LDRAIN
CINPUT
PWM
Control
FET
Driver
CESL
LSOURCE
Switch
Node
Lo
IL
LDRAIN
Sync
FET
Driver
Co
Load
CTOTAL
LSOURCE
Figure 28.
The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET
chipsets with lower RDS(ON). Figure 29 and Figure 30 compare the efficiency and power loss performance of the
CSD87355Q5D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD87355Q5D clearly highlights the importance of considering the Effective AC On-Impedance
(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s Power Block
technology.
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Application Information (continued)
9
94
PowerBlock RDS(ON) = 3.9 m:/1.5 m:
Discrete HS/LS RDS(ON) = 3.9 m:/1.5 m:
Discrete HS/LS RDS(ON) = 3.9 m:/0.9 m:
8
92
Output Current (A)
Output Current (A)
7
90
88
86
84
5
4
3
2
PowerBlock HS/LS RDS(ON) = 3.9 m:/1.5 m:
Discrete HS/LS RDS(ON) = 3.9 m:/1.5 m:
Discrete HS/LS RDS(ON) = 3.9 m:/0.9 m:
82
6
1
80
0
0
5
VIN = 12 V
ƒSW = 500 kHz
10
15
20
25
30
35
Ambient Temperature (qC)
40
VOUT = 1.3 V
VDD= 5 V
45
50
0
5
10
D030
LOUT = 0.3 µH
TA = 25°C
15
20
25
30
35
Ambient Temperature (qC)
VIN = 12 V
ƒSW = 500 kHz
Figure 29. Efficiency
40
45
50
D031
VOUT = 1.3 V
VDD = 5 V
LOUT = 0.3 µH
TA = 25°C
Figure 30. Power Loss
Table 1 compares the traditional DC measured RDS(ON) of CSD87355Q5D versus its ZDS(ON). This comparison
takes into account the improved efficiency associated with TI’s patented packaging technology. As such, when
comparing TI’s Power Block products to individually packaged discrete MOSFETs or dual MOSFETs in a
standard package, the in-circuit switching performance of the solution must be considered. In this example,
individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC
measured RDS(ON) values that are equivalent to CSD87355Q5D’s ZDS(ON) value in order to have the same
efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete
MOSFETs or dual MOSFETs in a standard package.
Table 1. Comparison of RDS(ON) vs ZDS(ON)
PARAMETER
HS
LS
TYP
MAX
TYP
Effective AC On-Impedance ZDS(ON) (VGS = 5 V)
3.9
-
0.9
MAX UNIT
-
mΩ
DC Measured RDS(ON) (VGS = 4.5 V)
3.9
4.7
1.5
1.8
mΩ
6.1.2 Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD87355Q5D as a function of load current. This curve
is measured by configuring and running the CSD87355Q5D as it would be in the final application (see
Figure 31).The measured power loss is the CSD87355Q5D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
(VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = Power Loss
(1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
6.1.3 Safe Operating Curves (SOA)
The SOA curves in the CSD87355Q5D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 4 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of
4” (W) × 3.5” (L) × 0.062” (T) and 6 copper layers of 1-oz. copper thickness.
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6.1.4 Normalized Curves
The normalized curves in the CSD87355Q5D data sheet provides guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of system conditions. The primary Y-axis is the normalized change in power
loss and the secondary Y-axis is the change is system temperature required in order to comply with the SOA
curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
6.2 Typical Application
Input Current (IIN)
Gate Drive
Current (IDD)
VDD
A
A
VDD
V
Input Voltage (VIN)
VIN
Gate Drive V
Voltage (VDD)
ENABLE
TG
DRVH
Control
FET
VSW
PWM
PWM
GND
Driver IC
VIN
BOOT
Output Current (IOUT)
A
TGR
LL
BG
DRVL
VOUT
Sync
FET
PGND
CSD87355Q5D
Averaging
Circuit
Averaged Switch
V Node Voltage
(VSW_AVG)
Figure 31.
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Typical Application (continued)
6.2.1 Design Example: Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Operating Conditions).
Though the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the
following procedure will outline the steps the user should take to predict product performance for any set of
system conditions.
6.2.2 Operating Conditions
• Output Current = 25 A
• Input Voltage = 7 V
• Output Voltage = 1.4 V
• Switching Frequency = 800 kHz
• Inductor = 0.2 µH
6.2.2.1 Calculating Power Loss
•
•
•
•
•
•
Power Loss at 25 A = 3.62 W (Figure 1)
Normalized Power Loss for input voltage ≈ 0.99 (Figure 6)
Normalized Power Loss for output voltage ≈ 1.02 (Figure 7)
Normalized Power Loss for switching frequency ≈ 1.06 (Figure 5)
Normalized Power Loss for output inductor ≈ 1.03 (Figure 8)
Final calculated Power Loss = 3.62 W × 0.99 × 1.02 × 1.06 × 1.03 ≈ 3.99 W
6.2.2.2 Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ –0.24ºC (Figure 6)
SOA adjustment for output voltage ≈ 0.63ºC (Figure 7)
SOA adjustment for switching frequency ≈ 2.12ºC (Figure 5)
SOA adjustment for output inductor ≈ 0.91ºC (Figure 8)
Final calculated SOA adjustment = –0.24 + 0.63 + 2.12 + 0.91 ≈ 3.42C
In the previous design example, the estimated power loss of the CSD87355Q5D would increase to 4 W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 3.4ºC. Figure 32
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 3.4ºC. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
Figure 32. Power Block SOA
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7 Layout
7.1 Layout Guidelines
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. The
following sections provide a brief description on how to address each parameter.
7.1.1 Electrical Performance
The Power Block has the ability to switch voltages at rates greater than 10 kV/µs. Take special care with the
PCB layout design and placement of the input capacitors, Driver IC, and output inductor.
• The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 33).
The example in Figure 33 uses 6 × 10-µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent).
Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias
interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8
should follow in order.
• The Driver IC should be placed relatively close to the Power Block Gate pins. TG and BG should connect to
the outputs of the Driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and
should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap
capacitor for the Driver IC will also connect to this pin.
• The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level.
• In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a Boost
Resistor or RC snubber can be an effective way to reduce the peak ring level. The recommended Boost
Resistor value will range between 1 Ω to 4.7 Ω depending on the output characteristics of Driver IC used in
conjunction with the Power Block. The RC snubber values can range from 0.5 Ω to 2.2 Ω for the R and 330
pF to 2200 pF for the C. Refer to TI App Note SLUP100 for more details on how to properly tune the RC
snubber values. The RC snubber should be placed as close as possible to the Vsw node and PGND see
Figure 33. (1)
7.1.2 Thermal Considerations
The Power Block has the ability to use the GND planes as the primary thermal path. As such, the use of thermal
vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids
and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of
solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 33 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
(1)
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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7.2 Layout Example
Input Capacitors
Input Capacitors
TGR
TG
VIN
PGND
Output Capacitors
Driver IC
Power Block
BG
V SW
VSW
V SW
RC Snubber
Power Block
Location on Top
Layer
Top Layer
Output Inductor
Bottom Layer
Figure 33. Recommended PCB Layout (Top View)
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8 Device and Documentation Support
8.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.2 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Q5D Package Dimensions
E2
K
d2
c1
4
5
4
q
L
d1
L
5
E1
6
3
6
3
b
9
D2
2
7
7
D1
2
E
e
8
1
8
1
d
d3
f
Top View
Bottom View
Side View
Pinout
Position
Exposed Tie Bar May Vary
q
a
c
E1
Front View
Pin 1
Designation
VIN
Pin 2
VIN
Pin 3
TG
Pin 4
TGR
Pin 5
BG
Pin 6
VSW
Pin 7
VSW
Pin 8
VSW
Pin 9
PGND
M0187-01
DIM
MILLIMETERS
MAX
MIN
MAX
a
1.40
1.5
0.055
0.059
b
0.360
0.460
0.014
0.018
c
0.150
0.250
0.006
0.010
c1
0.150
0.250
0.006
0.010
d
1.630
1.730
0.064
0.068
d1
0.280
0.380
0.011
0.015
d2
0.200
0.300
0.008
0.012
d3
0.291
0.391
0.012
0.015
D1
4.900
5.100
0.193
0.201
D2
4.269
4.369
0.168
0.172
E
4.900
5.100
0.193
0.201
E1
5.900
6.100
0.232
0.240
E2
3.106
3.206
0.122
e
1.27 TYP
0.126
0.050
f
0.396
0.496
0.016
0.020
L
0.510
0.710
0.020
0.028
θ
0.00
—
—
K
18
INCHES
MIN
0.812
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—
0.032
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9.2 Land Pattern Recommendation
3.480 (0.137)
0.530 (0.021)
0.415 (0.016)
0.345 (0.014)
0.650 (0.026)
5
4
0.650 (0.026)
4.460
(0.176)
0.620
(0.024)
0.620 (0.024)
4.460
(0.176)
1.270
(0.050)
1
1.920
(0.076)
8
0.850 (0.033)
0.400 (0.016)
0.850 (0.033)
6.240 (0.246)
M0188-01
NOTE: Dimensions are in mm (inches).
9.3 Stencil Recommendation
0.250 (0.010)
0.300 (0.012)
0.610 (0.024)
0.341 (0.013)
5
4
0.410 (0.016)
Stencil Opening
0.300 (0.012)
0.300 (0.012)
1.710
(0.067)
8
1
1.680
(0.066)
0.950 (0.037)
1.290 (0.051)
PCB Pattern
M0208-01
NOTE: Dimensions are in mm (inches).
Text For Spacing For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing
Ringing Through PCB Layout Techniques.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CSD87355Q5D
ACTIVE
LSON-CLIP
DQY
8
2500
RoHS-Exempt
& Green
NIPDAU
Level-1-260C-UNLIM
-55 to 150
87355D
CSD87355Q5DT
ACTIVE
LSON-CLIP
DQY
8
250
RoHS-Exempt
& Green
NIPDAU
Level-1-260C-UNLIM
-55 to 150
87355D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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