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CSD87355Q5DEVM-820

CSD87355Q5DEVM-820

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

  • 描述:

    CSD87355Q5D,TPS51218 - DC/DC,步降 1,非隔离 输出评估板

  • 数据手册
  • 价格&库存
CSD87355Q5DEVM-820 数据手册
User's Guide SLPU005 – June 2017 CSD87355Q5DEVM-820 The CSD87355Q5DEVM-820 evaluation module (EVM) is a synchronous buck converter featuring TI's NexFET™ Power Block technology to provide a high-current, ultra-high density power supply solution. The EVM provides a 1.2-V output at 25 A from a 12-V nominal input bus at over 92% efficiency. The EVM is designed to operate from a single supply, so no additional bias voltage is required. The EVM uses the TPS51218 high-performance, mid-input voltage, synchronous buck controller and TI’s NexFET Power Block to optimize the efficiency and power density of the total solution. 1 2 3 4 5 6 7 8 9 10 Contents Description .................................................................................................................... 3 Applications ................................................................................................................... 3 2.1 Features .............................................................................................................. 3 CSD87355Q5DEVM-820 Electrical Performance Specifications ...................................................... 3 CSD87355Q5DEVM-820 Schematic ...................................................................................... 4 Connector, Jumper, and Test Point Descriptions........................................................................ 5 5.1 Input Power (J1) .................................................................................................... 5 5.2 Output Power (J2) .................................................................................................. 5 5.3 5-V Bias Jumper (JP1) ............................................................................................. 5 5.4 Disable Jumper (JP2) .............................................................................................. 5 5.5 MODE Jumper (JP3) ............................................................................................... 5 5.6 Test Point Descriptions ............................................................................................ 5 Test Set Up ................................................................................................................... 6 6.1 Equipment ........................................................................................................... 6 6.2 Equipment Setup.................................................................................................... 7 6.3 Start-Up and Shutdown Procedure ............................................................................... 8 6.4 Output Ripple Voltage Measurement Procedure ............................................................... 9 6.5 Equipment Shutdown............................................................................................... 9 CSD87355Q5DEVM-820 Test Data ....................................................................................... 9 7.1 Efficiency (Full Load) ............................................................................................... 9 7.2 Efficiency (Light Load) ............................................................................................ 10 7.3 Output Voltage Ripple ............................................................................................ 10 7.4 Output Voltage Ripple ............................................................................................ 11 7.5 Input Voltage Ripple .............................................................................................. 11 7.6 Load Transient Response ........................................................................................ 12 7.7 Start-Up on VIN ..................................................................................................... 12 7.8 Start-Up on EN .................................................................................................... 13 7.9 Thermal Image..................................................................................................... 13 CSD87355Q5DEVM-820 Modifications ................................................................................. 14 8.1 Switching Frequency .............................................................................................. 14 8.2 Output Voltage ..................................................................................................... 14 8.3 Gate Drive Resistors .............................................................................................. 14 CSD87355Q5DEVM-820 Assembly Drawings and Layout ........................................................... 14 CSD87355Q5DEVM-820 Bill of Materials............................................................................... 17 List of Figures 1 CSD87355Q5DEVM-820 Schematic ...................................................................................... 4 2 CSD87355Q5DEVM-820 Recommended Test Set-Up ................................................................. 8 SLPU005 – June 2017 Submit Documentation Feedback CSD87355Q5DEVM-820 Copyright © 2017, Texas Instruments Incorporated 1 www.ti.com 3 Tip and Barrel Technique ................................................................................................... 8 4 CSD87355Q5DEVM-820 Efficiency vs Load Current ................................................................... 9 5 CSD87355Q5DEVM-820 Low Load Efficiency vs Load Current ..................................................... 10 6 CSD87355Q5DEVM-820 Output Voltage Ripple 7 8 9 10 11 12 13 14 15 16 17 ...................................................................... CSD87355Q5DEVM-820 Output Voltage Ripple ...................................................................... CSD87355Q5DEVM-820 Input Voltage Ripple ........................................................................ CSD87355Q5DEVM-820 Step Response .............................................................................. CSD87355Q5DEVM-820 Start-Up on VIN ............................................................................... CSD87355Q5DEVM-820 Start-Up on EN .............................................................................. CSD87355Q5DEVM-820 Thermal Image ............................................................................... CSD87355Q5DEVM-820 Top Component Placement (Top View) .................................................. CSD87355Q5DEVM-820 Top Copper (Top View) ..................................................................... CSD87355Q5DEVM-820 Internal Copper Layer 1 (X-Ray Top View) .............................................. CSD87355Q5DEVM-820 Internal Copper Layer 2 (X-Ray Top View) .............................................. CSD87355Q5DEVM-820 Bottom Copper (Bottom View) ............................................................. 10 11 11 12 12 13 13 15 15 16 16 17 List of Tables 1 2 3 4 ................................................ 3 Test Point Description ....................................................................................................... 5 R6 and Switching Frequency ............................................................................................. 14 CSD87355Q5DEVM-820 Bill of Materials............................................................................... 17 CSD87355Q5DEVM-820 Electrical and Performance Specifications Trademarks NexFET is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 2 CSD87355Q5DEVM-820 SLPU005 – June 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Description www.ti.com 1 Description The CSD87355Q5DEVM-820 is designed to use a regulated 12-V (8 V to 13 V) bus voltage to provide a regulated 1.2-V output at up to 25 A of load current. The CSD87355Q5DEVM-820 is designed to demonstrate the CSD87355Q5D NexFET Power Block in a typical 12-V bus to low-voltage application, while providing a number of non-invasive test points to evaluate the performance of the CSD87355Q5D NexFET Power Block in a given application. 2 Applications • • • 2.1 Features • • • • • • 3 Synchronous Buck Converters – High-Frequency Applications – High-Current, Low-Duty Cycle Applications Multiphase Synchronous Buck Converters POL DC-DC Converters 8-V to 13-V input voltage rating 1.2-V output voltage 25-A steady state load current 290-kHz switching frequency Simple access to IC features including enable, power good, and switching node Convenient test points for simple, non-invasive measurements of converter performance including input ripple, output ripple, and switching node CSD87355Q5DEVM-820 Electrical Performance Specifications Table 1. CSD87355Q5DEVM-820 Electrical and Performance Specifications PARAMETER NOTES AND CONDITIONS MIN TYP MAX 8 12 13 UNIT INPUT CHARACTERISTICS VIN Input voltage V IIN Input current VIN = 12 V, IOUT = 25 A — 2.8 — A No load input current VIN = 12 V, IOUT = 0 A, MODE = GND — 0.35 — mA Vbias External bias voltage JP1 open, Bias applied on pin 2 of JP1 4.5 5.0 6.5 V Ibias External bias current JP1 open, Bias applied on pin 2 of JP1 15 mA OUTPUT CHARACTERISTICS VOUT Output voltage VIN = 12 V, IOUT = 25 A VOUT_ripple Output voltage ripple VIN = 12 V, IOUT = 25 A, measured across output capacitor C12 IOUT Output current VIN = 8 V to 13 V 1.176 1.2 1.224 — 16 — mVp-p 25 A kHz 0 V SYSTEM CHARACTERISTICS FSW Switching frequency 266 290 314 ηpk Peak efficiency VIN = 12 V — 92.7 — % η Full load efficiency VIN = 12 V, IOUT = 25 A — 91.4 — % SLPU005 – June 2017 Submit Documentation Feedback CSD87355Q5DEVM-820 Copyright © 2017, Texas Instruments Incorporated 3 4 JP2 CSD87355Q5DEVM-820 Copyright © 2017, Texas Instruments Incorporated VIN CCM MODE Auto-Skip JP3 Open=On Short=Off EN GND 1 2 3 GND 1 2 C8 1µF TP3 R3 10.0k 5V R6 1 4 475k NC GND OUT TPS71550DCKR FB/NC IN U2 EN GND 3 2 5 R5 100k 5V C9 1µF 5V BIAS JP1 2 R8 GND 5V 6.98k 5V 61.9k R4 5 2 4 R7 10.0k GND EN 3 7 10 TPS51218DSCR RF TRIP VFB EN V5IN VBST Insert jumper to use onboard LDO Remove jumper to apply user gate drive voltage between 4.5V and 6.5V on pin 2 See user's guide 1 GND VOUT 10µF C2 U1 GND J1 SW GND PGOOD DRVL DRVH 2 1 GND 11 1 6 9 8 TP2 TP1 R9 R1 GND TP5 0 0 C5 10µF 0.1µF C1 GND TP6 GND C4 10µF C6 10µF C7 10µF 5 4 3 C14 1µF 2 1 GND 8 7 6 TP4 L1 440nH C3 2700pF C10 470µF TP8 C11 470µF TP7 C12 470µF 2 1 J2 GND VOUT VOUT Copyright © 2017, Texas Instruments Incorporated GND R2 1.80 Q1 CSD87355Q5D VIN 4 9 VIN 8V-13V CSD87355Q5DEVM-820 Schematic www.ti.com CSD87355Q5DEVM-820 Schematic For reference only. See Section 10 for specific values. Figure 1. CSD87355Q5DEVM-820 Schematic SLPU005 – June 2017 Submit Documentation Feedback Connector, Jumper, and Test Point Descriptions www.ti.com 5 Connector, Jumper, and Test Point Descriptions 5.1 Input Power (J1) 12-V input power connection to the CSD87355Q5DEVM-820. Connect the positive voltage to pin 2 and the return connection to pin 1. See Section 6.1.5 for the appropriate sizing of the wire. 5.2 Output Power (J2) 1.2-V output power connection from the CSD87355Q5DEVM-820. Connect the positive LOAD connection to pin 2 and the return LOAD connection to pin 1. See Section 6.1.5 for the appropriate sizing of the wire. 5.3 5-V Bias Jumper (JP1) The CSD87355Q5DEVM-820 contains an onboard 5-V bias regulator (a TPS71550 linear regulator) to power the TPS51218 controller. This allows the EVM to run off of a single 12-V input source. Insert the shunt in JP1 to use the onboard regulator. Removing the shunt allows the user to apply a different bias voltage to the EVM on pin 2 of JP1. This external bias voltage should be between 4.5 V and 6.5 V and be able to supply 15 mA to properly power the TPS51218. The ground reference of this external source should be TP5. 5.4 Disable Jumper (JP2) The CSD87355Q5DEVM-820 contains a disable jumper header (JP2). Installing the shunt in JP2 shuts down the TPS51218 and disables the power supply. Removing the shunt allows the EN pin on the TPS51218 to be pulled up to 5 V and enables the TPS51218. 5.5 MODE Jumper (JP3) The CSD87355Q5DEVM-820 contains a MODE jumper to select the mode of operation of the TPS51218. Installing the jumper in the 'Auto-Skip' position in JP3 (between pins 2 and 3) connects the RF pin to GND through R6 to increase efficiency at light loads. Installing the shunt in the CCM position in JP3 (between pins 1 and 2) connects the RF pin to PGOOD through R6 in order to maintain a constant switching frequency over the entire load range. 5.6 Test Point Descriptions Table 2. Test Point Description 5.6.1 Test Point Label Use Section TP1 VIN Measurement test point for input voltage Section 5.6.1 TP2 PGND Measurement test point for input voltage return Section 5.6.1 TP3 PGOOD Measurement test point for power good Section 5.6.4 TP4 SW Measurement test point for switch node voltage Section 5.6.3 TP5 AGND Reference test point for PGOOD and return connection for an external bias voltage applied to pin 2 of JP1 Section 5.6.4 TP6 PGND Measurement test point for switch node voltage return Section 5.6.3 TP7 VOUT Measurement test point for output voltage Section 5.6.2 TP8 PGND Measurement test point for output voltage return Section 5.6.2 Input Voltage Monitoring (TP1 and TP2) The CSD87355Q5DEVM-820 provides two test points for measuring the input voltage applied to the module. This allows the user to measure the actual input voltage without losses from input cables and connectors. All input voltage measurements should be made between TP1 and TP2. To use TP1 and TP2, connect a voltmeter positive input to TP1 and negative input to TP2. Tip and barrel measurement technique can be used on TP1 and TP2 to measure the input ripple of the EVM. See Figure 3. SLPU005 – June 2017 Submit Documentation Feedback CSD87355Q5DEVM-820 Copyright © 2017, Texas Instruments Incorporated 5 Test Set Up 5.6.2 www.ti.com Output Voltage Monitoring (TP7 and TP8) The CSD87355Q5DEVM-820 provides two test points for measuring the output voltage generated by the module. This allows the user to measure the actual output voltage without losses from output cables and connectors. All output voltage measurements should be made between TP7 and TP8. To use TP7 and TP8, connect a voltmeter positive input to TP7 and negative input to TP8. Tip and barrel measurement technique should not be used on TP7 and TP8 to measure the output ripple of the EVM, as the probe can pick up substantial radiated noise. It is recommended to measure the output voltage ripple as described in Section 6.4. 5.6.3 Switching Node Monitoring (TP4 and TP6) The CSD87355Q5DEVM-820 provides two test points for measuring the switching node of the module power stage. Tip and barrel measurement technique should be used on TP4 and TP6 to measure the switching node waveform. See Figure 3. 5.6.4 Power Good Voltage Monitoring (TP3 and TP5) The CSD87355Q5DEVM-820 provides a test point, TP3, and a local ground, TP5, for measuring the power good output voltage. A 100-kΩ resistor pull-up to 5 V (R5) is included on the EVM to allow the Power Good signal to be monitored without requiring an external pull-up. TP5 is the ground reference for the power good test point. TP5 also functions as the return connection for an external bias voltage source that may be supplied to pin 2 of JP1. 6 Test Set Up 6.1 Equipment 6.1.1 Voltage Source VIN — The input voltage source (VIN) should be a 0-V to 15-V variable DC source capable of supplying 5 A 6.1.2 Meters A1 — Input current meter. 0-A to 5-A ammeter V1 — Input voltage meter. 0-V to 15-V voltmeter V2 — Output voltage meter. 0-V to 2-V voltmeter 6.1.3 Load LOAD — Output load. Electronic load set for constant current or constant resistance capable of 0 A to 25 A at 1.2 V 6.1.4 Oscilloscope For Output Voltage Ripple — Oscilloscope should be an analog or digital oscilloscope set for AC coupled measurement with 20-MHz bandwidth limiting. Use 20-mV/division vertical resolution and 1-µs/division horizontal resolution. For Switch Node Waveform — Oscilloscope should be an analog or digital oscilloscope set for DC coupled measurement with 20-MHz bandwidth limiting. Use 2-V/division or 5-V/division vertical resolution and 1-µs/division horizontal resolution. 6 CSD87355Q5DEVM-820 SLPU005 – June 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Test Set Up www.ti.com 6.1.5 Recommended Wire Gauge VIN to J1 — The connection between the source voltage (VIN) and J1 of the CSD87355Q5DEVM-820 can carry as much as 5 A of current. The minimum recommended wire size is AWG #16 with the total length of wire less than 2 ft (1-ft input, 1-ft return). J2 to LOAD: — The connection between J2 and the LOAD of the CSD87355Q5DEVM-820 can carry as much as 25 A of current. The minimum recommended wire size is AWG #12 with the total length of wire less than 2 ft (1-ft input, 1-ft return). 6.1.6 Other FAN — The CSD87355Q5DEVM-820 evaluation module includes components that can get hot to the touch when operating. Because this evaluation module is not enclosed to allow probing of circuit nodes, a small fan capable of 200 lfm to 400 lfm is recommended to reduce component temperatures when operating. 6.2 Equipment Setup Shown in Figure 2 is the basic test set up recommended to evaluate the CSD87355Q5DEVM-820. Note that although the return for J1 and J2 are the same ground, the connections should remain separate as shown in Figure 2. 6.2.1 Procedure 1. Working at an ESD workstation, make sure that any wrist straps, bootstraps, or mats are connected referencing the user to earth ground before power is applied to the EVM. Electrostatic smock and safety glasses should also be worn. 2. Prior to connecting the DC input source, VIN, it is advisable to limit the source current from VIN to 5-A maximum. Make sure VIN is initially set to 0 V and connected as shown in Figure 2. 3. Connect VIN to J1 as shown in Figure 2. 4. Connect ammeter A1 between VIN and J1 as shown in Figure 2. 5. Connect voltmeter V1 to TP1 and TP2 as shown in Figure 2. 6. Connect voltmeter V2 to TP7 and TP8 as shown in Figure 2. 7. Connect oscilloscope probes to desired test points per Table 2. 8. Place fan as shown in Figure 2 and turn on making sure to blow air directly across the evaluation module. SLPU005 – June 2017 Submit Documentation Feedback CSD87355Q5DEVM-820 Copyright © 2017, Texas Instruments Incorporated 7 Test Set Up 6.2.2 www.ti.com Test Setup Diagram FAN + DC Load 1.2 V @ 25 A ± Vin + ± + ± V2 V1 ± + Copyright © 2017, Texas Instruments Incorporated Figure 2. CSD87355Q5DEVM-820 Recommended Test Set-Up Figure 3. Tip and Barrel Technique 6.3 Start-Up and Shutdown Procedure 1. 2. 3. 4. 5. 6. 7. 8. 9. 8 Install shunt in JP1 Remove shunt from JP2, if present Verify shunt position of JP3 for desired operating MODE per Section 5.5 Increase VIN from 0 V to 12 V Turn on FAN Vary LOAD from 0 A to 25 A Vary VIN from 8 V to 13 V Decrease LOAD to 0 A Decrease VIN to 0 V CSD87355Q5DEVM-820 SLPU005 – June 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Test Set Up www.ti.com 6.4 Output Ripple Voltage Measurement Procedure 1. Solder a bus wire onto the ground of output capacitor C12 2. Follow Section 6.3 (Start-Up and Shutdown Procedure) steps 1 – 7 to set VIN and LOAD to the desired operating condition 3. Set oscilloscope for output voltage ripple measurement as described in Section 6.1.4 4. Measure output voltage ripple across C12 using the soldered bus wire wrapped around the exposed oscilloscope probe ground barrel 5. Follow Section 6.3 (Start-Up and Shutdown Procedure) steps 8 and 9 to power down 6.5 Equipment Shutdown 1. 2. 3. 4. 7 Shut Shut Shut Shut down down down down oscilloscope LOAD VIN FAN CSD87355Q5DEVM-820 Test Data Figure 4 through Figure 12 present typical performance curves for the CSD87355Q5DEVM-820. Since actual performance data can be affected by measurement techniques and environmental variables, these curves are presented for reference and may differ from actual field measurements. 7.1 Efficiency (Full Load) 100 Efficiency (%) 95 90 85 80 75 CSD87355Q5D 12 Vin CSD87355Q5D 8 Vin 70 0 5 10 15 IO - Output Current (A) 20 25 D001 VIN = 8 V and 12 V, VOUT = 1.2 V, MODE = GND, AUTO-SKIP ON, no airflow Figure 4. CSD87355Q5DEVM-820 Efficiency vs Load Current SLPU005 – June 2017 Submit Documentation Feedback CSD87355Q5DEVM-820 Copyright © 2017, Texas Instruments Incorporated 9 CSD87355Q5DEVM-820 Test Data 7.2 www.ti.com Efficiency (Light Load) 100 Efficiency (%) 95 90 85 80 75 CSD87355Q5D 12 Vin CSD87355Q5D 8 Vin 70 0 0.2 0.4 0.6 IO - Output Current (A) 0.8 1 D002 VIN = 8 V and 12 V, VOUT = 1.2 V, MODE = GND, no airflow Figure 5. CSD87355Q5DEVM-820 Low Load Efficiency vs Load Current 7.3 Output Voltage Ripple VOUT (AC Coupled) 20 mV/div t - Time - 1 ms/div VIN = 12 V, VOUT = 1.2 V, IOUT = 25 A, measured across output capacitor C12 using a bus wire wrapped around exposed oscilloscope probe ground barrel Figure 6. CSD87355Q5DEVM-820 Output Voltage Ripple 10 CSD87355Q5DEVM-820 SLPU005 – June 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated CSD87355Q5DEVM-820 Test Data www.ti.com 7.4 Output Voltage Ripple VOUT (AC Coupled) 20 mV/div t - Time - 1 ms/div VIN = 12 V, VOUT = 1.2 V, IOUT = 25 A, measured at TP7 and TP8 using the tip and barrel measurement technique shown in Figure 3. Since the probe picks up substantial radiated noise, this method is not recommended to measure the output voltage ripple. Figure 7. CSD87355Q5DEVM-820 Output Voltage Ripple 7.5 Input Voltage Ripple VIN (AC Coupled) 200 mV/div SW 10 V/div t - Time - 1 ms/div VIN = 12 V, VOUT = 1.2 V, IOUT = 25 A Figure 8. CSD87355Q5DEVM-820 Input Voltage Ripple SLPU005 – June 2017 Submit Documentation Feedback CSD87355Q5DEVM-820 Copyright © 2017, Texas Instruments Incorporated 11 CSD87355Q5DEVM-820 Test Data 7.6 www.ti.com Load Transient Response VOUT (AC Coupled) 20 mV/div IOUT 10 A/div t - Time - 100 ms/div VIN = 12 V, VOUT = 1.2 V, IOUT = 12.5 A to 25 A, measured across output capacitor C12 using a bus wire wrapped around exposed oscilloscope probe ground barrel Figure 9. CSD87355Q5DEVM-820 Step Response 7.7 Start-Up on VIN VIN 5 V/div VOUT 200 mV/div t - Time - 200 ms/div VIN = 12 V, VOUT = 1.2 V, IOUT = 25 A Figure 10. CSD87355Q5DEVM-820 Start-Up on VIN 12 CSD87355Q5DEVM-820 SLPU005 – June 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated CSD87355Q5DEVM-820 Test Data www.ti.com 7.8 Start-Up on EN EN 5 V/div VOUT 200 mV/div t - Time - 200 ms/div VIN = 12 V, VOUT = 1.2 V, IOUT = 25 A Figure 11. CSD87355Q5DEVM-820 Start-Up on EN 7.9 Thermal Image Copyright © 2017, Texas Instruments Incorporated VIN = 12 V, VOUT = 1.2 V, IOUT = 25 A, no air flow Figure 12. CSD87355Q5DEVM-820 Thermal Image SLPU005 – June 2017 Submit Documentation Feedback CSD87355Q5DEVM-820 Copyright © 2017, Texas Instruments Incorporated 13 CSD87355Q5DEVM-820 Modifications 8 www.ti.com CSD87355Q5DEVM-820 Modifications Several modifications can be made to the CSD87355Q5DEVM-820. Making any of these changes will change the EVM's performance data and may require a modification to the inductor value or current limit trip point (R4 value). The design may also change thermally. Consult the TPS51218 datasheet for details on how to pick R4. 8.1 Switching Frequency The switching frequency of the CSD87355Q5DEVM-820 may be altered by changing the value of R6, per Table 3: Table 3. R6 and Switching Frequency 8.2 R6 Value (kΩ) Switching Frequency (fsw) (kHz) 470 290 200 340 100 380 39 430 Output Voltage The output voltage of the CSD87355Q5DEVM-820 may be changed by changing the value of R8, per Equation 1. ILripple is found from Equation 2. CAUTION The output voltage should not be set higher than 1.9 V or else damage may occur to the EVM. VOUT - (ILripple ´ 2mW) R8 = ILripple 8.3 2 0.7 (V - VOUT ) ´ VOUT = IN L ´ fsw ´ VIN - 0.7 ´ R7 (1) (2) Gate Drive Resistors The gate drive to the high side MOSFET may be slowed by increasing the value of resistors R1 and/or R9. This will slow down the turn on of the high side MOSFET and result in less ringing on the SW node. This will also result in slightly lower efficiency and higher operating temperatures. 9 CSD87355Q5DEVM-820 Assembly Drawings and Layout The following figures (Figure 13 through Figure 17) show the design of the CSD87355Q5DEVM-820 printed circuit board. The EVM has been designed using a 4-layer, 2-oz copper circuit board measuring 3 in × 3 in with all populated components on the top to allow the user to easily view, probe and evaluate the CSD87355Q5D solution. Moving components to both sides of the PCB can offer additional size reduction for space constrained systems. 14 CSD87355Q5DEVM-820 SLPU005 – June 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated CSD87355Q5DEVM-820 Assembly Drawings and Layout www.ti.com Copyright © 2017, Texas Instruments Incorporated Figure 13. CSD87355Q5DEVM-820 Top Component Placement (Top View) Figure 14. CSD87355Q5DEVM-820 Top Copper (Top View) SLPU005 – June 2017 Submit Documentation Feedback CSD87355Q5DEVM-820 Copyright © 2017, Texas Instruments Incorporated 15 CSD87355Q5DEVM-820 Assembly Drawings and Layout www.ti.com Figure 15. CSD87355Q5DEVM-820 Internal Copper Layer 1 (X-Ray Top View) Figure 16. CSD87355Q5DEVM-820 Internal Copper Layer 2 (X-Ray Top View) 16 CSD87355Q5DEVM-820 SLPU005 – June 2017 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated CSD87355Q5DEVM-820 Bill of Materials www.ti.com Figure 17. CSD87355Q5DEVM-820 Bottom Copper (Bottom View) 10 CSD87355Q5DEVM-820 Bill of Materials Table 4. CSD87355Q5DEVM-820 Bill of Materials QTY REFDES VALUE SIZE PART NUMBER 1 C1 0.1 µF Capacitor, Ceramic, 16 V, X7R, 10% DESCRIPTION 0603 Std Std 3 C10, C11, C12 470 µF Capacitor, Polymer Aluminum, 2V, 20% 7343 EEFSX0D471XE Panasonic 1 C2 10 µF Capacitor, Ceramic, 10 V, X5R, 10% 0805 Std Std 1 C3 2700 pF Capacitor, Ceramic, 50 V, X7R, 10% 0603 Std Std 4 C4, C5, C6, C7 10 µF Capacitor, Ceramic, 25 V, X5R, 20% 1206 Std Std 3 C8, C9, C14 1 µF Capacitor, Ceramic, 25 V, X5R, 10% 0603 Std Std 1 L1 0.44 µH 0.510 x 0.530 inch SLC1480-441ML Coilcraft 1 Q1 CSD87355Q5D 2 R1, R9 0 Inductor, SMT Power, 35 A, ±20% MOSFET, Dual N-Chan, 30 V, 45 A MFR QFN-8 POWER CSD87355Q5D TI Resistor, Chip, 1/16 W, 1% 0603 Std Std 1 R2 1.8 Resistor, Metal Film, ½ W, 1% 2010 Std Std 2 R3, R7 10.0 K Resistor, Chip, 1/16 W, 1% 0603 Std Std 1 R4 61.9 K Resistor, Chip, 1/16 W, 1% 0603 Std Std 1 R5 100 K Resistor, Chip, 1/16 W, 1% 0603 Std Std 1 R6 475 K Resistor, Chip, 1/16 W, 1% 0603 Std Std 1 R8 6.98 K Resistor, Chip, 1/16 W, 1% 0603 Std Std 1 U1 TPS51218DSC IC, Single Synchronous Step-Down Controller DSC-10 TPS51218DSC TI TPS71550DCKR IC, High Input Voltage, Micropower, 3.2 µA at 50 mA LDO, 5 V SC70-5 TPS71550DCKR TI 1 U2 SLPU005 – June 2017 Submit Documentation Feedback CSD87355Q5DEVM-820 Copyright © 2017, Texas Instruments Incorporated 17 STANDARD TERMS FOR EVALUATION MODULES 1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms. 1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions set forth herein but rather shall be subject to the applicable terms that accompany such Software 1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned, or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production system. 2 Limited Warranty and Related Remedies/Disclaimers: 2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License Agreement. 2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM. User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10) business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected. 2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day warranty period. 3 Regulatory Notices: 3.1 United States 3.1.1 Notice applicable to EVMs not FCC-Approved: FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter. 3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant: CAUTION This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. FCC Interference Statement for Class A EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. FCC Interference Statement for Class B EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • • • • Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. 3.2 Canada 3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247 Concerning EVMs Including Radio Transmitters: This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Concernant les EVMs avec appareils radio: Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. Concerning EVMs Including Detachable Antennas: Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur 3.3 Japan 3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に 輸入される評価用キット、ボードについては、次のところをご覧ください。 http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified by TI as conforming to Technical Regulations of Radio Law of Japan. If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs (which for the avoidance of doubt are stated strictly for convenience and should be verified by User): 1. 2. 3. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan, Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to EVMs, or Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan. 【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの 措置を取っていただく必要がありますのでご注意ください。 1. 2. 3. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用 いただく。 実験局の免許を取得後ご使用いただく。 技術基準適合証明を取得後ご使用いただく。 なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。 上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ ンスツルメンツ株式会社 東京都新宿区西新宿6丁目24番1号 西新宿三井ビル 3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page 電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/ /www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page 3.4 European Union 3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive): This is a class A product intended for use in environments other than domestic environments that are connected to a low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures. 4 EVM Use Restrictions and Warnings: 4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS. 4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information related to, for example, temperatures and voltages. 4.3 Safety-Related Warnings and Restrictions: 4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or property damage. If there are questions concerning performance ratings and specifications, User should contact a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit components may have elevated case temperatures. These components include but are not limited to linear regulators, switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the information in the associated documentation. When working with the EVM, please be aware that the EVM may become very warm. 4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems, and subsystems. User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees, affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or designees. 4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal, state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local requirements. 5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as accurate, complete, reliable, current, or error-free. 6. Disclaimers: 6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS. 6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED. 7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES, EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED. 8. Limitations on Damages and Liability: 8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS OCCURRED. 8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT. 9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s) will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s), excluding any postage or packaging costs. 10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas, without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas. Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2017, Texas Instruments Incorporated IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you (individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of this Notice. TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications (and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, you will thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. 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