D24051QM96G4Q1

CD74HCT4051-Q1 HIGH-SPEED CMOS LOGIC ANALOG MULTIPLEXER/DEMULTIPLEXER SCLS569B − JANUARY 2004 − REVISED APRIL 2008 D Qualified for Automotive Applications D Wide Analog Input Voltage Range: D D D D D +5 V Max Low ON Resistance − 70 W Typical (VCC − VEE = 4.5 V) − 40 W Typical (VCC − VEE = 9 V) D Operation Control Voltage: 4.5 V to 5.5 V D Switch Voltage: 0 V to 10 V D Direct LSTTL Input Logic Compatibility: D Low Crosstalk Between Switches Fast Switching and Propagation Speeds Break-Before-Make Switching Wide Operating Temperature Range: −405C to 1255C description/ordering information This device is a digitally controlled analog switch that utilizes silicon-gate CMOS technology to achieve operating speeds similar to LSTTL, with the low power consumption of standard CMOS integrated circuits. VIL = 0.8 V Max, VIH = 2 V Min CMOS Input Compatibility: II v 1 mA at VOL, VOH M PACKAGE (TOP VIEW) A4 A6 COM OUT/IN A A7 A5 E VEE GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC A2 A1 A0 A3 S0 S1 S2 This analog multiplexer/demultiplexer controls analog voltages that may vary across the voltage supply range (i.e., VCC to VEE ). It is a bidirectional switch that allows any analog input to be used as an output and vice-versa. The switch has low ON resistance and low OFF leakages. In addition, this device has an enable control that, when high, disables all switches to their OFF state. ORDERING INFORMATION{ PACKAGE‡ TA −40°C to 125°C SOIC − M Reel of 2500 ORDERABLE PART NUMBER§ CD74HCT4051QM96Q1 TOP-SIDE MARKING HCT4051Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. § The suffix 96 denotes tape and reel. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD74HCT4051-Q1 HIGH-SPEED CMOS LOGIC ANALOG MULTIPLEXER/DEMULTIPLEXER SCLS569B − JANUARY 2004 − REVISED APRIL 2008 FUNCTION TABLE INPUTS ON CHANNELS ENABLE S2 S1 L L L L A0 L L L H A1 L L H L A2 L L H H A3 L H L L A4 L H L H A5 L H H L A6 L H H H A7 H X X X None S0 X = Don’t care logic diagram (positive logic) Channel In/Out VCC A6 A7 16 4 2 A5 5 A4 1 A3 A2 A1 A0 12 15 14 13 TG TG S0 11 Address Select TG S1 10 Logic Level Conversion S2 TG Binary to 1 of 8 Decoder With Enable 9 3 TG TG TG E 8 TG 8 GND 2 7 VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 COM OUT/IN A CD74HCT4051-Q1 HIGH-SPEED CMOS LOGIC ANALOG MULTIPLEXER/DEMULTIPLEXER SCLS569B − JANUARY 2004 − REVISED APRIL 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range: VCC − VEE (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 10.5 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to +7 V VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to −7 V Input clamp current, IIK (VI < −0.5 V or VI > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < VEE − 0.5 V or VO > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Switch current (VI > VEE − 0.5 V or VI < VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA VEE current, IEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (during soldering): At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 300°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages referenced to GND unless otherwise specified. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC Supply voltage MIN MAX UNIT 4.5 5.5 V Supply voltage, VCC − VEE (see Figure 1) 2 10 V VEE Supply voltage (see Note 4 and Figure 2) 0 −6 V VIH High-level input voltage 2 VIL Low-level input voltage VI Input control voltage VIS Analog switch I/O voltage tt Input transition (rise and fall) time TA Operating free-air temperature VCC = 4.5 V V 0.8 V 0 VCC V VEE VCC V 0 500 ns −40 125 °C NOTES: 3. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4. In certain applications, the external load resistor current may include both VCC and signal-line components. To avoid drawing VCC current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6 V (calculated from ron values shown in electrical characteristics table). No VCC current flows through RL if the switch current flows into the COM OUT/IN A terminal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CD74HCT4051-Q1 HIGH-SPEED CMOS LOGIC ANALOG MULTIPLEXER/DEMULTIPLEXER SCLS569B − JANUARY 2004 − REVISED APRIL 2008 recommended operating area as a function of supply voltages 8 (VCC – GND) – V (VCC – GND) – V 8 6 HCT HC 4 2 6 HCT HC 4 2 0 0 0 2 4 6 8 10 0 12 −2 (VCC – VEE) – V −4 −6 −8 (VEE – GND) – V Figure 2 Figure 1 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VEE MIN ron VIS = VCC or VEE IO = 1 mA, VI = VIH or VIL, See Figure 9 VIS = VCC to VEE ∆ron Between any two channels IIZ For switch OFF: When VIS = VCC, VOS = VEE; When VIS = VEE, VOS = VCC For switch ON: All applicable combinations of VIS and VOS voltage levels, VI = VIH or VIL IIL ICC ∆ICC VI = VCC or GND IO = 0, VI = VCC or GND TYP MAX 4.5 V 70 160 240 4.5 V 40 120 180 0V 4.5 V 90 180 270 −4.5 V 4.5 V 45 130 195 0V 4.5 V 10 −4.5 V 4.5 V 5 0V 6V Ω Ω ±0.2 ±2 A µA −5 V 5V ±0.4 ±4 5.5 V ±0.1 ±1 When VIS = VEE, VOS = VCC 0V 5.5 V 8 160 When VIS = VCC, VOS = VEE −4.5 V 5.5 V 16 320 360 490 µA A µA 4.5 V to 5.5 V HCT input loading TYPE INPUT UNIT LOADS† 4051 All 0.5 Unit load is ∆ICC limit specified in the electrical characteristics table, e.g., 360 µA max at 25°C. POST OFFICE BOX 655303 UNIT MAX 0V 100 NOTE 5: For dual-supply systems, theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. 4 MIN −4.5 V Control input Per input pin: 1 unit load, See Note 5, VIN = VCC − 2.1 V † TA = −40°C TO 125°C TA = 25°C VCC • DALLAS, TEXAS 75265 µA CD74HCT4051-Q1 HIGH-SPEED CMOS LOGIC ANALOG MULTIPLEXER/DEMULTIPLEXER SCLS569B − JANUARY 2004 − REVISED APRIL 2008 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 8) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE VEE MIN CL = 15 pF tpd IN OUT 5V S or E OUT CI S or E OUT MAX MIN UNIT MAX 4 0V 4.5 V 12 18 CL = 50 pF −4.5 V 4.5 V 8 12 5V 0V 4.5 V 55 83 CL = 50 pF −4.5 V 4.5 V 39 59 5V ns 23 CL = 50 pF CL = 15 pF tdis TYP CL = 50 pF CL = 15 pF ten TA = −40°C TO 125°C TA = 25°C VCC ns 19 CL = 50 pF 0V 4.5 V 45 68 CL = 50 pF −4.5 V 4.5 V 32 48 10 10 Control ns pF operating characteristics, VCC = 5 V, TA = 25°C, input tr, tf = 6 ns PARAMETER Cpd TYP Power dissipation capacitance (see Note 6) 52 UNIT pF NOTE 6: Cpd is used to determine the dynamic power consumption (PD), per package. PD = (Cpd × VCC2 × fI) + Σ (CL + CS) VCC2 × fO fO = output frequency fI = input frequency CL = output load capacitance CS = switch capacitance VCC = supply voltage analog channel characteristics, TA = 25°C PARAMETER TEST CONDITIONS CI Switch input capacitance CCOM Common output capacitance fmax Minimum switch frequency response at −3 dB See Figure 3 and Figure 10 and Notes 7 and 8 Sine wave distortion Sine-wave See Figure 5 E or address select (S0, S1, S2) to switch feedthrough noise See Figure 6 and Notes 8 and 9 Switch OFF signal feedthrough See Figure 7 and Figure 11 and Notes 8 and 9 VEE VCC TYP UNIT 5 pF 25 pF −2.25 V 2.25 V 145 −4.5 V 4.5 V 180 −2.25 V 2.25 V 0.035 −4.5 V 4.5 V 0.018 −2.25 V 2.25 V TBE −4.5 V 4.5 V TBE −2.25 V 2.25 V −73 −4.5 V 4.5 V −75 MHz % mV dB NOTES: 7. Adjust input voltage to obtain 0 dBm at VOS for fIN = 1 MHz. 8. VIS is centered at (VCC − VEE)/2. 9. Adjust input for 0 dBm. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CD74HCT4051-Q1 HIGH-SPEED CMOS LOGIC ANALOG MULTIPLEXER/DEMULTIPLEXER SCLS569B − JANUARY 2004 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION VCC VIS R SWITCH ON VOS1 0.1 mF INPUT R fIS = 1-MHz Sine Wave R = 50 W C = 10 pF VCC/2 VCC VCC R VOS SWITCH ON VIS C 0.1 mF 50 Ω dB METER 10 pF VOS2 SWITCH OFF VCC/2 dB METER C R VCC/2 VCC/2 Figure 4. Crosstalk Between Two Switches Test Circuit Figure 3. Frequency-Response Test Circuit E VCC V P−P VCC V OS Sine Wave VIS SWITCH ON VOS 10 mF 10k Ω 50 pF SWITCH ALTERNATING ON AND OFF tr, tf ≤ 6 ns fCONT = 1 MHz 50% DUTY CYCLE 600 Ω VIS VI = VIH VCC/2 DISTORTION METER V OS 600 Ω 50 pF SCOPE VCC/2 VCC/2 fIS = 1 kHz to 10 kHz Figure 5. Sine-Wave Distortion Test Circuit Figure 6. Control-to-Switch Feedthrough Noise Test Circuit fIS ≥ 1-MHz Sine Wave R = 50 Ω C = 10 pF VCC 0.1 µF SWITCH V IS VC = VIL V OS OFF dB R R VCC/2 VCC/2 C METER Figure 7. Switch OFF Signal Feedthrough Test Circuit 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD74HCT4051-Q1 HIGH-SPEED CMOS LOGIC ANALOG MULTIPLEXER/DEMULTIPLEXER SCLS569B − JANUARY 2004 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test PARAMETER S1 ten RL = 1 kΩ tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd VEE LOAD CIRCUIT VCC Input 50% VCC 50% VCC VEE tPLH In-Phase Output 50% 10% 90% tPHL 90% 1.3 V 1.3 V 0V tPHL 90% tr Out-of-Phase Output 3V Output Control tPZL VOH 50% VCC 10% VOL tf 50% VCC 10% tf 50% 10% 90% tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% VCC tPZH VOH VOL ≈VCC Output Waveform 1 (see Note B) tPLH tPLZ Output Waveform 2 (see Note B) 10% VOL tPHZ 50% VCC 90% VOH ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 8. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 CD74HCT4051-Q1 HIGH-SPEED CMOS LOGIC ANALOG MULTIPLEXER/DEMULTIPLEXER SCLS569B − JANUARY 2004 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS 120 ON Resistance − Ω 100 80 VCC − VEE = 4.5 V 60 VCC − VEE = 6 V 40 VCC − VEE = 9 V 20 1 2 3 4 5 6 7 8 9 Input Signal Voltage − V Figure 9. Typical ON Resistance vs Input Signal Voltage 0 0 VCC = 4.5 V GND = −4.5 V VEE = −4.5 V RL = 50 Ω Pin 12 to 3 −4 −20 −40 dB VCC = 2.25 V GND = −2.25 V VEE = −2.25 V RL = 50 Ω Pin 12 to 3 −6 −60 VCC = 4.5 V GND = −4.5 V VEE = −4.5 V RL = 50 Ω Pin 12 to 3 −80 −8 −10 10K VCC = 2.25 V GND = −2.25 V VEE = −2.25 V RL = 50 Ω Pin 12 to 3 dB −2 100K 1M 10M 100M −100 10K 100K Frequency − Hz 10M 100M Frequency − Hz Figure 10. Channel ON Bandwidth 8 1M POST OFFICE BOX 655303 Figure 11. Channel OFF Feedthrough • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CD74HCT4051QM96Q1 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCT4051Q D24051QM96G4Q1 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCT4051Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of