D24066QM96G4Q1

CD74HCT4066-Q1 HIGH-SPEED CMOS LOGIC QUAD BILATERAL SWITCH SCLS581B − APRIL 2004 − REVISED APRIL 2008 D Qualified for Automotive Applications D Low ON Resistance D D D D Direct LSTTL Input Logic Compatibility: VIL = 0.8 V Max, VIH = 2 V Min − 25 W Typical (VCC = 4.5 V) Fast Switching and Propagation Speeds Low OFF Leakage Current Wide Operating Temperature Range: −405C to 1255C D CMOS Input Compatibility: II v 1 mA at VOL, VOH M OR PW PACKAGE (TOP VIEW) 1Y 1Z 2Z 2Y 2E 3E GND description/ordering information The CD74HCT4066 contains four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operation speeds similar to LSTTL, with the low power consumption of standard CMOS integrated circuits. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1E 4E 4Y 4Z 3Z 3Y These switches feature the characteristic linear ON resistance of the metal-gate CD4066B. Each switch is turned on by a high-level voltage on its control input. ORDERING INFORMATION{ PACKAGE‡ TA −40°C 40°C to 125°C ORDERABLE PART NUMBER§ TOP-SIDE MARKING SOIC − M Reel of 2500 CD74HCT4066QM96Q1 HCT4066Q TSSOP − PW Reel of 2000 CD74HCT4066QPWRQ1 HK4066Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. § The suffix 96 denotes tape and reel. FUNCTION TABLE INPUT nE SWITCH L Off H On H = High level L = Low level Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD74HCT4066-Q1 HIGH-SPEED CMOS LOGIC QUAD BILATERAL SWITCH SCLS581B − APRIL 2004 − REVISED APRIL 2008 logic diagram (positive logic) nY p n p nZ n nE absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to +7 V Input clamp current, IIK (VI < −0.5 V or VI > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < −0.5 V or VO > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Switch current, IO (see Note 2) (VO > −0.5 V or VO < VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Output source or sink current per output pin, IO (VO > −0.5 V or VO < VCC + 0.5 V) . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages referenced to GND unless otherwise specified. 2. In certain applications, the external load-resistor current may include both VCC and signal-line components. To avoid drawing VCC current when switch current flows into the transmission gate inputs (terminals 1, 4, 8, and 11), the voltage drop across the bidirectional switch must not exceed 0.6 V (calculated from ron values shown in the electrical characteristics table). No VCC current flows through RL if the switch current flows into terminals 2, 3, 9, and 10. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD74HCT4066-Q1 HIGH-SPEED CMOS LOGIC QUAD BILATERAL SWITCH SCLS581B − APRIL 2004 − REVISED APRIL 2008 recommended operating conditions (see Note 4) VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage tt Input transition (rise and fall) time TA Operating free-air temperature MIN MAX 4.5 5.5 2 VCC = 4.5 V UNIT V V 0.8 V 0 VCC V 0 VCC V 0 500 ns −40 125 °C NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VI TA = −40°C TO 125°C TA = 25°C VCC MIN TYP MAX MIN UNIT MAX VCC or GND 5.5 V ±0.1 ±1 µA VIL 5.5 V ±0.1 ±1 µA VIS = VCC or GND VCC 4.5 V 25 80 128 VIS = VCC to GND VCC 4.5 V 35 95 142 VCC 4.5 V 1 VCC or GND 5.5 V VCC − 2.1 V 4.5 V to 5.5 V IIL Any control IIZ VIS = VCC or GND ron IO = 1 mA, See Figure 7 ∆ron Between any two switches ICC ∆ICC Per input pin: 1 unit load, See Note 5 CI Control inputs 100 Ω Ω 2 40 µA 360 490 µA 10 10 pF NOTE 5: For dual-supply systems, theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. HCT input loading † INPUT UNIT LOADS† All 1 Unit load is ∆ICC limit specified in the electrical characteristics table, e.g., 360 µA max at 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CD74HCT4066-Q1 HIGH-SPEED CMOS LOGIC QUAD BILATERAL SWITCH SCLS581B − APRIL 2004 − REVISED APRIL 2008 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6) FROM (INPUT) TO (OUTPUT) tpd Y or Z Z or Y ten E Y or Z tdis E Y or Z PARAMETER LOAD CAPACITANCE VCC CL = 15 pF 5V CL = 50 pF 4.5 V MIN CL = 15 pF 5V CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V TA = −40°C TO 125°C TA = 25°C TYP MAX MIN UNIT MAX 4 12 18 24 36 35 53 ns 9 14 ns ns operating characteristics, VCC = 5 V, TA = 25°C, input tr, tf = 6 ns PARAMETER Cpd TYP Power dissipation capacitance (see Note 6) 38 UNIT pF NOTE 6: Cpd is used to determine the dynamic power consumption (PD), per package. PD = (Cpd × VCC2 × fI) + Σ (CL + CS) × VCC2 × fO fO = output frequency fI = input frequency CL = output load capacitance CS = switch capacitance VCC = supply voltage analog channel characteristics, TA = 25°C PARAMETER fmax CS VCC TYP UNIT Switch frequency response bandwidth at −3 dB See Figure 2 and Figure 8 and Notes 7 and 8 TEST CONDITIONS 4.5 V 200 MHz Crosstalk between any two switches See Figure 1 and Figure 9 and Notes 8 and 9 4.5 V −72 dB Total harmonic distortion See Figure 3, 1 kHz, VIS = 4 VP-P 4.5 V 0.023 % Control to switch feedthrough noise See Figure 4 4.5 V 130 mV Switch OFF signal feedthrough See Figure 5 and Figure 9 and Notes 8 and 9 4.5 V −72 dB 5 pF Switch input capacitance NOTES: 7. Adjust input voltage to obtain 0 dBm at output, f = 1 MHz. 8. VIS is centered at VCC/2. 9. Adjust input for 0 dBm at VIS. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD74HCT4066-Q1 HIGH-SPEED CMOS LOGIC QUAD BILATERAL SWITCH SCLS581B − APRIL 2004 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION VCC VCC VIS R INPUT R SWITCH ON 0.1 mF fIS = 1-MHz Sine Wave R = 50 W C = 10 pF VCC/2 C R VOS2 SWITCH OFF VOS1 dB METER C R VCC/2 VCC/2 Figure 1. Crosstalk Between Two Switches Test Circuit VCC VCC VIS VI = VIH VOS SWITCH ON VIS Sine Wave VIS 0.1 mF 50 Ω 10 pF SWITCH ON VOS 10 mF 10k Ω dB METER 50 pF DISTORTION METER VCC/2 fIS = 1 kHz to 10 kHz VCC/2 Figure 2. Frequency-Response Test Circuit Figure 3. Total Harmonic Distortion Test Circuit E VCC V OS 600 Ω VCC/2 SWITCH ALTERNATING ON AND OFF tr, tf ≤ 6 ns fCONT = 1 MHz 50% DUTY CYCLE fIS ≥ 1-MHz Sine Wave R = 50 Ω C = 10 pF V P−P VCC 0.1 µF V OS SWITCH V IS 600 Ω VC = V IL V OS OFF 50 pF SCOPE dB R R VCC/2 VCC/2 C METER VCC/2 Figure 4. Control-to-Switch Feedthrough Noise Test Circuit POST OFFICE BOX 655303 Figure 5. Switch OFF Signal Feedthrough Test Circuit • DALLAS, TEXAS 75265 5 CD74HCT4066-Q1 HIGH-SPEED CMOS LOGIC QUAD BILATERAL SWITCH SCLS581B − APRIL 2004 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test PARAMETER S1 ten RL = 1 kΩ tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd LOAD CIRCUIT 3V Input 1.3 V 1.3 V 0V tPLH In-Phase Output 1.3 V 10% 90% tPHL 90% 1.3 V 1.3 V 0V tPHL 90% tr Out-of-Phase Output 3V Output Control tPZL VOH 1.3 V 10% VOL tf 1.3 V 10% tf 1.3 V 10% 90% tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 1.3 V tPZH VOH VOL ≈VCC Output Waveform 1 (see Note B) tPLH tPLZ Output Waveform 2 (see Note B) 10% VOL tPHZ 1.3 V 90% VOH ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 6. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD74HCT4066-Q1 HIGH-SPEED CMOS LOGIC QUAD BILATERAL SWITCH SCLS581B − APRIL 2004 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS 40 VCC = 4.5 V, PIN 1 TO 2 30 20 10 0 1 2 3 4 4.5 5 6 Input Signal Voltage − V 7 8 0 −20 0 −1 −2 CL = 10 pF VCC = 4.5 V RL = 50 Ω TA = 255C Pin 4 to 3 −3 −4 104 9 105 106 107 Frequency − Hz 108 Figure 8. Switch Frequency Response, VCC = 4.5 V Figure 7. Typical ON Resistance vs Input Signal Voltage Crosstalk − dB Switch-Off Signal Feedthrough − dB ON Resistance − Ω 50 1 TA = 255C GND = 0 V Channel-ON Bandwidth − dB 60 CL = 10 pF VCC = 4.5 V RL = 50 Ω TA = 255C Pin 4 to 3 −40 −60 −80 −100 104 105 106 107 108 f − Frequency − Hz Figure 9. Switch-OFF Signal Feedthrough and Crosstalk vs Frequency, VCC = 4.5 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 21-Apr-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CD74HCT4066QM96Q1 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCT4066Q CD74HCT4066QPWRQ1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HK4066Q D24066QM96G4Q1 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HCT4066Q HCT4066QPWRG4Q1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HK4066Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of