DP83867ERGZR

DP83867CS, DP83867IS, DP83867E SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver 1 Features 3 Description • • • • • • • • The DP83867 device is a robust, low power, fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX and 1000BASE-T Ethernet protocols. Optimized for ESD protection, the DP83867 exceeds 8-kV IEC 61000-4-2 (direct contact). • • • • • • • • • • Extra low latency TX < 90 ns, RX < 290 ns Time Sensitive Network (TSN) compliant Low power consumption: 457 mW Exceeds 8000 V IEC 61000-4-2 ESD protection Meets EN55011 class B emission standards 16 programmable RGMII delay modes on RX/TX Integrated MDI termination resistors Programmable MAC interface termination impedance WoL (Wake-on-LAN) packet detection 25-MHz or 125-MHz synchronized clock output Start of Frame Detect for IEEE 1588 time stamp RJ45 mirror mode Fully compatible to IEEE 802.3 10BASE-Te, 100BASE-TX, and 1000BASE-T Specification Cable diagnostics RGMII and SGMII MAC interface options Configurable I/O voltage (3.3 V, 2.5 V, 1.8 V) Fast link drop mode JTAG support 2 Applications • • • • • • • The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet LANs. It interfaces directly to twisted pair media through an external transformer. This device interfaces directly to the MAC layer through Reduced GMII (RGMII) or embedded clock Serial GMII (SGMII). The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has low latency and provides IEEE 1588 Start of Frame Detection. Designed for low power, the DP83867 consumes only 457 mW under full operating power. Wake-on-LAN can be used to lower system power consumption. Device Information Motor drives Industrial factory automation Field Bus Support Industrial embedded computing Wired and wireless communications infrastructure Test and measurement Consumer electronics PART NUMBER TEMPERATURE (1) BODY SIZE (NOM) DP83867CSRGZ 0°C to +70°C VQFN (48) 7 mm × 7 mm DP83867ISRGZ –40°C to +85°C VQFN (48) 7 mm × 7 mm DP83867ERGZ –40°C to +105°C VQFN (48) 7 mm × 7 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 10BASE-Te 100BASE-TX 1000BASE-T RGMII SGMII Ethernet MAC PACKAGE DP83867 10/100/1000 Mbps Ethernet Physical Layer 25 MHz Crystal or Oscillator Magnetics RJ-45 Status LEDs An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison......................................................... 5 6 Pin Configuration and Functions...................................5 6.1 Pin Functions.............................................................. 6 6.2 Unused Pins................................................................9 7 Specifications................................................................ 10 7.1 Absolute Maximum Ratings...................................... 10 7.2 ESD Ratings............................................................. 10 7.3 Recommended Operating Conditions....................... 11 7.4 Thermal Information.................................................. 11 7.5 Electrical Characteristics...........................................11 7.6 Power-Up Timing...................................................... 13 7.7 Reset Timing............................................................. 14 7.8 MII Serial Management Timing................................. 14 7.9 SGMII Timing............................................................ 14 7.10 RGMII Timing.......................................................... 14 7.11 DP83867E Start of Frame Detection Timing........... 15 7.12 DP83867IS/CS Start of Frame Detection Timing....15 7.13 Timing Diagrams .................................................... 16 7.14 Typical Characteristics............................................ 19 8 Detailed Description......................................................20 8.1 Overview................................................................... 20 8.2 Functional Block Diagram......................................... 21 8.3 Feature Description...................................................22 8.4 Device Functional Modes..........................................25 8.5 Programming............................................................ 38 8.6 Register Maps...........................................................45 9 Application and Implementation................................ 103 9.1 Application Information........................................... 103 9.2 Typical Application.................................................. 103 10 Power Supply Recommendations............................110 11 Layout......................................................................... 113 11.1 Layout Guidelines..................................................113 11.2 Layout Example.....................................................115 12 Device and Documentation Support........................116 12.1 Documentation Support........................................ 116 12.2 Related Links........................................................ 116 12.3 Receiving Notification of Documentation Updates 116 12.4 Support Resources............................................... 116 12.5 Electrostatic Discharge Caution............................ 116 12.6 Glossary................................................................ 116 12.7 Trademarks........................................................... 116 4 Revision History Changes from Revision C (October 2019) to Revision D (November 2022) Page • Updated Start of Frame Detect for IEEE 1588 time stamp.................................................................................1 • Updated Electrical Characteristics.................................................................................................................... 11 • Added Phy has internal 100 Ohm differential termination in Section 8.4.1.1 ...................................................25 • Added following wording to the end of first paragraph in Section 8.4.3.9 "DP83867 devices manufactured after August, 2022, have an increased random seed value that now includes 255 different seed values to expedite Auto-MDIX resolution with a link partner."..........................................................................................33 • Changed Bit 11:10 SPEED_OPT_ATTEMPT_CNT to RW description in ........................................................65 • Changed bits 15:9, so that bit 12 can be '1'. Bit 7 description updated Section 8.6.31 ................................... 76 • Added Register 0x008A....................................................................................................................................82 • Added Register 0x00B3....................................................................................................................................83 • Added Register 0x00C0....................................................................................................................................83 • Added Register 0x0100.................................................................................................................................... 85 Changes from Revision B (March 2017) to Revision C (October 2019) Page • Added "Time Sensitive Network (TSN) Compliant" to Section 1 ....................................................................... 1 • Changed "Fast Link up / Link Drop Modes" to "Fast Link Drop Mode" in Section 1 .......................................... 1 • Added "Field Bus Support" to Section 2 ............................................................................................................ 1 • Deleted "NOTE: Internal pullup and pulldown resistors on the IO pins are disabled when the device enters functional mode after power up." from Pin Functions......................................................................................... 6 • Added XI pin voltage ratings to Section 7.1 .....................................................................................................10 • Added XI Input Voltage section to Section 7.5 .................................................................................................11 • Added SGMII Latency nominal values to Section 7.9 ......................................................................................14 • Changed links to RGMII timing diagrams in Section 7.10 ............................................................................... 14 • Changed TholdR parameter description in Section 7.10 ................................................................................... 14 • Added table note explaining how Duty Cycle % must be interpreted in Section 7.10 ..................................... 14 • Added table note explaining how Duty Cycle % must be interpreted in Section 7.10 ..................................... 14 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 Added RGMII TX and RX Latency values in Section 7.10 ...............................................................................14 Changed suggestion to program '10M_SGMII_RATE_ADAPT' bit in Section 8.4.1.1 ..................................... 25 Changed statement about PHY address in Section 8.4.2 ............................................................................... 28 Deleted mentions of pin strapping to configure Auto-MDIX in Section 8.4.3.9 ................................................ 33 Added Figure 8-9 ............................................................................................................................................. 33 Deleted "The BIST allows full control of the packet lengths and of the IPG." from Section 8.4.5 ....................35 Deleted mention of ALCD from Section 8.4.6 ..................................................................................................35 Deleted subsection describing ALCD from Section 8.4.6 ................................................................................ 35 Added sentence about the polarity of MDI signals in Section 8.4.6.5 ..............................................................36 Changed note after Table 8-5 to be a table note referenced within the table. ................................................. 38 Changed 'MMD3_PCS_CTRL' address to 'MMD3' register 0x0000 in Section 8.5.5.5 ................................... 44 Deleted mention of MMD7 in Section 8.5.5.5 .................................................................................................. 44 Added definition for register Bit Name type 'Strap' in Section 8.6 ................................................................... 45 Deleted Advanced Link Cable Diagnostics Control Register (ALCD_CTRL) .................................................. 45 Added PAP package default for '1000BASE-T FULL DUPLEX' in Section 8.6.10 ...........................................55 Changed 'SGMII_EN' default in Section 8.6.14 ............................................................................................... 58 Changed 'MDI_CROSSOVER' default in Section 8.6.14 .................................................................................58 Added PAP package default for 'SPEED_OPT_EN' in Section 8.6.18 ............................................................ 65 Added Section 8.6.28 ...................................................................................................................................... 74 Changed descriptions of bits 'FORCE_DROP' and 'FLD_EN' in Section 8.6.29 ............................................. 75 Added Section 8.6.30 ...................................................................................................................................... 76 Added 'INT_TST_MODE_1' to Section 8.6.31 .................................................................................................76 Changed 'PORT_MIRROR_EN' default in Section 8.6.31 ...............................................................................76 Added PAP package default for 'RGMII_EN' in Section 8.6.32 ....................................................................... 76 Added Section 8.6.36 ...................................................................................................................................... 79 Changed description of 'STRAP_FLD' from "Fast Link Detect" to "Fast Link Drop" in Section 8.6.39 ............ 81 Added Section 8.6.42 ...................................................................................................................................... 82 Added Section 8.6.43 ...................................................................................................................................... 82 Changed 'RGMII_TX_DELAY_CTRL' default value in Section 8.6.45 .............................................................83 Changed 'RGMII_RX_DELAY_CTRL' default value in Section 8.6.45 ............................................................ 83 Added Section 8.6.48 ...................................................................................................................................... 83 Added Section 8.6.53 ...................................................................................................................................... 85 Changed description of '10M_SGMIII_RATE_ADAPT' in Section 8.6.99 ........................................................ 93 Added GPIO_MUX_CTRL register for RGZ devices........................................................................................ 95 Added TDR registers 0x0190 to 0x01A4.......................................................................................................... 96 Added TDR registers........................................................................................................................................ 96 Added Section 8.6.124 .................................................................................................................................. 101 Changed 'PCS_RESET' description in Section 8.6.125 ................................................................................ 101 Changed capacitor value in Figure 9-2 and added footnotes......................................................................... 104 Added requirements for 2.5-V clock source capacitors in Section 9.2.1.2 .................................................... 106 Added Figure 9-4 ........................................................................................................................................... 106 Added "RMS Jitter" to Table 9-2 .................................................................................................................... 106 Added Section 9.2.1.4 ................................................................................................................................... 108 Changed capacitor placement in Figure 10-1 and footnote about decoupling capacitor placement.............. 110 Changed capacitor placement in Figure 10-2 and footnote about decoupling capacitor placement.............. 110 Changes from Revision A (February 2017) to Revision B (March 2017) Page • Changed pin 6 name in the pinout diagram from: VDDA1P0 to: VDD1P0......................................................... 5 • Changed INT / PWDN Interrupt description........................................................................................................6 • Changed RESERVED bit number from: 15:8 to: 15:9 ..................................................................................... 76 • Changed RESERVED bit number from: 7 to: 8:7 ............................................................................................ 76 • Changed the default and description of the CLK_O_DISABLE bit (bit 6)......................................................... 93 • Clarified Figure 9-2 ........................................................................................................................................ 104 • Changed text in MDI traces bullet from: or to: and......................................................................................... 109 Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E Submit Document Feedback 3 DP83867CS, DP83867IS, DP83867E SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 www.ti.com Changes from Revision * (October 2015) to Revision A (February 2017) Page • Updated data sheet text to the latest documentation and translations standards.............................................. 1 • Added storage temperature to Section 7.1 ...................................................................................................... 10 • Updated parameter symbol from VIH to VIH .................................................................................................... 11 • Added MDC toggling clarification to Section 7.7 ..............................................................................................14 • Added Section 7.11 ..........................................................................................................................................15 • Added DP83867IS/CS Start of Frame Detection Timing.................................................................................. 15 • Added section Section 8.3.2.1 ......................................................................................................................... 24 • Changed target strap voltage thresholds Table 8-4 ......................................................................................... 38 • Changed values for RX_CTRL pin for modes 1 and 2 to N/A in Table 8-5 ......................................................38 • Changed strap name SPEED_SEL to ANEG_SEL in Table 8-5 ......................................................................38 • Changed table name Speed Select Strap Details to Auto-Negotiation Select Strap Details in Table 8-6 ....... 38 • Changed strap option SPEED_SEL to ANEG_SEL in Table 8-6 .....................................................................38 • Changed mode 5 RGMII Clock Skew value from 4.0 ns to 0 ns in Table 8-7 .................................................. 38 • Changed strap control of Speed Select bit 13 in Table 8-9 ..............................................................................45 • Changed strap control of Speed Select bit 6 in Table 8-9 ................................................................................45 • Changed bit 9 name from 100BASE-T FULL DUPLEX to 1000BASE-T FULL DUPLEX in Table 8-18 .......... 55 • Changed bit 9 descriptions from half duplex to full duplex in Table 8-18 .........................................................55 • Changed 'Interrupt Status and Event Control Register (ISR)' to 'MII Interrupt Control Register (MICR)' in Section 8.6.16 ..................................................................................................................................................61 • Changed Register definition to move a statement from Section 8.6.17 to Section 8.6.16 ...............................61 • Changed default of bit 9 from '1' to '0' in Table 8-27 ........................................................................................ 65 • Changed default of bits 5:0 from '0' to '0 0111' in Table 8-27 ...........................................................................65 • Added Section 8.6.29 register.......................................................................................................................... 75 • Added Section 8.6.37 register.......................................................................................................................... 79 • Changed SPEED_SEL strap bit name to ANEG_SEL in Strap Configuration Status Register 1 (STRAP_STS1), Address 0x006E.................................................................................................................... 80 • Changed name of Bit 6:4 from 'STRAP_GMII_CLK_SKEW_TX' to 'STRAP_RGMII_CLK_SKEW_TX' in Table 8-48 ..................................................................................................................................................................81 • Changed name of Bit 6:4 from 'STRAP_GMII_CLK_SKEW_RX' to 'STRAP_RGMII_CLK_SKEW_RX' in Table 8-48 ..................................................................................................................................................................81 • Added Section 8.6.50 register.......................................................................................................................... 85 • Changed default of bits 12:8 to 0 1100 in Table 8-109 .................................................................................... 93 • Changed description for IO_IMPEDANCE_CTRL bits in Section 8.6.100 .......................................................93 • Changed Section 10 section........................................................................................................................... 110 • Added power down supply sequence sentence in Section 10 .......................................................................110 • Added Figure 10-3 ......................................................................................................................................... 110 • Added Table 10-1 ...........................................................................................................................................110 • Added note regarding 1.8-V supply sequence if no load exists on 2.5-V supply in Layout ........................... 110 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 5 Device Comparison Table 5-1. Device Features Comparison DEVICE MAC DP83867CSRGZ SGMII/RGMII TEMPERATURE RANGE 0°C TEMPERATURE GRADE DP83867ISRGZ SGMII/RGMII –40°C 85°C Industrial DP83867ERGZ SGMII/RGMII –40°C 105°C Extended 70°C Commercial VDDA1P8 LED_0 LED_1 LED_2 INT/PWDN RESET_N VDD1P0 VDDIO GPIO_1 GPIO_0 RX_CTRL TX_CTRL 6 Pin Configuration and Functions 48 47 46 45 44 43 42 41 40 39 38 37 TD_P_A 1 36 RX_D3/SGMII_SON TD_M_A 2 35 RX_D2/SGMII_SOP VDDA2P5 3 34 RX_D1/SGMII_CON TD_P_B 4 33 RX_D0/SGMII_COP DP83867 TD_M_B 5 32 RX_CLK 31 VDD1P0 VDDA2P5 9 28 TX_D0/SGMII_SIN TD_P_D 10 27 TX_D1/SGMII_SIP TD_M_D 11 26 TX_D2 RBIAS 12 25 TX_D3 13 14 15 16 17 18 19 20 21 22 23 24 VDD1P0 GTX_CLK JTAG_TDI 29 JTAG_TMS DAP = GND JTAG_TDO 8 JTAG_CLK TD_M_C VDDIO VDDIO CLK_OUT 30 MDIO 48-pin QFN Package MDC 7 XI TD_P_C XO 6 VDDA1P8 VDD1P0 TOP VIEW (not to scale) Figure 6-1. RGZ Package 48-Pin VQFN Top View Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E Submit Document Feedback 5 DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 6.1 Pin Functions PIN NAME NO. TYPE(1) DESCRIPTION MAC INTERFACES (SGMII, RGMII) TX_D3 25 I, PD TRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in RGMII mode. It is synchronous to the transmit clock GTX_CLK. TX_D2 26 I, PD TRANSMIT DATA Bit 2: This signal carries data from the MAC to the PHY in RGMII mode. It is synchronous to the transmit clock GTX_CLK. SGMII_SIP 27 I, PD Differential SGMII Data Input: This signal carries data from the MAC to the PHY in SGMII mode. It is synchronous to the differential SGMII clock input. This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when operating in SGMII mode. TX_D1 27 I, PD TRANSMIT DATA Bit 1: This signal carries data from the MAC to the PHY in RGMII mode. It is synchronous to the transmit clock GTX_CLK. SGMII_SIN 28 I, PD Differential SGMII Data Input: This signal carries data from the MAC to the PHY in SGMII mode. It is synchronous to the differential SGMII clock input. This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when operating in SGMII mode. TX_D0 28 I, PD TRANSMIT DATA Bit 0: This signal carries data from the MAC to the PHY in RGMII mode. It is synchronous to the transmit clock GTX_CLK. GTX_CLK 29 I, PD RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the MAC layer to the PHY. Nominal frequency is 125 MHz. RX_CLK 32 O RGMII RECEIVE CLOCK: Provides the recovered receive clocks for different modes of operation: 2.5 MHz in 10-Mbps mode. 25 MHz in 100-Mbps mode. 125 MHz in 1000-Mbps mode. SGMII_COP 33 S, O Differential SGMII Clock Output: This signal is a continuous 625-MHz clock signal driven by the PHY in SGMII mode. This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when operating in SGMII mode. RX_D0 33 S, O, PD RECEIVE DATA Bit 0: This signal carries data from the PHY to the MAC in RGMII mode. It is synchronous to the receive clock RX_CLK. Differential SGMII Clock Output: This signal is a continuous 625-MHz clock signal driven by the MAC in SGMII mode. This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when operating in SGMII mode. SGMII_CON 34 S, O, PD RX_D1 34 O, PD RECEIVE DATA Bit 1: This signal carries data from the PHY to the MAC in RGMII mode. It is synchronous to the receive clock RX_CLK. Differential SGMII Data Output: This signal carries data from the PHY to the MAC in SGMII mode. It is synchronous to the differential SGMII clock output. SGMII_SOP 35 S, O, PD RX_D2 35 S, O, PD RECEIVE DATA Bit 2: This signal carries data from the PHY to the MAC in RGMII mode. It is synchronous to the receive clock RX_CLK. SGMII_SON 36 S, O, PD Differential SGMII Data Output: This signal carries data from the PHY to the MAC in SGMII mode. It is synchronous to the differential SGMII clock output. This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when operating in SGMII mode. RX_D3 36 O, PD RECEIVE DATA Bit 3: This signal carries data from the PHY to the MAC in RGMII mode. It is synchronous to the receive clock RX_CLK. TX_CTRL 37 I, PD TRANSMIT CONTROL: In RGMII mode, it combines the transmit enable and the transmit error signals of GMII mode using both clock edges. RX_CTRL 38 S, O, PD RECEIVE CONTROL: In RGMII mode, the receive data available and receive error are combined (RXDV_ER) using both rising and falling edges of the receive clock (RX_CLK). This pin should be AC-coupled to the MAC through a 0.1-µF capacitor when operating in SGMII mode. GENERAL-PURPOSE I/O 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 PIN NAME TYPE(1) NO. DESCRIPTION GPIO_0 39 S, O, PD General-Purpose I/O: This signal provides a multi-function configurable I/O. Refer to the GPIO_MUX_CTRL register for details. GPIO_1 40 S, O, PD General-Purpose I/O: This signal provides a multi-function configurable I/O. Refer to the GPIO_MUX_CTRL register for details. MANAGEMENT INTERFACE MDC 16 I, PD MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial management input and output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25 MHz and no minimum. MDIO 17 I/O MANAGEMENT DATA I/O: Bidirectional management instruction and data signal that may be sourced by the management station or the PHY. This pin requires pullup resistor. The IEEE specified resistor value is 1.5 kΩ, but a 2.2 kΩ is acceptable. 44 I/O, PU INTERRUPT / POWER DOWN: The default function of this pin is POWER DOWN. POWER DOWN: This is an Active Low Input. Asserting this signal low enables the power-down mode of operation. In this mode, the device powers down and consume minimum power. Register access is available through the Management Interface to configure and power up the device. INTERRUPT: When operating this pin as an interrupt, it is an open-drain architecture. TI recommends using an external 2.2-kΩ resistor connected to the VDDIO supply. 43 I, PU RESET: The active low RESET initializes or reinitializes the DP83867. All internal registers re-initialize to their default state upon assertion of RESET. The RESET input must be held low for a minimum of 1 µs. XI 15 I CRYSTAL/OSCILLATOR INPUT: 25-MHz oscillator or crystal input (50 ppm) XO 14 O CRYSTAL OUTPUT: Second terminal for 25-MHz crystal. Must be left floating if a clock oscillator is used. CLK_OUT 18 O CLOCK OUTPUT: Output clock JTAG_CLK 20 I, PU JTAG_TDO 21 O JTAG_TMS 22 I, PU JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin sequences the Tap Controller (16-state FSM) to select the desired test instruction. TI recommends applying 3 clock cycles with JTAG_TMS high to reset the JTAG. JTAG_TDI 23 I, PU JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned into the device through TDI. LED_2 45 S, I/O, PD LED_2: By default, this pin indicates receive or transmit activity. Additional functionality is configurable through LEDCR1[11:8] register bits. LED_1 46 S, I/O, PD LED_1: By default, this pin indicates that 1000BASE-T link is established. Additional functionality is configurable through LEDCR1[7:4] register bits. LED_0 47 S, I/O, PD LED_0: By default, this pin indicates that link is established. Additional functionality is configurable through LEDCR1[3:0] register bits. INT / PWDN RESET RESET_N CLOCK INTERFACE JTAG INTERFACE JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test logic input and output controlled by the testing entity. JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent test results are scanned out of the device through TDO. LED INTERFACE MEDIA DEPENDENT INTERFACE TD_P_A 1 A Differential Transmit and Receive Signals TD_M_A 2 A Differential Transmit and Receive Signals TD_P_B 4 A Differential Transmit and Receive Signals TD_M_B 5 A Differential Transmit and Receive Signals Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E Submit Document Feedback 7 DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 PIN NAME NO. TYPE(1) DESCRIPTION TD_P_C 7 A Differential Transmit and Receive Signals TD_M_C 8 A Differential Transmit and Receive Signals TD_P_D 10 A Differential Transmit and Receive Signals TD_M_D 11 A Differential Transmit and Receive Signals 12 A Bias Resistor Connection. A 11-kΩ ±1% resistor should be connected from RBIAS to GND. 3, 9 P 2.5-V Analog Supply (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND. 6, 24, 31, 42 P 1-V Analog Supply (+15.5%, –5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND. 13, 48 P 1.8-V Analog Supply (±5%). No external supply is required for this pin. When unused, no connections should be made to this pin. For additional power savings, an external 1.8-V supply can be connected to these pins. When using an external supply, each pin requires a 1-µF and 0.1-µF capacitor to GND. 19, 30, 41 P I/O Power: 1.8 V (±5%), 2.5 V (±5%) or 3.3 V (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND Die Attach Pad P Ground OTHER PINS RBIAS POWER AND GROUND PINS VDDA2P5 VDD1P0 VDDA1P8 VDDIO GND (1) The definitions below define the functionality of each pin. • • • • • • • 8 Type: I Input Type: O Output Type: I/O Input/Output Type: PD, PU Internal Pulldown/Pullup Type: S Configuration Pin Type: P Power or GND Type: A Analog pins Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 6.2 Unused Pins DP83867 has internal pullups or pulldowns on most pins. The data sheet details which pins have internal pullups or pulldowns and which pins require external pull resistors. Even though a device may have internal pullup or pulldown resistors, a good practice is to terminate unused inputs rather than allowing them to float. Floating inputs could result in unstable conditions. Except for VDDA1P8 pins, if they are not used then they should be left floating. It is considered a safer practice to pull an unused input pin high or low with a pullup or pulldown resistor. It is also possible to group together adjacent unused input pins, and as a group pull them up or down using a single resistor. Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E Submit Document Feedback 9 DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage MIN MAX VDDA2P5 –0.3 3 VDDA1P8 –0.3 2.1 VDD1P0 –0.3 1.3 3.3-V option –0.3 3.8 2.5-V option –0.3 3 1.8-V option VDDIO Pins V –0.3 2.1 MDI –0.3 6.5 MAC interface, MDIO, MDC, GPIO –0.3 VDDIO + 0.3 INT/PWDN, RESET –0.3 VDDIO + 0.3 JTAG –0.3 VDDIO + 0.3 XI (Oscillator Clock Input) –0.3 2.1 V –60 150 °C Storage temperature, Tstg (1) UNIT V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE UNIT DP83867ERGZ and DP83867ISRGZ in the RGZ Package V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/ JEDEC JS-001(1) All pins except 1, 2, 4, 5, 7, 8, 10, and 11 ±2500 Pins 1, 2, 4, 5, 7, 8, 10, and 11(3) ±8000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) V ±1500 DP83867CSRGZ in the RGZ Package V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/ JEDEC JS-001(1) All pins except 1, 2, 4, 5, 7, 8, 10, and 11 ±2500 Pins 1, 2, 4, 5, 7, 8, 10, and 11(3) ±6000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) (1) (2) (3) 10 V ±1500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±8 V and/or ± 2 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance. MDI Pins tested as per IEC 61000-4-2 standards. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TYP MAX VDDA2P5 2.375 2.5 2.625 VDDA1P8 1.71 1.8 1.89 VDD1P0 Supply voltage VDDIO 0.95 1 1.155 3.3-V option 3.15 3.3 3.45 2.5-V option 2.375 2.5 2.625 1.8-V option 1.71 1.8 1.89 Commercial (DP83867CSRGZ) Operating junction temperature 0 90 Industrial (DP83867ISRGZ) –40 105 Extended (DP83867ERGZ) –40 Commercial (DP83867CSRGZ) Operating free air temperature UNIT V °C 125 0 25 70 Industrial (DP83867ISRGZ) –40 25 85 Extended (DP83867ERGZ) –40 25 105 °C 7.4 Thermal Information DP83867xS, DP83867E THERMAL METRIC(1) RGZ (VQFN) UNIT 48 PINS RθJA Junction-to-ambient thermal resistance 30.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 18.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.4 °C/W RθJB Junction-to-board thermal resistance 7.5 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 7.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Electrical Characteristics The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of the product containing it. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.3-V VDDIO VOH High level output voltage IOH = –4 mA VOL Low level output voltage IOL = 4 mA VIH High level input voltage VIL Low level input voltage 2 V 0.6 1.7 V V 0.7 V 2.5-V VVDDIO VOH High level output voltage IOH = –4 mA VOL Low level output voltage IOL = 4 mA VIH High level input voltage VIL Low level input voltage VDDIO × 0.8 V 0.6 1.7 V V 0.7 V 1.8-V VDDIO VOH High level output voltage IOH = –1 mA VOL Low level output voltage IOL = 1 mA VDDIO – 0.2 Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E V 0.2 V Submit Document Feedback 11 DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 7.5 Electrical Characteristics (continued) The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of the product containing it. PARAMETER VIH High level input voltage VIL Low level input voltage TEST CONDITIONS MIN TYP MAX 0.7 × VDDIO UNIT V 0.2 × VDDIO V XI INPUT VOLTAGE VOSC Input voltage for 25 MHz Oscillator 1.5 VIH High level input voltage 1.4 VIL Low level input voltage 1.9 Vpp V 0.45 V DC CHARACTERISTICS IIH Input high current IIL Input low current IOZ TRI-STATE output current CIN VIN = VDD, TA = –40°C to +85°C -10 10 µA VIN = VDD, TA = 85°C to +105°C -20 20 µA VIN = GND, TA = –40°C to +85°C -10 10 µA VIN = GND, TA = 85°C to +105°C -20 20 µA VOUT = VDD, VOUT = GND, TA = –40°C to +85°C -10 10 µA VOUT = VDD, VOUT = GND, TA = 85°C to +105°C -20 20 µA 5 pF See (3) Input capacitance PMD OUTPUTS VOD-10 MDI VOD-100 MDI VOD-1000 MDI ERGZ/ISRGZ 1.54 CSRGZ ERGZ/ISRGZ 1.96 V Peak Differential 1.05 V Peak Differential 0.82 V Peak Differential 1.75 0.95 CSRGZ ERGZ/ISRGZ 1.75 1 1 0.67 CSRGZ 0.745 0.745 POWER CONSUMPTION RGMII power consumption(1) P1000 (2) (4) IDD25 Supply current 2 supplies 495 Optional 3rd supply 457 2 supplies 137 mA 108 mA 24 mA IDD10 IDDIO (1.8 V) IDD25 86 mA IDD10 108 mA IDD18 50 mA IDDIO (1.8 V) 24 mA (1) (2) (3) (4) 12 Supply current Optional 3rd supply mW Power consumption represents total operational power for 1000BASE-T. See Section 10 for details on 2-supply and 3-supply configuration. Ensured by production test, characterization, or design. For detailed information about DP83867 power consumption for specific supplies under a wide set of conditions, see the DP83867E/IS/CS/IR/CR RGZ Power Consumption Data application report (SNLA241). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 7.6 Power-Up Timing See Figure 7-1. TEST CONDITIONS(1) PARAMETER MIN NOM MAX UNIT T1 Post power-up stabilization time prior to MDC MDIO is pulled high for 32-bit serial preamble for register accesses management initialization. 200 ms T2 Hardware configuration latch-in time from power up 200 ms T3 Hardware configuration pins transition to output drivers 64 ns (1) Hardware Configuration Pins are described in Section 8.5.1. Ensured by production test, characterization, or design. Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E Submit Document Feedback 13 DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 7.7 Reset Timing See Figure 7-2. TEST CONDITIONS (1) PARAMETER MIN NOM MAX UNIT Post RESET stabilization time prior to MDC preamble for register accesses MDIO is pulled high for 32-bit serial management initialization. MDC may toggle during this period when MDIO remains high. 195 µs T2 Hardware configuration latch-in time from the deassertion of RESET (either soft or hard) Hardware Configuration Pins are described in Section 8.5.1. 120 ns T3 Hardware configuration pins transition to output drivers 64 ns T1 T4 (1) X1 Clock must be stable for a minimum of 1 μs during RESET pulse low time RESET pulse width 1 µs Ensured by production test, characterization, or design. 7.8 MII Serial Management Timing See Figure 7-3. TEST CONDITIONS(1) PARAMETER MIN NOM MAX MDC to MDIO (output) delay time 0 T2 MDIO (input) to MDC setup time 10 ns T3 MDIO (input) to MDC hold time 10 ns T4 MDC frequency (1) 10 UNIT T1 2.5 ns 25 MHz MAX UNIT Ensured by production test, characterization, or design. 7.9 SGMII Timing See Figure 7-4. TEST CONDITIONS (3) PARAMETER MIN NOM T1 SGMII Clock Output Duty Cycle 48% 52% T2 Setup time See (1) 100 T3 Clock to Data relationship from either edges of the clock to valid See (2) data 250 550 ps TR VOD fall time 20% - 80% 100 200 ps TF VOD rise time 20% - 80% 100 200 ps (1) 100 ps Thold Hold time See TTXLAT SGMII to MDI Latency See (4) 201 ns TRXLAT MDI to SGMII Latency See (4) 289 ns (1) (2) (3) (4) ps Setup and hold time are measured at 50% of the transition. T3 is measured at 0 V differential. Ensured by production test, characterization, or design. Operating in 1000Base-T 7.10 RGMII Timing See Figure 7-5 and .Figure 7-6 TEST CONDITIONS(5) PARAMETER MIN NOM MAX UNIT See (1) –500 0 500 ps Data to Clock input Skew (at Receiver) See (1) 1 1.8 2.6 ns Data to Clock output Setup (at Transmitter – internal delay) See (4) 1.2 2 TskewT Data to Clock output Skew (at Transmitter) TskewR TsetupT 14 Submit Document Feedback ns Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 7.10 RGMII Timing (continued) See Figure 7-5 and .Figure 7-6 TEST CONDITIONS(5) PARAMETER MIN NOM See (4) 1.2 2 ns Data to Clock input Setup (at Reciever – internal delay) See (4) 1 2 ns TholdR Clock to Data input Hold (at Receiver – internal delay) See (4) 1 2 ns Tcyc Clock Cycle Duration See (2) TholdT Clock to Data output Hold (at Transmitter – internal delay) TsetupR MAX 7.2 8 8.8 (3) (7) 45 50 55% 40 50 60% UNIT ns Duty_G Duty Cycle for Gigabit See Duty_T Duty Cycle for 10/100T See (3) (7) TR Rise Time (20% to 80%) TF Fall Time (20% to 80%) TTXLAT RGMII to MDI Latency See (6) 88 ns MDI to RGMII Latency (6) 288 ns TRXLAT (1) (2) (3) (4) (5) (6) (7) See 0.75 ns 0.75 ns When operating without RGMII internal delay, the PCB design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. For 10-Mbps and 100-Mbps, Tcyc will scale to 400 ns ± 40 ns and 40 ns ± 4 ns. Duty cycle may be stretched or shrunk during speed changes or while transitioning to a received packet’s clock domain as long as minimum duty cycle is not violated and stretching occurs for no more that three Tcyc of the lowest speed transitioned between. Device may operate with or without internal delay. Ensured by production test, characterization, or design. Operating in 1000Base-T . Duty cycle values are defined in percentages of the nominal clock speed. For example, the minimum Gigabit RGMII clock pulse duration is 45 % of 8 ns. 7.11 DP83867E Start of Frame Detection Timing Figure 7-7 PARAMETER T1 T2 (1) (2) Transmit SFD TEST CONDITIONS variation(1) (2) Receive SFD variation(1) (2) MIN NOM MAX UNIT 1000-Mb Master 0 0 ns 1000-Mb Slave 0 0 ns 100-Mb 0 8 ns 1000-Mb Master –4 4 ns 1000-Mb Slave 0 0 ns 100-Mb 0 0 ns A larger variation may be seen on SFD pulses than the variation specified here. To achieve the determinism specification listed, see the Section 8.3.2.1 section for a method to compensate for variation in the SFD pulses. Variation of SFD pulses occurs from link-up to link-up. Packet to packet variation is fixed using the estimation method in Section 8.3.2.1. 7.12 DP83867IS/CS Start of Frame Detection Timing Figure 7-8 PARAMETER T1 T2 TEST CONDITIONS Transmit SFD variation(1) (2) Receive SFD variation(1) (2) NOM MAX UNIT 1000-Mb Master 0 0 ns 1000-Mb Slave 0 0 ns 100-Mb 0 16 ns 1000-Mb Master –8 8 ns 1000-Mb Slave –8 8 ns 0 0 ns 100-Mb (1) MIN A larger variation may be seen on SFD pulses than the variation specified here. To achieve the determinism specification listed, see the Section 8.3.2.1 section for a method to compensate for variation in the SFD pulses. Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E Submit Document Feedback 15 DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 (2) Variation of SFD pulses occurs from link-up to link-up. Packet to packet variation is fixed using the estimation method in Section 8.3.2.1. 7.13 Timing Diagrams VDD XI clock T1 Hardware RESET_N 32 CLOCKS MDC T2 Latch-In of Hardware Configuration Pins T3 Dual Function Pins Become Enabled As Outputs INPUT OUTPUT Figure 7-1. Power-Up Timing VDD XI clock T1 T4 Hardware RESET_N 32 CLOCKS MDC T2 Latch-In of Hardware Configuration Pins T3 Dual Function Pins Become Enabled As Outputs Input Output Figure 7-2. Reset Timing 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 MDC T4 T1 MDIO (output) MDC T2 MDIO (input) T3 Valid Data Figure 7-3. MII Serial Management Timing SG_RXCK (single ended) SG_RXCK (differential) tT2t tT1t SG_RXDA (single ended) SG_RXDA (differential) T3 (min) T3 (max) Figure 7-4. SGMII Timing GTX (at Transmitter) TskewT TXD [8:5][3:0] TXD [7:4][3:0] TX_CTL TXD [3:0] TXD [8:5] TXD [7:4] TXD [4] TXEN TXD [9] TXERR TskewR GTX (at Receiver) Figure 7-5. RGMII Transmit Multiplexing and Timing Diagram Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E Submit Document Feedback 17 DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 RXC with Internal Delay Added RXC (Source of Data) TsetupT RXD [8:5][3:0] RXD [7:4][3:0] RXD [3:0] RXD [8:5] RXD [7:4] TholdT RX_CTL RXD [4] RXDV RXD [9] RXERR RXC (at Receiver) TholdR TsetupR Figure 7-6. RGMII Receive Multiplexing and Timing Diagram T1 TX SFD Packet Transmitted on Wire Packet Received from Wire T2 RX SFD Figure 7-7. DP83867E Start of Frame Delimiter Timing T1 TX SFD Packet Transmitted on Wire Packet Received from Wire T2 RX SFD Figure 7-8. DP83867IS/CS Start of Frame Delimiter Timing 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 C1 (500 mV/DIV) C1 (200 mV/DIV) 7.14 Typical Characteristics Time (4 ns/DIV) 1000Base-T Signaling (Test Mode TM2 Output) Figure 7-9. 1000Base-T Signaling Time (32 ns/DIV) 100Base-TX Signaling (Scrambled Idles) Figure 7-10. 100Base-TX Signaling Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E Submit Document Feedback 19 DP83867CS, DP83867IS, DP83867E SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 www.ti.com 8 Detailed Description 8.1 Overview The DP83867 is a fully featured Physical Layer transceiver with integrated PMD sub-layers to support 10BASETe, 100BASE-TX and 1000BASE-T Ethernet protocols. The DP83867 is designed for easy implementation of 10-,100-, and 1000-Mbps Ethernet LANs. It interfaces directly to twisted pair media through an external transformer. This device interfaces directly to the MAC layer through the Reduced GMII (RGMII) or embedded clock Serial GMII (SGMII). The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has low jitter, low latency and provides IEEE 1588 Start of Frame Detection for time sensitive protocols. The DP83867 offers innovative diagnostic features including dynamic link quality monitoring for fault prediction during normal operation. It can support up to 130-m cable length. 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 8.2 Functional Block Diagram MGNT & PHY CNTRL 100BASE-TX Block 10BASE-Te PLS 100BASE-TX PMA 10BASE-Te PMA RXD[3:0] RX_CTRL RX_CLK TXD[3:0] MUX / DMUX 1000BASE-T Block 10BASE-Te Block 100BASE-TX PCS TX_CTRL GTX_CLK COMBINED RGMII / SGMII INTERFACE Interrupt MDC MDIO MGMT INTERFACE 1000BASE-T PCS Wake on LAN Echo cancellation Crosstalk cancellation ADC Decode / Descramble Equalization Timing Skew compensation BLW 10000BASE-T PMA AutoNegotiation Manchester 10 Mbps 100BASE-TX PMD MLT-3 100 Mbps PAM-5 17 Level PR Shaped 125 Msymbols/s DAC / ADC SUBSYSTEM TIMING DRIVERS / RECEIVERS DAC / ADC TIMING BLOCK MAGNETICS 4-pair CAT-5 Cable Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E Submit Document Feedback 21 DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 8.3 Feature Description 8.3.1 WoL (Wake-on-LAN) Packet Detection Wake-on-LAN provides a mechanism for bringing the DP83867 out of a low-power state using a special Ethernet packet called a Magic Packet. The DP83867 can be configured to generate an interrupt to wake up the MAC when a qualifying packet is received. An option is also available to generate a signal on a GPIO when a qualifying signal is received. Note Please ensure that BMCR (register address 0x0000) bit[10] is disabled, when using the WoL feature. This bit enables the MII ISOLATE function used to disable the MAC interface of the PHY, also disabling the WoL interrupt on this PHY. If the WoL feature is needed while MII ISOLATE is enabled please use TI's DP83869HM PHY instead. The Wake-on-LAN feature includes the following functionality: • Identification of magic packets in all supported speeds (1000BASE-T, 100BASE-TX, 10BASE-Te) • Wakeup interrupt generation upon receiving a valid magic packet • CRC checking of magic packets to prevent interrupt generation for invalid packets In addition to the basic magic packet support, the DP83867 also supports: • Magic packets that include secure-on password • Pattern match – one configurable 64 byte pattern of that can wake up the MAC similar to magic packet • Independent configuration for Wake on Broadcast and Unicast packet types. 8.3.1.1 Magic Packet Structure When configured for Magic Packet mode, the DP83867 scans all incoming frames addressed to the node for a specific data sequence. This sequence identifies the frame as a Magic Packet frame. Note The Magic Packet should be byte aligned. A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as SOURCE ADDRESS, DESTINATION ADDRESS (which may be the receiving station’s IEEE address or a BROADCAST address), and CRC. The specific Magic Packet sequence consists of 16 duplications of the IEEE address of this node, with no breaks or interruptions, followed by secure-on password if security is enabled. This sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The synchronization stream is defined as 6 bytes of FFh. 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 DEST (6 bytes) SRC (6 bytes) MISC (X bytes, X >= 0) ))« )) (6 bytes) MAGIC pattern DEST * 16 SecureOn Password (6 bytes) Only if Secure-On is enabled MISC (Y bytes, Y >= 0) CRC (4 bytes) Figure 8-1. Magic Packet Structure 8.3.1.2 Magic Packet Example The following is an example Magic Packet for a Destination Address of 11h 22h 33h 44h 55h 66h and a SecureOn Password 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh: DESTINATION SOURCE MISC FF FF FF FF FF FF 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 2A 2B 2C 2D 2E 2F MISC CRC 8.3.1.3 Wake-on-LAN Configuration and Status Wake-on-LAN functionality is configured through the RXFCFG register (address 0x0134). Wake-on-LAN status is reported in the RXFSTS register (address 0x0135). 8.3.2 Start of Frame Detect for IEEE 1588 Time Stamp The DP83867 supports an IEEE 1588 indication pulse at the SFD (start frame delimiter) for the receive and transmit paths. The pulse can be delivered to various pins. The pulse indicates the actual time the symbol is presented on the lines (for transmit), or the first symbol received (for receive). The exact timing of the pulse can be adjusted through register. Each increment of phase value is an 8-ns step. Figure 8-2. IEEE 1588 Message Timestamp Point Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E Submit Document Feedback 23 DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 The SFD pulse output can be configured using the GPIO Mux Control registers, GPIO_MUX_CTRL1 (register address 0x0171) and GPIO_MUX_CTRL2 (register address 0x0172). The ENHANCED_MAC_SUPPORT bit in RXCFG (register address 0x0134) must also be set to allow output of the SFD. For more information about configuring the DP83867's SFD feature, see the How to Configure DP83867 Start of Frame application report (SNLA242). 8.3.2.1 SFD Latency Variation and Determinism Time stamping packet transmission and reception using the RX_CTRL and TX_CTRL signals of RGMII is not accurate enough for latency sensitive protocols. SFD pulses offers system designers a method to improve the accuracy of packet time stamping. The SFD pulse, while varying less than RGMII signals inherently, still exhibits latency variation due to the defined architecture of 1000BASE-T. This section provides a method to determine when an SFD latency variation has occurred and how to compensate for the variation in system software to improve timestamp accuracy. In the following section the terms baseline latency and SFD variation are used. Baseline latency is the time measured between the TX_SFD pulse to the RX_SFD pulse of a connected link partner, assuming an Ethernet cable with all 4 pairs perfectly matched in propagation time. In the scenario where all 4 pairs being perfectly matched, a 1000BASE-T PHY will not have to align the 4 received symbols on the wire and will not introduce extra latency due to alignment. TX SFD Baseline Latency RX SFD SFD Variation Figure 8-3. Baseline Latency and SFD Variation in Latency Measurement SFD variation is additional time added to the baseline latency before the RX_SFD pulse when the PHY must introduce latency to align the 4 symbols from the Ethernet cable. Variation can occur when a new link is established either by cable connection, auto-negotiation restart, PHY reset, or other external system effects. During a single, uninterrupted link, the SFD variation will remain constant. The DP83867 can limit and report the variation applied to the SFD pulse while in the 1000-Mb operating mode. Before a link is established in 1000-Mb mode, the Sync FIFO Control Register (register address 0x00E9) must be set to value 0xDF22. The below SFD variation compensation method can only be applied after the Sync FIFO Control Register has been initialized and a new link has been established. It is acceptable to set the Sync FIFO Control register value and then perform a software restart by setting the SW_RESTART bit[14] in the Control Register (register address 0x001F) if a link is already present. 8.3.2.1.1 1000-Mb SFD Variation in Master Mode When the DP83867 is operating in 1000-Mb master mode, variation of the RX_SFD pulse can be estimated using the Skew FIFO Status register (register address 0x0055) bit[7:4]. The value read from the Skew FIFO Status register bit[7:4] must be multiplied by 8 ns to estimate the RX_SFD variation added to the baseline latency. Example: While operating in master 1000-Mb mode, a value of 0x2 is read from the Skew FIFO register bit[7:4]. 2 × 8 ns = 16 ns is subtracted from the TX_SFD to RX_SFD measurement to determine the baseline latency. 8.3.2.1.2 1000-Mb SFD Variation in Slave Mode When the DP83867 is operating in 1000-Mb slave mode, the variation of the RX_SFD pulse can be determined using the Skew FIFO Status register (register address 0x0055) bit[3:0].The value read from the Skew FIFO Status register bit[3:0] should be multiplied by 8ns to estimate the RX_SFD variation added to the baseline latency. 24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 Example: While operating in slave 1000-Mb mode, a value of 0x1 is read from the Skew FIFO register bit[3:0]. 1 × 8 ns = 8 ns is subtracted from the TX_SFD to RX_SFD measurement to determine the baseline latency. 8.3.2.1.3 100-Mb SFD Variation The latency variation in 100-Mb mode of operation is determined by random process and does not require any register readout or system level compensation of SFD pulses. 8.3.3 Clock Output The DP83867 has several internal clocks, including the local reference clock, the Ethernet transmit clock, and the Ethernet receive clock. An external crystal or oscillator provides the stimulus for the local reference clock. The local reference clock acts as the central source for all clocking in the device. The local reference clock is embedded into the transmit network packet traffic and is recovered from the network packet traffic at the receiver node. The receive clock is recovered from the received Ethernet packet data stream and is locked to the transmit clock in the partner. Using the I/O Configuration register (address 0x0170), the DP83867 can be configured to output these internal clocks through the CLK_OUT pin. By default, the output clock is synchronous to the XI oscillator / crystal input. The default output clock is suitable for use as the reference clock of another DP83867 device. Through registers, the output clock can be configured to be synchronous to the receive data at the 125-MHz data rate or at the divide by 5 rate of 25 MHz. It can also be configured to output the line driver transmit clock. When operating in 1000Base-T mode, the output clock can be configured for any of the four transmit or receive channels. The output clock can be disabled using the CLK_O_DISABLE bit of the I/O Configuration register. 8.4 Device Functional Modes 8.4.1 MAC Interfaces The DP83867 supports connection to an Ethernet MAC through the following interfaces: SGMII and RGMII. The SGMII Enable (LED_0) strap allows the user to turn the SGMII MAC interface on or off. The SGMII Enable strap corresponds to the SGMII Enable (bit 11) in the PHYCR register (address 0x0010). The SGMII enable has higher priority than the RGMII enable. Table 8-1 is the configuration table for the MAC interfaces: Table 8-1. Configuration Table for the MAC Interfaces SGMII ENABLE (REGISTER 0x0010, BIT 11) RGMII ENABLE (REGISTER 0x0032, BIT 7) DEVICE FUNCTIONAL MODE 0x1 0x1 SGMII 0x1 0x0 SGMII 0x0 0x1 RGMII The initial strap values for the SGMII enable and the RGMII disable are also available in the Strap Configuration Status Register 1 (STRAP_STS1). 8.4.1.1 Serial GMII (SGMII) The Serial Gigabit Media Independent Interface (SGMII) provides a means of conveying network data and port speed between a 100/1000 PHY and a MAC with significantly less signal pins (4 or 6 pins) than required for GMII (24 pins) or RGMII (12 pins). The SGMII interface uses 1.25-Gbps LVDS differential signaling which has the added benefit of reducing EMI emissions relative to GMII or RGMII. Because the internal clock and data recovery circuitry (CDR) of DP83867 can detect the transmit timing of the SGMII data, TX_CLK is not required. SGMII interface is capable of working as a 4-wire or 6-wire SGMII interface. The default SGMII connection is through four wires. Two differential pairs are used for the transmit and receive connections. Clock and data recovery are performed in the MAC and in the PHY, so no additional differential pair is required for clocking. Alternately, if the MAC is not capable of recovering the clock from the SGMII receive data, the DP83867 can be configured to provide the SGMII receive clock through a differential pair. Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E Submit Document Feedback 25 DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 The 1.25-Gbps rate of SGMII is excessive for 100-Mbps operation. When operating in 100-Mbps mode, the PHY elongates the frame by replicating each frame byte 10 times. This frame elongation takes place above the IEEE 802.3 PCS layer, thus the start of frame delimiter only appears once per frame. The SGMII interface includes Auto-Negotiation capability. Auto-Negotiation provides a mechanism for control information to be exchanged between the PHY and the MAC. This allows the interface to be automatically configured based on the media speed mode resolution on the MDI side. In MAC loopback mode, the SGMII speed is determined by the MDI speed selection. The SGMII interface works in both Auto-Negotiation and forced speed mode during the MAC loopback operation. SGMII Auto-Negotiation is the default mode of the operation. The SGMII Auto-Negotiation process can be disabled and the SGMII speed mode can be forced to the MDI resolved speed. The SGMII forced speed mode can be enabled with the MDI auto-negotiation or MDI manual speed mode. SGMII Auto-Negotiation can be disabled through the SGMII_AUTONEG_EN register bit in the CFG2 register (address 0x0014). The 10M_SGMII_RATE_ADAPT bit (bit 7) does not need to be changed for 10M speed as the PHY will automatically adapt the rate of SGMII. SGMII is enabled through a resistor strap option. See Section 8.5.1 for details. All SGMII connections must be AC-coupled through an 0.1-µF capacitor. PHY has inbuilt 100 Ω differential termination at receive and transmit pins of SGMII. The connection diagrams for 4-wire SGMII and 6-wire SGMII are shown in Figure 8-4 and Figure 8-5. PHY MAC 0.1 µF SGMII_SIP 0.1 µF SGMII_SIN 0.1 µF SGMII_SOP 0.1 µF SGMII_SON Figure 8-4. SGMII 4-Wire Connections 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 PHY MAC 0.1 µF SGMII_SIP 0.1 µF SGMII_SIN 0.1 µF SGMII_SOP 0.1 µF SGMII_SON 0.1 µF SGMII_COP 0.1 µF SGMII_CON Figure 8-5. SGMII 6-Wire Connections 8.4.1.2 Reduced GMII (RGMII) The Reduced Gigabit Media Independent Interface (RGMII) is designed to reduce the number of pins required to interconnect the MAC and PHY (12 pins for RGMII relative to 24 pins for GMII). To accomplish this goal, the data paths and all associated control signals are reduced and are multiplexed. Both rising and trailing edges of the clock are used. For Gigabit operation the GTX_CLK and RX_CLK clocks are 125 MHz, and for 10- and 100-Mbps operation, the clock frequencies are 2.5 MHz and 25 MHz, respectively. For more information about RGMII timing, see the RGMII Interface Timing Budgets application report (SNLA243). 8.4.1.2.1 1000-Mbps Mode Operation All RGMII signals are positive logic. The 8-bit data is multiplexed by taking advantage of both clock edges. The lower 4 bits are latched on the positive clock edge and the upper 4 bits are latched on trailing clock edge. The control signals are multiplexed into a single clock cycle using the same technique. To reduce power consumption of RGMII interface, TXEN_ER and RXDV_ER are encoded in a manner that minimizes transitions during normal network operation. This is done by following encoding method. Note that the value of GMII_TX_ER and GMII_TX_EN are valid at the rising edge of the clock. In RGMII mode, GMII_TX_ER is presented on TX_CTRL at the falling edge of the GTX_CLK clock. RX_CTRL coding is implemented the same fashion. When receiving a valid frame with no error, RX_CTRL = True is generated as a logic high on the rising edge of RX_CLK and RX_CTRL = False is generated as a logic high at the falling edge of RX_CLK. When no frame is being received, RX_CTRL = False is generated as a logic low on the rising edge of RX_CLK and RX_CTRL = False is generated as a logic low on the falling edge of RX_CLK. TX_CTRL is treated in a similar manner. During normal frame transmission, the signal stays at a logic high for both edges of GTX_CLK and during the period between frames where no error is indicated, the signal stays low for both edges. Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E Submit Document Feedback 27 DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 8.4.1.2.2 1000-Mbps Mode Timing The DP83867 provides configurable clock skew for the GTX_CLK and RX_CLK to optimize timing across the interface. The transmit and receive paths can be optimized independently. Both the transmit and receive path support 16 programmable RGMII delay modes through register configuration. Strap configuration can also be used to configure 8 programmable RGMII modes for both the transmit and receive paths. See Section 8.5.1 for details. The timing paths can either be configured for Aligned mode or Shift mode. In Aligned mode, no clock skew is introduced. In Shift mode, the clock skew can be introduced in 0.5-ns increments (through strap configuration) or in 0.25-ns increments (through register configuration). Configuration of the Aligned mode or Shift mode is accomplished through the RGMII Control Register (RGMIICTL), address 0x0032. In Shift mode, the clock skew can be adjusted using the RGMII Delay Control Register (RGMIIDCTL), address 0x0086. 8.4.1.2.3 10- and 100-Mbps Mode When the RGMII interface is operating in the 100-Mbps mode, the Ethernet Media Independent Interface (MII) is implemented by reducing the clock rate to 25 MHz. For 10-Mbps operation, the clock is further reduced to 2.5 MHz. In the RGMII 10/100 mode, the transmit clock RGMII TX_CLK is generated by the MAC and the receive clock RGMII RX_CLK is generated by the PHY. During the packet receiving operation, the RGMII RX_CLK may be stretched on either the positive or negative pulse to accommodate the transition from the free-running clock to a data synchronous clock domain. When the speed of the PHY changes, a similar stretching of the positive or negative pulses is allowed. No glitch is allowed on the clock signals during clock speed transitions. This interface operates at 10- and 100-Mbps speeds the same way it does at 1000-Mbps mode with the exception that the data may be duplicated on the falling edge of the appropriate clock. The MAC holds the RGMII TX_CLK low until it has ensured that it is operating at the same speed as the PHY. PHY MAC TX_CTRL GTX_CLK TX_D [3:0] RX_CTRL RX_CLK RX_D [3:0] Figure 8-6. RGMII Connections 8.4.2 Serial Management Interface The Serial Management Interface (SMI), provides access to the DP83867 internal register space for status information and configuration. The SMI is compatible with IEEE 802.3-2002 clause 22. The implemented register set consists of the registers required by the IEEE 802.3, plus several others to provide additional visibility and controllability of the DP83867 device. The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock is sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of 25 MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when the bus is idle. 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E DP83867CS, DP83867IS, DP83867E www.ti.com SNLS504D – OCTOBER 2015 – REVISED NOVEMBER 2022 The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the rising edge of the MDC clock. The MDIO pin requires a pullup resistor (2.2 kΩ) which, during IDLE and turnaround, pulls MDIO high. Up to 16 PHYs can share a common SMI bus. To distinguish between the PHYs, a 4-bit address is used. During power-up reset, the DP83867 latches the PHY_ADD configuration pins to determine its address. The DP83867IRPAP 64-pin variant can support up to 32 PHYs and uses a 5-bit address. The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is deasserted. In normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific). The data field is used for both reading and writing. The Start code is indicated by a pattern. This pattern makes sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device may actively drive the MDIO signal during the first bit of turnaround. The addressed DP83867 drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 8-7 shows the timing relationship between MDC and the MDIO as driven and received by the Station (STA) and the DP83867 (PHY) for a typical register read access. For write transactions, the station-management entity writes data to the addressed DP83867, thus eliminating the requirement for MDIO turnaround. The turnaround time is filled by the management entity by inserting . Figure 8-7 shows the timing relationship for a typical MII register write access. The frame structure and general read and write transactions are shown in Table 8-2, Figure 8-7, and Figure 8-8. Table 8-2. Typical MDIO Frame Format TYPICAL MDIO FRAME FORMAT