DP83867IR, DP83867CR
SNLS484G – FEBRUARY 2015 – REVISED OCTOBER 2022
DP83867IR/CR Robust, High Immunity 10/100/1000 Ethernet Physical Layer
Transceiver
1 Features
3 Description
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The DP83867 device is a robust, low power, fully
featured Physical Layer transceiver with integrated
PMD sublayers to support 10BASE-Te, 100BASE-TX
and 1000BASE-T Ethernet protocols. Optimized for
ESD protection, the DP83867 exceeds 8-kV IEC
61000-4-2 (direct contact).
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Ultra low RGMII latency TX < 90ns, RX < 290ns
Time Sensitive Network (TSN) compliant
Low power consumption 457 mW
Exceeds 8000 V IEC 61000-4-2 ESD protection
Meets EN55011 class B emission standards
16 programmable RGMII delay modes on RX/TX
Integrated MDI termination resistors
Programmable MII/GMII/RGMII termination
impedance
WoL (Wake-on-LAN) packet detection
25-MHz or 125-MHz synchronized clock output
Start of Frame Detect for IEEE 1588 time stamp
RJ45 mirror mode
Fully compatible to IEEE 802.3 10BASE-Te,
100BASE-TX, and 1000BASE-T Specification
Cable diagnostics
MII, GMII and RGMII MAC interface options
Configurable I/O voltage (3.3 V, 2.5 V, 1.8 V)
Fast link drop mode
JTAG support
2 Applications
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Motor drives
Industrial factory automation
Field Bus Support
Industrial embedded computing
Wired and wireless communications infrastructure
Test and measurement
Consumer electronics
The DP83867 is designed for easy implementation
of 10/100/1000 Mbps Ethernet LANs. It interfaces
directly to twisted pair media via an external
transformer. This device interfaces directly to the
MAC layer through the IEEE 802.3 Standard Media
Independent Interface (MII), the IEEE 802.3 Gigabit
Media Independent Interface (GMII) or Reduced GMII
(RGMII). The QFP package supports MII/GMII/RGMII
whereas the QFN package supports RGMII.
The
DP83867
provides
precision
clock
synchronization, including a synchronous Ethernet
clock output. It has low latency and provides IEEE
1588 Start of Frame Detection.
The DP83867 consumes only 490mW (PAP) and 457
mW (RGZ) under full operating power. Wake on LAN
can be used to lower system power consumption.
Device Information
PART NUMBER
TEMPERATURE
(1)
BODY SIZE (NOM)
DP83867IRPAP
–40°C to +85°C
QFP (64)
10 mm x 10 mm
DP83867IRRGZ
–40°C to +85°C
QFN (48)
7 mm x 7 mm
DP83867CRRGZ
0°C to +70°C
QFN (48)
7 mm x 7 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
MII (PAP)
GMII (PAP)
RGMII (PAP, RGZ)
Ethernet MAC
PACKAGE
10BASE-Te
100BASE-TX
1000BASE-T
DP83867
10/100/1000 Mbps
Ethernet Physical Layer
25 MHz
Crystal or Oscillator
Magnetics
RJ-45
Status
LEDs
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DP83867IR, DP83867CR
www.ti.com
SNLS484G – FEBRUARY 2015 – REVISED OCTOBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 8
6 Pin Configuration and Functions...................................8
6.1 Unused Pins .............................................................14
7 Specifications................................................................ 15
7.1 Absolute Maximum Ratings...................................... 15
7.2 ESD Ratings............................................................. 15
7.3 Recommended Operating Conditions.......................15
7.4 Thermal Information..................................................16
7.5 Electrical Characteristics...........................................16
7.6 Power-Up Timing...................................................... 18
7.7 Reset Timing............................................................. 19
7.8 MII Serial Management Timing................................. 19
7.9 RGMII Timing............................................................ 19
7.10 GMII Transmit Timing(2) ......................................... 20
7.11 GMII Receive Timing(2) .......................................... 20
7.12 100-Mbps MII Transmit Timing(1) ........................... 20
7.13 100-Mbps MII Receive Timing(2) ............................ 20
7.14 10-Mbps MII Transmit Timing(2) ............................. 21
7.15 10-Mbps MII Receive Timing(2) .............................. 21
7.16 DP83867IR/CR Start of Frame Detection Timing... 21
7.17 Timing Diagrams .................................................... 25
7.18 Typical Characteristics............................................ 30
8 Detailed Description......................................................31
8.1 Overview................................................................... 31
8.2 Functional Block Diagram......................................... 32
8.3 Feature Description...................................................34
8.4 Device Functional Modes..........................................37
8.5 Programming............................................................ 51
8.6 Register Maps...........................................................59
9 Application and Implementation................................ 118
9.1 Application Information............................................118
9.2 Typical Application.................................................. 118
10 Power Supply Recommendations............................125
11 Layout......................................................................... 128
11.1 Layout Guidelines................................................. 128
11.2 Layout Example.................................................... 130
12 Device and Documentation Support........................131
12.1 Documentation Support........................................ 131
12.2 Related Links........................................................ 131
12.3 Receiving Notification of Documentation Updates131
12.4 Support Resources............................................... 131
12.5 Electrostatic Discharge Caution............................131
12.6 Glossary................................................................131
12.7 Trademarks........................................................... 131
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (October 2019) to Revision G (August 2022)
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• Updated Start of Frame Detect for IEEE 1588 time stamp.................................................................................1
• Added following wording to the end of first paragraph in Section 8.4.3.9 "DP83867 devices manufactured
after August, 2022, have an increased random seed value that now includes 255 different seed values to
expedite Auto-MDIX resolution with a link partner."..........................................................................................46
• Removed Reg 0x01D5 Programmable Gain Register (PROG_GAIN)............................................................. 59
• Changed Bit 11:10 SPEED_OPT_ATTEMPT_CNT to RW description in ........................................................79
• Changed bits 15:9, so that bit 12 can be '1'. Bit 7 description updated Section 8.6.31 ................................... 90
• Added Register 0x008A....................................................................................................................................96
• Added Register 0x00B3....................................................................................................................................97
• Added Register 0x00C0....................................................................................................................................97
• Added Register 0x0100.................................................................................................................................... 98
Changes from Revision E (March 2017) to Revision F (October 2019)
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• Added "Time Sensitive Network (TSN) Compliant" to Section 1 ....................................................................... 1
• Changed "Fast Link up / Link Drop Modes" to "Fast Link Drop Mode" in Section 1 .......................................... 1
• Added "Field Bus Support" to Section 2 ............................................................................................................ 1
• Changed 'TX_EN / TX_CTRL' pin type in Pin Functions.................................................................................. 10
• Deleted "NOTE: Internal Pull-Up/Pull-Down resistors on the IO pins are disabled when the device enters
functional mode after power up." from Pin Functions....................................................................................... 10
• Added XI pin voltage ratings to Section 7.1 .....................................................................................................15
• Added XI Input Voltage section to Section 7.5 .................................................................................................16
• Changed links to RGMII timing diagrams in Section 7.9 ................................................................................. 19
• Changed TholdR parameter description in Section 7.9 ..................................................................................... 19
• Added table note explaining how Duty Cycle % must be interpreted in Section 7.9 ....................................... 19
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DP83867IR, DP83867CR
SNLS484G – FEBRUARY 2015 – REVISED OCTOBER 2022
Added table note explaining how Duty Cycle % must be interpreted in Section 7.9 ....................................... 19
Changed Figure 7-10 .......................................................................................................................................21
Changed statement about PHY address in Section 8.4.2 ............................................................................... 41
Added Figure 8-11 ........................................................................................................................................... 46
Deleted "The BIST allows full control of the packet lengths and of the IPG." from Section 8.4.5 ....................48
Deleted mention of ALCD from Section 8.4.6 ..................................................................................................48
Deleted subsection describing ALCD from Section 8.4.6 ................................................................................ 48
Added sentence about the polarity of MDI signals in Section 8.4.6.5 ..............................................................49
Changed 'CRS' strap function from "Fast Link Detect" to "Fast Link Drop" in Table 8-4 ................................. 51
Changed notes after Table 8-4 to be table notes referenced within the table. .................................................51
Added definition for register Bit Name type 'Strap' in Section 8.6 ................................................................... 59
Deleted Advanced Link Cable Diagnostics Control Register (ALCD_CTRL) .................................................. 59
Added PAP package default for '1000BASE-T FULL DUPLEX' in Section 8.6.10 ...........................................69
Changed 'MDI_CROSSOVER' default in Section 8.6.14 .................................................................................72
Added PAP package default for 'SPEED_OPT_EN' in Section 8.6.18 ............................................................ 79
Added Section 8.6.28 ...................................................................................................................................... 88
Changed descriptions of 'FORCE_DROP' and 'FLD_EN' in Section 8.6.29 ....................................................89
Added Section 8.6.30 ...................................................................................................................................... 90
Added 'INT_TST_MODE_1' to Section 8.6.31 .................................................................................................90
Changed 'PORT_MIRROR_EN' default in Section 8.6.31 ...............................................................................90
Added PAP package default for 'RGMII_EN' in Section 8.6.32 ....................................................................... 90
Added Section 8.6.35 ...................................................................................................................................... 93
Changed description of 'STRAP_FLD' from "Fast Link Detect" to "Fast Link Drop" in Section 8.6.38 ............ 95
Added Section 8.6.41 ...................................................................................................................................... 96
Added Section 8.6.42 ...................................................................................................................................... 96
Added RGZ package default for 'RGMII_TX_DELAY_CTRL' in Section 8.6.44 .............................................. 97
Added RGZ package default for 'RGMII_RX_DELAY_CTRL' in Section 8.6.44 ..............................................97
Added Section 8.6.47 ...................................................................................................................................... 97
Added Section 8.6.51 ...................................................................................................................................... 98
Changed capacitor value in Figure 9-2 and added footnotes......................................................................... 119
Added requirements for 2.5-V clock source capacitors in Section 9.2.1.2 .................................................... 121
Added Figure 9-4 ........................................................................................................................................... 121
Added "RMS Jitter" to Table 9-2 .................................................................................................................... 121
Added Section 9.2.1.4 ................................................................................................................................... 123
Changed capacitor placement in Figure 10-1 and footnote about decoupling capacitor placement.............. 125
Changed capacitor placement in Figure 10-2 and footnote about decoupling capacitor placement.............. 125
Changes from Revision C (November 2015) to Revision D (July 2016)
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• Added '(Straps Required)' to RX_DV/RX_CTRL pin in Pin Functions table..................................................... 10
• Changed '1nF' to '1µF' for VDD1P1 and VDD1P0 pin in Pin Functions table...................................................10
• Added Operating Junction Temperature to Section 7.3 ................................................................................... 15
• Changed parameter symbol from VIH to VIH in Section 7.5 ............................................................................ 16
• Added MDC toggling clarification to Section 7.7 ..............................................................................................19
• Changed target strap voltage thresholds in Table 8-3 ..................................................................................... 51
• Changed 'SPEED_SEL1' to 'ANEG_SEL1' in Table 8-4 ..................................................................................51
• Added '(Straps Required)' to RX_DV/RX_CTRL in Table 8-4 ..........................................................................51
• Changed 'SPEED_SEL0' to 'ANEG_SEL' in Table 8-4 ....................................................................................51
• Changed 'SPEED_SEL0' to 'ANEG_SEL0' in Table 8-4 ..................................................................................51
• Changed table name from 'PAP Speed Select Strap Details' to Table 8-5 ...................................................... 51
• Changed 'SPEED_SEL0' and 'SPEED_SEL' to 'ANEG_SEL0' and 'ANEG_SEL1' in Table 8-5 ..................... 51
• Changed table name from 'RGZ Speed Select Strap Details' to Table 8-6 ..................................................... 51
• Changed 'SPEED_SEL' to 'ANEG_SEL' in Table 8-6 ......................................................................................51
• Changed Default state of from 'Strap' to '0' for bit 13 in Table 8-9 ...................................................................59
• Changed Default state of from 'Strap' to '1' for bit 6 in Table 8-9 .....................................................................59
• Changed bit 9 name from 100BASE-T FULL DUPLEX to 1000BASE-T FULL DUPLEX in Table 8-18 .......... 69
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SNLS484G – FEBRUARY 2015 – REVISED OCTOBER 2022
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Changed bit 9 descriptions from half duplex to full duplex in Table 8-18 .........................................................69
Changed 'Interrupt Status and Event Control Register (ISR)' to 'MII Interrupt Control Register (MICR)' in
Section 8.6.16 ..................................................................................................................................................75
Changed Register definition to move a statement from Section 8.6.17 to Section 8.6.16 ...............................75
Changed default of bit 9 from '1' to '0' in Configuration Register 2 (CFG2), Address 0x0014 ......................... 79
Changed default of bits 5:0 from '0' to '0 0111' in Table 8-27 ...........................................................................79
Added Section 8.6.29 register.......................................................................................................................... 89
Changed Name of Bits 6:5 from 'STRAP_SPEED_SEL' to 'STRAP_ANEG_SEL' in Table 8-46 .................... 94
Changed Name of Bit 6 from 'RESERVED' to 'RESERVED (RGZ)' in Table 8-46 .......................................... 94
Changed Name of Bit 5 from 'STRAP_SPEED_SEL (PAP)' to 'STRAP_SPEED_SEL (RGZ)' in Table 8-46 ..94
Changed name of Bit 6:4 from 'RESERVED' to 'RESERVED (PAP)' in Table 8-47 .........................................95
Added description for 'STRAP_RGMII_CLK_SKEW_TX (RGZ)' in Table 8-47 ............................................... 95
Changed name of Bit 2:0 from 'RESERVED' to 'RESERVED (PAP)' in Table 8-47 .........................................95
Added description for 'STRAP_RGMII_CLK_SKEW_RX (RGZ)' in Table 8-47 ...............................................95
Changed default value of bit 4:0 from '10000' to 'TRIM' in Section 8.6.97 .................................................... 106
Changed description for IO_IMPEDANCE_CTRL bits in Section 8.6.97 .......................................................106
Changed Section 10 section...........................................................................................................................125
Added "The 2.5-V VDDA2P5 can come up with or after the 1.8-V VDDA1P8 but not before it" to Section 10 ...
125
Added Figure 10-3 ......................................................................................................................................... 125
Added Table 10-1 ...........................................................................................................................................125
Added note regarding 1.8-V supply sequence if no load exists on 2.5-V supply in Layout ........................... 125
Changes from Revision B (August 2015) to Revision C (November 2015)
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• Changed the title to add DP83867IRRGZ/CRRGZ in the datasheet. ................................................................ 1
• Added part numbers .......................................................................................................................................... 1
• Changed latency bullet point in Section 1for better description of the Low Latency Feature............................. 1
• Changed Power consumption number in Features section................................................................................ 1
• Added Radiated Emissions performance to Section 1 ...................................................................................... 1
• Added MDI Termination Resistor in Section 1 ................................................................................................... 1
• Added Programmable MAC Interface Impedance in ......................................................................................... 1
• Added 'RJ45 Mirror Mode' to Section 1 ............................................................................................................. 1
• Added compatibility to Section 1 ........................................................................................................................1
• Changed Section 1 to merge 'Highlights' and 'Key Specifications' into a single section.................................... 1
• Deleted specification about dual voltage from Section 1 ................................................................................... 1
• Added Dual supply voltage for RGZ devices in Section 1 ................................................................................. 1
• Deleted Auto-Crossover bullet point from Section 1 ..........................................................................................1
• Deleted duplicate Low latency specification ...................................................................................................... 1
• Deleted MDIO bullet point from key specification............................................................................................... 1
• Added MAC interface information in Description ............................................................................................... 1
• Added QFN power Consumption in Description ................................................................................................ 1
• Added Package information for the new devices in the Device Information table.............................................. 1
• Added Device Comparison Table....................................................................................................................... 8
• Changed Pin Functions table to add information about new RGZ devices...................................................... 10
• Changed bypass capacitor information for power pins in Pin Functions table................................................. 10
• Added information about pull-up pull-down resistors in the table note of the table ......................................... 10
• Added Unused Pins section .............................................................................................................................14
• Added Absolute Maximum Ratings table..........................................................................................................15
• Added ESD information about new RGZ devices in Section 7.2 ..................................................................... 15
• Added VDD1P0 information in Recommended Operating Conditions .............................................................15
• Added temperature information about RGZ devices in Recommended Operating Conditions ....................... 15
• Added thermal information for RGZ Devices in Section 7.4 ............................................................................ 16
• Added PMD output voltage data for new RGZ devices in Section 7.5 ............................................................ 16
• Added RGMII TX and RX Latency values in Section 7.9 .................................................................................19
• Added FBD for new RGZ devices in Functional Block Diagram ......................................................................32
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DP83867IR, DP83867CR
SNLS484G – FEBRUARY 2015 – REVISED OCTOBER 2022
Added "Magic Packet should be byte aligned" in Magic Packet Structure section...........................................34
Changed "Auto-MDIX is independent of Auto-Negotiation" to "For 10/100, Auto-MDIX is independent of AutoNegotiation" in Section 8.4.3.9 .........................................................................................................................46
Added Loopback Availability table.................................................................................................................... 46
Changed description for Section 8.4.4.1.4 .......................................................................................................47
Added description for Section 8.4.4.2 ..............................................................................................................47
Deleted mention of ALCD from Section 8.4.6 ..................................................................................................48
Changed "improperly-terminated cables with ±1m accuracy" to "improperly-terminated cables, and crossed
pairs wires with ±1m accuracy" in Section 8.4.6.1 ...........................................................................................48
Changed Mirror Mode Configuration table........................................................................................................49
Added internal resistor to the diagram inFigure 8-12 .......................................................................................51
Added Target voltage range in Table 8-3 ......................................................................................................... 51
Added strapping information for RGZ devices in Table 8-4 ............................................................................. 51
Changed incorrect pin number for LED_1 and LED_0 in Table 8-4 table.........................................................51
Added RGMII TX and RX Skew Strap information to Table 8-4 ...................................................................... 51
Added Table 8-6 ...............................................................................................................................................51
Added Table 8-7 ...............................................................................................................................................51
Added Table 8-8 ...............................................................................................................................................51
Added information regarding address configuration of RGZ devices to Section 8.5.4 .................................... 55
Added Power Saving Modes section................................................................................................................ 57
Deleted repeated bits from Auto-Negotiate Expansion Register ..................................................................... 66
Changed Bit 13 description in Register 0x14 ...................................................................................................79
Deleted "in Robust Auto MDI-X modes" in bit 15 description of Section 8.6.25 .............................................. 85
Added "ms" to timer values in bit 13:12 in Section 8.6.25 ............................................................................... 85
Deleted Registers FLD_CFG and FLD_THR_CFG from Datasheet................................................................ 87
Added Section 8.6.28 ...................................................................................................................................... 88
Added Section 8.6.30 ...................................................................................................................................... 90
Changed description for bit 11 in Section 8.6.34 ............................................................................................. 92
Added information in bit 10:7 description for Section 8.6.34 ........................................................................... 92
Added Section 8.6.35 ...................................................................................................................................... 93
Added Section 8.6.41 ...................................................................................................................................... 96
Added Section 8.6.42 ...................................................................................................................................... 96
Added Section 8.6.47 ...................................................................................................................................... 97
Added Section 8.6.51 ...................................................................................................................................... 98
Added comment about RGZ devices in Section 8.6.98 ................................................................................. 108
Added comment about RGZ devices in Section 8.6.99 ................................................................................. 110
Added GPIO_MUX_CTRL register for RGZ devices.......................................................................................111
Added TDR registers 0x0190 to 0x01A4.........................................................................................................112
Added TDR registers.......................................................................................................................................112
Added footnote about voltage level for RGZ devices in Figure 10-1 ............................................................. 125
Added Comment for VDDA1P8 pins in Figure 10-1. ..................................................................................... 125
Added footnote about Voltage level for RGZ devices in Figure 10-2 .............................................................125
Added power down supply sequence sentence in Section 10 .......................................................................125
Changes from Revision A (June 2015) to Revision B (August 2015)
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• Added "Power consumption as low as 490 mW" to the Section 1 list................................................................ 1
• Changed Section 3 text From: "The DP83867 consumes only 565 mW" To: "The DP83867 consumes only
490 mW"............................................................................................................................................................. 1
• Changed Pin RBIAS Description From: "A 10 kΩ +/-1% resistor" To: "A 11 kΩ ±1% resistor"......................... 10
• Changed Power consumption, 2 supplies TYP value From 565 mW To 530 mW in the Section 7.5 .............. 16
• Changed Power consumption, optional 3rd supply TYP value From 545 mW To 490 mW in the Section 7.5 ....
16
• Changed Register address: From: "BICSR1 register (0x0039)" To: "BICSR2 register (0x0072)", and changed
From: "read from the BISCR register (0x0016h)" To: "read from the STS2 register (0x0017h)" in the Section
8.4.5 .................................................................................................................................................................48
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Changed section Section 8.6.39 and Table 8-48 From: Address 0x0039 To: Address 0x0071........................95
Changed section Section 8.6.40 and Table 8-49 From: Address 0x003A To: Address 0x0072....................... 95
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DP83867IR, DP83867CR
SNLS484G – FEBRUARY 2015 – REVISED OCTOBER 2022
Changes from Revision * (February 2015) to Revision A (June 2015)
Page
• Changed the document title From: "Robust, Low Power" To: "Robust, High Immunity" .................................... 1
• Changed the Section 1 listed under "Highlights" ............................................................................................... 1
• Changed the Section 2 list .................................................................................................................................1
• Changed the Section 3 text and layout ..............................................................................................................1
• Added storage temperature to Section 7.1 ...................................................................................................... 15
• Added TF fall time = 0.75 ns (Max) in Section 7.9 ........................................................................................... 19
• Added T4, MDI to GMII Latency = 264 ns (NOM) to Section 7.11. ..................................................................20
• Added section Section 8.3.2.1 ......................................................................................................................... 36
• Moved text From the end of Table 8-9 To Section 8.6.3 .................................................................................. 62
• Changed format of loopback control bits in Table 8-29 "BIST Control Register (BISCR)" ...............................80
• Changed BIT NAME (11:8) From: "LED_ACT_SEL To: LED_2_SEL in Table 8-31 ........................................ 82
• Changed BIT NAME (7:4) From: "LED_SPD_SEL To: LED_1_SEL in Table 8-31 ..........................................82
• Changed BIT NAME (3:0 From: "LED_LNK_SEL To: LED_0_SEL in Table 8-31 ........................................... 82
• Added Section 8.6.36 register.......................................................................................................................... 93
• Changed the title of Table 8-47 from: Address 0x006FE to: Address 0x006F .................................................95
• Added Section 8.6.48 register.......................................................................................................................... 98
• Changed default of bits 12:8 to 0 1100 in Table 8-106 .................................................................................. 106
• Deleted text "of the 64-HTQFP package" from the second paragraph in section Section 9.2.1.1 ................. 119
• Deleted text "for MII Mode" from the second paragraph in section Section 9.2.1.2 ...................................... 121
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SNLS484G – FEBRUARY 2015 – REVISED OCTOBER 2022
5 Device Comparison
Table 5-1. Device Features Comparison
DEVICE
MAC
DP83867CRRGZ
RGMII
TEMPERATURE RANGE
0°C
70°C
TEMPERATURE GRADE
Commercial
DP83867IRRGZ
RGMII
–40°C
85°C
Industrial
DP83867IRPAP
MII/GMII/RGMII
–40°C
85°C
Industrial
RX_D5/GPIO
RX_D6/GPIO
RXD_7/GPIO
TX_EN/TX_CTRL
RX_DV/RX_CTRL
RX_ER/GPIO
COL/GPIO
VDDIO
CS/GPIO
VDD1P1
RESET_N
INT/PWDN
LED_2
LED_1
LED_0
VDDA1P8
6 Pin Configuration and Functions
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RESERVED
1
48
RX_D4/GPIO
TD_P_A
2
47
RX_D3
TD_M_A
3
46
RX_D2
VDDA2P5
4
45
RX_D1
TD_P_B
5
44
RX_D0
TD_M_B
6
43
RX_CLK
RESERVED
7
42
VDD1P1
VDD1P1
8
41
VDDIO
RESERVED
9
40
GTX_CLK
DP83867
TD_P_C
10
39
TX_ER
TD_M_C
11
38
TX_D0
VDDA2P5
12
37
TX_D1
TD_P_D
13
36
TX_D2
TD_M_D
14
35
TX_D3
15
34
TX_D4
16
33
TX_D5
RBIAS
RESERVED
TX_D6
TX_D7
TX_CLK
VDD1P1
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_CLK
JTAG_TRSTN
VDDIO
CLK_OUT
MDIO
MDC
X_I
X_O
VDDA1P8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 6-1. PAP Package 64-Pin HTQFP Top View
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VDDA1P8
LED_0
LED_1
LED_2
INT/PWDN
RESET_N
VDD1P0
VDDIO
GPIO_1
GPIO_0
RX_CTRL
TX_CTRL
SNLS484G – FEBRUARY 2015 – REVISED OCTOBER 2022
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47
46
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44
43
42
41
40
39
38
37
TD_P_A
1
36
RX_D3
TD_M_A
2
35
RX_D2
VDDA2P5
3
34
RX_D1
TD_P_B
4
33
RX_D0
DP83867
TD_M_B
5
32
RX_CLK
31
VDD1P0
VDDA2P5
9
28
TX_D0
TD_P_D
10
27
TX_D1
TD_M_D
11
26
TX_D2
RBIAS
12
25
TX_D3
13
14
15
16
17
18
19
20
21
22
23
24
VDD1P0
GTX_CLK
JTAG_TDI
29
JTAG_TMS
DAP = GND
JTAG_TDO
8
JTAG_CLK
TD_M_C
VDDIO
VDDIO
CLK_OUT
30
MDIO
48-pin QFN Package
MDC
7
X_I
TD_P_C
X_O
6
VDDA1P8
VDD1P0
TOP VIEW
(not to scale)
Figure 6-2. RGZ Package 48-Pin QFN Top View
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Table 6-1. Pin Functions
PIN
NAME
HTQFP
MAC INTERFACES
TX_CLK
VQFN
TYPE(1)
DESCRIPTION
O
MII TRANSMIT CLOCK: TX_CLK is a continuous clock signal driven by the
PHY during 10 Mbps or 100 Mbps MII mode. TX_CLK clocks the data or error
out of the MAC layer and into the PHY.
RGMII
30
The TX_CLK clock frequency is 2.5 MHz in 10BASE-Te and 25 MHz in
100BASE-TX mode.
TX_D7
31
I, PD
GMII TRANSMIT DATA Bit 7: This signal carries data from the MAC to the
PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D6
30
I, PD
GMII TRANSMIT DATA Bit 6: This signal carries data from the MAC to the
PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D5
33
I, PD
GMII TRANSMIT DATA Bit 5: This signal carries data from the MAC to the
PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D4
34
I, PD
GMII TRANSMIT DATA Bit 4: This signal carries data from the MAC to the
PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D3
35
25
I, PD
TRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in
GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to
the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit
clock TX_CLK.
TX_D2
36
26
I, PD
TRANSMIT DATA Bit 2: This signal carries data from the MAC to the PHY in
GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to
the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit
clock TX_CLK.
I, PD
TRANSMIT DATA Bit 1: This signal carries data from the MAC to the PHY in
GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to
the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit
clock TX_CLK.
I, PD
TRANSMIT DATA Bit 0: This signal carries data from the MAC to the PHY in
GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to
the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit
clock TX_CLK.
TX_D1
TX_D0
37
38
27
28
GMII TRANSMIT ERROR: This signal is used in GMII mode to force the PHY
to transmit invalid symbols. The TX_ER signal is synchronous to the GMII
transmit clock GTX_CLK.
TX_ER
39
I, PD
In MII 4B nibble mode, assertion of Transmit Error by the controller causes
the PHY to issue invalid symbols followed by Halt (H) symbols until
deassertion occurs.
In GMII mode, assertion causes the PHY to emit one or more code-groups
that are invalid data or delimiter in the transmitted frame.
GTX_CLK
40
29
I, PD
GMII and RGMII TRANSMIT CLOCK: This continuous clock signal is sourced
from the MAC layer to the PHY. Nominal frequency is 125 MHz.
RECEIVE CLOCK: Provides the recovered receive clocks for different modes
of operation:
RX_CLK
43
32
O
2.5 MHz in 10-Mbps mode.
25 MHz in 100-Mbps mode.
125 MHz in 1000-Mbps GMII and RGMII mode.
RX_D0
44
33
S, O, PD
RECIEVE DATA Bit 0: This signal carries data from the PHY to the MAC in
GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RX_D1
45
34
O, PD
RECIEVE DATA Bit 1: This signal carries data from the PHY to the MAC in
GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RX_D2
46
35
S, O, PD
RECIEVE DATA Bit 2: This signal carries data from the PHY to the MAC in
GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RX_D3
47
36
O, PD
RECIEVE DATA Bit 3: This signal carries data from the PHY to the MAC in
GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
10
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Table 6-1. Pin Functions (continued)
PIN
NAME
HTQFP
VQFN
TYPE(1)
DESCRIPTION
RX_D4
48
S, O, PD
RECIEVE DATA Bit 4: This signal carries data from the PHY to the MAC in
GMII mode. It is synchronous to the receive clock RX_CLK.
RX_D5
49
S, O, PD
RECIEVE DATA Bit 5: This signal carries data from the PHY to the MAC in
GMII mode. It is synchronous to the receive clock RX_CLK.
RX_D6
50
S, O, PD
RECIEVE DATA Bit 6: This signal carries data from the PHY to the MAC in
GMII mode. It is synchronous to the receive clock RX_CLK.
RX_D7
51
S, O, PD
RECIEVE DATA Bit 7: This signal carries data from the PHY to the MAC in
GMII mode. It is synchronous to the receive clock RX_CLK.
TX_EN / TX_CTRL
52
37
I, PD
TRANSMIT ENABLE or TRANSMIT CONTROL: In MII or GMII mode,it is an
active high input sourced from MAC layer to indicate transmission data is
available on the TXD.
In RGMII mode, it combines the transmit enable and the transmit error signals
of GMII mode using both clock edges.
RX_DV / RX_CTRL
53
38
S, O, PD
(Straps Required)
RX_ER / GPIO
O, PD
RECEIVE DATA VALID or RECEIVE CONTROL: In MII and GMII modes, it
is asserted high to indicate that valid data is present on the corresponding
RXD[3:0] in MII mode and RXD[7:0] in GMII mode.
In RGMII mode, the receive data available and receive error are combined
(RXDV_ER) using both rising and falling edges of the receive clock
(RX_CLK).
RECEIVE ERROR: In 10 Mbps, 100 Mbps and 1000 Mbps mode this active
high output indicates that the PHY has detected a Receive Error. The RX_ER
signal is synchronous with the receive clock (RX_CLK).
In RGMII, the RX_ER pin is not used.
COL / GPIO
O, PD
COLLISION DETECT: Asserted high to indicate detection of a collision
condition (assertion of CRS due to simultaneous transmit and receive activity)
in Half-Duplex modes. This signal is not synchronous to either MII clock
(GTX_CLK, TX_CLK or RX_CLK).
This signal is not defined and stays low for Full-Duplex modes.
In RGMII mode, COL is not used.
CARRIER SENSE: CRS is asserted high to indicate the presence of a carrier
due to receive or transmit activity in Half-Duplex mode.
CRS
56
S, O, PD
For 10BASE-Te and 100BASE-TX Full-Duplex operation CRS is asserted
when a received packet is detected. This signal is not defined for 1000BASET Full-Duplex mode.
In RGMII mode, CRS is not used.
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Table 6-1. Pin Functions (continued)
PIN
NAME
HTQFP
VQFN
TYPE(1)
DESCRIPTION
GENERAL PURPOSE I/O
GPIO_0
39
S, O, PD
General Purpose I/O: This signal provides a multi-function configurable I/O.
Please refer to the GPIO_MUX_CTRL register for details.
GPIO_1
40
S, O, PD
General Purpose I/O: This signal provides a multi-function configurable I/O.
Please refer to the GPIO_MUX_CTRL register for details.
16
I, PD
MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial
management input/output data. This clock may be asynchronous to the MAC
transmit and receive clocks. The maximum clock rate is 25MHz and no
minimum.
I/O
MANAGEMENT DATA I/O: Bi-directional management instruction/data signal
that may be sourced by the management station or the PHY. This pin requires
pullup resistor. The IEEE specified resistor value is 1.5kΩ, but a 2.2kΩ is
acceptable.
MANAGEMENT INTERFACE
MDC
20
MDIO
21
17
INTERRUPT / POWER DOWN:
The default function of this pin is POWER DOWN.
INT / PWDN
60
44
I/O, PU
POWER DOWN: Asserting this signal low enables the Power Down mode of
operation. In this mode, the device will power down and consume minimum
power. Register access will be available through the Management Interface to
configure and power up the device.
INTERRUPT: This pin may be programmed as an interrupt output instead of
a Power down input. In this mode, Interrupts will be asserted low using this
pin. When operating this pin as an interrupt, it is an open-drain architecture.
Register access is required for the pin to be used as an interrupt mechanism.
When operating this pin as an interrupt, an external 2.2kΩ connected to the
VDDIO supply is recommended.
RESET
RESET_N
RESET: The active low RESET initializes or re-initializes the DP83867. All
internal registers will re-initialize to their default state upon assertion of
RESET. The RESET input must be held low for a minimum of 1µs.
59
43
I, PU
XI
19
15
I
CRYSTAL/OSCILLATOR INPUT: 25 MHz oscillator or crystal input (50 ppm)
XO
18
14
O
CRYSTAL OUTPUT: Second terminal for 25 MHz crystal. Must be left floating
if a clock oscillator is used.
CLK_OUT
22
18
O
CLOCK OUTPUT: Output clock
JTAG_CLK
25
20
I, PU
JTAG_TDO
26
21
O
JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most
recent test results are scanned out of the device via TDO.
JTAG_TMS
27
22
I, PU
JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS
pin sequences the Tap Controller (16-state FSM) to select the desired test
instruction.
JTAG_TDI
28
23
I, PU
JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is
scanned into the device via TDI.
JTAG_TRSTN
24
I, PU
JTAG TEST RESET: IEEE 1149.1 Test Reset pin, active low reset provides
for asynchronous reset of the Tap Controller. This reset has no effect on the
device registers.
CLOCK INTERFACE
JTAG INTERFACE
12
JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for
all test logic input and output controlled by the testing entity.
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Table 6-1. Pin Functions (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
HTQFP
VQFN
LED_1
62
46
S, I/O, PD
LED_1: By default, this pin indicates that 1000BASE-T link is established.
Additional functionality is configurable via LEDCR1[7:4] register bits.
LED_0
63
47
S, I/O, PD
LED_0: By default, this pin indicates that link is established. Additional
functionality is configurable via LEDCR1[3:0] register bits.
LED INTERFACE
MEDIA DEPENDENT INTERFACE
TD_P_A
2
1
A
Differential Transmit and Receive Signals
TD_M_A
3
2
A
Differential Transmit and Receive Signals
TD_P_B
5
4
A
Differential Transmit and Receive Signals
TD_M_B
6
5
A
Differential Transmit and Receive Signals
TD_P_C
10
7
A
Differential Transmit and Receive Signals
TD_M_C
11
8
A
Differential Transmit and Receive Signals
TD_P_D
13
10
A
Differential Transmit and Receive Signals
TD_M_D
14
11
A
Differential Transmit and Receive Signals
A
Reserved
12
A
Bias Resistor Connection. A 11 kΩ +/-1% resistor should be connected from
RBIAS to GND.
19, 30, 41
P
I/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a 1µF &
0.1µF capacitor to GND
OTHER PINS
Reserved
RBIAS
1, 7, 9, 16
15
POWER AND GROUND PINS
VDDIO
23, 41, 57
1.8V Analog Supply (+/-5%).
No external supply is required for this pin. When unused, no connections
should be made to this pin.
VDDA1P8
17, 64
13, 48
P
VDDA2P5
4, 12
3, 9
P
2.5V Analog Supply (+/-5%). Each pin requires a 1µF & 0.1µF capacitor to
GND
P
1.1V Analog Supply (+/-5%). Each pin requires a 1µF & 0.1µF capacitor to
GND
6, 24, 31,
42
P
1.0V Analog Supply (+15.5%,-5%). Each pin requires a 1µF & 0.1µF capacitor
to GND
Die Attach
Pad
P
Ground
VDD1P1
8, 29, 42, 58
VDD1P0
Die Attach
Pad
GND
(1)
For additional power savings, an external 1.8V supply can be connected to
these pins. When using an external supply, each pin requires a 1µF & 0.1µF
capacitor to GND.
The functionalities of the pins are defined below.
•
•
•
•
•
•
Type I: Input
Type O: Output
Type I/O: Input /Output
Type PD or PU: Internal Pull-down or Pull-up
Type S: Strap Configuration Pin
Type: A Analog pins
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6.1 Unused Pins
DP83867 has internal pullups or pulldowns on most pins. The data sheet details which pins have internal pullups
or pulldowns and which pins require external pull resistors.
Even though a device may have internal pullup or pulldown resistors, a good practice is to terminate
unused inputs rather than allowing them to float. Floating inputs could result in unstable conditions. This
recommendation does not apply to VDD1P8 pins. When unused, these pins should be left floating. It is
considered a safer practice to pull an unused input pin high or low with a pullup or pulldown resistor. It is
also possible to group together adjacent unused input pins, and as a group pull them up or down using a single
resistor.
14
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
MIN
MAX
VDDA2P5
–0.3
3
VDDA1P8
–0.3
2.1
(VDD1P1/VDD1P0)
–0.3
1.3
3.3-V option
–0.3
3.8
2.5-V option
–0.3
3
1.8-V option
VDDIO
Pins
V
–0.3
2.1
MDI
–0.3
6.5
MAC interface, MDIO, MDC, GPIO
–0.3
VDDIO + 0.3
INT/PWDN, RESET
–0.3
VDDIO + 0.3
JTAG
–0.3
VDDIO + 0.3
XI (Oscillator Clock Input)
–0.3
2.1
V
–60
150
°C
Storage temperature, Tstg
(1)
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/
ESDA/JEDEC JS-001(1)
All pins except Media
Dependent Interface pins
±2500
Media Dependent Interface
pins (IRPAP/IRRGZ) (2)
±8000
Media Dependent Interface
pins (CRRGZ)
±6000
Charged-device model (CDM), per JEDEC specification JESD22-C101(3)
(1)
(2)
(3)
UNIT
V
±1500 (RGZ)
±750 (PAP)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing
with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±8 V and/or ± 2 V may actually have higher
performance.
MDI Pins tested as per IEC 61000-4-2 standards.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDDA2P5
VDDA1P8
VDD1P1 (PAP)
Supply voltage
VDD1P0 (RGZ)
VDDIO
Operating free air temperature
MIN
TYP
MAX
2.375
2.5
2.625
1.71
1.8
1.89
1.045
1.1
1.155
UNIT
0.95
1
1.155
3.3-V option
3.15
3.3
3.45
2.5-V option
2.375
2.5
2.625
1.8-V option
1.71
1.8
1.89
0
25
70
°C
–40
25
85
°C
Commercial (DP83867CRRGZ)
V
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7.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
Commercial (DP83867CRRGZ)
Operating junction temperature
Industrial (DP83867IRRGZ)
Industrial (DP83867IRPAP)
TYP
MAX
UNIT
0
90
°C
–40
105
°C
7.4 Thermal Information
THERMAL METRIC(1)
DP83867IR
DP83867IR,
DP83867CR
PAP (HTQFP)
RGZ (QFN)
UNIT
64 PINS
48 PINS
RθJA
Junction-to-ambient thermal resistance
30.9
30.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
13.6
18.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.9
1.4
°C/W
RθJB
Junction-to-board thermal resistance
15.6
7.5
°C/W
ψJT
Junction-to-top characterization parameter
0.4
0.3
°C/W
ψJB
Junction-to-board characterization parameter
15.5
7.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life
of the product containing it.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.3-V VDDIO
VOH
High level output voltage
IOH = –4 mA
VOL
Low level output voltage
IOL = 4 mA
VIH
High level input voltage
VIL
Low level input voltage
2
V
0.6
1.7
V
V
0.7
V
2.5-V VVDDIO
VOH
High level output voltage
IOH = –4 mA
VOL
Low level output voltage
IOL = 4 mA
VIH
High level input voltage
VIL
Low level input voltage
VDDIO × 0.8
V
0.6
1.7
V
V
0.7
V
1.8-V VDDIO
VOH
High level output voltage
IOH = –1 mA
VOL
Low level output voltage
IOL = 1 mA
VIH
High level input voltage
VIL
Low level input voltage
VDDIO – 0.2
V
0.2
0.7 × VDDIO
V
V
0.2 × VDDIO
V
XI INPUT VOLTAGE
VOSC
Input voltage for 25 MHz
Oscillator
1.5
VIH
High level input voltage
1.4
VIL
Low level input voltage
1.9
Vpp
V
0.45
V
DC CHARACTERISTICS
16
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7.5 Electrical Characteristics (continued)
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life
of the product containing it.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
Input high current
VIN = VDD, TA = –40°C to
+85°C
–10
10
µA
IIL
Input low current
VIN = GND, TA = –40°C to
+85°C
–10
10
µA
IOZ
TRI-STATE output current
VOUT = VDD, VOUT = GND,
TA = –40°C to +85°C
–10
10
µA
CIN
Input capacitance
See (3)
5
pF
PMD OUTPUTS
VOD-10
MDI
VOD-100
MDI
VOD-1000
MDI
IRPAP/IRRGZ
1.54
CRRGZ
IRPAP/IRRGZ
1.96
V Peak
Differential
1.05
V Peak
Differential
0.82
V Peak
Differential
1.75
0.95
CRRGZ
IRPAP/IRRGZ
1.75
1
1
0.67
CRRGZ
0.745
0.745
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7.5 Electrical Characteristics (continued)
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life
of the product containing it.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER CONSUMPTION
PAP
P1000
Power consumption, 2
supplies (1) (2)
530
mW
P1000
Power consumption, optional
3rd supply(1) (2)
490
mW
IDD25
Supply Current, 2 supplies
141
mA
125
mA
22
mA
90
mA
IDD11
125
mA
IDD18
51
mA
IDDIO (1.8 V)
19
mA
IDD11
IDDIO (1.8 V)
IDD25
Supply Current, optional 3rd
supply
RGZ
P1000
Power consumption, 2
supplies (1) (2)
495
mW
P1000
Power consumption, optional
3rd supply(1) (2)
457
mW
IDD25
Supply Current, 2 supplies
137
mA
108
mA
24
mA
86
mA
IDD10
108
mA
IDD18
50
mA
IDDIO (1.8 V)
24
mA
IDD10
IDDIO (1.8 V)
IDD25
(1)
(2)
(3)
Supply Current, optional 3rd
supply
Power consumption represents total operational power for 1000BASE-T.
See Section 10 for details on 2-supply and 3-supply configuration.
Ensured by production test, characterization, or design.
7.6 Power-Up Timing
See Figure 7-13.
TEST CONDITIONS(1)
PARAMETER
MIN
NOM
MAX
UNIT
T1
Post power-up stabilization time prior to MDC MDIO is pulled high for 32-bit serial
preamble for register accesses
management initialization.
200
ms
T2
Hardware configuration latch-in time from
power up
200
ms
T3
Hardware configuration pins transition to
output drivers
64
ns
(1)
18
Hardware Configuration Pins are
described in Section 8.5.1.
Ensured by production test, characterization, or design.
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7.7 Reset Timing
See Figure 7-14.
TEST CONDITIONS (1)
PARAMETER
MIN
NOM
MAX
UNIT
Post RESET stabilization time prior to MDC
preamble for register accesses
MDIO is pulled high for 32-bit serial
management initialization.
MDC may toggle during this period when
MDIO remains high.
195
µs
T2
Hardware configuration latch-in time from the
deassertion of RESET (either soft or hard)
Hardware Configuration Pins are
described in Section 8.5.1.
120
ns
T3
Hardware configuration pins transition to
output drivers
64
ns
T1
T4
(1)
X1 Clock must be stable for a minimum of
1 μs during RESET pulse low time
RESET pulse width
1
µs
Ensured by production test, characterization, or design.
7.8 MII Serial Management Timing
See Figure 7-15.
TEST CONDITIONS(1)
PARAMETER
MIN
NOM
MAX
MDC to MDIO (output) delay time
0
T2
MDIO (input) to MDC setup time
10
ns
T3
MDIO (input) to MDC hold time
10
ns
T4
MDC frequency
(1)
10
UNIT
T1
2.5
ns
25
MHz
Ensured by production test, characterization, or design.
7.9 RGMII Timing
See Figure 7-16 and .Figure 7-17
PARAMETER
TEST CONDITIONS(5)
MIN
NOM
MAX
UNIT
See (1)
–500
0
500
ps
Data to Clock input Skew
(at Receiver)
See (1)
1
1.8
2.6
ns
TsetupT
Data to Clock output Setup
(at Transmitter – internal delay)
See (4)
1.2
2
ns
TholdT
Clock to Data output Hold
(at Transmitter – internal delay)
See (4)
1.2
2
ns
TsetupR
Data to Clock input Setup
(at Reciever – internal delay)
See (4)
1
2
ns
TholdR
Clock to Data input Hold
(at Receiver – internal delay)
See (4)
1
2
ns
Tcyc
Clock Cycle Duration
See (2)
7.2
8
8.8
Duty_G
Duty Cycle for Gigabit
See (3) (7)
45
50
55%
Duty_T
Duty Cycle for 10/100T
See (3) (7)
40
50
60%
TR
Rise Time (20% to 80%)
TF
Fall Time (20% to 80%)
TTXLAT
RGMII to MDI Latency
See (6)
88
ns
MDI to RGMII Latency
(6)
288
ns
TskewT
Data to Clock output Skew
(at Transmitter)
TskewR
TRXLAT
(1)
(2)
(3)
(4)
See
ns
0.75
ns
0.75
ns
When operating without RGMII internal delay, the PCB design requires clocks to be routed such that an additional trace delay of
greater than 1.5 ns is added to the associated clock signal.
For 10-Mbps and 100-Mbps, Tcyc will scale to 400 ns ± 40 ns and 40 ns ± 4 ns.
Duty cycle may be stretched or shrunk during speed changes or while transitioning to a received packet’s clock domain as long as
minimum duty cycle is not violated and stretching occurs for no more that three Tcyc of the lowest speed transitioned between.
Device may operate with or without internal delay.
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(5)
(6)
(7)
Ensured by production test, characterization, or design.
Operating in 1000Base-T .
Duty cycle values are defined in percentages of the nominal clock speed. For example, the minimum Gigabit RGMII clock pulse
duration is 45 % of 8 ns.
7.10 GMII Transmit Timing(2)
See Figure 7-6.
PARAMETER
T1
GTX_CLK Duty Cycle
T2
GTX_CLK Rise / Fall Time
T3
Setup from valid TXD, TX_EN
and TX_ER to rising edge of
GTX_CLK
T4
GTX_CLK Stability
T6
GMII to MDI Latency
MIN
NOM
40%
MAX
UNIT
60%
1
ns
2
ns
Hold from rising edge of
GTX_CLK to invalid TXD,
TX_EN, and TX_ER
T5
(1)
(2)
TEST CONDITIONS
0.5
ns
–100
See (1)
100
72
ppm
ns
Operating in 1000Base-T .
Ensured by production test, characterization, or design.
7.11 GMII Receive Timing(2)
See Figure 7-7.
PARAMETER
T1
Rising edge of RX_CLK to RXD,
RX_DV, and RX_ER delay
T2
RX_CLK Duty Cycle
T3
RX_CLK Rise / Fall Time
T4
MDI to GMII Latency
(1)
(2)
TEST CONDITIONS
MIN
NOM
MAX
0.5
5.5
40%
60%
1
See (1)
264
UNIT
ns
ns
ns
Operating in 1000Base-T.
Ensured by production test, characterization, or design.
7.12 100-Mbps MII Transmit Timing(1)
See Figure 7-8.
MIN
NOM
MAX
T1
TX_CLK High/Low Time
PARAMETER
16
20
24
T2
TXD[3:0], TX_EN Data Setup to
TX_CLK
10
ns
T3
TXD[3:0], TX_EN Data Hold from
TX_CLK
0
ns
(1)
TEST CONDITIONS
UNIT
ns
Ensured by production test, characterization, or design.
7.13 100-Mbps MII Receive Timing(2)
See Figure 7-9.
PARAMETER
T1
RX_CLK High/Low Time
T2
RX_CLK to RXD[3:0], RX_DV,
RX_ER Delay
(1)
(2)
20
TEST CONDITIONS
See
(1)
MIN
NOM
MAX
16
20
24
10
30
UNIT
ns
ns
RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high
and low times will not be violated.
Ensured by production test, characterization, or design.
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7.14 10-Mbps MII Transmit Timing(2)
See Figure 7-10.
PARAMETER
T1
TX_CLK High/Low Time
T2
TXD[3:0], TX_EN Data Setup to
TX_CLK falling edge
T3
TXD[3:0], TX_EN Data Hold from
TX_CLK rising edge
(1)
(2)
TEST CONDITIONS
See
(1)
MIN
NOM
MAX
UNIT
190
200
210
ns
25
ns
0
ns
An attached MAC should drive the transmit signals using the positive edge of TX_CLK. As shown below, the MII signals are sampled
on the falling edge of TX_CLK.
Ensured by production test, characterization, or design.
7.15 10-Mbps MII Receive Timing(2)
See Figure 7-11.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
160
200
240
ns
300
ns
T1
RX_CLK High/Low Time
T2
RXD[3:0], RX_DV transition delay
from RX_CLK rising edge
100
T3
RX_CLK rising edge delay from
RXD[3:0], RX_DV valid data
100
(1)
(2)
See
(1)
RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low
times will not be violated.
Ensured by production test, characterization, or design.
7.16 DP83867IR/CR Start of Frame Detection Timing
See Figure 7-12.
PARAMETER
T1
T2
Transmit SFD
variation(1) (2)
Receive SFD variation(1) (2)
TEST CONDITIONS
MIN
1000-Mb Master
0
1000-Mb Slave
100-Mb
(2)
MAX
UNIT
0
ns
0
0
ns
0
16
ns
1000-Mb Master
–8
8
ns
1000-Mb Slave
–8
8
ns
0
0
ns
100-Mb
(1)
NOM
A larger variation may be seen on SFD pulses than the variation specified here. To achieve the determinism specification listed, see
the Section 8.3.2.1 section for a method to compensate for variation in the SFD pulses.
Variation of SFD pulses occurs from link-up to link-up. Packet to packet variation is fixed using the estimation method in Section
8.3.2.1.
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VDD
XI clock
T1
Hardware
RESET_N
32
CLOCKS
MDC
T2
Latch-In of Hardware
Configuration Pins
T3
Dual Function Pins
Become Enabled As Outputs
INPUT
OUTPUT
Figure 7-1. Power-Up Timing
VDD
XI clock
T1
T4
Hardware
RESET_N
32
CLOCKS
MDC
T2
Latch-In of Hardware
Configuration Pins
T3
Dual Function Pins
Become Enabled As Outputs
Input
Output
Figure 7-2. Reset Timing
MDC
T4
T1
MDIO
(output)
MDC
T2
MDIO
(input)
T3
Valid Data
Figure 7-3. MII Serial Management Timing
22
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GTX
(at Transmitter)
TskewT
TXD [8:5][3:0]
TXD [7:4][3:0]
TX_CTL
TXD [3:0]
TXD [8:5]
TXD [7:4]
TXD [4]
TXEN
TXD [9]
TXERR
TskewR
GTX
(at Receiver)
Figure 7-4. RGMII Transmit Multiplexing and Timing Diagram
RXC with Internal
Delay Added
RXC
(Source of Data)
TsetupT
RXD [8:5][3:0]
RXD [7:4][3:0]
RXD [3:0]
RXD [8:5]
RXD [7:4]
TholdT
RX_CTL
RXD [4]
RXDV
RXD [9]
RXERR
RXC
(at Receiver)
TholdR
TsetupR
Figure 7-5. RGMII Receive Multiplexing and Timing Diagram
tT5t
tT1t
GTX_CLK
T2
T4
T2
TXD [7:0]
TX_EN
TX_ER
T3
tT6t
MDI
Start of Frame
Figure 7-6. GMII Transmit Timing
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tT2t
T3
T3
RX_CLK
tT1t
RXD [7:0]
RX_DV
RX_ER
Valid Data
tT4t
Start of Frame
MDI
Figure 7-7. GMII Receive Timing
T1
T1
TX_CLK
T2
TXD[3:0]
TX_EN
T3
Valid Data
Figure 7-8. 100-Mbps MII Transmit Timing
T1
T1
RX_CLK
T2
RXD[3:0]
RX_DV
RX_ER
Valid Data
Figure 7-9. 100-Mbps MII Receive Timing
T1
T1
TX_CLK
T2
T3
TXD[3:0]
Valid Data
TX_EN
Figure 7-10. 10-Mbps MII Transmit Timing
24
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T1
T1
RX_CLK
T2
T3
RXD[3:0]
RX_DV
Valid Data
Figure 7-11. 10-Mbps MII Receive Timing
T1
TX SFD
Packet
Transmitted
on Wire
Packet
Received
from Wire
T2
RX SFD
Figure 7-12. DP83867IR/CR Start of Frame Delimiter Timing
7.17 Timing Diagrams
VDD
XI clock
T1
Hardware
RESET_N
32
CLOCKS
MDC
T2
Latch-In of Hardware
Configuration Pins
T3
Dual Function Pins
Become Enabled As Outputs
INPUT
OUTPUT
Figure 7-13. Power-Up Timing
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VDD
XI clock
T1
T4
Hardware
RESET_N
32
CLOCKS
MDC
T2
Latch-In of Hardware
Configuration Pins
T3
Dual Function Pins
Become Enabled As Outputs
Input
Output
Figure 7-14. Reset Timing
MDC
T4
T1
MDIO
(output)
MDC
T2
MDIO
(input)
T3
Valid Data
Figure 7-15. MII Serial Management Timing
GTX
(at Transmitter)
TskewT
TXD [8:5][3:0]
TXD [7:4][3:0]
TX_CTL
TXD [3:0]
TXD [8:5]
TXD [7:4]
TXD [4]
TXEN
TXD [9]
TXERR
TskewR
GTX
(at Receiver)
Figure 7-16. RGMII Transmit Multiplexing and Timing Diagram
26
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RXC with Internal
Delay Added
RXC
(Source of Data)
TsetupT
RXD [8:5][3:0]
RXD [7:4][3:0]
RXD [3:0]
RXD [8:5]
RXD [7:4]
TholdT
RX_CTL
RXD [4]
RXDV
RXD [9]
RXERR
RXC
(at Receiver)
TholdR
TsetupR
Figure 7-17. RGMII Receive Multiplexing and Timing Diagram
tT5t
tT1t
GTX_CLK
T2
T4
T2
TXD [7:0]
TX_EN
TX_ER
T3
tT6t
MDI
Start of Frame
Figure 7-18. GMII Transmit Timing
tT2t
T3
T3
RX_CLK
tT1t
RXD [7:0]
RX_DV
RX_ER
Valid Data
tT4t
MDI
Start of Frame
Figure 7-19. GMII Receive Timing
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T1
T1
TX_CLK
T2
TXD[3:0]
TX_EN
T3
Valid Data
Figure 7-20. 100-Mbps MII Transmit Timing
T1
T1
RX_CLK
T2
RXD[3:0]
RX_DV
RX_ER
Valid Data
Figure 7-21. 100-Mbps MII Receive Timing
T1
T1
TX_CLK
T2
T3
TXD[3:0]
Valid Data
TX_EN
Figure 7-22. 10-Mbps MII Transmit Timing
T1
T1
RX_CLK
T2
RXD[3:0]
RX_DV
T3
Valid Data
Figure 7-23. 10-Mbps MII Receive Timing
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T1
TX SFD
Packet
Transmitted
on Wire
Packet
Received
from Wire
T2
RX SFD
Figure 7-24. DP83867IR/CR Start of Frame Delimiter Timing
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C1
(500 mV/DIV)
C1
(200 mV/DIV)
7.18 Typical Characteristics
Time (4 ns/DIV)
Time (32 ns/DIV)
1000Base-T Signaling
(Test Mode TM2 Output)
Figure 7-25. 1000Base-T Signaling
30
100Base-TX Signaling
(Scrambled Idles)
Figure 7-26. 100Base-TX Signaling
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8 Detailed Description
8.1 Overview
The DP83867 is a fully featured Physical Layer transceiver with integrated PMD sub-layers to support 10BASETe, 100BASE-TX and 1000BASE-T Ethernet protocols.
The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet LANs. It interfaces directly
to twisted pair media via an external transformer. This device interfaces directly to the MAC layer through the
IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface
(GMII), or Reduced GMII (RGMII).
The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has
low jitter, low latency and provides IEEE 1588 Start of Frame Detection for time sensitive protocols.
The DP83867 offers innovative diagnostic features including dynamic link quality monitoring for fault prediction
during normal operation. It can support up to 130-m cable length.
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8.2 Functional Block Diagram
MGNT
& PHY CNTRL
RXD[7:0]
GMII
1000BASE-T
Block
10BASE-Te
Block
MII
RX_DV
MUX / DMUX
MII
100BASE-TX
Block
RX_ER
CRS
COL
RX_CLK
TX_CLK
TXD[7:0]
TX_EN
TX_ER
GTX_CLK
COMBINED MII / GMII / RGMII INTERFACE
Interrupt
MDC
MDIO
MGMT INTERFACE
MII
100BASE-TX
PCS
10BASE-Te PLS
100BASE-TX
PMA
10BASE-Te
PMA
GMII
1000BASE-T
PCS
Wake on
LAN
Echo cancellation
Crosstalk cancellation
ADC
Decode / Descramble
Equalization
Timing
Skew compensation
BLW
10000BASE-T
PMA
AutoNegotiation
100BASE-TX
PMD
Manchester
10 Mbps
PAM-5
17 Level PR Shaped
125 Msymbols/s
MLT-3
100 Mbps
DAC / ADC
SUBSYSTEM
TIMING
DRIVERS /
RECEIVERS
DAC / ADC
TIMING BLOCK
MAGNETICS
4-pair CAT-5 Cable
Figure 8-1. DP83867IRPAP
32
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MGNT
& PHY CNTRL
100BASE-TX
Block
10BASE-Te PLS
100BASE-TX
PMA
10BASE-Te
PMA
RXD[3:0]
RX_CTRL
RX_CLK
MUX / DMUX
1000BASE-T
Block
10BASE-Te
Block
100BASE-TX
PCS
TX_CTRL
TXD[3:0]
GTX_CLK
RGMII INTERFACE
Interrupt
MDC
MDIO
MGMT INTERFACE
1000BASE-T
PCS
Wake on
LAN
Echo cancellation
Crosstalk cancellation
ADC
Decode / Descramble
Equalization
Timing
Skew compensation
BLW
10000BASE-T
PMA
AutoNegotiation
Manchester
10 Mbps
100BASE-TX
PMD
MLT-3
100 Mbps
PAM-5
17 Level PR Shaped
125 Msymbols/s
DAC / ADC
SUBSYSTEM
TIMING
DRIVERS /
RECEIVERS
DAC / ADC
TIMING BLOCK
MAGNETICS
4-pair CAT-5 Cable
Figure 8-2. DP83867IRRGZ, DP83867CRRGZ
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8.3 Feature Description
8.3.1 WoL (Wake-on-LAN) Packet Detection
Wake-on-LAN provides a mechanism for bringing the DP83867 out of a low-power state using a special Ethernet
packet called a Magic Packet. The DP83867 can be configured to generate an interrupt to wake up the MAC
when a qualifying packet is received. An option is also available to generate a signal on a GPIO when a
qualifying signal is received.
Note
Please ensure that BMCR (register address 0x0000) bit[10] is disabled, when using the WoL feature.
This bit enables the MII ISOLATE function used to disable the MAC interface of the PHY, also
disabling the WoL interrupt on this PHY. If the WoL feature is needed while MII ISOLATE is enabled
please use TI's DP83869HM PHY instead.
The Wake-on-LAN feature includes the following functionality:
• Identification of magic packets in all supported speeds (1000BASE-T, 100BASE-TX, 10BASE-Te)
• Wakeup interrupt generation upon receiving a valid magic packet
• CRC checking of magic packets to prevent interrupt generation for invalid packets
In addition to the basic magic packet support, the DP83867 also supports:
• Magic packets that include secure-on password
• Pattern match – one configurable 64 byte pattern of that can wake up the MAC similar to magic packet
• Independent configuration for Wake on Broadcast and Unicast packet types.
8.3.1.1 Magic Packet Structure
When configured for Magic Packet mode, the DP83867 scans all incoming frames addressed to the node for a
specific data sequence. This sequence identifies the frame as a Magic Packet frame.
Note
The Magic Packet should be byte aligned.
A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as SOURCE
ADDRESS, DESTINATION ADDRESS (which may be the receiving station’s IEEE address or a BROADCAST
address), and CRC.
The specific Magic Packet sequence consists of 16 duplications of the IEEE address of this node, with no breaks
or interruptions, followed by secure-on password if security is enabled. This sequence can be located anywhere
within the packet, but must be preceded by a synchronization stream. The synchronization stream is defined as
6 bytes of FFh.
34
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DEST (6 bytes)
SRC (6 bytes)
MISC (X bytes, X >= 0)
))« )) (6 bytes)
MAGIC pattern
DEST * 16
SecureOn Password (6 bytes)
Only if Secure-On is enabled
MISC (Y bytes, Y >= 0)
CRC (4 bytes)
Figure 8-3. Magic Packet Structure
8.3.1.2 Magic Packet Example
The following is an example Magic Packet for a Destination Address of 11h 22h 33h 44h 55h 66h and a
SecureOn Password 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh:
DESTINATION SOURCE MISC FF FF FF FF FF FF 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11
22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44
55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11
22 33 44 55 66 11 22 33 44 55 66 2A 2B 2C 2D 2E 2F MISC CRC
8.3.1.3 Wake-on-LAN Configuration and Status
Wake-on-LAN functionality is configured through the RXFCFG register (address 0x0134). Wake-on-LAN status
is reported in the RXFSTS register (address 0x0135).
8.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
The DP83867 supports an IEEE 1588 indication pulse at the SFD (start frame delimiter) for the receive and
transmit paths. The pulse can be delivered to various pins. The pulse indicates the actual time the symbol is
presented on the lines (for transmit), or the first symbol received (for receive). The exact timing of the pulse can
be adjusted through register. Each increment of phase value is an 8-ns step.
Figure 8-4. IEEE 1588 Message Timestamp Point
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The SFD pulse output can be configured using the GPIO Mux Control registers, GPIO_MUX_CTRL1 (register
address 0x0171) and GPIO_MUX_CTRL2 (register address 0x0172). The RGZ devices support only register
GPIO_MUX_CTRL2 (address 0x172).
For more information about configuring the DP83867's SFD feature, see the How to Configure DP83867 Start of
Frame application report (SNLA242).
8.3.2.1 SFD Latency Variation and Determinism
Time stamping packet transmission and reception using the RX_CTRL and TX_CTRL signals of RGMII is not
accurate enough for latency sensitive protocols. SFD pulses offers system designers a method to improve the
accuracy of packet time stamping. The SFD pulse, while varying less than RGMII signals inherently, still exhibits
latency variation due to the defined architecture of 1000BASE-T. This section provides a method to determine
when an SFD latency variation has occurred and how to compensate for the variation in system software to
improve timestamp accuracy.
In the following section the terms baseline latency and SFD variation are used. Baseline latency is the time
measured between the TX_SFD pulse to the RX_SFD pulse of a connected link partner, assuming an Ethernet
cable with all 4 pairs perfectly matched in propagation time. In the scenario where all 4 pairs being perfectly
matched, a 1000BASE-T PHY will not have to align the 4 received symbols on the wire and will not introduce
extra latency due to alignment.
TX SFD
Baseline Latency
RX SFD
SFD Variation
Figure 8-5. Baseline Latency and SFD Variation in Latency Measurement
SFD variation is additional time added to the baseline latency before the RX_SFD pulse when the PHY must
introduce latency to align the 4 symbols from the Ethernet cable. Variation can occur when a new link is
established either by cable connection, auto-negotiation restart, PHY reset, or other external system effects.
During a single, uninterrupted link, the SFD variation will remain constant.
The DP83867 can limit and report the variation applied to the SFD pulse while in the 1000-Mb operating mode.
Before a link is established in 1000-Mb mode, the Sync FIFO Control Register (register address 0x00E9) must
be set to value 0xDF22. The below SFD variation compensation method can only be applied after the Sync FIFO
Control Register has been initialized and a new link has been established. It is acceptable to set the Sync FIFO
Control register value and then perform a software restart by setting the SW_RESTART bit[14] in the Control
Register (register address 0x001F) if a link is already present.
8.3.2.1.1 1000-Mb SFD Variation in Master Mode
When the DP83867 is operating in 1000-Mb master mode, variation of the RX_SFD pulse can be estimated
using the Skew FIFO Status register (register address 0x0055) bit[7:4]. The value read from the Skew FIFO
Status register bit[7:4] must be multiplied by 8 ns to estimate the RX_SFD variation added to the baseline
latency.
Example: While operating in master 1000-Mb mode, a value of 0x2 is read from the Skew FIFO register bit[7:4].
2 × 8 ns = 16 ns is subtracted from the TX_SFD to RX_SFD measurement to determine the baseline latency.
8.3.2.1.2 1000-Mb SFD Variation in Slave Mode
When the DP83867 is operating in 1000-Mb slave mode, the variation of the RX_SFD pulse can be determined
using the Skew FIFO Status register (register address 0x0055) bit[3:0].The value read from the Skew FIFO
Status register bit[3:0] should be multiplied by 8ns to estimate the RX_SFD variation added to the baseline
latency.
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Example: While operating in slave 1000-Mb mode, a value of 0x1 is read from the Skew FIFO register bit[3:0].
1 × 8 ns = 8 ns is subtracted from the TX_SFD to RX_SFD measurement to determine the baseline latency.
8.3.2.1.3 100-Mb SFD Variation
The latency variation in 100-Mb mode of operation is determined by random process and does not require any
register readout or system level compensation of SFD pulses.
8.3.3 Clock Output
The DP83867 has several internal clocks, including the local reference clock, the Ethernet transmit clock, and
the Ethernet receive clock. An external crystal or oscillator provides the stimulus for the local reference clock.
The local reference clock acts as the central source for all clocking in the device.
The local reference clock is embedded into the transmit network packet traffic and is recovered from the network
packet traffic at the receiver node. The receive clock is recovered from the received Ethernet packet data stream
and is locked to the transmit clock in the partner.
Using the I/O Configuration register (address 0x0170), the DP83867 can be configured to output these internal
clocks through the CLK_OUT pin. By default, the output clock is synchronous to the XI oscillator / crystal input.
Through registers, the output clock can be configured to be synchronous to the receive data at the 125-MHz
data rate or at the divide by 5 rate of 25 MHz. It can also be configured to output the line driver transmit clock.
When operating in 1000Base-T mode, the output clock can be configured for any of the four transmit or receive
channels.
The output clock can be disabled using the CLK_O_DISABLE bit of the I/O Configuration register. It can also be
disabled by default using the Clock Out Disable strap. This strap is only available for the PAP devices. For more
information, see Section 8.5.1.
8.4 Device Functional Modes
8.4.1 MAC Interfaces
The DP83867 supports connection to an Ethernet MAC via the following interfaces: RGMII, GMII, and MII.
The RGMII Disable strap (RX_D6) determines the default state of the MAC interface. The RGMII Disable strap
corresponds to the RGMII Enable (bit 7) in the RGMIICTL register (address 0x0032). When RGMII mode is
disabled, the DP83867 operates in GMII mode.
RGMII ENABLE (Register 0x0032, bit 7)
DEVICE FUNCTIONAL MODE
0x1
RGMII
0x0
GMII
The initial strap value for the RGMII disable is also available in the Strap Configuration Status Register 1
(STRAP_STS1).
8.4.1.1 Reduced GMII (RGMII)
The Reduced Gigabit Media Independent Interface (RGMII) is designed to reduce the number of pins required
to interconnect the MAC and PHY (12 pins for RGMII relative to 24 pins for GMII). To accomplish this goal, the
data paths and all associated control signals are reduced and are multiplexed. Both rising and trailing edges
of the clock are used. For Gigabit operation the GTX_CLK and RX_CLK clocks are 125 MHz, and for 10- and
100-Mbps operation, the clock frequencies are 2.5 MHz and 25 MHz, respectively.
For more information about RGMII timing, see the RGMII Interface Timing Budgets application report
(SNLA243).
8.4.1.1.1 1000-Mbps Mode Operation
All RGMII signals are positive logic. The 8-bit data is multiplexed by taking advantage of both clock edges. The
lower 4 bits are latched on the positive clock edge and the upper 4 bits are latched on trailing clock edge. The
control signals are multiplexed into a single clock cycle using the same technique.
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To reduce power consumption of RGMII interface, TXEN_ER and RXDV_ER are encoded in a manner that
minimizes transitions during normal network operation. This is done by following encoding method. Note that the
value of GMII_TX_ER and GMII_TX_EN are valid at the rising edge of the clock. In RGMII mode, GMII_TX_ER
is presented on TX_CTRL at the falling edge of the GTX_CLK clock. RX_CTRL coding is implemented the same
fashion.
When receiving a valid frame with no error, RX_CTRL = True is generated as a logic high on the rising edge of
RX_CLK and RX_CTRL = False is generated as a logic high at the falling edge of RX_CLK. When no frame is
being received, RX_CTRL = False is generated as a logic low on the rising edge of RX_CLK and RX_CTRL =
False is generated as a logic low on the falling edge of RX_CLK.
TX_CTRL is treated in a similar manner. During normal frame transmission, the signal stays at a logic high for
both edges of GTX_CLK and during the period between frames where no error is indicated, the signal stays low
for both edges.
8.4.1.1.2 1000-Mbps Mode Timing
The DP83867 provides configurable clock skew for the GTX_CLK and RX_CLK to optimize timing across the
interface. The transmit and receive paths can be optimized independently. Both the transmit and receive path
support 16 programmable RGMII delay modes via register configuration.
The timing paths can either be configured for Aligned mode or Shift mode. In Aligned mode, no clock skew is
introduced. In Shift mode, the clock skew can be introduced in 0.25 ns increments (via register configuration).
Configuration of the Aligned mode or Shift mode is accomplished via the RGMII Control Register (RGMIICTL),
address 0x0032. In Shift mode, the clock skew can be adjusted using the RGMII Delay Control Register
(RGMIIDCTL), address 0x0086.
8.4.1.1.3 10- and 100-Mbps Mode
When the RGMII interface is operating in the 100-Mbps mode, the Ethernet Media Independent Interface (MII)
is implemented by reducing the clock rate to 25 MHz. For 10-Mbps operation, the clock is further reduced to 2.5
MHz. In the RGMII 10/100 mode, the transmit clock RGMII TX_CLK is generated by the MAC and the receive
clock RGMII RX_CLK is generated by the PHY. During the packet receiving operation, the RGMII RX_CLK may
be stretched on either the positive or negative pulse to accommodate the transition from the free-running clock
to a data synchronous clock domain. When the speed of the PHY changes, a similar stretching of the positive or
negative pulses is allowed. No glitch is allowed on the clock signals during clock speed transitions.
This interface operates at 10- and 100-Mbps speeds the same way it does at 1000-Mbps mode with the
exception that the data may be duplicated on the falling edge of the appropriate clock.
The MAC holds the RGMII TX_CLK low until it has ensured that it is operating at the same speed as the PHY.
PHY
MAC
TX_CTRL
GTX_CLK
TX_D [3:0]
RX_CTRL
RX_CLK
RX_D [3:0]
Figure 8-6. RGMII Connections
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8.4.1.2 Gigabit MII (GMII)
The Gigabit Media Independent Interface (GMII) is the IEEE defined interface for use between an Ethernet PHY
and an Ethernet MAC. GMII is available on the PAP devices only. The purpose of GMII is to make various
physical media transparent to the MAC layer. The GMII Interface accepts either GMII or MII data, control and
status signals and routes them either to the 1000BASE-T, 100BASE-TX, or 10BASE-Te modules, respectively.
The GMII interface has the following characteristics:
•
•
•
•
•
Supports 10/100/1000 Mbps operation
Data and delimiters are synchronous to clock references
Provides independent 8-bit wide transmit and receive data paths
Provides a simple management interface
Provides for Full-Duplex operation
The GMII interface is defined in IEEE 802.3 Clause 35. In each direction of data transfer, there are Data (an
eight-bit bundle), Delimiter, Error, and Clock signals. GMII signals are defined such that an implementation may
multiplex most GMII signals with the similar PCS service interface defined in IEEE 802.3 Clause 22. Two media
status signals are provided. One indicates the presence of carrier (CRS), and the other indicates the occurrence
of a collision (COL). The MII signal names have been retained and the functions of most signals are the same,
but additional valid combinations of signals have been defined for 1000 Mbps operation.
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The connection diagram for GMII is shown in Figure 8-7.
Figure 8-7. GMII Connections
8.4.1.3 Media Independent Interface (MII)
MII connections are used for 10/100 data. MII is compatible with GMII and will be used for 10/100 data when the
device is configured for GMII. MII is available on PAP devices only.
The DP83867 incorporates the Media Independent Interface (MII) as specified in Clause 22 of the IEEE 802.3
standard. This interface may be used to connect PHY devices to a MAC in 10/100 Mbps systems. This section
describes the nibble wide MII data interface.
The nibble wide MII data interface consists of a receive bus and a transmit bus each with control signals to
facilitate data transfer between the PHY and the upper layer (MAC).
8.4.1.3.1 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3 specification defines the Media Independent Interface. This interface includes a
dedicated receive bus and a dedicated transmit bus. These two data buses, along with various control and
status signals, allow for the simultaneous exchange of data between the DP83867 and the upper layer agent
(MAC).
The receive interface consists of a nibble wide data bus RXD[3:0], a receive error signal RX_ER, a receive data
valid flag RX_DV, and a receive clock RX_CLK for synchronous transfer of the data. The receive clock operates
at either 2.5 MHz to support 10 Mbps operation modes or at 25 MHz to support 100 Mbps operational modes.
The transmit interface consists of a nibble wide data bus TXD[3:0], a transmit enable control signal TX_EN, and
a transmit clock TX_CLK which runs at either 2.5 MHz or 25 MHz. Additionally, the MII includes the carrier sense
signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data
from the network or as a function of transmit data in Half-Duplex mode. The COL signal asserts as an indication
of a collision which can occur during Half-Duplex operation when both a transmit and receive operation occur
simultaneously.
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8.4.1.3.2 Collision Detect
When in Half-Duplex mode, a 10BASE-Te or 100BASE-TX collision is detected when the receive and transmit
channels are active simultaneously. Collisions are reported by the COL signal on the MII.
The COL signal remains set for the duration of the collision. If the PHY is receiving when a collision is detected,
it is reported immediately (through the COL pin).
Collision is not indicated during Full-Duplex operation.
8.4.1.3.3 Carrier Sense
In 10 Mbps operation, Carrier Sense (CRS) is asserted due to receive activity once valid data is detected via the
squelch function. During 100 Mbps operation CRS is asserted when a valid link (SD) and two non-contiguous
zeros are detected on the line.
For 10 or 100 Mbps Half-Duplex operation, CRS is asserted during either packet transmission or reception.
For 10 or 100 Mbps Full-Duplex operation, CRS is asserted only due to receive activity.
CRS is deasserted following an end of packet.
The connection diagram for MII is shown in Figure 8-8.
Figure 8-8. MII Connections
8.4.2 Serial Management Interface
The Serial Management Interface (SMI), provides access to the DP83867 internal register space for status
information and configuration. The SMI is compatible with IEEE 802.3-2002 clause 22. The implemented register
set consists of the registers required by the IEEE 802.3, plus several others to provide additional visibility and
controllability of the DP83867 device.
The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock is
sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of
25 MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when
the bus is idle.
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The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched
on the rising edge of the MDC clock. The MDIO pin requires a pullup resistor (2.2 kΩ) which, during IDLE and
turnaround, pulls MDIO high.
Up to 16 PHYs can share a common SMI bus. To distinguish between the PHYs, a 4-bit address is used.
During power-up reset, the DP83867 latches the PHY_ADD configuration pins to determine its address. The
DP83867IRPAP 64-pin variant can support up to 32 PHYs and uses a 5-bit address.
The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain
valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is deasserted. In
normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field,
thus allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific).
The data field is used for both reading and writing. The Start code is indicated by a pattern. This pattern
makes sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle
bit time inserted between the Register Address field and the Data field. To avoid contention during a read
transaction, no device may actively drive the MDIO signal during the first bit of turnaround. The addressed
DP83867 drives the MDIO with a zero for the second bit of turnaround and follows this with the required data.
Figure 8-9 shows the timing relationship between MDC and the MDIO as driven and received by the Station
(STA) and the DP83867 (PHY) for a typical register read access.
For write transactions, the station-management entity writes data to the addressed DP83867, thus eliminating
the requirement for MDIO turnaround. The turnaround time is filled by the management entity by inserting .
Figure 8-9 shows the timing relationship for a typical MII register write access. The frame structure and general
read and write transactions are shown in Table 8-1, Figure 8-9, and Figure 8-10.
Table 8-1. Typical MDIO Frame Format
TYPICAL MDIO FRAME FORMAT
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