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DRV8803
SLVSAW5C – JULY 2011 – REVISED NOVEMBER 2015
DRV8803 Quad Low-Side Driver IC
1 Features
3 Description
•
The DRV8803 provides a 4-channel low side driver
with overcurrent protection. It has built-in diodes to
clamp turnoff transients generated by inductive loads
and can be used to drive unipolar stepper motors, DC
motors, relays, solenoids, or other loads.
1
•
•
•
•
4-Channel Protected Low-Side Driver
– Four NMOS FETs With Overcurrent Protection
– Integrated Inductive Clamp Diodes
– Parallel Interface
DW Package: 1.5-A (Single Channel On) /
800-mA (Four Channels On) Maximum Drive
Current per Channel (at 25°C)
PWP Package: 2-A (Single Channel On) /
1-A (Four Channels On) Maximum Drive Current
per Channel (at 25°C, With Proper PCB
Heatsinking)
8.2-V to 60-V Operating Supply Voltage Range
Thermally Enhanced Surface Mount Package
2 Applications
•
•
•
•
Relay Drivers
Unipolar Stepper Motor Drivers
Solenoid Drivers
General Low-Side Switch Applications
In the SOIC (DW) package, the DRV8803 can supply
up to 1.5-A (one channel on) or 800-mA (all channels
on) continuous output current per channel, at 25°C. In
the HTSSOP (PWP) package, it can supply up to 2-A
(one channel on) or 1-A (four channels on)
continuous output current per channel, at 25°C with
proper PCB heatsinking.
The device is controlled through a simple parallel
interface.
Internal shutdown functions are provided for over
current
protection,
short
circuit
protection,
undervoltage lockout and overtemperature and faults
are indicated by a fault output pin.
The DRV8803 is available in a 20-pin thermallyenhanced SOIC package and a 16-pin HTSSOP
package (Eco-friendly: RoHS & no Sb/Br).
Device Information(1)
PART NUMBER
DRV8803
PACKAGE
BODY SIZE (NOM)
SOIC (20)
12.80 mm × 7.50 mm
HTSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
8.2V to 60V
5
RESET
nFAULT
Fault
Protection
Clamp
Diodes
1A
M
1A
1A
–
DRV8803
Quad
Low-Side
Driver
+
Controller
EN / IN
+
–
1A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8803
SLVSAW5C – JULY 2011 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specification...........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
9
Power Supply Recommendations...................... 12
9.1 Bulk Capacitance .................................................... 12
10 Layout................................................................... 13
10.1 Layout Guidelines ................................................. 13
10.2 Layout Example .................................................... 13
10.3 Thermal Consideration.......................................... 13
11 Device and Documentation Support ................. 15
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2012) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed Continuous output current, single channel on, TA = 25°C, HTSSOP package MAX value from 1.5 A to 2 A ....... 4
•
Changed Continuous output current, four channels on, TA = 25°C, HTSSOP package MAX value from 0.8 A to 1 A ........ 4
2
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SLVSAW5C – JULY 2011 – REVISED NOVEMBER 2015
5 Pin Configuration and Functions
DW Package
20-Pin SOIC
Top View
VM
VCLAMP
OUT1
OUT2
GND
GND
GND
OUT3
OUT4
nENBL
PWP Package
16-Pin HTSSOP
Top View
1
20
2
19
3
18
4
17
5
6
16
15
7
14
8
13
9
12
10
11
nFAULT
NC
IN1
IN2
GND
GND
GND
IN3
IN4
RESET
VM
VCLAMP
OUT1
OUT2
GND
OUT3
OUT4
nENBL
1
16
2
15
3
14
13
4
5
GND
12
6
11
7
10
8
9
nFAULT
NC
IN1
IN2
GND
IN3
IN4
RESET
Pin Functions
PIN
NAME
SOIC
HTSSOP
I/O (1)
DESCRIPTION
EXTERNAL COMPONENTS
OR CONNECTIONS
POWER AND GROUND
5, 6, 7,
14, 15, 16
5, 12,
PPAD
—
Device ground
All pins must be connected to GND.
1
1
—
Device power supply
Connect to motor supply (8.2 V - 60 V).
nENBL
10
8
I
Enable input
Active low enables outputs – internal pulldown
RESET
11
9
I
Reset input
Active high resets internal logic and OCP –
internal pulldown
IN1
18
14
I
Channel 1 input
IN1 = 1 drives OUT1 low – internal pulldown
IN2
17
13
I
Channel 2input
IN2 = 1 drives OUT2 low – internal pulldown
IN3
13
11
I
Channel 3 input
IN3 = 1 drives OUT3 low – internal pulldown
IN4
12
10
I
Channel 4 input
IN4 = 1 drives OUT4 low – internal pulldown
20
16
OD
Fault
Logic low when in fault condition
(overtemperature, overcurrent)
OUT1
3
3
O
Output 1
Connect to load 1
OUT2
4
4
O
Output 2
Connect to load 2
OUT3
8
6
O
Output 3
Connect to load 3
OUT4
9
7
O
Output 4
Connect to load 4
VCLAMP
2
2
—
Output clamp voltage
Connect to VM supply, or zener diode to VM
supply
GND
VM
CONTROL
STATUS
nFAULT
OUTPUT
(1)
Directions: I = input, O = output, OD = open-drain output
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SLVSAW5C – JULY 2011 – REVISED NOVEMBER 2015
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6 Specification
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VM
Power supply voltage
–0.3
65
V
VOUTx
Output voltage
–0.3
65
V
VCLAMP
Clamp voltage
–0.3
65
V
nFAULT
Output current
20
mA
Peak clamp diode current
2
A
DC or RMS clamp diode current
1
A
nFAULT
Digital input pin voltage
–0.5
7
V
Digital output pin voltage
–0.5
7
V
Internally limited
A
Peak motor drive output current, t < 1 μS
Continuous total power dissipation
See Thermal Information
TJ
Operating virtual junction temperature
–40
150
°C
Tstg
Storage temperature
–60
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(1)
UNIT
±3000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VM
Power supply voltage
VCLAMP
Output clamp voltage (1)
SOIC package (2), TA = 25°C
IOUT
Continuous output current
HTSSOP package
(1)
(2)
(2)
, TA = 25°C
NOM
MAX
UNIT
8.2
60
V
0
60
V
Single channel on
1.5
Four channels on
0.8
Single channel on
2
Four channels on
1
A
VCLAMP is used only to supply the clamp diodes. It is not a power supply input.
Power dissipation and thermal limits must be observed.
6.4 Thermal Information
DRV8803
THERMAL METRIC (1)
DW (SOIC)
PWP (HTSSOP)
20 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
67.7
39.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32.9
24.6
°C/W
RθJB
Junction-to-board thermal resistance
35.4
20.3
°C/W
ψJT
Junction-to-top characterization parameter
8.2
0.7
°C/W
ψJB
Junction-to-board characterization parameter
34.9
20.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
2.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.6
2.1
mA
8.2
V
0.7
V
POWER SUPPLIES
IVM
VM operating supply current
VM = 24 V
VUVLO
VM undervoltage lockout
voltage
VM rising
LOGIC-LEVEL INPUTS (SCHMITT TRIGGER INPUTS WITH HYSTERESIS)
VIL
Input low voltage
VIH
Input high voltage
0.6
VHYS
Input hysteresis
IIL
Input low current
VIN = 0
IIH
Input high current
VIN = 3.3 V
RPD
Pulldown resistance
2
V
0.45
–20
V
20
μA
100
μA
100
kΩ
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL
Output low voltage
IO = 5 mA
IOH
Output high leakage current
VO = 3.3 V
0.5
V
1
μA
LOW-SIDE FETS
RDS(ON)
FET on resistance
IOFF
Off-state leakage current
VM = 24 V, IO = 700 mA, TJ = 25°C
0.5
VM = 24 V, IO = 700 mA, TJ = 85°C
0.75
0.8
Ω
50
μA
–50
50
μA
–50
HIGH-SIDE DIODES
VF
Diode forward voltage
VM = 24 V, IO = 700 mA, TJ = 25°C
IOFF
Off-state leakage current
VM = 24 V, TJ = 25°C
1.2
V
tR
Rise time
VM = 24 V, IO = 700 mA, Resistive load
50
300
ns
tF
Fall time
VM = 24 V, IO = 700 mA, Resistive load
50
300
ns
2.3
3.8
A
OUTPUTS
PROTECTION CIRCUITS
IOCP
Overcurrent protection trip level
tOCP
Overcurrent protection deglitch
time
3.5
µs
tRETRY
Overcurrent protection retry
time
1.2
ms
tTSD
Thermal shutdown temperature
(1)
Die temperature (1)
150
160
180
°C
Not production tested.
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6.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted) (1)
MIN
(1)
MAX
UNIT
1
tOE(ENABLE)
Enable time, nENBL to output low
50
ns
2
tPD(L-H)
Propagation delay time, INx to OUTx, low to high
800
ns
3
tPD(H-L)
Propagation delay time, INx to OUTx, high to low
800
—
tRESET
RESET pulse width
20
ns
µs
Not production tested.
nENBL
INx
OUTx
1
2
3
Figure 1. DRV8803 Timing Requirements
6
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1.80
1.80
1.75
1.75
1.70
1.70
Supply Current (mA)
Supply Current (mA)
6.7 Typical Characteristics
1.65
1.60
1.55
1.50
1.45
1.40
1.35
8V
24 V
30 V
60 V
1.65
1.60
1.55
1.50
1.45
1.40
-40° C
1.35
1.30
1.30
-40° C
25° C
75° C
8V
125° C
Temperature (ƒC)
25° C
75° C
24 V
125° C
30 V
60 V
Supply Voltage (V)
C001
C002
Figure 3. Supply Current Over VM
Figure 2. Supply Current Over Temperature
900
1000
900
800
-40° C
25° C
75° C
125° C
700
Rdson (mŸ)
Rdson (mŸ)
800
600
500
700
600
500
400
400
8V
300
60 V
300
200
-40° C
25° C
75° C
8V
125° C
Temperature (ƒC)
C005
Figure 4. RDS(on) Over Temperature
60 V
Supply Voltage (V)
Figure 5. RDS(on) Over VM
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7 Detailed Description
7.1 Overview
The DRV8803 device is an integrated 4-channel low side driver solution for any low side switch application. The
integrated overcurrent protection limits the motor current to a fixed maximum. Four logic inputs control the lowside driver outputs which consist of four N-channel MOSFETs that have a typical RDS(on) of 500 mΩ. A single
power input VM serves as device power and is internally regulated to power the internal low side gate drive.
Motor speed can be controlled with pulse-width modulation at frequencies from 0 kHz to 100 kHz. The device
outputs can be disabled by bringing nENBL pin high. The thermal shutdown protection enables the device to
automatically shut down if the die temperature exceeds a TTSD limit. UVLO protection will disable all circuitry in
the device if VM drops below the undervoltage lockout threshold.
7.2 Functional Block Diagram
8.2V – 60V
Internal
Reference
Regs
UVLO
VM
nENBL
LS Gate
Drive
OCP
&
Gate
Drive
RESET
8.2V – 60V
Optional
Zener
Int. VCC
VCLAMP
OUT1
Inductive
Load
IN1
IN2
IN3
Control
Logic
IN4
nFAULT
Thermal
Shut down
OCP
&
Gate
Drive
OUT2
Inductive
Load
OCP
&
Gate
Drive
OUT3
OCP
&
Gate
Drive
OUT4
Inductive
Load
Inductive
Load
GND
(multiple pins)
7.3 Feature Description
7.3.1 Output Drivers
The DRV8803 device contains four protected low-side drivers. Each output has an integrated clamp diode
connected to a common pin, VCLAMP.
VCLAMP can be connected to the main power supply voltage, VM. VCLAMP can also be connected to a Zener
or TVS diode to VM, allowing the switch voltage to exceed the main supply voltage VM. This connection can be
beneficial when driving loads that require very fast current decay, such as unipolar stepper motors.
In all cases, the voltage on the outputs must not be allowed to exceed the maximum output voltage specification.
8
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Feature Description (continued)
7.3.2 Protection Circuits
The DRV8803 device is fully protected against undervoltage, overcurrent and overtemperature events.
7.3.2.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the tOCP deglitch time (approximately 3.5 µs), the driver will be
disabled and the nFAULT pin will be driven low. The driver will remain disabled for the tRETRY retry time
(approximately 1.2 ms), then the fault will be automatically cleared. The fault will be cleared immediately if either
RESET pin is activated or VM is removed and reapplied.
7.3.2.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low.
Once the die temperature has fallen to a safe level, operation will automatically resume.
7.3.2.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled, and internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold.
7.4 Device Functional Modes
7.4.1 Parallel Interface Operation
The DRV8803 device is controlled with a simple parallel interface. Logically, the interface is shown in Figure 6.
nENBL
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
Figure 6. Parallel Interface Operation
7.4.2 nENBL and RESET Operation
The nENBL pin enables or disables the output drivers. nENBL must be low to enable the outputs. Note that
nENBL has an internal pulldown.
The RESET pin, when driven active high, resets internal logic. All inputs are ignored while RESET is active. Note
that RESET has an internal pulldown. An internal power-up reset is also provided, so it is not required to drive
RESET at power up.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8803 device can be used to drive one unipolar stepper motor.
8.2 Typical Application
VM
+
0.1 µF
100 µF
1
–
3
+
2
4
M
5
+
–
VCLAMP
NC
OUT 1
IN1
OUT 2
IN2
GND
6
7
8
9
10
nFAULT
VM
GND
DRV8803
GND
GND
GND
GND
OUT 3
IN3
OUT 4
IN4
nENBL
RESET
20
19
18
17
16
15
14
13
12
11
Figure 7. Typical Application Schematic
8.2.1 Design Requirements
Table 1 lists the design parameters for this design example.
Table 1. Design Parameters
DESIGN PARAMETER
REFERENCE
Supply Voltage
VM
EXAMPLE VALUE
24 V
Motor Winding Resistance
RL
7.4 Ω/phase
Motor Full Step Angle
θstep
1.8°/step
Motor Rated Current
IRATED
0.75 A
PWM frequency
fPWM
31.25 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Motor Voltage
The motor voltage to use will depend on the ratings of the motor selected and the desired torque. A higher
voltage shortens the current rise time in the coils of the stepper motor allowing the motor to produce a greater
average torque. Using a higher voltage also allows the motor to operate at a faster speed than a lower voltage.
8.2.2.2 Drive Current
The current path is starts from the supply VM, moves through the inductive winding load, and low-side sinking
NMOS power FET. Power dissipation losses in one sink NMOS power FET are shown in Equation 1.
P = I2 × RDS(on)
10
(1)
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The DRV8803 device has been measured to be capable of 1.5-A Single Channel or 800-mA Four Channels with
the DW package and 2-A Single Channel or 1-A Four Channels with the PWP package at 25°C on standard FR4 PCBs. The maximum RMS current varies based on PCB design and the ambient temperature.
8.2.3 Application Curves
Figure 8. Current Ramp With a 16-Ω, 1-mH RL Load and VM
= 8.2 V
Figure 9. Current Ramp With a 16-Ω, 1-mH RL Load and VM
= 30 V
Figure 10. OCP With VM = 8.2 V and OUT1 Shorted to VM
Figure 11. OCP Separated by tRETRY With VM = 8.2-V and
OUT1 Shorted to VM
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9 Power Supply Recommendations
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system.
• The power supply’s capacitance and ability to source current.
• The amount of parasitic inductance between the power supply and motor system.
• The acceptable voltage ripple.
• The type of motor used (Brushed DC, Brushless DC, Stepper).
• The motor braking method.
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
–
+
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Example Setup of Motor Drive System with External Power Supply
Figure 12. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
12
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10 Layout
10.1 Layout Guidelines
The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver
device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used
when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high
current.
Small-value capacitors should be ceramic, and placed closely to device pins.
The high-current device outputs should use wide metal traces.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias help dissipate the
I2 × RDS(on) heat that is generated in the device.
10.2 Layout Example
+
VM
nFA ULT
VCLAMP
NC
OUT1
IN1
OUT2
IN2
GND
GND
OUT3
IN3
OUT4
IN4
nENBL
RESET
Figure 13. Recommended Layout
10.3 Thermal Consideration
10.3.1 Thermal Protection
The DRV8803 device has thermal shutdown (TSD) as described above. If the die temperature exceeds
approximately 150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
10.3.2 Power Dissipation
Power dissipation in the DRV8803 device is dominated by the power dissipated in the output FET resistance, or
RDS(on). Average power dissipation of each FET when running a static load can be roughly estimated by
Equation 2:
P = RDS(ON) · (IOUT)2
where
•
P is the power dissipation of one FET
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DRV8803
SLVSAW5C – JULY 2011 – REVISED NOVEMBER 2015
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Thermal Consideration (continued)
•
•
RDS(ON) is the resistance of each FET
IOUT is equal to the average current drawn by the load.
(2)
At start-up and fault conditions, this current is much higher than normal running current; consider these peak
currents and their duration. When driving more than one load simultaneously, the power in all active output
stages must be summed.
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(on) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
10.3.3 Heatsinking
The DRV8803DW package uses a standard SOIC outline, but has the center pins internally fused to the die pad
to more efficiently remove heat from the device. The two center leads on each side of the package should be
connected together to as large a copper area on the PCB as is possible to remove heat from the device. If the
copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat
between top and bottom layers.
In general, the more copper area that can be provided, the more power can be dissipated.
The DRV8803PWP package uses an HTSSOP package with an exposed PowerPAD™. The PowerPAD package
uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally
connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be
accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without
internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on
the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom
layers.
For details about how to design the PCB, see the TI Application Report, PowerPAD Thermally Enhanced
Package (SLMA002), and TI Application Brief, PowerPAD Made Easy (SLMA004), available at www.ti.com.
14
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DRV8803
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SLVSAW5C – JULY 2011 – REVISED NOVEMBER 2015
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD Thermally Enhanced Package, SLMA002.
• PowerPAD Made Easy, SLMA004.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: DRV8803
15
PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV8803DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8803DW
DRV8803DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8803DW
DRV8803PWP
ACTIVE
HTSSOP
PWP
16
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8803
DRV8803PWPR
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8803
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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