DRV8837CDSGT

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DRV8837C SLVSD61A – JULY 2016 – REVISED JULY 2016 DRV8837C 1-A Low-Voltage H-Bridge Driver 1 Features 3 Description • The DRV8837C device provides an integrated motor driver solution for cameras, consumer products, toys, and other low-voltage or battery-powered motion control applications. The device can drive one DC motor or other devices like solenoids. The output driver block consists of N-channel power MOSFETs configured as an H-bridge to drive the motor winding. An internal charge pump generates needed gate drive voltages. 1 • • • • • • H-Bridge Motor Driver – Drives a DC Motor or Other Loads – Low MOSFET On-Resistance: HS + LS 1 Ω 1-A Maximum Drive Current 0- to 11-V Operating Supply-Voltage Range Standard PWM Interface (IN1/IN2) Low-Power Sleep Mode With 120-nA Maximum Sleep Current – nSLEEP pin Small Package and Footprint – 8 WSON (With Thermal Pad) – 2.0 × 2.0 mm Protection Features – VCC Undervoltage Lockout (UVLO) – Overcurrent Protection (OCP) – Thermal Shutdown (TSD) The DRV8837C device can supply up to 1 A of output current. The device operates on a motor power supply voltage from 0 to 11 V, and control logic can operate on 1.8-V to 5-V rails. The DRV8837C device has a PWM (IN/IN) input interface. Internal shutdown functions are provided for overcurrent protection, short circuit protection, undervoltage lockout, and overtemperature. Device Information(1) 2 Applications • • • • • • PART NUMBER DRV8837C Cameras DSLR Lenses Consumer Products Toys Robotics Medical Devices PACKAGE WSON (8) BODY SIZE (NOM) 2.00 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. DRV8837C Simplified Diagram 0 to 11 V 3.3 or 5.0 V VCC DRV8837C PWM 1A BDC BLDC Controller H-Bridge PWM Driver nSLEEP Protection Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV8837C SLVSD61A – JULY 2016 – REVISED JULY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 7.2 7.3 7.4 Overview ................................................................... 8 Functional Block Diagram ......................................... 8 Feature Description................................................... 9 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Application .................................................. 11 9 Power Supply Recommendations...................... 12 9.1 Bulk Capacitance .................................................... 12 10 Layout................................................................... 14 10.1 Layout Guidelines ................................................. 14 10.2 Layout Example .................................................... 14 10.3 Power Dissipation ................................................. 14 11 Device and Documentation Support ................. 15 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 15 15 15 15 15 15 12 Mechanical, Packaging, and Orderable Information ........................................................... 15 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (July 2016) to Revision A • 2 Page Changed the device status from Product Preview to Production Data .................................................................................. 1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C DRV8837C www.ti.com SLVSD61A – JULY 2016 – REVISED JULY 2016 5 Pin Configuration and Functions DSG Package 8-Pin WSON With Exposed Thermal Pad Top View VM 1 OUT1 2 OUT2 3 GND 4 Thermal Pad 8 VCC 7 nSLEEP 6 IN1 5 IN2 Not to scale Pin Functions PIN NAME NO. TYPE DESCRIPTION POWER AND GROUND GND 4 PWR Device ground This pin must be connected to the PCB ground. VCC 8 PWR Logic power supply Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VCC. VM 1 PWR Motor power supply Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VM. IN1 6 I IN1 input IN2 5 I IN2 input nSLEEP 7 I Sleep mode input When this pin is in logic low, the device enters low-power sleep mode. The device operates normally when this pin is logic high. The pin has an internal pulldown resistor to GND. OUT1 2 O OUT2 3 O CONTROL OUTPUT Motor output Connect this pin to the motor winding. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C 3 DRV8837C SLVSD61A – JULY 2016 – REVISED JULY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT Motor power-supply voltage VM –0.3 12 V Logic power-supply voltage VCC –0.3 7 V Control pin voltage IN1, IN2, nSLEEP –0.5 7 V Peak drive current OUT1, OUT2 Internally limited A Operating virtual junction temperature, TJ –40 150 ºC Storage temperature, Tstg –60 150 ºC (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground pin. 6.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) (2) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted) MIN MAX VVM Motor power-supply voltage 0 11 UNIT V VCC Logic power-supply voltage 1.8 7 V IOUT Motor peak current 0 1 A fPWM Externally applied PWM frequency 0 250 VLOGIC Logic level input voltage 0 5.5 V TA Operating ambient temperature –40 85 °C kHz 6.4 Thermal Information over operating free-air temperature range (unless otherwise noted) DRV8837C THERMAL METRIC (1) DSG (WSON) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 60.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 71.4 °C/W RθJB Junction-to-board thermal resistance 32.2 °C/W ψJT Junction-to-top characterization parameter 1.6 °C/W ψJB Junction-to-board characterization parameter 32.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 9.8 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C DRV8837C www.ti.com SLVSD61A – JULY 2016 – REVISED JULY 2016 6.5 Electrical Characteristics TA = 25°C, over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM, VCC) VVM VM operating voltage IVM VM operating supply current IVMQ VM sleep mode supply current VCC VCC operating voltage IVCC VCC operating supply current IVCCQ VCC sleep mode supply current 0 11 V 40 100 μA VVM = 5 V; VCC = 3 V; 50 kHz PWM 0.8 1.5 mA VVM = 5 V; VCC = 3 V; nSLEEP = 0 30 95 nA 7 V VVM = 5 V; VCC = 3 V; No PWM 1.8 VVM = 5 V; VCC = 3 V; No PWM 300 500 μA VVM = 5 V; VCC = 3 V; 50 kHz PWM 0.7 1.5 mA VVM = 5 V; VCC = 3 V; nSLEEP = 0 5 25 nA 0.25 × VCC V CONTROL INPUTS (IN1/PH, IN2/EN, nSLEEP) VIL Input logic-low voltage VIH Input logic-high voltage VHYS Input logic hysteresis IIL Input logic-low current VINx = 0 V IIH Input logic-high current VINx = 3.3 V RPD Pulldown resistance 0.5 × VCC V 0.08 × VCC –5 V 5 μA 50 μA 100 kΩ 1000 mΩ MOTOR DRIVER OUTPUTS (OUT1, OUT2) RDS(ON) HS + LS FET on-resistance VVM = 5 V; VCC = 3.3 V; IO = 200 mA; TJ = 25°C IOFF Off-state leakage current VOUTx = 0 V –200 200 nA 1.7 V 1.8 V PROTECTION CIRCUITS VCC falling VUVLO VCC undervoltage lockout IOCP Overcurrent protection trip level tDEG Overcurrent deglitch time 1 μs Overcurrent retry time 1 ms tRETRY TTSD (1) (1) Thermal shutdown temperature VCC rising 1.2 Die temperature TJ 150 A 160 180 °C Not tested in production; limits are based on characterization data Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C 5 DRV8837C SLVSD61A – JULY 2016 – REVISED JULY 2016 www.ti.com 6.6 Timing Requirements TA = 25°C, VVM = 5 V, VCC = 3 V, RL = 20 Ω NO. MIN MAX UNIT 1 t7 Output enable time 300 ns 2 t8 Output disable time 300 ns 3 t9 Delay time, INx high to OUTx high 160 ns 4 t10 Delay time, INx low to OUTx low 160 ns 5 t11 Output rise time 20 188 ns 6 t12 Output fall time 20 188 ns — twake Wake time, nSLEEP rising edge to part active 30 μs See Figure 1. IN1 IN2 1 OUT1 2 4 z z 3 OUT2 z z DRV8837C 80% 80% OUTx 20% 20% 5 6 Figure 1. Input and Output Timing for DRV8837C 6 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C DRV8837C www.ti.com SLVSD61A – JULY 2016 – REVISED JULY 2016 6.7 Typical Characteristics Plots generated using characterization data. 100 70 VCC Sleep Current (nA) VM Sleep Current (nA) 65 60 55 50 45 40 80 60 40 20 35 30 -40 -20 VVM = 5 V 0 20 40 60 Ambient Temperature (qC) 80 0 -40 100 0.57 0.565 0.56 0.555 0.55 0.545 0.54 VVM = 5 V 0 20 40 60 Ambient Temperature (qC) 80 100 D002 VCC = 3 V 0.56 0.54 0.52 0.5 0.48 0.46 0.44 -40 -20 0 20 40 60 Ambient Temperature (qC) VVM = 5 V Figure 4. VM Operating Current vs Ambient Temperature 100 0.58 D003 VCC = 3 V 80 Figure 3. VCC Sleep Current vs Ambient Temperature VCC Operating Current, 50 KHz PWM (mA) VM Operating Current, 50 kHz PWM (mA) 0.575 -20 0 20 40 60 Ambient Temperature (°C) VVM = 5 V VCC = 3 V Figure 2. VM Sleep Current vs Ambient Temperature 0.535 -40 -20 D001 80 100 D004 VCC = 3 V Figure 5. VCC Operating Current vs Ambient Temperature 2.75 VM = 2 V, VCC = 2 V VM = 5 V, VCC = 3 V VM = 11 V, VCC = 7 V 2.5 RDS(ON) HS+LS (:) 2.25 2 1.75 1.5 1.25 1 0.75 0.5 -40 -20 0 20 40 60 Ambient Temperature (°C) 80 100 D005 Figure 6. HS + LS RDS(ON) vs Ambient Temperature Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C 7 DRV8837C SLVSD61A – JULY 2016 – REVISED JULY 2016 www.ti.com 7 Detailed Description 7.1 Overview The DRV8837C device is an H-bridge driver that can drive one DC motor or other devices like solenoids. The outputs are controlled using a PWM interface (IN1/IN2). A low-power sleep mode is included, which can be enabled using the nSLEEP pin. This device greatly reduces the component count of motor driver systems by integrating the necessary driver FETs and FET control circuitry into a single device. In addition, the DRV8837C device adds protection features beyond traditional discrete implementations: undervoltage lockout, overcurrent protection, and thermal shutdown. 7.2 Functional Block Diagram VM Power VM VM Charge Pump VCC OUT1 Gate Drive VCC Logic nSLEEP IN1 OUT2 Gate Drive Control Inputs IN2 BDC BDC VM Core Logic Overcurrent Undervoltage Thermal GND PPAD Copyright © 2016, Texas Instruments Incorporated 8 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C DRV8837C www.ti.com SLVSD61A – JULY 2016 – REVISED JULY 2016 7.3 Feature Description 7.3.1 Bridge Control The DRV8837C device is controlled using a PWM input interface, also called an IN/IN interface. Each output is controlled by a corresponding input pin. Table 1 shows the logic for the DRV8837C device. Table 1. DRV8837C Device Logic nSLEEP IN1 IN2 OUT1 OUT2 FUNCTION (DC MOTOR) 0 X X Z Z Coast 1 0 0 Z Z Coast 1 0 1 L H Reverse 1 1 0 H L Forward 1 1 1 L L Brake 7.3.2 Sleep Mode If the nSLEEP pin is brought to a logic-low state, the DRV8837C device enters a low-power sleep mode. In this state, all unnecessary internal circuitry is powered down. 7.3.3 Power Supplies and Input Pins The input pins can be driven within the recommended operating conditions with or without the VCC, VM, or both power supplies present. No leakage current path exists to the supply. Each input pin has a weak pulldown resistor (approximately 100 kΩ) to ground. The VCC and VM supplies can be applied and removed in any order. When the VCC supply is removed, the device enters a low-power state and draws very little current from the VM supply. The VCC and VM pins can be connected together if the supply voltage is between 1.8 and 7 V. The VM voltage supply does not have any undervoltage-lockout protection (UVLO). As long as VCC > 1.8 V, the internal device logic remains active which means that the VM pin voltage can drop to 0 V, however, the load may not be sufficiently driven at low VM voltages. 7.3.4 Protection Circuits The DRV8837C is fully protected against VCC undervoltage, overcurrent, and overtemperature events. VCC undervoltage lockout If at any time the voltage on the VCC pin falls below the undervoltage lockout threshold voltage, all FETs in the H-bridge are disabled. Operation resumes when the VCC pin voltage rises above the UVLO threshold. Overcurrent protection (OCP) An analog current-limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than tDEG, all FETs in the Hbridge are disabled. Operation resumes automatically after tRETRY has elapsed. Overcurrent conditions are detected on both the high-side and low-side devices. A short to the VM pin, GND, or from the OUT1 pin to theOUT2 pin results in an overcurrent condition. Thermal shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge are disabled. After the die temperature falls to a safe level, operation automatically resumes. Table 2. Fault Behavior FAULT CONDITION H-BRIDGE RECOVERY VCC undervoltage (UVLO) VCC < 1.7 V Disabled VCC > 1.8 V Overcurrent (OCP) IOUT > 1.2 A (MIN) Disabled (retries automatically) tRETRY elapses Thermal Shutdown (TSD) TJ > 150°C (MIN) Disabled (retries automatically) TJ < 150°C Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C 9 DRV8837C SLVSD61A – JULY 2016 – REVISED JULY 2016 www.ti.com 7.4 Device Functional Modes The DRV8837C device is active unless the nSLEEP pin is brought logic low. In sleep mode the H-bridge FETs are disabled Hi-Z. The DRV8837C device is brought out of sleep mode automatically if nSLEEP is brought logic high. The H-bridge outputs are disabled during undervoltage lockout, overcurrent, and overtemperature fault conditions. Table 3. Operation Modes 10 MODE CONDITION H-BRIDGE Operating Operating nSLEEP pin = 1 Sleep mode nSLEEP pin = 0 Disabled Fault encountered Any fault condition met Disabled (retries automatically) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C DRV8837C www.ti.com SLVSD61A – JULY 2016 – REVISED JULY 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The DRV8837C device is device is used to drive one DC motor or other devices like solenoids. The following design procedure can be used to configure the DRV8837C device. 8.2 Typical Application VM DRV8837C 1 0.1 µF 8 VM 0.1 µF 7 OUT1 3 OUT2 4 GND Thermal Pad 2 M VCC VCC nSLEEP 6 IN1 5 IN2 Copyright © 2016, Texas Instruments Incorporated Figure 7. Schematic of DRV8837C Application 8.2.1 Design Requirements Table 4 lists the required parameters for a typical usage case. Table 4. System Design Requirements DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor supply voltage VM 9V Logic supply voltage VCC 3.3 V Target RMS current IOUT 0.8 A 8.2.2 Detailed Design Procedure 8.2.2.1 Motor Voltage The appropriate motor voltage depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed dc motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. 8.2.2.2 Low-Power Operation When entering sleep mode, TI recommends setting all inputs as a logic low to minimize system power. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C 11 DRV8837C SLVSD61A – JULY 2016 – REVISED JULY 2016 www.ti.com 8.2.3 Application Curves Figure 8. 50% Duty Cycle, Forward Direction Figure 9. 50% Duty Cycle, Reverse Direction Figure 10. 20% Duty Cycle, Forward Direction Figure 11. 20% Duty Cycle, Reverse Direction 9 Power Supply Recommendations 9.1 Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor-drive system design. It is generally beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: • The highest current required by the motor system • The power-supply capacitance and ability to source current • The amount of parasitic inductance between the power supply and motor system • The acceptable voltage ripple • The type of motor used (brushed dc, brushless dc, stepper) • The motor braking method The inductance between the power supply and motor drive system limits the rate at which current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate size of bulk capacitor. 12 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C DRV8837C www.ti.com SLVSD61A – JULY 2016 – REVISED JULY 2016 Bulk Capacitance (continued) Power Supply Parasitic Wire Inductance Motor Drive System VM + – + Motor Driver GND Local Bulk Capacitor IC Bypass Capacitor Figure 12. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C 13 DRV8837C SLVSD61A – JULY 2016 – REVISED JULY 2016 www.ti.com 10 Layout 10.1 Layout Guidelines The VM and VCC pins should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value of 0.1 µF rated for the VM and VCC supplies. These capacitors should be placed as close to the VM and VCC pins as possible with a thick trace or ground plane connection to the device GND pin. In addition bulk capacitance is required on the VM pin. 10.2 Layout Example 0.1 µF 0.1 µF VM VCC OUT1 SLEEPn OUT2 IN1 GND IN2 Figure 13. Simplified Layout Example 10.3 Power Dissipation Power dissipation in the DRV8837C device is dominated by the power dissipated in the output FET resistance, or RDS(ON). Use Equation 1 to estimate the average power dissipation when running a brushed-DC motor. PTOT = RDS(ON) ´ (IOUT(RMS) )2 where • • • PTOT is the total power dissipation RDS(ON) is the resistance of the HS plus LS FETs IOUT(RMS) is the RMS or DC output current being supplied to the load (1) The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking. NOTE The value of RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. The DRV8837C device has thermal shutdown protection. If the die temperature exceeds approximately 150°C, the device is disabled until the temperature drops to a safe level. Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. 14 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C DRV8837C www.ti.com SLVSD61A – JULY 2016 – REVISED JULY 2016 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • Calculating Motor Driver Power Dissipation (SLVA504) • DRV8837C Evaluation Module User's Guide (SLVUAS3) • Understanding Motor Driver Current Ratings (SLVA505) 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV8837C 15 PACKAGE OPTION ADDENDUM www.ti.com 19-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) DRV8837CDSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 837C Samples DRV8837CDSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 837C Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of