DRV8840PWPR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents DRV8840 SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 DRV8840 DC Motor Driver IC 1 Features 3 Description • • • The DRV8840 provides an integrated motor driver solution for printers, scanners, and other automated equipment applications. The device has one H-bridge driver, and is intended to drive one DC motor. The output driver block for each consists of N-channel power MOSFETs configured as full H-bridges to drive the motor windings. The DRV8840 can supply up to 5-A peak or 3.5-A output current (with proper heatsinking at 24 V and 25°C). 1 • • • • • • Single H-Bridge Current-Control Motor Driver 8.2-V to 45-V Operating Supply Voltage Range Five Bit Current Control Allows up to 32 Current Levels Low MOSFET RDS(on) Typical 0.65 Ω (HS + LS) 5-A Maximum Drive Current at 24 V, TA = 25°C Built-In 3.3-V Reference Output Parallel Digital Control Interface Thermal Enhanced Surface Mount Package Protection Features: – Overcurrent Protection (OCP) – Thermal Shutdown (TSD) – VM Undervoltage Lockout (UVLO) – Fault Condition Indication Pin (nFAULT) 2 Applications • • • • • • Printers Scanners Office Automation Machines Gaming Machines Factory Automation Robotics A simple parallel digital control interface is compatible with industry-standard devices. Decay mode is programmable to allow braking or coasting of the motor when disabled. Internal shutdown functions are provided for overcurrent protection, short-circuit protection, undervoltage lockout, and overtemperature. The DRV8840 is available in a 28-pin HTSSOP package with PowerPAD™ (Eco-friendly: RoHS & no Sb/Br). Device Information(1) PART NUMBER DRV8840 PACKAGE HTSSOP (28) BODY SIZE (NOM) 9.70 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic 8.2 to 45 V ENBL DRV8840 Controller PHASE Current Control Decay Mode + H-Bridge 5A Motor Driver - nFAULT Current Control 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV8840 SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 7.2 7.3 7.4 Overview ................................................................... 8 Functional Block Diagram ......................................... 9 Feature Description................................................... 9 Device Functional Modes........................................ 13 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application ................................................. 14 9 Power Supply Recommendations...................... 17 9.1 Bulk Capacitance Sizing ......................................... 17 10 Layout................................................................... 18 10.1 Layout Guidelines ................................................. 18 10.2 Layout Example .................................................... 18 10.3 Thermal Considerations ........................................ 19 11 Device and Documentation Support ................. 20 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 12 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (August 2013) to Revision D Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • Updated Features bullets ....................................................................................................................................................... 1 • Added MIN value for ISENSEx row from –0.3 V to –0.8 V ................................................................................................... 4 2 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 DRV8840 www.ti.com SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 5 Pin Configuration and Functions PWP Package 28-Pin HTSSOP Top View CP1 CP2 VCP VM OUT1 ISEN OUT2 OUT2 ISEN OUT1 VM VREF VREF GND 1 2 3 28 4 25 24 27 26 5 6 23 GND (PPAD) 7 8 22 21 9 20 10 19 11 18 12 17 13 16 14 15 GND I4 I3 I2 I1 I0 NC ENBL PHASE DECAY nFAULT nSLEEP nRESET V3P3OUT Pin Functions PIN NAME NO. I/O (1) EXTERNAL COMPONENTS OR CONNECTIONS DESCRIPTION POWER AND GROUND GND 14, 28 — Device ground VM 4, 11 — Bridge A power supply Connect to motor supply (8.2 - 45 V). Both pins must be connected to same supply. V3P3OUT 15 O 3.3-V regulator output Bypass to GND with a 0.47-μF, 6.3-V ceramic capacitor. Can be used to supply VREF. CP1 1 IO Charge pump flying capacitor CP2 2 IO Charge pump flying capacitor VCP 3 IO High-side gate drive voltage Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ resistor to VM. PHASE 20 I Bridge phase (direction) Logic high sets OUT1 high, OUT2 low. Internal pulldown. ENBL 21 I Bridge enable Logic high to enable H-bridge. Internal pulldown. I0 23 I I1 24 I I2 25 I Current set inputs Sets winding current as a percentage of fullscale. Internal pulldown. I3 26 I I4 27 I DECAY 19 I Decay (brake) mode Low = brake (slow decay), high = coast (fast decay). Internal pulldown and pullup. nRESET 16 I Reset input Active-low reset input initializes the logic and disables the H-bridge outputs. Internal pulldown. nSLEEP 17 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode. Internal pulldown. 12,13 I Current set reference input Reference voltage for winding current set. Both pins must be connected together on the PCB. Connect a 0.01-μF 50-V capacitor between CP1 and CP2. CONTROL VREF (1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 3 DRV8840 SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 www.ti.com Pin Functions (continued) PIN NAME NO. I/O (1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS STATUS 18 OD Fault Logic low when in fault condition (overtemperature, overcurrent) ISEN 6, 9 IO Bridge ground / Isense Connect to current sense resistor. Both pins must be connected together on the PCB. OUT1 5, 10 O Bridge output 1 Connect to motor winding. Both pins must be connected together on the PCB. OUT2 7, 8 O Bridge output 2 Connect to motor winding. Both pins must be connected together on the PCB. nFAULT OUTPUT 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) VMx VREF MIN MAX UNIT Power supply voltage –0.3 47 V Digital pin voltage –0.5 7 V Input voltage –0.3 4 V ISENSEx pin voltage (3) –0.8 0.8 V Peak motor drive output current, t < 1 μS Internally limited A Continuous motor drive output current (4) 0 Continuous total power dissipation TJ Operating virtual junction temperature –40 TA Operating ambient temperature Tstg Storage temperature (1) (2) (3) (4) 5 A See Thermal Information 150 °C –40 85 °C –60 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground pin. Transients of ±1 V for less than 25 ns are acceptable. Power dissipation and thermal limits must be observed. 6.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Motor power supply voltage (1) VM (2) MIN MAX 8.2 45 UNIT V VREF VREF input voltage 1 3.5 IV3P3 V3P3OUT load current 0 1 mA fPWM Externally applied PWM frequency 0 100 kHz (1) (2) 4 V All VM pins must be connected to the same supply voltage. Operational at VREF between 0 V and 1 V, but accuracy is degraded. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 DRV8840 www.ti.com SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 6.4 Thermal Information DRV8840 THERMAL METRIC (1) PWP (HTSSOP) UNIT 28 PINS RθJA Junction-to-ambient thermal resistance 31.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 15.9 °C/W RθJB Junction-to-board thermal resistance 5.6 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 5.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 5 DRV8840 SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 www.ti.com 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES IVM VM operating supply current VM = 24 V, fPWM < 50 kHz 5 8 mA IVMQ VM sleep mode supply current VM = 24 V 10 20 μA VUVLO VM undervoltage lockout voltage VM rising 7.8 8.2 V 3.3 3.4 V V3P3OUT REGULATOR V3P3 V3P3OUT voltage IOUT = 0 to 1 mA 3.2 LOGIC-LEVEL INPUTS VIL Input low voltage VIH Input high voltage 2.2 0.6 VHYS Input hysteresis 0.3 IIL Input low current VIN = 0 IIH Input high current VIN = 3.3 V RPD Internal pulldown resistance 0.7 V 5.25 V 0.45 0.6 V 20 μA 33 100 μA –20 100 kΩ nFAULT OUTPUT (OPEN-DRAIN OUTPUT) VOL Output low voltage IO = 5 mA IOH Output high leakage current VO = 3.3 V 0.5 V 1 μA 0.8 V ±40 μA DECAY INPUT VIL Input low threshold voltage For slow decay (brake) mode 0 VIH Input high threshold voltage For fast decay (coast) mode 2 IIN Input current RPU Internal pullup resistance RPD Internal pulldown resistance V 130 kΩ 80 kΩ H-BRIDGE FETS RDS(ON) HS FET on resistance RDS(ON) LS FET on resistance IOFF Off-state leakage current VM = 24 V, IO = 1 A, TJ = 25°C 0.1 VM = 24 V, IO = 1 A, TJ = 85°C 0.13 VM = 24 V, IO = 1 A, TJ = 25°C 0.1 VM = 24 V, IO = 1 A, TJ = 85°C 0.13 –40 0.16 0.16 40 Ω Ω μA MOTOR DRIVER fPWM Internal current control PWM frequency tBLANK Current sense blanking time tR Rise time 30 200 ns tF Fall time 30 200 ns 160 180 °C 3 μA 660 685 mV 50 kHz μs 3.75 PROTECTION CIRCUITS IOCP Overcurrent protection trip level tTSD Thermal shutdown temperature 6 Die temperature 150 A CURRENT CONTROL IREF VREF input current VREF = 3.3 V VTRIP ISENSE trip voltage VREF = 3.3 V, 100% current setting ΔITRIP Current trip accuracy (relative to programmed value) AISENSE Current sense amplifier gain 6 –3 635 VREF = 3.3 V, 5% current setting –25% 25% VREF = 3.3 V, 10% - 34% current setting –15% 15% VREF = 3.3 V, 38% - 67% current setting –10% 10% VREF = 3.3 V, 71% - 100% current setting –5% 5% Reference only Submit Documentation Feedback 5 V/V Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 DRV8840 www.ti.com SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 6.6 Typical Characteristics 7 14 6.5 12 IVMQ (PA) IVM (mA) 6 5.5 10 5 8 -40qC 25qC 85qC 125qC 4.5 4 10 15 20 25 30 V(VMx) (V) 35 40 45 -40qC 25qC 85qC 125qC 6 10 15 20 Figure 1. IVMx vs V(VMx) 35 40 45 D002 Figure 2. IVMxQ vs V(VMx) 350 400 -40°C 25°C 85°C 125°C 325 RDS(ON) HS + LS (mŸ) 350 RDS(ON) HS + LS (mŸ) 25 30 V(VMx) (V) D001 300 250 300 275 250 225 200 200 8V 24 V 45 V 175 150 150 8 13 18 23 28 33 V(VMx) (V) 38 43 ±50 C001 ±25 0 25 50 75 100 TA (ƒC) 125 C002 Figure 4. RDS(ON) vs Temperature Figure 3. RDS(ON) vs V(VMx) Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 7 DRV8840 SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The DRV8840 is an integrated motor driver solution for printers, scanners, and other automated equipment applications. The device integrates a single NMOS H-bridge, charge pump, current sense, current regulation, and device protection circuitry. The DRV8828 can be powered from a single voltage supply from 8.2 V to 45 V, and is capable of providing a continuous output current up to 5 A. A simple PHASE/ENBL interface allows for easy interfacing to an external controller. A 5 bit current control scheme allows for up to 32 discrete current levels. The current regulation method is adjustable between slow and fast decay. Integrated protection circuits allows the device to monitor and protect against overcurrent, undervoltage, and overtemperature faults which are all reported through a fault indication pin (nFAULT). A low power sleep mode is integrated which allows the system to lower power consumption when not driving the motor. 8 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 DRV8840 www.ti.com SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 7.2 Functional Block Diagram VM 3.3V V3P3OUT LS Gate Drive CP1 V3P3OUT Internal VCC Charge Pump Low Side Gate Drive CP2 HS Gate Drive VM VCP 3.3V VM VREF VM VM + VREF Additional Bulk Cap VM PHASE OUT1 ENBL OUT1 I0 I1 + I2 Stepper Motor BDC I4 Motor Driver DECAY OUT2 nRESET OUT2 - - Control Logic/ Indexer + I3 nSLEEP ISEN Thermal Shut Down nFAULT GND PPAD ISEN GND 7.3 Feature Description 7.3.1 PWM Motor Driver The DRV8840 device contains one H-bridge motor driver with current-control PWM circuitry. A block diagram of the motor control circuitry is shown in Figure 5. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 9 DRV8840 SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 www.ti.com Feature Description (continued) VM OCP VM VCP, VGD OUT1 Predrive DCM OUT2 ENBL PHASE PWM DECAY OCP ISEN + I[4:0] A =5 DAC 5 VREF Figure 5. Motor Control Circuitry There are multiple VM, ISEN, OUT, and VREF pins. All like-named pins must be connected together on the PCB. 7.3.2 Bridge Control The PHASE input pin controls the direction of current flow through the H-bridge, and hence the direction of rotation of a DC motor. The ENBL input pin enables the H-bridge outputs when active high, and can also be used for PWM speed control of the motor. Note that the state of the DECAY pin selects the behavior of the bridge when ENBL = 0, allowing the selection of slow decay (brake) or fast decay (coast). Table 1 shows the logic. Table 1. H-Bridge Logic DECAY ENBL PHASE OUT1 OUT2 0 0 X L L 1 0 X Z Z X 1 1 H L X 1 0 L H The control inputs have internal pulldown resistors of approximately 100 kΩ. 7.3.3 Current Regulation The maximum current through the motor winding is regulated by a fixed-frequency PWM current regulation, or current chopping. When the H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding. Once the current hits the current chopping threshold, the bridge disables the current until the beginning of the next PWM cycle. For DC motors, current regulation is used to limit the start-up and stall current of the motor. Speed control is typically performed by providing an external PWM signal to the ENBLx input pins. If the current regulation feature is not needed, it can be disabled by connecting the ISENSE pins directly to ground and the VREF pins to V3P3. The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the ISEN pin, multiplied by a factor of 5, with a reference voltage. The reference voltage is input from the VREF pin, and is scaled by a 5-bit DAC that allows current settings of zero to 100% in an approximately sinusoidal sequence. 10 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 DRV8840 www.ti.com SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 The full-scale (100%) chopping current is calculated in Equation 1. VREFX ICHOP 5 u RISENSE (1) Example: If a 0.25-Ω sense resistor is used and the VREFx pin is 2.5 V, the full-scale (100%) chopping current will be 2.5 V / (5 × 0.25 Ω) = 2 A. Five input pins (I0 - I4) are used to scale the current in the bridge as a percentage of the full-scale current set by the VREF input pin and sense resistance. The I0 - I4 pins have internal pulldown resistors of approximately 100 kΩ. The function of the pins is shown in Table 2. Table 2. Pin Functions I[4..0] RELATIVE CURRENT (% FULL-SCALE CHOPPING CURRENT) 0x00h 0% 0x01h 5% 0x02h 10% 0x03h 15% 0x04h 20% 0x05h 24% 0x06h 29% 0x07h 34% 0x08h 38% 0x09h 43% 0x0Ah 47% 0x0Bh 51% 0x0Ch 56% 0x0Dh 60% 0x0Eh 63% 0x0Fh 67% 0x10h 71% 0x11h 74% 0x12h 77% 0x13h 80% 0x14h 83% 0x15h 86% 0x16h 88% 0x17h 90% 0x18h 92% 0x19h 94% 0x1Ah 96% 0x1Bh 97% 0x1Ch 98% 0x1Dh 99% 0x1Eh 100% 0x1Fh 100% Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 11 DRV8840 SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 www.ti.com 7.3.4 Decay Mode and Braking During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 6 as case 1. The current flow direction shown indicates the state when the xENBL pin is high. Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay. In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 6 as case 2. In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown in Figure 6 as case 3. Figure 6. Decay Mode The DRV8840 device supports fast decay and slow decay mode. Slow or fast decay mode is selected by the state of the DECAY pin - logic low selects slow decay, and logic high sets fast decay mode. The DECAY pin has both an internal pullup resistor of approximately 130 kΩ and an internal pulldown resistor of approximately 80 kΩ. This sets the mixed decay mode if the pin is left open or undriven. DECAY mode also affects the operation of the bridge when it is disabled (by taking the ENBL pin inactive). This applies if the ENABLE input is being used for PWM speed control of the motor, or if it is simply being used to start and stop motor rotation. If the DECAY pin is high (fast decay), when the bridge is disabled fast decay mode will be entered until the current through the bridge reaches zero. Once the current is at zero, the bridge is disabled to prevent the motor from reversing direction. This allows the motor to coast to a stop. If the DECAY pin is low (slow decay), both low-side FETs will be turned on when ENBL is made inactive. This essentially shorts out the back EMF of the motor, causing the motor to brake, and stop quickly. The low-side FETs will stay in the ON state even after the current reaches zero. 12 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 DRV8840 www.ti.com SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 7.3.5 Blanking Time After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also sets the minimum on time of the PWM. 7.3.6 Protection Circuits The DRV8840 device is fully protected against undervoltage, overcurrent and overtemperature events. 7.3.6.1 Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is removed and re-applied. Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage. 7.3.6.2 Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume. 7.3.6.3 Undervoltage Lockout (UVLO) If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled and internal logic will be reset. Operation will resume when VM rises above the UVLO threshold. 7.4 Device Functional Modes 7.4.1 nRESET and nSLEEP Operation The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge driver. All inputs are ignored while nRESET is active. Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time (approximately 1 ms) needs to pass before the motor driver becomes fully operational. Note that nRESET and nSLEEP have internal pulldown resistors of approximately 100 kΩ. These signals need to be driven to logic high for device operation. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 13 DRV8840 SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The DRV8840 device is used in brushed motor or stepper motor control. The onboard current regulation allows for limiting the motor current through simple pin configurations. 8.2 Typical Application 1 CP1 GND DRV8840 28 0.01 µF 2 CP2 I4 VCP I3 VM I2 OUT1 I1 ISEN I0 27 VM 3 0.1 µF 0.1 µF 26 1M 4 5 25 24 100 m 6 7 BDC 8 9 10 OUT2 NC OUT2 ENBL ISEN PHASE OUT1 DECAY VM nFAULT VREF nSLEEP VREF nRESET 23 22 21 20 19 VM 11 100 µF 18 0.1 µF 12 17 14 GND PPAD 10 kŸ 13 V3P3OUT 16 15 0.47 µF R1 R2 Figure 7. Typical Application Schematic 14 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 DRV8840 www.ti.com SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 Typical Application (continued) 8.2.1 Design Requirements Table 3 shows the design parameters for this application. Table 3. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Supply Voltage VM 24 V Motor Winding Resistance RM 3.9 V Motor Winding Inductance LM 2.9 mH Target Chopping Current ITRIP 1.5 A Sense Resistor RSENSE 100 mΩ VREF Voltage VREF 0.75 V 8.2.2 Detailed Design Procedure 8.2.2.1 Current Regulation The maximum current (ITRIP) is set by the Ix pins, the VREF analog voltage, and the sense resistor value (RSENSE). When starting a brushed DC motor, a large inrush current may occur because there is no back-EMF and high detent torque. Current regulation will act to limit this inrush current and prevent high current on start-up. ITRIP / (5 × RSENSE) (2) Example: If the desired chopping current is 1.5 A: • Set RSENSE = 100 mΩ • VREF would have to be 0.75 V • Create a resistor divider network from V3P3OUT (3.3 V) to set VREF = 0.75 V • Set R2 = 10 kΩ and set R1 = 3 kΩ 8.2.2.2 Sense Resistor For optimal performance, it is important for the sense resistor to be: • Surface-mount • Low inductance • Rated for high enough power • Placed closely to the motor driver The power dissipated by the sense resistor equals Irms2 × R. For example, if the RMS motor current is 1.5 A and a 200-mΩ sense resistor is used, the resistor will dissipate 1.5 A2 × 0.2 Ω = 0.3 W. The power quickly increases with greater current levels. Resistors typically have a rated power within some ambient temperature range, along with a de-rated power curve for high ambient temperatures. When a PCB is shared with other components generating heat, margin should be added. It is always best to measure the actual sense resistor temperature in a final system, along with the power MOSFETs, as those are often the hottest components. Because power resistors are larger and more expensive than standard resistors, it is common practice to use multiple standard resistors in parallel, between the sense node and ground. This distributes the current and heat dissipation. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 15 DRV8840 SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 www.ti.com 8.2.3 Application Curves Figure 8. DRV8842 Current Regulation 16 Submit Documentation Feedback Figure 9. DRV8842 Direction Change Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 DRV8840 www.ti.com SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 9 Power Supply Recommendations The DRV8840 is designed to operate from an input voltage supply (VM) range from 8.2 V to 45 V. The device has an absolute maximum rating of 47 V. A 0.1-μF ceramic capacitor rated for VM must be placed at each VM pin as close to the DRV8840 as possible. In addition, a bulk capacitor must be included on VM. 9.1 Bulk Capacitance Sizing Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: • The highest current required by the motor system. • The power supply’s capacitance and ability to source current. • The amount of parasitic inductance between the power supply and motor system. • The acceptable voltage ripple. • The type of motor used (Brushed DC, Brushless DC, Stepper). • The motor braking method. The inductance between the power supply and motor drive system will limit the rate current can change from the power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. The voltage rating for bulk capacitors should be greater than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Parasitic Wire Inductance Motor Drive System VM + ± + Motor Driver GND Local Bulk Capacitor IC Bypass Capacitor Figure 10. Setup of Motor Drive System With External Power Supply Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 17 DRV8840 SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 www.ti.com 10 Layout 10.1 Layout Guidelines Each VM terminal must be bypassed to GND using a low-ESR ceramic bypass capacitors with recommended values of 0.1 μF rated for VM. These capacitors should be placed as close to the VM pins as possible with a thick trace or ground plane connection to the device GND pin. The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component may be an electrolytic. A low-ESR ceramic capacitor must be placed in between the CP1 and CP2 pins. TI recommends a value of 0.1 μF rated for VM . Place this component as close to the pins as possible. A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. TI recommends a value of 0.47 μF rated for 16 V. Place this component as close to the pins as possible. In addition, place a 1 MΩ between VM and VCP. Bypass V3P3OUT to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin as possible. The current sense resistor should be placed as close as possible to the device pins to minimize trace inductance between the pin and resistor. 10.2 Layout Example + 0.1 µF CP1 GND CP2 I4 VCP I3 VM I2 OUT1 I1 0.1 µF 1 MŸ RISEN 0.47 µF 0.1 µF ISEN I0 OUT2 NC OUT2 ENBL ISEN PHASE OUT1 DECAY VM nFAULT VREF nSLEEP VREF nRESET GND V3P3OUT 0.1 µF Figure 11. Example Layout 18 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 DRV8840 www.ti.com SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 10.3 Thermal Considerations The DRV8840 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. 10.3.1 Power Dissipation Average power dissipation in the DRV8840 when running a DC motor can be roughly estimated by: Equation 3. P 2 u RDS(ON) u IOUT 2 where • • • P is the power dissipation of one H-bridge RDS(ON) is the resistance of each FET IOUT is the RMS output current being applied to each winding. (3) IOUT is equal to the average current drawn by the DC motor. Note that at start-up and fault conditions this current is much higher than normal running current; these peak currents and their duration also need to be taken into consideration. The factor of 2 comes from the fact that at any instant two FETs are conducting winding current (one high-side and one low-side). The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. 10.3.2 Heatsinking The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multilayer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, see the TI application report, PowerPAD™ Thermally Enhanced Package (SLMA002), and the TI application brief, PowerPAD™ Made Easy (SLMA004), available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 19 DRV8840 SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • PowerPAD™ Thermally Enhanced Package, SLMA002 • PowerPAD™ Made Easy, SLMA004 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DRV8840 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DRV8840PWP ACTIVE HTSSOP PWP 28 50 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DRV8840 DRV8840PWPR ACTIVE HTSSOP PWP 28 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DRV8840 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of