DRV8844PWPR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DRV8844 SLVSBA2D – JULY 2012 – REVISED MAY 2016 DRV8844 Quad ½-H-Bridge Driver IC 1 Features 3 Description • The DRV8844 provides four individually controllable 1/2-H-bridge drivers. It can be used to drive two DC motors, one stepper motor, four solenoids, or other loads. The output driver channel for each channel consists of N-channel power MOSFET’s configured in a 1/2-H-bridge configuration. 1 • • • • • • • Quad 1/2-H-Bridge DC Motor Driver – Can Drive Four Solenoids, Two DC Motors, One Stepper Motor, or Other Loads – Full Individual Half Bridge Control – Low MOSFET On-Resistance 2.5-A Maximum Drive Current at 24 V, 25°C Floating Input Buffers Allow Dual (Bipolar) Supplies (up to ±30 V) Built-In 3.3-V, 10-mA LDO Regulator Industry Standard IN/IN Digital Control Interface 8-V to 60-V Operating Supply Voltage Range Outputs Can Be Connected in Parallel Thermally Enhanced Surface Mount Package 2 Applications • • • • • The DRV8844 can supply up to 2.5-A peak or 1.75-A RMS output current per channel (with proper PCB heatsinking at 24 V and 25°C) per H-bridge. Separate inputs to independently control each 1/2-Hbridge are provided. To allow operation with split supplies, the logic inputs and nFAULT output are referenced to a separate floating ground pin. Internal shutdown functions are provided for over current protection, short circuit protection, undervoltage lockout, and overtemperature. The DRV8844 is available in a 28-pin HTSSOP package with PowerPAD™ (Eco-friendly: RoHS & no Sb/Br). Textile Machines Office Automation Machines Gaming Machines Factory Automation Robotics Device Information(1) PART NUMBER DRV8844 PACKAGE BODY SIZE (NOM) HTSSOP (28) 9.70 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic 8 to 60 V 8 EN / IN M BDC 4 Half-H Bridges ± SLEEP Controller 2.5 A + DRV8844 2.5 A FAULT Protection + ± BDC MOSFETs Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV8844 SLVSBA2D – JULY 2012 – REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 7.2 7.3 7.4 Overview ................................................................... 8 Functional Block Diagram ......................................... 8 Feature Description................................................... 9 Device Functional Modes........................................ 11 8 Application and Implementation ........................ 12 8.1 Application Information............................................ 12 8.2 Typical Application .................................................. 12 9 Power Supply Recommendations...................... 15 9.1 Bulk Capacitance .................................................... 15 10 Layout................................................................... 16 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. Layout Example .................................................... Thermal Considerations ........................................ Power Dissipation ................................................. 16 16 16 17 11 Device and Documentation Support ................. 18 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 18 12 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (May 2015) to Revision D Page • Added parallel output connection to the Features section .................................................................................................... 1 • Changed pins 6 and 9 from VNEG to SRC12 and SRC34 (respectively) in the Pin Configuration and Functions section ................................................................................................................................................................................... 3 • Added SRC12, SRC34 to VNEG pins parameter to the Absolute Maximum Ratings table ................................................. 4 • Changed the Functional Block Diagram to show the change of pin 6 and 9 from VNEG to SRC12 and SRC34 ................ 8 • Added parallel output description and sense-resistor option to the Application Information section .................................. 12 Changes from Revision B (January 2015) to Revision C • Added ambient temperature to Recommended Operating Conditions .................................................................................. 4 Changes from Revision A (October 2012) to Revision B • 2 Page Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 4 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 DRV8844 www.ti.com SLVSBA2D – JULY 2012 – REVISED MAY 2016 5 Pin Configuration and Functions PWP Package 28-Pin HTSSOP Top View CP1 CP2 VCP VM OUT1 SRC12 OUT2 OUT3 SRC34 OUT4 VM NC NC VNEG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND (PPAD) VNEG IN1 EN1 IN2 EN2 IN3 EN3 IN4 EN4 LGND nFAULT nSLEEP NRESET V3P3OUT Pin Functions PIN NAME NO. TYPE (1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS POWER AND GROUND CP1 1 P Charge pump flying capacitor CP2 2 P Charge pump flying capacitor LGND 19 P Logic input reference ground Connect to logic ground. This may be any voltage between VNEG and VM – 8 V. V3P3OUT 15 P 3.3-V regulator output Bypass to VNEG with a 0.47-μF 6.3-V ceramic capacitor. Can be used to supply VREF. VCP 3 P High-side gate drive voltage Connect a 0.1-μF 16-V ceramic capacitor to VM. VM 4, 11 P Main power supply Connect to motor supply (8 V to 60 V). Both pins must be connected to same supply. Bypass to VNEG with a 10-µF (minimum) capacitor. 6 P Low-side FET source for OUT1 and OUT2 SRC12 Connect a 0.01-μF 100-V capacitor between CP1 and CP2. Connect to VNEG directly or through optional current-sense resistor SRC34 9 P Low-side FET source for OUT3 and OUT4 VNEG 14, 28, PPAD P Negative power supply (dual supplies) or ground (single supply) EN1 26 I Channel 1 enable Logic high enables OUT1. Internal pulldown. EN2 24 I Channel 2 enable Logic high enables OUT2. Internal pulldown. EN3 22 I Channel 3 enable Logic high enables OUT3. Internal pulldown. EN4 20 I Channel 4 enable Logic high enables OUT4. Internal pulldown. IN1 27 I Channel 1 input Logic input controls state of OUT1. Internal pulldown. IN2 25 I Channel 2 input Logic input controls state of OUT2. Internal pulldown. IN3 23 I Channel 3 input Logic input controls state of OUT3. Internal pulldown. IN4 21 I Channel 4 input Logic input controls state of OUT4. Internal pulldown. nRESET 16 I Reset input Active-low reset input initializes internal logic and disables the Hbridge outputs. Internal pulldown. nSLEEP 17 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode. Internal pulldown. CONTROL (1) I = input, O = output, OD = open-drain output, P = power Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 3 DRV8844 SLVSBA2D – JULY 2012 – REVISED MAY 2016 www.ti.com Pin Functions (continued) PIN NAME NO. TYPE (1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS STATUS nFAULT 18 OD OUT1 5 O Output 1 OUT2 7 O Output 2 OUT3 8 O Output 3 OUT4 10 O Output 4 12, 13 — No connect Logic low when in fault condition (overtemperature, overcurrent, UVLO). Open-drain output. Fault OUTPUT Connect to loads NO CONNECT NC No connection to these pins 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VM Power supply voltage Logic ground voltage (LGND) MIN MAX UNIT –0.3 65 V –0.5 VM - 8 V LGND – 0.5 LGND + 7 V –0.6 0.6 V Peak motor drive output current, t < 1 μs Internally limited A Continuous motor drive output current (2) 2.5 A Digital pin voltage SRC12, SRC34 (pins 6 and 9 with optional sense resistor) to VNEG pins (pins 14 and 28) TJ Operating virtual junction temperature –40 150 °C Tstg Storage temperature –60 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Power dissipation and thermal limits must be observed. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±3000 Charged device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range, all voltages relative to VNEG terminal (unless otherwise noted) MIN VM Motor power supply voltage IV3P3 V3P3OUT load current TA Ambient temperature (1) 4 (1) NOM MAX UNIT 8 60 V 0 10 mA –40 125 °C All VM pins must be connected to the same supply voltage. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 DRV8844 www.ti.com SLVSBA2D – JULY 2012 – REVISED MAY 2016 6.4 Thermal Information DRV8844 THERMAL METRIC (1) PWP (HTSSOP) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 31.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 15.9 °C/W RθJB Junction-to-board thermal resistance 5.6 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 5.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics TA = 25°C, over operating free-air temperature range, all voltages relative to VNEG terminal (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES IVM VM operating supply current VM = 24 V, fPWM < 50 kHz 1 5 mA IVMQ VM sleep mode supply current VM = 24 V 500 800 μA VUVLO VM undervoltage lockout voltage VM rising 6.3 8 V 3.3 3.52 V LGND + 0.6 LGND + 0.7 V V3P3OUT REGULATOR V3P3 V3P3OUT voltage IOUT = 0 to 1 mA 3.18 LOGIC-LEVEL INPUTS VIL Input low voltage VIH Input high voltage VHYS Input hysteresis IIL Input low current VIN = LGND IIH Input high current VIN = LGND + 3.3 V RPD Internal pulldown resistance LGND + 2.2 LGND + 5.25 50 600 mV –5 5 μA 100 μA 100 V kΩ nFAULT OUTPUT (OPEN-DRAIN OUTPUT) VOL Output low voltage IO = 5 mA IOH Output high leakage current VO = LGND + 3.3 V LGND + 0.5 V 1 μA H-BRIDGE FETS HS FET on resistance RDS(ON) LS FET on resistance IOFF VM = 24 V, IO = 1 A, TJ = 25°C 0.24 VM = 24 V, IO = 1 A, TJ = 85°C 0.29 VM = 24 V, IO = 1 A, TJ = 25°C 0.24 VM = 24 V, IO = 1 A, TJ = 85°C 0.29 Off-state leakage current –2 0.39 Ω 0.39 2 μA PROTECTION CIRCUITS IOCP Overcurrent protection trip level tDEAD Output dead time tOCP Overcurrent protection deglitch time TTSD Thermal shutdown temperature 3 Die temperature 150 5 A 90 ns 5 µs 160 180 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 °C 5 DRV8844 SLVSBA2D – JULY 2012 – REVISED MAY 2016 www.ti.com 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) (1) (see Figure 1) NUMBER (1) PARAMETER TEST CONDITIONS MIN MAX UNIT 1 t1 Delay time, ENx high to OUTx high, INx = 1 130 330 ns 2 t2 Delay time, ENx low to OUTx low, INx = 1 275 475 ns 3 t3 Delay time, ENx high to OUTx low, INx = 0 100 300 ns 4 t4 Delay time, ENx low to OUTx high, INx = 0 200 400 ns 5 t5 Delay time, INx high to OUTx high 300 500 ns 6 t6 Delay time, INx low to OUTx low 275 475 ns 7 tR Output rise time, resistive load to VNEG 30 150 ns 8 tF Output fall time, resistive load to VNEG 30 150 ns Not production tested – specified by design ENx 50% 50% 1 OUTx 3 2 50% 50% OUTx INx = 1, resistive load to GND INx 50% 5 50% 80% 80% OUTx 6 50% 4 INx = 0, resistive load to VM 50% 50% 50% 50% ENx 20% 50% 20% OUTx 7 ENx = 1 resistive load to GND 8 Figure 1. DRV8844 Switching Characteristics 6 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 DRV8844 www.ti.com SLVSBA2D – JULY 2012 – REVISED MAY 2016 6.7 Typical Characteristics 140% 500 495 Sleep-mode Current (uA) 130% Rds(on) 120% 110% 100% 490 485 480 475 470 465 90% 460 80% -50 455 0 50 Temperature (qC) 100 150 0 10 20 D001 Figure 2. RDS(ON) vs Temperature 30 VM (V) 40 50 60 D002 Figure 3. Sleep-Mode Current vs VM 125% 120% Sleep-mode Current 115% 110% 105% 100% 95% 90% 85% 80% -50 0 50 Temperature (qC) 100 150 D003 Figure 4. Sleep-Mode Current vs Temperature Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 7 DRV8844 SLVSBA2D – JULY 2012 – REVISED MAY 2016 www.ti.com 7 Detailed Description 7.1 Overview The DRV8844 integrates four independent 2.5-A half-H bridges, protection circuits, sleep mode, and fault reporting. Its single power supply supports a wide 8 to 60 V, making it well-suited for motor drive applications, including brushed DC, steppers, and solenoids. 7.2 Functional Block Diagram VM VM VM 10µF 0.1µF VCP VCP Power VM Predriver VCP OUT1 OCP VNEG CP1 VCP Charge Pump 0.1µF VM CP2 Predriver V3P3OUT OUT2 OCP Regulators 0.47µF SRC12 LGND Core Logic PPAD VNEG VCP VM Predriver IN1 Optional Sense Resistor OUT3 OCP EN1 IN2 VCP VM EN2 Predriver IN3 EN3 Control Inputs OUT4 OCP SRC34 IN4 Protection EN4 Temperature sensor nRESET Overcurrent monitors Optional Sense Resistor Output nFAULT nSLEEP Undervoltage monitor VNEG VNEG Copyright © 2016, Texas Instruments Incorporated 8 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 DRV8844 www.ti.com SLVSBA2D – JULY 2012 – REVISED MAY 2016 7.3 Feature Description 7.3.1 Output Stage The DRV8844 contains four 1/2-H-bridge drivers using N-channel MOSFETs. A block diagram of the output circuitry is shown in Figure 5. VM VM VM Predrive IN1 EN1 OUT 1 OCP IN2 EN2 IN3 EN3 Predrive IN4 EN4 OUT2 OCP Logic Predrive OUT 3 OCP Predrive OUT4 OCP Figure 5. Motor Control Circuitry The output pins are driven between VM and VNEG. VNEG is normally ground for single supply applications, and a negative voltage for dual supply applications. Note that there are multiple VM motor power supply pins. All VM pins must be connected together to the motor supply voltage. 7.3.2 Logic Inputs The logic inputs and nFAULT output are referenced to the LGND pin. This pin would be connected to the logic ground of the source of the logic signals (for example, microcontroller). This allows LGND to be at a different voltage than VNEG; for example, the designer can drive a load with bipolar power supplies by driving VM with +24 V and VNEG with -24 V, and connect LGND to 0 V (ground). Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 9 DRV8844 SLVSBA2D – JULY 2012 – REVISED MAY 2016 www.ti.com Feature Description (continued) 7.3.3 Bridge Control The INx input pins directly control the state (high or low) of the OUTx outputs; the ENx input pins enable or disable the OUTx driver. Table 1 shows the logic. Table 1. H-Bridge Logic INx ENx OUTx X 0 Z 0 1 L 1 1 H The inputs can also be used for PWM control of, for example, the speed of a DC motor. When controlling a winding with PWM, when the drive current is interrupted, the inductive nature of the motor requires that the current must continue to flow. This is called recirculation current. To handle this recirculation current, the Hbridge can operate in two different states, fast decay or slow decay. In fast decay mode, the H-bridge is disabled and recirculation current flows through the body diodes; in slow decay, the motor winding is shorted. To PWM using fast decay, the PWM signal is applied to the ENx pin; to use slow decay, the PWM signal is applied to the INx pin. Table 2 is an example of driving a DC motor using OUT1 and OUT2 as an H-bridge: Table 2. PWM Function IN1 EN1 IN2 EN2 PWM 0 FUNCTION 1 0 1 Forward PWM, slow decay 1 PWM 1 Reverse PWM, slow decay 1 PWM 0 PWM Forward PWM, fast decay 0 PWM 1 PWM Reverse PWM, fast decay Figure 6 shows the current paths in different drive and decay modes: VM VM 1 Forward drive 1 OUT2 OUT1 1 Reverse drive 1 2 Fast decay 3 Slow decay OUT1 2 2 3 3 FORWARD 2 Fast decay OUT2 3 Slow decay REVERSE Figure 6. Current Paths 7.3.4 Charge Pump Because the output stages use N-channel FETs, a gate drive voltage higher than the VM power supply is needed to fully enhance the high-side FETs. The DRV8844 integrates a charge pump circuit that generates a voltage above the VM supply for this purpose. 10 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 DRV8844 www.ti.com SLVSBA2D – JULY 2012 – REVISED MAY 2016 The charge pump requires two external capacitors for operation. Refer to the block diagram and pin descriptions for details on these capacitors (value, connection, and so forth). The charge pump is shut down when nSLEEP is low. VM VM 10uF CP1 0.01uF 100V CP2 Charge Pump VCP 0.1uF 16V To pre-drivers Figure 7. Charge Pump 7.3.5 Protection Circuits The DRV8844 is fully protected against undervoltage, overcurrent and overtemperature events. 7.3.5.1 Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP deglitch time, the channel experiencing the overcurrent will be disabled and the nFAULT pin will be driven low. The driver will remain off until either RESET is asserted or VM power is cycled. Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. 7.3.5.2 Thermal Shutdown (TSD) If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume. 7.3.5.3 Undervoltage Lockout (UVLO) If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all outputs will be disabled, internal logic will be reset, and the nFAULT pin will be driven low. Operation will resume when VM rises above the UVLO threshold. 7.4 Device Functional Modes 7.4.1 nRESET and nSLEEP Operation The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge drivers. All inputs are ignored while nRESET is active. Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped and all internal clocks are stopped. In this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time (approximately 1 ms) needs to pass before the motor driver becomes fully operational. Note that nRESET and nSLEEP have internal pulldown resistors of approximately 100 kΩ. These signals need to be driven to logic high for device operation. The V3P3OUT LDO regulator remains operational in sleep mode. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 11 DRV8844 SLVSBA2D – JULY 2012 – REVISED MAY 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The DRV8844 can be used to drive one stepper motor, multiple brushed DC motors, or multiple other inductive loads. The outputs can be connected in parallel to increase the drive current. If connecting the outputs as in a fullbridge configuration, any two outputs can be connected in parallel. If configured as two independent half bridges, OUT1 and OUT2 must be paired, and OUT3 and OUT4 must be paired. This pairing is because pin 6 (SRC12) is the source for the low-side FETs of OUT1 and OUT2, and pin 9 (SRC34) is the source for the low-side FETs of OUT3 and OUT4. An optional sense resistor can be used to monitor the current. If using sense resistors, place the resistor between the SRC12 or SRC34 pins and the VNEG pins. 8.2 Typical Application OUT1 M OUT2 OUT3 OUT4 Copyright © 2016, Texas Instruments Incorporated Figure 8. Stepper Motor Connections 12 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 DRV8844 www.ti.com SLVSBA2D – JULY 2012 – REVISED MAY 2016 Typical Application (continued) OUT1 VM BDC OUT2 BDC OUT3 OUT4 Copyright © 2016, Texas Instruments Incorporated Figure 9. Example Showing a Bidirectional Brushed DC Motor, Single-Direction Brushed DC Motor, and an Inductive Load 8.2.1 Design Requirements The following truth tables describe how to control the arrangement in Figure 8. Table 3. Brushed DC Motor FUNCTION EN1 EN2 IN1 IN2 OUT1 Forward 1 1 PWM 0 H OUT2 L Reverse 1 1 0 PWM L H Brake 1 1 0 0 L L Brake 1 1 1 1 H H Coast 0 X X X Z X Coast X 0 X X X Z Table 4. Single-Direction Brushed DC Motor FUNCTION EN3 IN3 On 1 PWM OUT3 L Brake 1 1 H Coast 0 X Z Table 5. Inductive Loads FUNCTION EN4 IN4 OUT4 On 1 PWM H Off or slow decay 1 0 L Off or coast 0 X Z Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 13 DRV8844 SLVSBA2D – JULY 2012 – REVISED MAY 2016 www.ti.com 8.2.2 Detailed Design Procedure 8.2.2.1 Motor Voltage The ratings of the motor selected and the desired RPM determine the motor voltage the designer should use. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. 8.2.3 Application Curves Figure 10. DC Motor With 80 PWM 14 Submit Documentation Feedback Figure 11. IN1 to OUT1 Propagation Delay Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 DRV8844 www.ti.com SLVSBA2D – JULY 2012 – REVISED MAY 2016 9 Power Supply Recommendations 9.1 Bulk Capacitance Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: • The highest current required by the motor system • The power supply’s capacitance and ability to source current • The amount of parasitic inductance between the power supply and motor system • The acceptable voltage ripple • The type of motor used (Brushed DC, Brushless DC, Stepper) • The motor braking method The inductance between the power supply and the motor drive system limits the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Power Supply Parasitic Wire Inductance Motor Drive System VM + ± + Motor Driver GND Local Bulk Capacitor IC Bypass Capacitor Figure 12. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 15 DRV8844 SLVSBA2D – JULY 2012 – REVISED MAY 2016 www.ti.com 10 Layout 10.1 Layout Guidelines The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current. Small-value capacitors should be ceramic, and placed closely to device pins. The high-current device outputs should use wide metal traces. The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias help dissipate the I2 × RDS(on) heat that is generated in the device. 10.2 Layout Example + CP1 VNEG CP2 IN1 VCP EN1 VM IN2 OUT1 EN2 SRC12 IN3 OUT2 EN3 OUT3 IN4 SRC34 EN4 OUT4 LGND VM nFAULT NC nSLEEP NC nRESET VNEG V3P3OUT Figure 13. Layout Schematic 10.3 Thermal Considerations The DRV8844 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. 16 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 DRV8844 www.ti.com SLVSBA2D – JULY 2012 – REVISED MAY 2016 Thermal Considerations (continued) 10.3.1 Heatsinking The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers. For details about how to design the PCB, refer to TI application report SLMA002, PowerPAD™ Thermally Enhanced Package and TI application brief SLMA004, PowerPAD™ Made Easy, available at www.ti.com. In general, the more copper area that can be provided, the more power can be dissipated. 10.4 Power Dissipation Power dissipation in the DRV8844 is dominated by the power dissipated in the output FET resistance, or RDS(ON). Average power dissipation of each H-bridge when running a DC motor can be roughly estimated by Equation 1. P 2 u RDS(ON) u IOUT 2 where • • • P is the power dissipation of one H-bridge RDS(ON) is the resistance of each FET IOUT is the RMS output current being applied to each winding (1) IOUT is equal to the average current drawn by the DC motor. Note that at start-up and fault conditions this current is much higher than normal running current; these peak currents and their duration also need to be taken into consideration. The factor of 2 comes from the fact that at any instant two FETs are conducting winding current (one high-side and one low-side). The total device dissipation will be the power dissipated in each of the two H-bridges added together. The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 17 DRV8844 SLVSBA2D – JULY 2012 – REVISED MAY 2016 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • Calculating Motor Driver Power Dissipation, SLVA504 • DRV8844 Evaluation Module, SLVU762 • Understanding Motor Driver Current Ratings, SLVA505 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: DRV8844 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DRV8844PWP ACTIVE HTSSOP PWP 28 50 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 DRV8844 DRV8844PWPR ACTIVE HTSSOP PWP 28 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 DRV8844 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of