DS125DF1610FBE/NOPB

Product Folder Order Now Support & Community Tools & Software Technical Documents DS125DF1610 SNLS482B – APRIL 2014 – REVISED JANUARY 2017 DS125DF1610 9.8 to 12.5 Gbps 16-Channel Retimer 1 Features 3 Description • The DS125DF1610 is a sixteen-channel multi-rate retimer with integrated signal conditioning features. The device includes a fully adaptive Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), clock and data recovery (CDR), and a transmit FIR filter to enhance the reach and robustness over long, lossy, crosstalk impaired high speed serial links to achieve BER < 1×10-15. 1 • • • • • • • • • • • • • • • • • Pin-Compatible Family – DS150DF1610: 12.5 to 15 G – DS125DF1610: 9.8 to 12.5 G – DS110DF1610: 8.5 to 11.3 G 4x4 Analog Cross Point Switch for Each Quad Fully Adaptive CTLE Self tuning DFE, with Optional Continuous Adaption Configurable VGA Adjustable Transmit VOD Adjustable 3-tap Transmit FIR Filter On-chip AC Coupling on Receive Inputs Locks to Half/Quarter/Eighth Data Rates for Legacy Support On-chip Eye Monitor(EOM), PRBS Checker, Pattern Generator Supports JTAG Boundary Scan Programmable Output Polarity Inversion Input Signal Detection, CDR Lock Detection Single 2.5 V ±5% Power Supply SMBus Based Register Configuration Optional EEPROM Configuration 15 mm × 15 mm, 196-pin FCBGA Package Operating Temp Range : –40°C to +85°C Each channel of the DS125DF1610 independently locks to serial data at 9.8 to 12.5 Gbps and the divide by 2, 4 and 8 sub-multiples. A simple external oscillator (±100ppm) that is synchronous or asynchronous with the incoming data stream is used as a reference clock. Integrated 4x4 cross point switches allow for full non-blocking routing or broadcasting within each quad of the DS125DF1610. Programmable transmit FIR filter offers control of the pre-cursor, main tap and post-cursor for transmit equalization. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnects and backplanes with multiple connectors. A non-disruptive mission mode eye-monitor feature allows link monitoring internal to the receiver. The built-in PRBS generator and checker compliment the internal diagnostic features to complete standalone BERT measurements. Built-in JTAG enables manufacturing tests. Device Information 2 Applications • • • • SFF-8431 CPRI 10G/40G Ethernet Backplanes PART NUMBER DS125DF1610 (1) PACKAGE BODY SIZE NOM FCBGA (196) 15.00 mm x 15.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet Simplified Schematic DS125DF1610 . . . TX_0A_P TX_0A_N RX_7B_P RX_7B_N TX_7B_P TX_7B_N __________ INTERR_IO _________ . . . TDI_IO TDO_IO TRST_IO TMS_IO TCK_IO 25 MHz 1 F 2.5V 1 F 22 F (1x) 0.1 F (8x) 100nF RX_0A_P RX_0A_N REF_CLK_P REF_CLK_N VDD GND . . . . 100nF . . 100nF 2.5V or 3.3V 2k: 100nF 2k: 2k: 2k: RESET_IO SDA_IO SCL_IO CLK_MON_P CLK_MON_N EN_SMB READ_EN ADDR0 ADDR1 1k: 1k: 1k: 1k: 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS125DF1610 SNLS482B – APRIL 2014 – REVISED JANUARY 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 8 6.1 6.2 6.3 6.4 6.5 6.6 8 8 8 8 8 9 Absolute Maximum Ratings ..................................... Handling Ratings ...................................................... Recommended Operating Conditions....................... Thermal Information ................................................. Additional Thermal Information ................................ Electrical Characteristics........................................... Detailed Description ............................................ 13 7.1 7.2 7.3 7.4 7.5 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... 13 13 14 24 26 8 Application and Implementation ........................ 69 8.1 Application Information............................................ 69 8.2 Typical Applications ................................................ 70 8.3 Initialization Setup ................................................... 73 9 Power Supply Recommendations...................... 75 9.1 Power Supply Filtering ............................................ 75 10 Layout................................................................... 75 10.1 Layout Guidelines ................................................. 75 10.2 Layout Example .................................................... 76 11 Device and Documentation Support ................. 77 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support .................................................... Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 77 77 77 77 77 77 77 12 Mechanical, Packaging, and Orderable Information ........................................................... 77 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2015) to Revision B Page • Changed the minimum temperature from -20°C to -40°C ...................................................................................................... 1 • Changed the minimum temperature from -20°C to -40°C ..................................................................................................... 8 Changes from Original (April 2014) to Revision A • 2 Page Added full datasheet .............................................................................................................................................................. 1 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: DS125DF1610 DS125DF1610 www.ti.com SNLS482B – APRIL 2014 – REVISED JANUARY 2017 5 Pin Configuration and Functions Plastic Ball Grid Array 196 Balls Bottom View P N M L 01 02 TX_6B_N TX_6B_P GND GND GND GND TX_5B_N 03 04 05 06 TX_7A_N TX_7A_P GND 07 08 09 10 REF_CLK _P 11 12 13 14 K J H G F E D C B A TX_4B_N TX_4B_P GND GND TX_3A_N TX_3A_P GND GND TX_1A_N TX_1A_P TX_5B_P GND GND TX_4A_N TX_4A_P GND GND TX_2A_N TX_2A_P GND GND GND GND TX_5A_N TX_5A_P GND GND TX_2B_N TX_2B_P GND GND TX_0B_N TX_0B_P GND TX_6A_N TX_6A_P GND GND TX_3B_N TX_3B_P GND GND TX_1B_N TX_1B_P GND GND TX_7B_N TX_7B_P GND ALL_DON E VDD VDD GND READ_E N VDD VDD ADDR1 GND TX_0A_N TX_0A_P GND GND N/C SCL_IO VDD GND VDD GND VDD GND TCK_IO N/C ADDR0 GND N/C SDA_IO N/C GND VDD GND VDD GND VDD TDI_IO TDO_IO TMS_IO CLK_MO N_P REF_CLK _N EN_SMB INTERR# _IO RESET#_ IO VDD GND VDD GND VDD GND N/C TRST_IO N/C CLK_MO N_N GND GND N/C N/C GND VDD GND VDD GND VDD N/C N/C GND GND RX_7B_N RX_7B_P GND GND VDD VDD GND GND VDD VDD GND GND RX_0A_N RX_0A_P GND GND RX_6A_N RX_6A_P GND GND RX_3B_N RX_3B_P GND GND RX_1B_N RX_1B_P GND GND RX_7A_N RX_7A_P GND GND RX_5A_N RX_5A_P GND GND RX_2B_N RX_2B_P GND GND RX_0B_N RX_0B_P GND GND RX_5B_N RX_5B_P GND GND RX_4A_N RX_4A_P GND GND RX_2A_N RX_2A_P GND GND RX_6B_N RX_6B_P GND GND RX_4B_N RX_4B_P GND GND RX_3A_N RX_3A_P GND GND RX_1A_N RX_1A_P P N J H G F E D C B A M L K 01 02 03 04 05 06 07 08 09 10 11 12 13 14 (TOP VIEW) Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: DS125DF1610 3 DS125DF1610 SNLS482B – APRIL 2014 – REVISED JANUARY 2017 www.ti.com Pin Functions DS110DF1610, DS125DF1610 PIN NAME DS150DF1610 PIN NAME PIN I/O DESCRIPTION HIGH SPEED DIFFERENTIAL I/O RX_1A_P RX_1A_N RX_0_0P RX_0_0N A14 B14 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_0B_P Rx_0B_N RX_0_1P RX_0_1N A12 B12 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_0A_P RX_0A_N RX_0_2P RX_0_2N A10 B10 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_2A_P RX_2A_N RX_0_3P RX_0_3N C13 D13 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_1B_P RX_1B_N RX_0_4P RX_0_4N C11 D11 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_3A_P RX_3A_N RX_0_5P RX_0_5N E14 F14 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_2B_P RX_2B_N RX_0_6P RX_0_6N E12 F12 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_4A_P RX_4A_N RX_0_7P RX_0_7N G13 H13 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_3B_P RX_3B_N RX_1_0P RX_1_0N G11 H11 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_4B_P Rx_4B_N RX_1_1P RX_1_1N J14 K14 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_5A_P RX_5A_N RX_1_2P RX_1_2N J12 K12 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_5B_P RX_5B_N RX_1_3P RX_1_3N L13 M13 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_6A_P RX_6A_N RX_1_4P RX_1_4N L11 M11 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_6B_P RX_6B_N RX_1_5P RX_1_5N N14 P14 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_7A_P RX_7A_N RX_1_6P RX_1_6N N12 P12 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. RX_7B_P RX_7B_N RX_1_7P RX_1_7N N10 P10 I, CML Inverting and non-inverting CML-compatible, AC coupled differential inputs. An on-chip 100 Ohm differential termination resistor connects these inputs. TX_1A_P TX_1A_N TX_0_0P TX_0_0N A1 B1 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_0B_P TX_0B_N TX_0_1P TX_0_1N A3 B3 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_0A_P TX_0A_N TX_0_2P TX_0_2N A5 B5 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. 4 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: DS125DF1610 DS125DF1610 www.ti.com SNLS482B – APRIL 2014 – REVISED JANUARY 2017 Pin Functions (continued) DS110DF1610, DS125DF1610 PIN NAME DS150DF1610 PIN NAME PIN I/O DESCRIPTION TX_2A_P TX_2A_N TX_0_3P TX_0_3N C2 D2 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_1B_P TX_1B_N TX_0_4P TX_0_4N C4 D4 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_3A_P TX_3A_N TX_0_5P TX_0_5N E1 F1 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_2B_P TX_2B_N TX_0_6P TX_0_6N E3 F3 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_4A_P TX_4A_N TX_0_7P TX_0_7N G2 H2 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_3B_P TX_3B_N TX_1_0P TX_1_0N G4 H4 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_4B_P TX_4B_N TX_1_1P TX_1_1N J1 K1 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_5A_P TX_5A_N TX_1_2P TX_1_2N J3 K3 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_5B_P TX_5B_N TX_1_3P TX_1_3N L2 M2 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_6A_P TX_6A_N TX_1_4P TX_1_4N L4 M4 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_6B_P TX_6B_N TX_1_5P TX_1_5N N1 P1 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_7A_P TX_7A_N TX_1_6P TX_1_6N N3 P3 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. TX_7B_P TX_7B_N TX_1_7P TX_1_7N N5 P5 O, CML Inverting and non-inverting CML-compatible differential outputs. Driver presents an output impedance of 100 ohms between these outputs when switching. REF_CLK_P REF_CLK_N P7 P8 I, LVDS/ LVCMOS Inverting and non-inverting CML-compatible differential inputs for 25 MHz, 125 MHz, or 312.5 MHz clock. These differential signals are typically AC coupled with 1 µF capacitors When configured for single-ended input operation, apply LVCMOS ref clock to REF_CLK_P and float REF_CLK_N. Single-ended signals should be DC coupled. CLK_MON_P CLK_MON_N A7 A8 O, LVDS Inverting and non-inverting CML-compatible differential outputs to monitor system differential clock. When daisy chaining to another retimer the output frequency should be set to 25 MHz. M7 I/O, Open Drain CLOCK PINS SMBUS INTERFACE SDA_IO Data Input / Open Drain Output External pull-up resistor is required, typically in the 2kΩ to 5kΩ range. Pull-up value should be selected according to system implementation. Pin is 3.3 V LVCMOS tolerant. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: DS125DF1610 5 DS125DF1610 SNLS482B – APRIL 2014 – REVISED JANUARY 2017 www.ti.com Pin Functions (continued) DS110DF1610, DS125DF1610 PIN NAME DS150DF1610 PIN NAME PIN I/O DESCRIPTION L6 I/O, Open Drain Clock input/output External pull-up resistor is required, typically in the 2kΩ to 5kΩ range. Pull-up value should be selected according to system implementation. Pin is 3.3 V LVCMOS tolerant EEPROM configuration (SMBus Master mode) TMS_IO B7 I, LVCMOS JTAG Test Mode Select, internal pull-up TDO_IO C7 O, LVCMOS JTAG Test Data Out TRST_IO C8 I, LVCMOS JTAG Test Reset, internal pull-up TCK_IO D6 I, LVCMOS JTAG Test clock, internal pull-up TDI_IO D7 I, LVCMOS JTAG Test Data Input, internal pull-up RESET_IO L8 I, LVCMOS Resets registers and state machines on rising edge. Pulse LOW for minimum of 10µs to perform reset. Pin should be pulled HIGH during power on. INTERR_IO M8 O, Open Drain Active Low interrupt signal. Pin goes low when an interrupt event occurs. Interrupts must be enabled via SMBus. ADDR0 B6 I, LVCMOS 4 level input strap pin for SMBus address code LSB. Standard LVCMOS output. ADDR1 D5 I, LVCMOS 4 level input strap pin for SMBus address code MSB. Standard LVCMOS output. READ_EN G5 I, LVCMOS Tie LOW for SMBus slave mode normal operation. Pin has internal pull down. In SMBus slave mode, tie HIGH to force SMBus address = 0x30. ALL_DONE L5 O, LVCMOS EEPROM load status. Pin goes LOW when EEPROM load is complete. EN_SMB N8 I, LVCMOS Connect to GND through ≤1kΩ resistor for SMBus slave operation. Connect to VDD through ≤1kΩ resistor for EEPROM configuration E5, E7, E9, E10, F5, F6, F8, F10, G7, G9, H6, H8, J5, J7, J9, J10, K5, K6, K8, K10 Power SCL_IO JTAG INTERFACE (1) OTHER PINS POWER VDD (1) 6 VDD = 2.5 V +/- 5% Refer to the DS125DF1610 Programming Guide for additional information Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: DS125DF1610 DS125DF1610 www.ti.com SNLS482B – APRIL 2014 – REVISED JANUARY 2017 Pin Functions (continued) DS110DF1610, DS125DF1610 PIN NAME DS150DF1610 PIN NAME PIN I/O GND A2, A4, A6, A9, A11, A13, B2, B4, B9, B11, B13, C1, C3, C5, C10, C12, C14, D1, D3, D10, D12, D14, E2, E4, E6, E8, E11, E13, F2, F4, F7, F9, F11, F13, G1, G3, G6, G8, G10, G12, G14, H1, H3, H5, H7, H9, H10, H12, H14, J2, J4, J6, J8, J11, J13, K2, K4, K7, K9, K11, K13, L1, L3, L10, L12, L14, M1, M3, M5, M10, M12, M14, N2, N4, N6, N9, N11, N13, P2, P4, P6, P9, P11, P13 Power N/C B8, C6, C9, D8, D9, L7, L9, M6, M9, N7 DESCRIPTION Ground reference No Connect, leave floating Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: DS125DF1610 7 DS125DF1610 SNLS482B – APRIL 2014 – REVISED JANUARY 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) Over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply Voltage (VDD) –0.5 2.75 V LVCMOS Input/Output Voltage –0.5 2.75 V Open Drain I/O Supply Voltage –0.5 4.0 V CML Input Voltage –0.5 (VDD + 0.5) V CML Input Current –30 30 mA Storage temperature range, Tstg -40 150 °C (1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications 6.2 Handling Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±4,000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) V ±1,000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted) Supply Voltage Ambient Temperature MIN TYP MAX 2.375 2.5 2.625 V –40 25 85 °C 2.5 3.6 V 115 °C SMBus (SDA, SCL), INTERR_IO Maximum Continuous Junction Temperature while Device is Operational UNIT 6.4 Thermal Information THERMAL METRIC (1) DS125DF1610 FCBGA ABB (196) PINS (2) RθJA Junction-to-ambient thermal resistance 18.2 RθJC(top) Junction-to-case (top) thermal resistance 0.7 RθJB Junction-to-board thermal resistance 5.3 ψJT Junction-to-top characterization parameter 0.8 ψJB Junction-to-board characterization parameter 5.3 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A (1) (2) UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal model available upon request 6.5 Additional Thermal Information 8 BOARD θJC (°C / W) θJA (°C / W) ψJT(°C / W) ψJB(°C / W) JEDEC 4 layer board, no airflow 0.7 18.2 0.8 5.3 8x6 inches 10 layer, no airflow 0.7 7.2 0.3 3.2 8x6 inches 20 layer, no airflow 0.7 6.4 0.3 3.2 8x6 inches 30 layer, no airflow 0.7 6.3 0.3 3.2 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: DS125DF1610 DS125DF1610 www.ti.com SNLS482B – APRIL 2014 – REVISED JANUARY 2017 6.6 Electrical Characteristics Over operating free-air temperature range (unless otherwise noted) SYMBOL R_baud PARAMETER CONDITIONS Input Data Rate MIN TYP MAX UNIT Full Rate 9.8 12.5 Gbps Half Rate 4.9 6.25 Gbps Quarter Rate 2.45 3.125 Gbps Eighth Rate 1.225 1.5625 Gbps POWER SUPPLY W Power Consumption per Active Channel WSTATIC Device Static Power Consumption NTPS Power Supply Noise Tolerance CTLE only, 800mVp-p VOD, per channel, CDR locked 175 mW CDR Locking with CTLE only, 800mVp-p VOD, per channel 325 mW CTLE and DFE, 800mVpp VOD, per channel, CDR locked 200 323 mW CDR Locking with CTLE and DFE, 800mVp-p VOD 350 535.5 mW PRBS Checker 100 mW PRBS Generator 105 mW Power Applied to Device, No Signals Present 325 50 Hz to 100 Hz 100 100 Hz to 10 MHz 40 10 MHz to 5.0 GHz 10 1325 mW mVPP LVCMOS V IH High level input voltage VIL Low level input voltage VOH High level output voltage IOH = 4mA VOL Low level output voltage IOL = -4mA 0.4 V Vinput = VDD, Open Drain terminals 30 µA Vinput = VDD, JTAG terminals, Ref_CLK terminals 25 µA Vinput = VDD, ADDR, READ_EN, ALL_DONE terminals, EN_SMB terminal 75 µA IIH IIL Input High Leakage current Input Low Leakage current 1.75 VDD V GND 0.7 V 2 V Vinput = 0V, Open drain terminals -15 µA Vinput = 0V, JTAG terminals, Ref_CLK terminals -45 µA Vinput = 0V, ADDR, READ_EN, ALL_DONE terminals, EN_SMB terminal -120 µA Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: DS125DF1610 9 DS125DF1610 SNLS482B – APRIL 2014 – REVISED JANUARY 2017 www.ti.com Electrical Characteristics (continued) Over operating free-air temperature range (unless otherwise noted) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT 80 100 120 Ω 1600 mVPP RX INPUTS RRD DC Input Resistance VRX-IN Input Differential Voltage VSDAT Signal Detect Assert Threshold Signal Detect De-Assert Threshold VSDDT Vcm-RX Input common mode Differential voltage seen at the high speed input terminals (1) Default setting 1T pattern, 12.5 Gbps 110 Default setting PRBS-31, 12.5 Gbps 24 Default setting 1T pattern, 12.5 Gbps 70 Default setting PRBS-31, 12.5 Gbps 21 Internal coupling cap mVPP mVPP VDD - (VRXIN/ 4) VRX-IN / 4 V TX OUTPUTS VOD Output Differential Voltage ΔVOD Step Size for drv_sel_vod Control ΔVODVT drv_sel_vod[5:0] = 31, DEM, FIR = default 725 935 1135 drv_sel_vod[5:0] = 15, DEM, FIR = default 350 470 595 mVPP Default DEM, and FIR settings 50 mVPP Change in Output Differential Voltage due to Change in Temperature and Voltage