DS250DF230
SNLS590C – AUGUST 2018 – REVISED JUNE 2021
DS250DF230 25-Gbps Multi-Rate 2-Channel Retimer
1 Features
3 Description
•
The DS250DF230 is a dual-channel multi-rate retimer
with integrated signal conditioning. The device is used
to extend the reach and robustness of long, lossy,
crosstalk-impaired high-speed serial links and while
achieving a bit error rate (BER) of 10–15 or less.
•
•
•
•
•
•
•
•
•
•
•
Dual-channel multi-rate retimer with integrated
signal conditioning
All channels lock independently from 19.6 to
25.8 Gbps (including sub-rates, such as 12.16512
Gbps, 9.8304 Gbps, 6.144 Gbps, and more)
Ultra-low latency: 2, then a fixed EQ
setting, from Reg_0x3A will be used.
However, if Reg_0x6F[7]=1, then an
EQ adaptation will be performed
instead.
6
0
RW
Y
RESERVED
RESERVED
5
0
RW
Y
RESERVED
RESERVED
4
0
RW
N
RESERVED
RESERVED
3
0
RW
N
RESERVED
RESERVED
2
0
RW
N
RESERVED
RESERVED
1
0
RW
N
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
7
0
RW
N
RESERVED
RESERVED
6
0
RW
N
RESERVED
RESERVED
5
0
RW
N
RESERVED
RESERVED
4
0
RW
N
RESERVED
RESERVED
3
0
RW
Y
EQ_LB_CNT[3]
2
1
RW
Y
EQ_LB_CNT[2]
CTLE look-beyond count for
adaptation
1
0
RW
Y
EQ_LB_CNT[1]
0
1
RW
Y
EQ_LB_CNT[0]
7
0
R
N
PRBS_INT
70
71
MODE
EEPROM
FIELD NAME
DESCRIPTION
When enabled by Reg_0x31[7], goes
HI if a PRBS stream is detected.
Clears on reading.
PRBS checker must be enabled with
Reg_0x30[3].
Once cleared, if a PRBS error occurs,
then the interrupt will again go HI.
Clears on reading.
If signal detect is lost, this is
considered a PRBS error, and the
interrupt will go HI. Clears on reading.
76
6
0
R
N
RESERVED
RESERVED
5
0
R
N
DFE_POL_1_OBS
DFE tap 1 polarity observation
4
0
R
N
DFE_WT1_OBS[4]
DFE tap 1 weight observation
3
0
R
N
DFE_WT1_OBS[3]
2
0
R
N
DFE_WT1_OBS[2]
1
0
R
N
DFE_WT1_OBS[1]
0
0
R
N
DFE_WT1_OBS[0]
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Product Folder Links: DS250DF230
DS250DF230
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SNLS590C – AUGUST 2018 – REVISED JUNE 2021
Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
72
7
0
R
N
RESERVED
RESERVED
6
0
R
N
RESERVED
RESERVED
5
0
R
N
RESERVED
RESERVED
4
0
R
N
DFE_POL_2_OBS
Primary observation point for DFE tap
2 polarity
3
0
R
N
DFE_WT2_OBS[3]
2
0
R
N
DFE_WT2_OBS[2]
Primary observation point for DFE tap
2 weight
1
0
R
N
DFE_WT2_OBS[1]
0
0
R
N
DFE_WT2_OBS[0]
7
0
R
N
RESERVED
RESERVED
6
0
R
N
RESERVED
RESERVED
5
0
R
N
RESERVED
RESERVED
4
0
R
N
DFE_POL_3_OBS
Primary observation point for DFE tap
3 polarity
3
0
R
N
DFE_WT3_OBS[3]
2
0
R
N
DFE_WT3_OBS[2]
Primary observation point for DFE tap
3 weight
1
0
R
N
DFE_WT3_OBS[1]
0
0
R
N
DFE_WT3_OBS[0]
7
0
R
N
RESERVED
RESERVED
6
0
R
N
RESERVED
RESERVED
5
0
R
N
RESERVED
RESERVED
4
0
R
N
DFE_POL_4_OBS
Primary observation point for DFE tap
4 polarity
3
0
R
N
DFE_WT4_OBS[3]
2
0
R
N
DFE_WT4_OBS[2]
Primary observation point for DFE tap
4 weight
1
0
R
N
DFE_WT4_OBS[1]
0
0
R
N
DFE_WT4_OBS[0]
7
0
R
N
RESERVED
RESERVED
6
0
R
N
RESERVED
RESERVED
5
0
R
N
RESERVED
RESERVED
4
0
R
N
DFE_POL_5_OBS
Primary observation point for DFE tap
5 polarity
3
0
R
N
DFE_WT5_OBS[3]
2
0
R
N
DFE_WT5_OBS[2]
Primary observation point for DFE tap
5 weight
1
0
R
N
DFE_WT5_OBS[1]
0
0
R
N
DFE_WT5_OBS[0]
73
74
75
MODE
EEPROM
FIELD NAME
DESCRIPTION
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77
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SNLS590C – AUGUST 2018 – REVISED JUNE 2021
Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
76
7
0
RW
Y
POST_LOCK_VEO_THR[3]
6
0
RW
Y
POST_LOCK_VEO_THR[2]
5
1
RW
Y
POST_LOCK_VEO_THR[1]
4
0
RW
Y
POST_LOCK_VEO_THR[0]
3
0
RW
Y
POST_LOCK_HEO_THR[3]
2
0
RW
Y
POST_LOCK_HEO_THR[2]
1
0
RW
Y
POST_LOCK_HEO_THR[1]
0
1
RW
Y
POST_LOCK_HEO_THR[0]
7
0
RW
N
PRBS_GEN_POL_EN
1: Force polarity inversion on
generated PRBS data
6
0
RW
Y
RESERVED
RESERVED
5
0
RW
Y
RESERVED
RESERVED
4
1
RW
Y
RESERVED
RESERVED
3
1
RW
Y
RESERVED
RESERVED
2
0
RW
Y
RESERVED
RESERVED
1
1
RW
Y
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
77
78
MODE
EEPROM
FIELD NAME
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DESCRIPTION
VEO threshold after LOCK is
established
HEO threshold after LOCK is
established
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SNLS590C – AUGUST 2018 – REVISED JUNE 2021
Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
78
7
0
R
N
RESERVED
RESERVED
6
0
R
N
RESERVED
RESERVED
5
0
R
N
SD_STATUS
Primary observation point for signal
detect status
4
0
R
N
CDR_LOCK_STATUS
Primary observation point for CDR
lock status
3
0
R
N
CDR_LOCK_INT
Requires that channel Reg_0x79[1] be
set.
1: Indicates CDR has achieved lock,
lock goes from LOW to HIGH. This bit
is cleared after reading. This bit will
MODE
EEPROM
FIELD NAME
DESCRIPTION
stay set until it has been cleared by
reading.
79
2
0
R
N
SD_INT
Requires that channel Reg_0x79[0] be
set.
1: Indicates signal detect status has
changed. This will trigger when signal
detect goes from LOW to HIGH or
HIGH to LOW. This bit is cleared after
reading. This bit will stay set until it
has been cleared by reading.
1
0
R
N
EOM_VRANGE_LIMIT_ERROR
Goes high if GET_HEO_VEO
indicates high during adaptation
0
0
R
N
HEO_VEO_INT
Requires that channel Reg_0x36[6] be
set.
1: Indicates that HEO/VEO dropped
below the limits set in channel
Reg_0x76 This bit is cleared after
reading. This bit will stay set until it
has been cleared by reading.
7
0
RW
N
RESERVED
RESERVED
6
0
RW
N
PRBS_CHKR_EN
1: Enable the PRBS checker.
0: Disable the PRBS checker
5
0
RW
N
PRBS_GEN_EN
1: Enable the pattern generator
0: Disable the pattern generator
4
1
RW
N
RESERVED
RESERVED
3
0
RW
N
RESERVED
RESERVED
2
0
RW
N
RESERVED
RESERVED
1
0
RW
Y
CDR_LOCK_INT_EN
1: Enable CDR lock interrupt,
observable in channel Reg_0x78[3]
0: Disable CDR lock interrupt
0
0
RW
Y
SD_INT_EN
1: Enable signal detect interrupt,
observable in channel Reg_0x78[3]
0: Disable signal detect interrupt
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SNLS590C – AUGUST 2018 – REVISED JUNE 2021
Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
7A
7
0
RW
N
RESERVED
RESERVED
6
0
RW
N
RESERVED
RESERVED
5
0
RW
N
RESERVED
RESERVED
4
0
RW
N
RESERVED
RESERVED
3
0
RW
N
RESERVED
RESERVED
2
0
RW
N
RESERVED
RESERVED
1
0
RW
N
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
7
0
RW
N
RESERVED
RESERVED
6
0
RW
N
RESERVED
RESERVED
5
0
RW
N
RESERVED
RESERVED
4
0
RW
N
RESERVED
RESERVED
3
0
RW
N
RESERVED
RESERVED
2
0
RW
N
RESERVED
RESERVED
1
0
RW
N
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
7
0
R
N
PRBS_FIXED[7]
6
0
R
N
PRBS_FIXED[6]
5
0
R
N
PRBS_FIXED[5]
Pattern generator user defined pattern
LSB. MSB located at channel
Reg_0x97.
4
0
R
N
PRBS_FIXED[4]
3
0
R
N
PRBS_FIXED[3]
2
0
R
N
PRBS_FIXED[2]
1
0
R
N
PRBS_FIXED[1]
0
0
R
N
PRBS_FIXED[0]
7B
7C
80
MODE
EEPROM
FIELD NAME
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DESCRIPTION
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DS250DF230
DS250DF230
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SNLS590C – AUGUST 2018 – REVISED JUNE 2021
Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
7D
7
0
RW
Y
CONT_ADAPT_HEO_CHNG_TH
RS[3]
6
1
RW
Y
CONT_ADAPT_HEO_CHNG_TH
RS[2]
5
0
RW
Y
CONT_ADAPT_HEO_CHNG_TH
RS[1]
4
0
RW
Y
CONT_ADAPT_HEO_CHNG_TH
RS[0]
3
1
RW
Y
CONT_ADAPT_VEO_CHNG_TH
RS[3]
2
0
RW
Y
CONT_ADAPT_VEO_CHNG_TH
RS[2]
1
0
RW
Y
CONT_ADAPT_VEO_CHNG_TH
RS[1]
0
0
RW
Y
CONT_ADAPT_VEO_CHNG_TH
RS[0]
7
0
RW
Y
CONT_ADPT_TAP_INCR[3]
6
0
RW
Y
CONT_ADPT_TAP_INCR[2]
5
0
RW
Y
CONT_ADPT_TAP_INCR[1]
4
1
RW
Y
CONT_ADPT_TAP_INCR[0]
3
0
RW
Y
RESERVED
RESERVED
2
0
RW
Y
RESERVED
RESERVED
1
1
RW
Y
RESERVED
RESERVED
0
1
RW
Y
RESERVED
RESERVED
7E
MODE
EEPROM
FIELD NAME
DESCRIPTION
Limit for HEO change before triggering
a DFE adaption while continuous DFE
adaption is enabled.
Limit for VEO change before triggering
a DFE adaption while continuous DFE
adaption is enabled.
(Refer to the Programming Guide for
more details)
Limit for allowable tap increase from
the previous base point
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SNLS590C – AUGUST 2018 – REVISED JUNE 2021
Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
7F
7
0
RW
N
EN_OBS_ALT_FOM
1: Allows for alternate FoM calculation
to be shown in channel registers
Reg_0x27, Reg_0x28 and Reg_0x29
instead of HEO and VEO
6
0
RW
N
RESERVED
RESERVED
5
1
RW
Y
RESERVED
RESERVED
4
0
RW
Y
EN_DFE_CONT_ADAPT
1: Continuous DFE adaption is
enabled
0: DFE adapts only during lock and
then freezes
(Refer to the Programming Guide for
MODE
EEPROM
FIELD NAME
DESCRIPTION
more details)
80
81
82
3
1
RW
Y
CONT_ADPT_CMP_BOTH
1: If continuous DFE adaption is
enabled, a DFE adaption will trigger if
either HEO orVEO degrades
2
0
RW
Y
CONT_ADPT_COUNT[2]
1
1
RW
Y
CONT_ADPT_COUNT[1]
0
0
RW
Y
CONT_ADPT_COUNT[0]
Limit for number of weights the
DFE can look ahead in continuous
adaption.
(Refer to the Programming Guide for
more details)
7
0
R
N
RESERVED
RESERVED
6
0
R
N
RESERVED
RESERVED
5
0
R
N
RESERVED
RESERVED
4
0
R
N
RESERVED
RESERVED
3
0
R
N
RESERVED
RESERVED
2
0
R
N
RESERVED
RESERVED
1
0
R
N
RESERVED
RESERVED
0
0
R
N
RESERVED
RESERVED
7
1
R
N
RESERVED
RESERVED
6
1
R
N
RESERVED
RESERVED
5
1
R
N
RESERVED
RESERVED
4
0
R
N
RESERVED
RESERVED
3
0
R
N
RESERVED
RESERVED
2
1
R
N
RESERVED
RESERVED
1
0
R
N
RESERVED
RESERVED
0
0
R
N
RESERVED
RESERVED
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Product Folder Links: DS250DF230
DS250DF230
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SNLS590C – AUGUST 2018 – REVISED JUNE 2021
Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
82
7
0
RW
N
FREEZE_PRBS_CNTR
1: Freeze the PRBS error count to
allow for readback.
0: Normal operation. Error counters
is allowed to increment if the PRBS
checker is properly configured
6
0
RW
N
RST_PRBS_CNTS
1: Reset the PRBS error counter.
0: Normal operation. Error counter is
released from reset.
5
0
RW
N
PRBS_PATT_OV
1: Override PRBS pattern autodetection. Forces the pattern checker
to only lock onto the pattern defined in
Reg_0x82[4:2].
0: Normal operation. Pattern checker
will automatically detect the PRBS
pattern
4
0
RW
N
PRBS_PATT[2]
3
0
RW
N
PRBS_PATT[1]
2
0
RW
N
PRBS_PATT[0]
Used with the PRBS checker. Usage
is enabled with Reg_0x82[5]. Select
PRBS pattern to be checked:
000 - PRBS7
001 - PRBS9
010 - PRBS11
011 - PRBS15
100 - PRBS23
101 - PRBS31
110 - PRBS58
111 - PRBS63
1
0
RW
N
PRBS_POL_OV
MODE
EEPROM
FIELD NAME
DESCRIPTION
1: Override PRBS pattern auto polarity
detection. Forces the pattern checker
to only lock onto the polarity defined in
bit 0 of this register.
0: Normal operation, pattern checker
will automatically detect the PRBS
pattern polarity
83
0
0
RW
N
PRBS_POL
Usage is enabled with Reg_0x82[1]=1
0: Forced polarity = true
1: Forced polarity = inverted
7
0
R
N
RESERVED
RESERVED
6
0
R
N
RESERVED
RESERVED
5
0
R
N
RESERVED
RESERVED
4
0
R
N
RESERVED
RESERVED
3
0
R
N
RESERVED
RESERVED
2
0
R
N
PRBS_ERR_CNT[10]
PRBS checker error count
1
0
R
N
PRBS_ERR_CNT[9]
0
0
R
N
PRBS_ERR_CNT[8]
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SNLS590C – AUGUST 2018 – REVISED JUNE 2021
Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
84
7
0
R
N
PRBS_ERR_CNT[7]
6
0
R
N
PRBS_ERR_CNT[6]
5
0
R
N
PRBS_ERR_CNT[5]
4
0
R
N
PRBS_ERR_CNT[4]
3
0
R
N
PRBS_ERR_CNT[3]
2
0
R
N
PRBS_ERR_CNT[2]
1
0
R
N
PRBS_ERR_CNT[1]
0
0
R
N
PRBS_ERR_CNT[0]
7
0
R
N
RESERVED
RESERVED
6
0
R
N
RESERVED
RESERVED
5
0
R
N
RESERVED
RESERVED
4
0
R
N
RESERVED
RESERVED
3
0
R
N
RESERVED
RESERVED
2
0
R
N
RESERVED
RESERVED
1
0
R
N
RESERVED
RESERVED
0
0
R
N
RESERVED
RESERVED
7
0
R
N
RESERVED
RESERVED
6
0
R
N
RESERVED
RESERVED
5
0
R
N
RESERVED
RESERVED
4
0
R
N
RESERVED
RESERVED
3
0
R
N
RESERVED
RESERVED
2
0
R
N
RESERVED
RESERVED
1
0
R
N
RESERVED
RESERVED
0
0
R
N
RESERVED
RESERVED
7
0
R
N
RESERVED
RESERVED
6
0
R
N
RESERVED
RESERVED
5
0
R
N
RESERVED
RESERVED
4
0
R
N
RESERVED
RESERVED
3
0
R
N
RESERVED
RESERVED
2
0
R
N
RESERVED
RESERVED
1
0
R
N
RESERVED
RESERVED
0
0
R
N
RESERVED
RESERVED
85
86
87
84
MODE
EEPROM
FIELD NAME
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DESCRIPTION
PRBS checker error count
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DS250DF230
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SNLS590C – AUGUST 2018 – REVISED JUNE 2021
Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
88
7
0
R
N
RESERVED
RESERVED
6
0
R
N
RESERVED
RESERVED
5
0
R
N
RESERVED
RESERVED
4
0
R
N
RESERVED
RESERVED
3
0
R
N
RESERVED
RESERVED
2
0
R
N
RESERVED
RESERVED
1
0
R
N
RESERVED
RESERVED
0
0
R
N
RESERVED
RESERVED
7
0
R
N
RESERVED
RESERVED
6
0
R
N
RESERVED
RESERVED
5
0
R
N
RESERVED
RESERVED
4
0
R
N
RESERVED
RESERVED
3
0
R
N
RESERVED
RESERVED
2
0
R
N
RESERVED
RESERVED
1
0
R
N
RESERVED
RESERVED
0
0
R
N
RESERVED
RESERVED
7
0
R
N
RESERVED
RESERVED
6
0
R
N
RESERVED
RESERVED
5
0
R
N
RESERVED
RESERVED
4
0
R
N
RESERVED
RESERVED
3
0
R
N
RESERVED
RESERVED
2
0
R
N
RESERVED
RESERVED
1
0
R
N
RESERVED
RESERVED
0
0
R
N
RESERVED
RESERVED
7
0
RW
N
RESERVED
RESERVED
6
0
RW
N
RESERVED
RESERVED
5
0
RW
N
RESERVED
RESERVED
4
0
RW
N
RESERVED
RESERVED
3
0
RW
N
RESERVED
RESERVED
2
0
RW
N
RESERVED
RESERVED
1
0
RW
N
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
89
8A
8B
MODE
EEPROM
FIELD NAME
DESCRIPTION
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SNLS590C – AUGUST 2018 – REVISED JUNE 2021
Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
8C
7
0
RW
N
RESERVED
RESERVED
6
0
RW
N
RESERVED
RESERVED
5
0
RW
N
RESERVED
RESERVED
4
0
RW
N
RESERVED
RESERVED
3
0
RW
N
RESERVED
RESERVED
2
0
RW
N
RESERVED
RESERVED
1
0
RW
N
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
7
0
RW
N
RESERVED
RESERVED
6
0
RW
N
RESERVED
RESERVED
5
0
RW
N
RESERVED
RESERVED
4
0
RW
N
RESERVED
RESERVED
3
0
RW
N
RESERVED
RESERVED
2
0
RW
N
RESERVED
DS250DF230: RESERVED, 0
1
1
RW
N
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
7
0
RW
N
RESERVED
RESERVED
6
0
RW
N
RESERVED
RESERVED
5
0
RW
N
RESERVED
RESERVED
4
0
RW
N
RESERVED
RESERVED
3
0
RW
N
RESERVED
RESERVED
2
0
RW
N
RESERVED
RESERVED
1
0
RW
N
RESERVED
RESERVED
0
0
RW
Y
VGA_SEL_GAIN
VGA selection bit :
1: VGA high-gain mode
0: VGA low-gain mode
(Refer to the Programming Guide for
more details)
7
0
R
N
EQ_BST_TO_EQ[7]
6
0
R
N
EQ_BST_TO_EQ[6]
Primary observation point for the EQ
boost setting.
5
0
R
N
EQ_BST_TO_EQ5]
4
0
R
N
EQ_BST_TO_EQ[4]
3
0
R
N
EQ_BST_TO_EQ[3]
2
0
R
N
EQ_BST_TO_EQ[2]
1
0
R
N
EQ_BST_TO_EQ[1]
0
0
R
N
EQ_BST_TO_EQ[0]
8D
8E
8F
86
MODE
EEPROM
FIELD NAME
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DESCRIPTION
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Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
90
7
0
RW
N
RESERVED
RESERVED
6
0
RW
N
RESERVED
RESERVED
5
0
RW
N
RESERVED
RESERVED
4
0
RW
N
RESERVED
RESERVED
3
0
RW
N
RESERVED
RESERVED
2
0
RW
N
RESERVED
RESERVED
1
0
RW
N
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
7
0
RW
N
RESERVED
RESERVED
6
0
RW
N
RESERVED
RESERVED
5
0
RW
N
RESERVED
RESERVED
4
0
RW
N
RESERVED
RESERVED
3
0
RW
N
RESERVED
RESERVED
2
0
RW
N
RESERVED
RESERVED
1
0
RW
N
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
92
7:0
0
RW
N
RESERVED
RESERVED
93
7:0
0
RW
N
RESERVED
RESERVED
94
7:0
0
RW
N
RESERVED
RESERVED
95
`
0
RW
N
SD_ENABLE
1: Force enable signal detect
0: Normal operation
6
0
RW
N
SD_DISABLE
1: Force disable signal detect
0: Normal operation
5
0
RW
N
DC_OFF_ENABLE
1: Force enable DC offset
compensation
0: Normal operation
4
0
RW
N
DC_OFF_DISABLE
1: Force disable DC offset
compensation
0: Normal operation
3
0
RW
N
EQ_ENABLE
DS250DF230: 0
1: Force enable the CTLE
0: Normal operation
2
0
RW
N
EQ_DISABLE
1: Force disable the CTLE
0: Normal operation
1
0
RW
N
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
91
MODE
EEPROM
FIELD NAME
DESCRIPTION
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Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
96
7
0
RW
N
RESERVED
RESERVED
6
0
RW
N
RESERVED
RESERVED
5
0
RW
N
RESERVED
RESERVED
4
0
RW
N
RESERVED
RESERVED
3
1
RW
Y
EQ_EN_LOCAL
1: Enable the ebuf for the local output.
Can be set independently of other
controls.
(Refer to the Programming Guide for
more details)
2
0
RW
Y
EQ_EN_FANOUT
1: Enable the ebuf for the fanout. Can
be set independently of other controls.
(Refer to the Programming Guide for
more details)
1
0
RW
Y
EQ_SEL_XPNT
1: Indicates to a channel where it is
getting its data from. 0 indicates local.
1-indicates from the cross.
(Refer to the Programming Guide for
more details)
0
0
RW
Y
XPNT_SLAVE
1: Indicates to a channel if it needs to
wait for the other channel to complete
its lock/adaptation. The need for this
condition comes up when input of one
channel is routed to the other channel
or multiple channels.
(Refer to the Programming Guide for
more details)
7
0
R
N
PRBS_FIXED[15]
6
0
R
N
PRBS_FIXED[14]
5
0
R
N
PRBS_FIXED[13]
Pattern generator user defined pattern
MSB. LSB located at channel
Reg_0x7C.
4
0
R
N
PRBS_FIXED[12]
3
0
R
N
PRBS_FIXED[11]
2
0
R
N
PRBS_FIXED[10]
1
0
R
N
PRBS_FIXED[9]
0
0
R
N
PRBS_FIXED[8]
7:6
0
RW
N
RESERVED
RESERVED
5:0
0
RW
Y
RESERVED
RESERVED
97
98
88
MODE
EEPROM
FIELD NAME
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Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
99
7
0
RW
Y
RESERVED
RESERVED
6
0
RW
Y
RESERVED
RESERVED
5
1
RW
Y
RESERVED
RESERVED
4
1
RW
Y
RESERVED
RESERVED
3
1
RW
Y
RESERVED
RESERVED
2
1
RW
Y
RESERVED
RESERVED
1
1
RW
Y
RESERVED
RESERVED
0
1
RW
Y
RESERVED
RESERVED
7
0
RW
Y
RESERVED
RESERVED
6
0
RW
Y
RESERVED
RESERVED
5
1
RW
Y
RESERVED
RESERVED
4
1
RW
Y
RESERVED
RESERVED
3
1
RW
Y
RESERVED
RESERVED
2
1
RW
Y
RESERVED
RESERVED
1
1
RW
Y
RESERVED
RESERVED
0
1
RW
Y
RESERVED
RESERVED
7
1
RW
Y
RESERVED
RESERVED
6
1
RW
Y
RESERVED
RESERVED
5
1
RW
Y
RESERVED
RESERVED
4
0
RW
Y
RESERVED
RESERVED
3
0
RW
Y
RESERVED
RESERVED
2
0
RW
Y
RESERVED
RESERVED
1
0
RW
N
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
7
0
RW
N
RESERVED
RESERVED
6
0
RW
N
RESERVED
RESERVED
5
1
RW
Y
RESERVED
RESERVED
4
0
RW
Y
RESERVED
RESERVED
3
0
RW
Y
RESERVED
RESERVED
2
1
RW
Y
RESERVED
RESERVED
1
0
RW
Y
RESERVED
RESERVED
0
0
RW
Y
RESERVED
RESERVED
9A
9B
9C
MODE
EEPROM
FIELD NAME
DESCRIPTION
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Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
9D
7
1
RW
N
RESERVED
RESERVED
6
0
RW
N
RESERVED
RESERVED
5
1
RW
N
RESERVED
RESERVED
4
0
RW
N
RESERVED
RESERVED
3
0
RW
Y
RESERVED
RESERVED
2
1
RW
Y
RESERVED
RESERVED
1
0
RW
Y
RESERVED
RESERVED
0
1
RW
N
RESERVED
RESERVED
7
0
RW
Y
CP_EN_IDAC_PD[2]
6
1
RW
Y
CP_EN_IDAC_PD[1]
5
0
RW
Y
CP_EN_IDAC_PD[0]
Phase detector charge pump setting,
when override is enabled. See reg_0C
for other bits.
4
0
RW
Y
CP_EN_IDAC_FD[2]
3
1
RW
Y
CP_EN_IDAC_FD[1]
2
0
RW
Y
CP_EN_IDAC_FD[0]
1
0
RW
N
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
9F
7:0
0
R
N
NOT USED
A0
7:0
0
R
N
NOT USED
A1
7:0
0
R
N
NOT USED
A2
7:0
0
R
N
NOT USED
A3
7:0
0
R
N
NOT USED
A4
7:0
0
R
N
NOT USED
A5
7
0
RW
Y
PFD_SEL_DATA_PSTLCK[2]
6
0
RW
Y
PFD_SEL_DATA_PSTLCK[1]
5
1
RW
Y
PFD_SEL_DATA_PSTLCK[0]
4
0
RW
N
RESERVED
RESERVED
3
0
RW
N
RESERVED
RESERVED
2
0
RW
N
RESERVED
RESERVED
1
0
RW
N
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
9E
90
MODE
EEPROM
FIELD NAME
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DESCRIPTION
Frequency detector charge pump
setting, when override is enabled. See
reg_0C for other bits.
Output mode for when the CDR is in
lock. For these values to take effect,
Reg_0x09[5] must be set to 0, which
is the default.
000: Raw Data
001: Retimed data (default)
100: PRBS Generator or Fixed Pattern
Generator Data
101: 10M clock
111: Mute
All other values are reserved. (Refer
to the Programming Guide for more
details)
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Table 8-11. Channel Registers, 3A to A9 (continued)
ADDRESS
(Hex)
BITS
DEFAULT
VALUE
(Hex)
A6
7
0
RW
N
INCR_HIST_TMR
Provides an option to increase EOM
timer given by 0x2A[7:4] for histogram
collection by +8 for selection values <
8
6
1
RW
Y
EOM_TMR_ABRT_ON_HIT
Enables faster scan through the eyematrix by moving on to the next matrix
point as soon as hit is observed
Note: This bit does not affect when
slope measurement are in progress
5
0
RW
Y
SLP_MIN_REQ_HITS[1]
4
0
RW
Y
SLP_MIN_REQ_HITS[0]
Minimum required hit count for
registering a hit during slope
measurements.
3
0
RW
Y
LFT_SLP
0: allows slope measurement for the
right side of the eye
1: allows slope measurement for the
left side of the eye
2
0
RW
Y
TOP_SLP
0: allows slope measurement for the
bottom side of the eye
1: allows slope measurement for the
top side of the eye
1
1
RW
Y
DFE_BATHTUB_FOM
Enables slope-based bathtub FoM for
DFE adaptation
0
1
RW
Y
CTLE_BATHTUB_FOM
Enables slope-based bathtub FoM for
CTLE adaptation
A7
7:0
0
R
N
RESERVED
RESERVED
A8
7:0
0
RW
N
RESERVED
RESERVED
A9
7:0
0
RW
Y
RESERVED
RESERVED
AC
(DS250DF23
0 Only)
7
0
RW
N
MR_DIS_PRELCK_HV
Disable heo veo acquisiton before lock
6
1
RW
N
MR_LPF_SAR_ADJST_EN
Enables the use of temperature
dependent LPF for Fastcap search
5
0
RW
N
RESERVED
RESERVED
4
1
RW
N
RESERVED
RESERVED
3
0
RW
N
MR_CPRI_CLK_DIV_SEL_OV
clk divider enable for select,
rclk_sel_div_lv
2
1
RW
N
MR_VCO_TLR_EN
Enable the Cap extension of the VCO
for TLR
1
0
RW
N
RESERVED
RESERVED
0
0
RW
N
RESERVED
RESERVED
MODE
EEPROM
FIELD NAME
DESCRIPTION
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The DS250DF230 is a high-speed retimer which extends the reach of differential channels and cleans jitter and
other signal impairments in the process. It can be deployed in a variety of different systems from backplanes
to front ports to active cable assemblies. The following sections outline a few typical applications and their
associated design considerations.
9.2 Typical Applications
The DS250DF230 is typically used in the following application scenarios:
1. Front-Port Jitter Cleaning Applications
2. Active Cable Applications
3. Backplane and Mid-Plane Applications
Line Card
Switch Fabric
25G-VSR
25G-LR
DS250DF230
x4
25G-LR
Optical
SFP28/QSFP28
Connector
FPGA
x4
DS250DF230
ASIC
DS250DF230
DS250DF230
ASIC
x4
x4
25G-LR
FPGA
Active Copper
DS250DF230
x4 25G
DS250DF230
QSFP28
Figure 9-1. Typical Uses for the DS250DF230 in a System
92
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9.2.1 Front-Port Jitter Cleaning Applications
The DS250DF230 has strong equalization capabilities that allow it to equalize insertion loss, reduce jitter, and
extend the reach of front-port interfaces. Two pieces DS250DF230 can be used to support all four egress
channels for a 100GbE port. Another two pieces DS250DF230 can be used to support all four ingress channels
for the same 100GbE ports. Alternatively, a single DS250DF230 can be used to support all egress channels for
two 25GbE ports, and another DS250DF230 can be used to support all two ingress channels for the same four
25GbE ports.
A flow-through pinout for the high-speed signals on DS250DF230 makes placement and routing easy for
unidirectional application. By using the 2x2 cross point inside the device, DS250DF230 can also be configured
for Figure 9-2, where one single device supports both egress and ingress channels.
RD
DS250DF230
SFP28
RX0
TX0
RX1
TX1
TD
ASIC
FPGA
Figure 9-2. Bidirectional Application
For applications which require IEEE802.3 100GBASE-CR4 or 25GBASE-CR auto-negotiation and link training, a
linear repeater device such as the DS280BR820 (or similar) is recommended.
Figure 9-3 shows this configuration, and Figure 9-4 shows an example simplified schematic for a typical frontport application.
Network Interface Card (NIC) or Host Bus Adapter (HBA)
25G/28G-LR
x4
25G/28G-VSR
DS250DF230
x2
DS250DF230
x2
x4
Optical or
fixed-rate Copper
1 x 100GbE QSFP28
PCIe
ASIC
FPGA
25G/28G-LR
25G/28G-VSR
DS250DF230
2
x2
Optical or Copper
x2
DS250DF230
Optical or Copper
2 x 25GbE SFP28
Or
1 x 50GbE SFP28
Figure 9-3. Front-Port Application Block Diagram
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RX0P
RX0N
RX
CDR
RX1P
RX1N
RX
CDR
TX
TX0P
TX0N
TX
TX1P
TX1N
No AC coupling
capacitors needed
X
2.5 V or
3.3 V
VDD
SMBus
Slave mode
1 NŸ
EN_SMB
TEST0 /RCK0
INT_N
To other
open-drain
interrupt pins
SDA
SDC
To system
SMBus(1)
THR/TEST1
Address straps
(pull-up, pulldown, or float)
ADDR0
ADDR1
30.72 MHz or 25 MHz
CAL_CLK_OUT
CAL_CLK_IN
SMBus Slave
mode
READ_EN_N
ALL_DONE_N
2.5 V
Minimum 0.01 F
(2x)
recommended
decoupling
0.1 F
(2x)
VDD
7R QH[W GHYLFH¶V
CAL_CLK_IN
Output can float
in slave mode
GND
Host
ASIC /
FPGA
QSFP28
or
SFP28
TX0P
TX0N
TX
CDR
RX
RX0P
RX0N
No AC coupling
capacitors needed
X
TX1P
TX1N
TX
CDR
RX
RX1P
RX1N
VDD
SMBus
1 NŸ
Slave mode
EN_SMB
TEST0 /RCK0
THR/TEST1
INT_N
SDA
SDC
Address straps
(pull-up, pulldown, or float)
ADDR0
ADDR1
SMBus Slave
mode
CAL_CLK_IN
CAL_CLK_OUT
READ_EN_N
ALL_DONE_N
2.5 V
Minimum 0.01 F
(2x)
recommended
decoupling
0.1 F
(2x)
VDD
Output can float
in slave mode
GND
(1) SMBus signals need to be pulled up elsewhere in the system.
Figure 9-4. Front-Port Application Schematic
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9.2.1.1 Design Requirements
For this design example, the following guidelines outlined in Table 9-1 apply.
Table 9-1. Front-Port Application Design Guidelines
DESIGN PARAMETER
REQUIREMENT
AC-coupling capacitors
Egress (ASIC-to-module) direction: AC-coupling capacitors in the
range of 100 to 220 nF are required for the RX inputs and are NOT
required for the TX outputs.
Ingress (module-to-ASIC) direction: AC-coupling capacitors in the
range of 100 to 220 nF are required for the TX outputs and are NOT
required for the RX inputs.
Input channel insertion loss
≤ 35 dB at 25.78125-Gbps Nyquist frequency (12.9 GHz)
Output channel insertion loss
Egress (ASIC-to-module) direction: Follow CAUI-4 / CEI-25G-VSR
host channel requirements (approximately 7 dB at 12.9 GHz).
Ingress (module-to-ASIC) direction: Depends on downstream ASIC /
FPGA capabilities. The DS250DF230 has a low-jitter output driver
with 3-tap FIR filter for equalizing a portion of the output channel.
Host ASIC TX launch amplitude
800 mVppd to 1200 mVppd.
Host ASIC TX FIR filter
Depends on channel loss. Refer to the Setting the Output VOD, PreCursor, and Post-Cursor Equalization section.
9.2.1.2 Detailed Design Procedure
The design procedure for front-port applications is as follows:
1. Determine the total number of channels on the board which require a DS250DF230 for signal conditioning.
This will dictate the total number of DS250DF230 devices required for the board. It is generally
recommended that channels connected to the same front-port cage be grouped together in the same
DS250DF230 device. This will simplify the device settings, as similar loss channels generally use similar
settings.
2. Determine the maximum current draw required for all DS250DF230 retimers. This may impact the selection
of the regulator for the 2.5-V supply rail. To calculate the maximum current draw, multiply the maximum
transient power supply current by the total number of DS250DF230 devices.
3. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two
ways to approach this calculation:
a. Maximum mission-mode operational power consumption is when all channels are locked and retransmitting the data which is received. PRBS pattern checkers/generators are not used in this mode
because normal traffic cannot be checked with a PRBS checker. For this calculation, multiply the
worst-case power consumption in mission mode by the total number of DS250DF230 devices.
b. Maximum debug-mode operational power consumption is when all channels are locked and retransmitting the data which is received. At the same time, some channels’ PRBS checkers or generators
may be enabled. For this calculation, multiply the worst-case power consumption in debug mode by the
total number of DS250DF230 devices.
4. Determine the SMBus address scheme needed to uniquely address each DS250DF230 device on the board,
depending on the total number of devices identified in step 2. Each DS250DF230 can be strapped with one
of 16 unique SMBus addresses. If there are more DS250DF230 devices on the board than the number of
unique SMBus addresses which can be assigned, then use an I2C expander like the TCA/PCA family of
I2C/SMBus switches and multiplexers to split up the SMBus into multiple busses.
5. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus
(SMBus Slave Mode).
a. If SMBus Master Mode will be used, provisions must be made for an EEPROM on the board with 8-bit
SMBus address 0xA0. Refer to SMBus Master Mode for more details on SMBus Master Mode including
EEPROM size requirements.
b. If SMBus Slave Mode will be used for all device configurations, an EEPROM is not needed.
6. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD
supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details.
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7. Make provisions in the schematic and layout for a 30.72 MHz (±100 ppm) or 25 MHz (±100 ppm) singleended CMOS clock. Each DS250DF230 retimer buffers the clock on the CAL_CLK_IN pin and presents
the buffered clock on the CAL_CLK_OUT pin. This allows multiple (up to 20) retimers’ calibration clocks
to be daisy chained to avoid the need for multiple oscillators on the board. If the oscillator used on the
board has a 2.5-V CMOS output, then no AC-coupling capacitor or resistor ladder is required at the input
to CAL_CLK_IN. No AC coupling or resistor ladder is needed between one retimer’s CAL_CLK_OUT output
and the next retimer’s CAL_CLK_IN input. The final retimer’s CAL_CLK_OUT output can be left floating.
8. Connect the INT_N open-drain output to an FPGA or CPU if interrupt monitoring is desired. Note that
multiple retimers’ INT_N outputs can be connected together because this is an open-drain output. The
common INT_N net must be pulled high.
9. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in
Recommended Operating Conditions, take care to ensure the operating junction temperature is met as well
as the CDR stay-in-lock junction temperature range defined in Electrical Characteristics. For example, if
initial CDR lock acquisition occurs at an junction temperature of 110°C, then maintaining CDR lock would
require the ambient temperature surrounding the DS250DF230 to be kept above (110°C – TEMPLOCK–).
9.2.1.3 Application Curves
Figure 9-5 shows a typical output eye diagram for the DS250DF230 operating at 25.78125 Gbps with PRBS9
pattern using FIR main-cursor of +28, pre-cursor of 0 and post-cursor of +3. All other device settings are left at
default.
Figure 9-6 shows an example of DS250DF230 FIR transmit equalization while operating at 25.78125 Gbps. In
this example, the Tx FIR filter main-cursor is set to +25, post-cursor to –3 and pre-cursor to –3. An 8T pattern is
used to evaluate the FIR filter, which consists of 0xFF00. All other device settings are left at default.
Figure 9-5. DS250DF230 Operating at 25.78125
Gbps
96
Figure 9-6. DS250DF230 FIR Transmit Equalization
While Operating at 25.78125 Gbps
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9.2.2 Active Cable Applications
The DS250DF230 has strong equalization capabilities that allow it to recover data over long and/or thin-gauge
copper cables. Two pcs DS250DF230s can be used on a QSFP28 paddle card to create a half-active cable
assembly which is longer and/or thinner than passive cables. Alternatively, four pcs DS250DF230 devices can
be used on a QSFP28 paddle card to create a full-active cable assembly and achieve even longer reach and/or
thinner cables.
Figure 9-7 shows these configurations, Figure 9-8 shows an example simplified schematic for a half-active cable
application, and Figure 9-9 shows an example simplified schematic for a full-active cable application.
Line Card
Full-Active Cable
x4 25G VSR
QSFP
DS250DF230
x2
DS250DF230
x2
DS250DF230
x2
DS250DF230
x2
ASIC
FPGA
Half-Active Cable
x4 25G VSR
QSFP
DS250DF230
x2
DS250DF230
x2
Figure 9-7. Active Cable Application Block Diagram
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No Retimer and no AC coupling capacitors needed
RX Retimer
TX0P
TX0N
TX
CDR
RX
RX0P
RX0N
RX
RX1P
RX1N
X
TX1P
TX1N
Paddle
card host
side
TX
CDR
VDD
SMBus
Slave mode
2.5 V or 3.3 V
To other opendrain interrupt
pins
1 NŸ
EN_SMB
INT_N
TEST0 /RCK0
Paddle
card cable
side
To system
SMBus
SDA
SDC
THR /TEST1
Address straps
(pull-up, pulldown, or float)
ADDR0
ADDR1
SMBus Slave
mode
2.5 V
Minimum 0.01 F
(2x)
recommended
decoupling
0.1 F
(2x)
CAL_CLK_IN
CAL_CLK_OUT
READ_EN_N
ALL_DONE_N
VDD
Output can float
in slave mode
GND
(1) SMBus signals need to be pulled up elsewhere in the system.
Figure 9-8. Half-Active Cable Application Schematic
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TX Retimer
RX0P
RX0N
RX
CDR
TX
TX0P
TX0N
TX
TX1P
TX1N
X
RX1P
RX1N
RX
CDR
2.5 V or
3.3 V
VDD
SMBus
1 NŸ
Slave mode
EN_SMB
TEST0 /RCK0
INT_N
To other
open-drain
interrupt pins
SDA
SDC
To system
SMBus(1)
THR /TEST1
Address straps
(pull-up, pulldown, or float)
ADDR0
ADDR1
30.72 MHz or 25 MHz
CAL_CLK_OUT
CAL_CLK_IN
SMBus Slave
mode
2.5 V
0.01 F
Minimum
(2x)
recommended
decoupling
0.1 F
(2x)
READ_EN_N
7R QH[W GHYLFH¶V
CAL_CLK_IN
ALL_DONE_N
VDD
Output can float
in slave mode
GND
Paddle
card host
side
Paddle
card cable
side
RX Retimer
TX0P
TX0N
TX
CDR
TX1P
TX1N
TX
CDR
RX
RX0P
RX0N
RX
RX1P
RX1N
X
VDD
SMBus
1 NŸ
Slave mode
EN_SMB
TEST0 /RCK0
INT_N
SDA
SDC
THR /TEST1
Address straps
(pull-up, pulldown, or float)
ADDR0
ADDR1
SMBus Slave
mode
2.5 V
0.01 F
Minimum
(2x)
recommended
decoupling
0.1 F
(2x)
CAL_CLK_IN
CAL_CLK_OUT
READ_EN_N
ALL_DONE_N
VDD
Output can float
in slave mode
GND
(1) SMBus signals need to be pulled up elsewhere in the system.
Figure 9-9. Full-Active Cable Application Schematic
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9.2.2.1 Design Requirements
For this design example, the following guidelines outlined in Table 9-2 and Table 9-3 apply.
Table 9-2. Half-Active Cable Application Design Guidelines
DESIGN PARAMETER
REQUIREMENT
Device placement
Place the DS250DF230s on the receive side of the paddle card such
that it is receiving data from the cable, and transmitting towards the
host.
AC-coupling capacitors
100-nF, AC-coupling capacitors are required for the RX inputs and
the TX outputs.
Cable insertion loss
The raw cable insertion loss including the insertion loss of the
paddle card must be ≤ 27 dB at 25.78125-Gbps Nyquist frequency
(12.9 GHz). This is to ensure that the total loss at the input to the
DS250DF230 is ≤ 35 dB at 12.9 GHz. Assuming a worst-case hostside PCB loss of 7 dB, plus a connector loss of 1 dB, the remaining
loss allocated for the raw cable and paddle cards is 27 dB.
Table 9-3. Full-Active Cable Application Design Guidelines
DESIGN PARAMETER
REQUIREMENT
Device placement
A full-active QSFP cable will uses 4 pieces of DS250DF230 per
paddle card. Typically, two devices will be placed on each side of the
paddle card.
AC-coupling capacitors
Transmit-side Retimer: 100-nF, AC coupling capacitors are required
for the RX inputs and are not required for the TX outputs. This link
segment will be AC coupled on the paddle card at the opposite end
of the cable.
Receive-side Retimer: 100-nF, AC-coupling capacitors are required
for the RX inputs and the TX outputs.
Cable insertion loss
The raw cable insertion loss including the insertion loss of the paddle
card must be ≤ 35 dB at 25.78125-Gbps Nyquist frequency (12.9
GHz).
9.2.2.2 Detailed Design Procedure
The design procedure for active cable applications is as follows:
1. Determine the maximum current draw required for one or more of the DS250DF230 retimers on the paddle
card. This may impact the selection of the regulator for the 2.5-V supply rail. To calculate the maximum
current draw, multiply the maximum transient power supply current by the total number of DS250DF230
devices.
2. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two
ways to approach this calculation:
a. Maximum mission-mode operational power consumption is when all channels are locked and retransmitting the data which is received. PRBS pattern checkers/generators are not used in this mode
because normal traffic cannot be checked with a PRBS checker. For this calculation, multiply the
worst-case power consumption in mission mode by the total number of DS250DF230 devices.
b. Maximum debug-mode operational power consumption is when all channels are locked and retransmitting the data which is received. At the same time, some channels’ PRBS checkers or generators
may be enabled. For this calculation, multiply the worst-case power consumption in debug mode by the
total number of DS250DF230 devices.
3. Determine the SMBus address for one or more of the DS250DF230 retimers. The ADDR[1:0] pins can be left
floating for an 8-bit SMBus slave address of 0x44. For the second DS250DF230, a single pullup or pulldown
resistor can be used on one address pin. For example, with ADDR0 = Float and ADDR1 = 1 kΩ to GND，
the 8-bit SMBus slave address will be 0x34.
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4. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus
(SMBus Slave Mode).
a. If SMBus Master Mode will be used, provisions must be made for an EEPROM on the board with 8-bit
SMBus address 0xA0. Refer to SMBus Master Mode for more details on SMBus Master Mode including
EEPROM size requirements.
b. If SMBus Slave Mode will be used for all device configurations, for example when one or more of the
retimers is configured with a microcontroller, an EEPROM is not needed.
5. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD
supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details.
6. Make provisions in the schematic and layout for a 30.72-MHz (±100 ppm) or 25-MHz (±100 ppm) singleended CMOS clock. The DS250DF230 retimer buffers the clock on the CAL_CLK_IN pin and presents the
buffered clock on the CAL_CLK_OUT pin. When using two Retimers on a paddle card, only one 30.72-MHz
or 25-MHz clock is required. The CAL_CLK_OUT pin of one retimer can be connected to the CAL_CLK_IN
pin of the other retimer.
7. Connect the INT_N open-drain output to the paddle card MCU if interrupt monitoring is desired, otherwise
leave it floating. Note that multiple retimers’ INT_N outputs can be connected together because this is an
open-drain output. The common INT_N net should be pulled high.
8. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in
Recommended Operating Conditions, take care to ensure the operating junction temperature is met as well
as the CDR stay-in-lock junction temperature range defined in Electrical Characteristics. For example, if
initial CDR lock acquisition occurs at an junction temperature of 110°C, then maintaining CDR lock would
require the junction temperature on DS250DF230 to be kept above (110°C – TEMPLOCK–).
9.2.2.3 Application Curves
See Application Curves in section Front-Port Jitter Cleaning Applications.
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9.2.3 Backplane and Mid-Plane Applications
The DS250DF230 has strong equalization capabilities that allow it to recover data over channels up to 35-dB
insertion loss. As a result, the optimum placement for the DS250DF230 in a backplane/mid-plane application
is with the higher-loss channel segment at the input and the lower-loss channel segment at the output. This
reduces the equalization burden on the downstream ASIC/FPGA, as the DS250DF230 is equalizing a majority of
the overall channel. This type of asymmetric placement is not a requirement, but when an asymmetric placement
is required due to the presence of a passive backplane or mid-plane, then this becomes the recommended
placement.
Passive Backplane/
Midplane
Switch Fabric Card
Connector
Connector
FPGA
x2 25G
x2 25G
ASIC
DS250DF230
DS250DF230
ASIC
Line Card
FPGA
Figure 9-10. Backplane/Mid-Plane Application Block Diagram
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RX0P
RX0N
RX
CDR
RX1P
RX1N
RX
CDR
TX
TX0P
TX0N
TX
TX1P
TX1N
X
2.5 V or
3.3 V
VDD
SMBus
Slave mode
1 NŸ
EN_SMB
TEST0 /RCK0
INT_N
To other
open-drain
interrupt pins
SDA
SDC
To system
SMBus(1)
THR /TEST1
Address straps
(pull-up, pulldown, or float)
ADDR0
ADDR1
30.72 MHz or 25 MHz
CAL_CLK_OUT
CAL_CLK_IN
SMBus Slave
mode
READ_EN_N
ALL_DONE_N
2.5 V
Minimum 0.01 F
(2x)
recommended
decoupling
0.1 F
(2x)
Backplane
/ Midplane
Connector
VDD
7R QH[W GHYLFH¶V
CAL_CLK_IN
Output can float
in slave mode
GND
ASIC /
FPGA
TX0P
TX0N
TX
CDR
RX
RX0P
RX0N
RX
RX1P
RX1N
X
TX1P
TX1N
TX
CDR
VDD
SMBus
1 NŸ
Slave mode
EN_SMB
TEST0 /RCK0
INT_N
SDA
SDC
THR /TEST1
Address straps
(pull-up, pulldown, or float)
ADDR0
ADDR1
SMBus Slave
mode
2.5 V
Minimum 0.01 F
(2x)
recommended
decoupling
0.1 F
(2x)
CAL_CLK_IN
CAL_CLK_OUT
READ_EN_N
ALL_DONE_N
VDD
Output can float
in slave mode
GND
(1) SMBus signals need to be pulled up elsewhere in the system.
Figure 9-11. Backplane/Mid-Plane Application Schematic
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9.2.3.1 Design Requirements
For this design example, the following guidelines outlined in Table 9-4 apply.
Table 9-4. Backplane/Mid-Plane Application Design Guidelines
DESIGN PARAMETER
REQUIREMENT
AC coupling capacitors
AC-coupling capacitors in the range of 100 to 220 nF are required for
the RX inputs and TX outputs.
Input channel insertion loss
≤ 35 dB at 25.78125-Gbps Nyquist frequency (12.9 GHz)
Output channel insertion loss
Depends on downstream ASIC / FPGA capabilities. The
DS250DF230 has a low-jitter output driver with 3-tap FIR filter for
equalizing a portion of the output channel.
Link partner TX launch amplitude
800 mVppd to 1200 mVppd
Link partner TX FIR filter
Depends on channel loss. Refer to the Setting the Output VOD, PreCursor, and Post-Cursor Equalization section.
9.2.3.2 Detailed Design Procedure
The design procedure for backplane/mid-plane applications is as follows:
1. Determine the total number of channels on the board which require a DS250DF230 for signal conditioning.
This will dictate the total number of DS250DF230 devices required for the board. It is generally
recommended that channels with similar total insertion loss on the board be grouped together in the same
DS250DF230 device. This will simplify the device settings, as similar loss channels generally use similar
settings.
2. Determine the maximum current draw required for all DS250DF230 retimers. This may impact the selection
of the regulator for the 2.5-V supply rail. To calculate the maximum current draw, multiply the maximum
transient power supply current by the total number of DS250DF230 devices.
3. Determine the maximum operational power consumption for the purpose of thermal analysis. There are two
ways to approach this calculation:
a. Maximum mission-mode operational power consumption is when all channels are locked and retransmitting the data which is received. PRBS pattern checkers/generators are not used in this mode
because normal traffic cannot be checked with a PRBS checker. For this calculation, multiply the
worst-case power consumption in mission mode by the total number of DS250DF230 devices.
b. Maximum debug-mode operational power consumption is when all channels are locked and retransmitting the data which is received. At the same time, some channels’ PRBS checkers or generators
may be enabled. For this calculation, multiply the worst-case power consumption in debug mode by the
total number of DS250DF230 devices.
4. Determine the SMBus address scheme needed to uniquely address each DS250DF230 device on the board,
depending on the total number of devices identified in step 2. Each DS250DF230 can be strapped with one
of 16 unique SMBus addresses. If there are more DS250DF230 devices on the board than the number of
unique SMBus addresses which can be assigned, then use an I2C expander like the TCA/PCA family of
I2C/SMBus switches and multiplexers to split up the SMBus into multiple busses.
5. Determine if the device will be configured from EEPROM (SMBus Master Mode) or from the system I2C bus
(SMBus Slave Mode).
a. If SMBus Master Mode will be used, provisions must be made for an EEPROM on the board with 8-bit
SMBus address 0xA0. Refer to SMBus Master Mode for more details on SMBus Master Mode including
EEPROM size requirements.
b. If SMBus Slave Mode will be used for all device configurations, an EEPROM is not needed.
6. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD
supply and GND. Refer to the pin function description in Pin Configuration and Functions for more details.
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7. Make provisions in the schematic and layout for a 30.72-MHz (±100 ppm) or 25-MHz (±100 ppm) singleended CMOS clock. Each DS250DF230 retimer buffers the clock on the CAL_CLK_IN pin and presents
the buffered clock on the CAL_CLK_OUT pin. This allows multiple (up to 20) retimers’ calibration clocks
to be daisy chained to avoid the need for multiple oscillators on the board. If the oscillator used on the
board has a 2.5-V CMOS output, then no AC-coupling capacitor or resistor ladder is required at the input
to CAL_CLK_IN. No AC coupling or resistor ladder is needed between one retimer’s CAL_CLK_OUT output
and the next retimer’s CAL_CLK_IN input. The final retimer’s CAL_CLK_OUT output can be left floating.
8. Connect the INT_N open-drain output to an FPGA or CPU if interrupt monitoring is desired. Note that
multiple retimers’ INT_N outputs can be connected together because this is an open-drain output. The
common INT_N net must be pulled high.
9. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in
Recommended Operating Conditions, take care to ensure the operating junction temperature is met as well
as the CDR stay-in-lock junction temperature range defined in Electrical Characteristics. For example, if
initial CDR lock acquisition occurs at an junction temperature of 110 °C, then maintaining CDR lock would
require the junction temperature on DS250DF230 to be kept above (110°C - TEMPLOCK-).
9.2.3.3 Application Curves
See Application Curves in section Front-Port Jitter Cleaning Applications.
10 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply must be designed to provide the recommended operating conditions outlined in
Specifications in terms of DC voltage, AC noise, and start-up ramp time.
2. The maximum current draw for the DS250DF230 is provided in Specifications. This figure can be used to
calculate the maximum current the power supply must provide. Typical mission-mode current draw can be
inferred from the typical power consumption in Specifications.
3. The DS250DF230 does not require any special power supply filtering (that is, ferrite bead), provided the
recommended operating conditions are met. Only standard supply decoupling is required. Refer to the Pin
Configuration and Functions section for details concerning the recommended supply decoupling.
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11 Layout
11.1 Layout Guidelines
Follow these guidelines when designing the layout:
1. Decoupling capacitors must be placed as close to the VDD pins as possible. Placing them directly
underneath the device is one option if the board design permits.
2. High-speed differential signals TXnP/TXnN and RXnP/RXnN must be tightly coupled, skew matched, and
impedance controlled.
3. Vias must be avoided when possible on the high-speed differential signals. When vias must be used, take
care to minimize the via stub, either by transitioning through most or all layers, or by back drilling.
4. GND relief can be used beneath the high-speed differential signal pads to improve signal integrity by
counteracting the pad capacitance.
5. GND relief can be used beneath the AC-coupling capacitor pads to improve signal integrity by counteracting
the pad capacitance.
6. GND vias must be placed directly beneath the device connecting the GND plane attached to the device
to the GND planes on other layers. This has the added benefit of improving thermal conductivity from the
device to the board.
7. If vias are used for the high-speed signals, the ground via must be implemented adjacent to the signal via
to provide return path and isolation. For differential pair, the typical via configuration is ground-signal-signalground.
11.2 Layout Examples
The example layouts in Figure 11-1 through Figure 11-5 demonstrate how all signals can be escaped from the
BGA array using microstrip routing on a generic multi-layer stackup.
Figure 11-2. Layer 1 GND
Figure 11-1. Top Layer
Figure 11-3. Internal Low-Speed Signal Layers
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Figure 11-5. Bottom Layer
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For additional information, see TI’s Surface Mount Technology (SMT) References at:
http://focus.ti.com/quality/docs under the Quality & Lead (Pb)-Free Data menu.
For device and channel model simulation, refer to the DS250DF230 IBIS-AMI Model:
•
Texas Instruments, DS250DF230 IBIS-AMI Model IBIS Model
Click here to request access to the DS250DF230 IBIS-AMI Model (SNLM215) in the DS250DF230 MySecure
folder.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
•
Texas Instruments DS2x0DF810, DS250DFx10, DS250DF230 Programmer's Guide
Click here to request access to the DS250DF230 Programming Guide in the DS250DF230 MySecure folder.
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
14 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DS250DF230RTVR
ACTIVE
WQFN
RTV
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DS250
DF2
DS250DF230RTVT
ACTIVE
WQFN
RTV
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DS250
DF2
DS250DF230ZLSR
ACTIVE
NFBGA
ZLS
36
3000
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
D250DF230
DS250DF230ZLST
ACTIVE
NFBGA
ZLS
36
250
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
D250DF230
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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