DS90LV027AQMA/NOPB

Product Folder Sample & Buy Technical Documents Support & Community Tools & Software DS90LV027A SNLS026D – MARCH 2000 – REVISED JUNE 2016 DS90LV027A LVDS Dual High Speed Differential Driver 1 Features 3 Description • • • • • • • • • • • • • The DS90LV027A is a dual LVDS driver device optimized for high data rate and low-power applications. The device is designed to support data rates in excess of 600 Mbps (300 MHz) using Low Voltage Differential Signaling (LVDS) technology. The DS90LV027A is a current mode driver allowing power dissipation to remain low even at high frequency. In addition, the short circuit fault current is also minimized. 1 >600-Mbps (300 MHz) Switching Rates 0.3-ns Typical Differential Skew 0.7-ns Maximum Differential Skew 1.5-ns Maximum Propagation Delay 3.3-V Power Supply Design ±360-mV Differential Signaling Low Power Dissipation (46 mW at 3.3-V Static) Flow-Through Design Simplifies PCB Layout Interoperable With Existing 5-V LVDS Devices Power-Off Protection (Outputs in High Impedance) Conforms to TIA/EIA-644 Standard 8-Pin SOIC Package Saves Space Industrial Temperature Operating Range: −40°C to 85°C The device is in a 8-pin SOIC package. The DS90LV027A has a flow-through design for easy printed-circuit board (PCB) layout. The differential driver outputs provides low EMI with its typical low output swing of 360 mV. It is perfect for high-speed transfer of clock and data. The DS90LV027A can be paired with its companion dual line receiver, the DS90LV028A, or with any of TI's LVDS receivers, to provide a high-speed point-to-point LVDS interface. 2 Applications • • • • Device Information(1) Multi-Function Printers LVCMOS-to-LVDS Translation Building and Factory Automation Grid Infrastructure PART NUMBER DS90LV027A PACKAGE SOIC (8) BODY SIZE (NOM) 4.90 mm × 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. space Functional Diagrams DO+ 1 DI 1 D DO- 1 Copyright © 2016, Texas Instruments Incorporated DO+ 2 DI 2 D DO- 2 Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS90LV027A SNLS026D – MARCH 2000 – REVISED JUNE 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics .......................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 9 Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagrams ..................................... 10 8.3 Feature Description................................................. 11 8.4 Device Functional Modes........................................ 11 9 Application and Implementation ........................ 12 9.1 Application Information............................................ 12 9.2 Typical Application .................................................. 12 10 Power Supply Recommendations ..................... 13 11 Layout................................................................... 14 11.1 Layout Guidelines ................................................. 14 11.2 Layout Example .................................................... 14 12 Device and Documentation Support ................. 15 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 15 15 15 15 15 15 13 Mechanical, Packaging, and Orderable Information ........................................................... 15 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (April 2013) to Revision D • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Changes from Revision B (April 2013) to Revision C • 2 Page Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: DS90LV027A DS90LV027A www.ti.com SNLS026D – MARCH 2000 – REVISED JUNE 2016 5 Pin Configuration and Functions D Package 8-Pin SOIC Top View VCC 1 8 D0- 1 DI 1 2 7 D0+ 1 DI 2 3 6 D0+ 2 GND 4 5 D0- 2 Pin Functions PIN I/O DESCRIPTION NAME NO. DI 2, 3 I TTL/CMOS driver input pins DO+ 6, 7 O Noninverting LVDS driver output pin DO– 5, 8 O Inverting LVDS driver output pin GND 4 — Ground pin VCC 1 — Positive power supply pin, 3.3 V ± 0.3 V Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: DS90LV027A 3 DS90LV027A SNLS026D – MARCH 2000 – REVISED JUNE 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage, VCC –0.3 4 V Input voltage, DI –0.3 3.6 V Output voltage, DO± –0.3 3.9 V 1190 mW 9.5 mW/°C above 25°C °C 260 °C 150 °C D package Maximum package power dissipation at 25°C Derate D package Lead temperature range, soldering (4 s) Storage temperature, Tstg (1) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±8000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 EIAJ, 0 Ω, 200 pF ±1000 IEC direct, 330 Ω, 150 pF ±4000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC Supply voltage TA Operating free-air temperature MIN NOM MAX UNIT 3 3.3 3.6 V –40 25 85 °C 6.4 Thermal Information DS90LV027A THERMAL METRIC (1) D (SOIC) UNIT 8 PINS Low-K thermal resistance (2) 212 High-K thermal resistance (2) 112 RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 69.1 °C/W RθJB Junction-to-board thermal resistance 47.7 °C/W ψJT Junction-to-top characterization parameter 15.2 °C/W ψJB Junction-to-board characterization parameter 47.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W (1) (2) 4 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages. Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: DS90LV027A DS90LV027A www.ti.com SNLS026D – MARCH 2000 – REVISED JUNE 2016 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) (1) (2) PARAMETER TEST CONDITIONS MIN TYP (3) MAX UNIT 250 VOD Output differential voltage RL = 100 Ω (see Figure 15), DO+, DO− pins 360 450 mV ΔVOD VOD magnitude change RL = 100 Ω (see Figure 15), DO+, DO− pins 1 35 mV VOH Output high voltage RL = 100 Ω (see Figure 15), DO+, DO− pins 1.4 1.6 V VOL Output low voltage RL = 100 Ω (see Figure 15), DO+, DO− pins 0.9 1.1 VOS Offset voltage RL = 100 Ω (see Figure 15), DO+, DO− pins 1.125 1.2 1.375 ΔVOS Offset magnitude change RL = 100 Ω (see Figure 15), DO+, DO− pins 0 3 25 mV IOXD Power-off leakage VOUT = VCC or GND, VCC = 0 V, DO+, DO− pins ±1 ±10 μA IOSD Output short-circuit current DO+, DO− pins –8 mA VIH Input high voltage DI pin 2 VCC V VIL Input low voltage DI pin GND 0.8 V IIH Input high current VIN = 3.3 V or 2.4 V, DI pin ±2 ±10 μA IIL Input low current VIN = GND or 0.5 V, DI pin ±1 ±10 μA VCL Input clamp voltage ICL = −18 mA, DI pin ICC (1) (2) (3) Power supply current –5.7 –1.5 VIN = VCC or GND, VCC pin –0.6 No load RL = 100 Ω V V V 8 14 14 20 mA Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD. The DS90LV027A is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers outputs. All typicals are given for: VCC = 3.3 V and TA = 25°C. 6.6 Switching Characteristics RL = 100 Ω and CL = 15 pF, see Figure 16 and Figure 17 (unless otherwise noted) (1) (2) (3) PARAMETER TEST CONDITIONS MIN TYP (4) MAX UNIT tPHLD Differential propagation delay high to low 0.3 0.8 1.5 ns tPLHD Differential propagation delay low to high 0.3 1.1 1.5 ns tSKD1 Differential pulse skew |tPHLD − tPLHD| (5) 0 0.3 0.7 ns 0 0.4 (6) tSKD2 Channel to channel skew 0.8 ns tSKD3 Differential part to part skew (7) 0 1 ns tSKD4 Differential part to part skew (8) 0 1.2 ns tTLH Transition low to high time 0.2 0.5 1 ns tTHL Transition high to low time 0.2 0.5 1 fMAX Maximum operating frequency (9) (1) (2) (3) (4) (5) (6) (7) (8) (9) 350 ns MHz These parameters are ensured by design. The limits are based on statistical analysis of the device over PVT (process, voltage, temperature) ranges. CL includes probe and fixture capacitance. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns (10%-90%). All typicals are given for: VCC = 3.3 V and TA = 25°C. tSKD1, |tPHLD − tPLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. tSKD2 is the Differential Channel to Channel Skew of any event on the same device. tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. tSKD4, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% / 55%, VOD > 250 mV, all channels switching. Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: DS90LV027A 5 DS90LV027A SNLS026D – MARCH 2000 – REVISED JUNE 2016 www.ti.com 6.7 Typical Characteristics 6 Figure 1. Output High Voltage vs Power Supply Voltage Figure 2. Output Low Voltage vs Power Supply Voltage Figure 3. Output Short-Circuit Current vs Power Supply Voltage Figure 4. Differential Output Voltage vs Power Supply Voltage Figure 5. Differential Output Voltage vs Load Resistor Figure 6. Offset Voltage vs Power Supply Voltage Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: DS90LV027A DS90LV027A www.ti.com SNLS026D – MARCH 2000 – REVISED JUNE 2016 Typical Characteristics (continued) Figure 7. Power Supply Current vs Power Supply Voltage Figure 8. Power Supply Current vs Ambient Temperature Figure 9. Differential Propagation Delay vs Power Supply Voltage Figure 10. Differential Propagation Delay vs Ambient Temperature Figure 11. Differential Skew vs Power Supply Voltage Figure 12. Differential Skew vs Ambient Temperature Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: DS90LV027A 7 DS90LV027A SNLS026D – MARCH 2000 – REVISED JUNE 2016 www.ti.com Typical Characteristics (continued) Figure 13. Transition Time vs Power Supply Voltage 8 Figure 14. Transition Time vs Ambient Temperature Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: DS90LV027A DS90LV027A www.ti.com SNLS026D – MARCH 2000 – REVISED JUNE 2016 7 Parameter Measurement Information DO+ RL / 2 2V DI VOS D VOD 0.8 V SI RL / 2 DOCopyright © 2016, Texas Instruments Incorporated Figure 15. Differential Driver DC Test Circuit DI Generator D DO+ CL RL 50 Ÿ DO- Copyright © 2016, Texas Instruments Incorporated Figure 16. Differential Driver Propagation Delay and Transition Time Test Circuit 3V DI 1.5 V 1.5 V tPHLD tPLH DO- 0V 0 V (Differential) DO+ 0V VOH VOL 80 % VDIFF 80 % 0V 20 % 0V VDIFF = (DO+) ± (DO-) tTHL 20 % tTHL Figure 17. Differential Driver Propagation Delay and Transition Time Waveforms Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: DS90LV027A 9 DS90LV027A SNLS026D – MARCH 2000 – REVISED JUNE 2016 www.ti.com 8 Detailed Description 8.1 Overview LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 19. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media is in the range of 100 Ω. A termination resistor of 100 Ω (selected to match the media), and is placed as close to the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be considered. The DS90LV027A differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The output current is typically 3.1 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode driver requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 19. AC or unterminated configurations are not allowed. The 3.1-mA loop current develops a differential voltage of 310 mV across the 100-Ω termination resistor which the receiver detects with a 250-mV minimum differential noise margin, (driven signal minus receiver threshold (250 mV – 100 mV = 150 mV). The signal is centered around 1.2 V (Driver Offset, VOS) with respect to ground as shown in Figure 18. NOTE The steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 620 mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most case from 20 MHz to 50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires >80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers. 8.2 Functional Block Diagrams DO+ 1 DI 1 D DO- 1 Copyright © 2016, Texas Instruments Incorporated DO+ 2 DI 2 D DO- 2 Copyright © 2016, Texas Instruments Incorporated 10 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: DS90LV027A DS90LV027A www.ti.com SNLS026D – MARCH 2000 – REVISED JUNE 2016 8.3 Feature Description 8.3.1 LVDS Fail-Safe This section addresses the common concerns of fail-safe biasing of LVDS interconnects, specifically looking at the DS90LV027A driver outputs and the DS90LV028A receiver inputs. The LVDS receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, take care to prevent noise from appearing as a valid signal. The internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated, or shorted receiver inputs. 1. Open Input Pins: The DS90LV028A is a dual receiver device, and if an application requires only 1 receiver, the unused channel inputs must be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pullup and pulldown resistors to set the output to a HIGH state. This internal circuitry ensures a HIGH, stable output state for open inputs. 2. Terminated Input: If the DS90LV027A driver is disconnected (cable unplugged), or if the DS90LV027A driver is in a TRI-STATE or power-off condition, the receiver output is in a HIGH state again, even with the end of cable 100-Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10 mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect must be used. Twisted pair cable offers better balance than flat ribbon cable. 3. Shorted Inputs: If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0-V differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4 V). It is only supported with inputs shorted and no external common-mode voltage applied. External lower value pullup and pulldown resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pullup and pulldown resistors must be in the 5-kΩ to 15-kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point must be set to approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry. 3V DIN 0V V0H DOUT- V0S (1.2V typical) V0D SINGLE-ENDED DOUT+ V0L +V0D DOUT+ ± DOUT- VSS 0V 0V (DIFF.) DIFFERENTIAL OUTPUT -V0D Figure 18. Driver Output Levels 8.4 Device Functional Modes Table 1 lists the functional modes of the DS90LV027A. Table 1. Truth Table INPUT OUTPUTS DI DO+ DO– L L H H H L Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: DS90LV027A 11 DS90LV027A SNLS026D – MARCH 2000 – REVISED JUNE 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The DS90LV027A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side. General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: • LVDS Owner's Manual • AN-808 Long Transmission Lines and Data Signal Quality • AN-977 LVDS Signal Quality: Jitter Measurements Using Eye Patterns Test Report • AN-971 An Overview of LVDS Technology • AN-916 A Practical Guide To Cable Selection • AN-805 Calculating Power Dissipation for Differential Line Drivers • AN-903 A Comparison of Differential Termination Techniques 9.2 Typical Application Any LVDS Receiver DATA INPUT RT 100: + - DATA OUTPUT Copyright © 2016, Texas Instruments Incorporated Figure 19. LVDS Application Schematic 9.2.1 Design Requirements When using LVDS devices, it is important to remember to specify controlled impedance PCB traces, cable assemblies, and connectors. All components of the transmission media must have a matched differential impedance of about 100 Ω. They must not introduce major impedance discontinuities. Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the LVDS receiver. For cable distances < 0.5 M, most cables can be made to work effectively. For distances 0.5 M ≤ d ≤ 10 M, CAT5 (Category 5) twisted pair cable works well, is readily available, and relatively inexpensive. 12 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated Product Folder Links: DS90LV027A DS90LV027A www.ti.com SNLS026D – MARCH 2000 – REVISED JUNE 2016 Typical Application (continued) 9.2.2 Detailed Design Procedure 9.2.2.1 Probing LVDS Transmission Lines Always use high impedance (>100 kΩ), low capacitance (